JP4547490B2 - Nonvolatile memory device and control method thereof - Google Patents

Description

  The present invention relates to a nonvolatile memory device in which the erasure of a nonvolatile memory cell or the permission / prohibition state of a program is controlled for each sector, and a control method thereof, and more particularly, to erase / program permission / inhibition information instructing the permission / inhibition state. The present invention relates to a non-volatile storage device having a function and a control method thereof.

  The nonvolatile storage device includes a volatile storage unit that manages sector erase control. The volatile storage unit includes three types of volatile storage units including first to third memory banks. The first memory bank manages whether or not the contents of the third memory bank can be rewritten. The first memory bank is management information that can be rewritten at any time. However, when the second memory bank is set to active, the contents corresponding to the address at which the second memory bank is set active in the first memory bank cannot be rewritten. The second memory bank is management information that can be set only once, and the set management information cannot be erased unless the memory power is turned off.

  The third memory bank manages whether each sector should be erased when the non-volatile storage device is erased. The management information is determined as to whether or not the management information electrically set from the outside of the nonvolatile storage device is input to the third memory bank according to the state of the management information stored in the first memory bank. To do. Whether the state machine (MCU) that executes the erase control executes the erase operation for each sector of the nonvolatile storage device according to the management information stored in the volatile storage unit (third memory bank) when executing the erase. Includes control to determine whether or not.

Patent Documents 1 to 3 disclose the related technology of such a volatile storage unit.
JP 2004-199825 A JP 2002-366436 A JP-A-8-44628

  However, in the above-described background art, the first to third memory banks are realized as individual volatile storage units, and there is a problem that the scale of the decoder and the like of each volatile storage unit and the control device thereof are increased. In addition, prior to writing to the third memory bank, it is necessary to read the contents of the first memory bank in advance, which increases the time required for access.

  The present invention has been made in view of the above-mentioned background art, and when storing information indicating the erasure of a nonvolatile memory cell or a program permission / rejection state and its security information in each storage unit, address decoding of each storage unit is performed. It is an object of the present invention to provide a nonvolatile memory device and a control method thereof that can simplify the circuit configuration and reduce the writing time by sharing.

  The non-volatile memory device according to the present invention made to achieve the above object includes, for each sector, an erasure permission / inhibition information storage unit that stores erasure permission / inhibition information instructing the erasure / program permission state of the nonvolatile memory cells; A security information storage unit that stores security information related to rewriting of the erasure permission / inhibition information storage unit for each erasure permission / inhibition information, and a decoder common to the erasure permission / inhibition information storage unit and the security information storage unit, Access to the security information storage unit is performed in a simultaneous cycle. Note that the erase includes a program.

  In the nonvolatile memory device according to the present invention, the erasure permission / inhibition information storage unit and the security information storage unit are selected by a common decoder.

As a result, it is only necessary to provide one set of word decoders, word line drivers, and column decoders that are originally required for each storage unit, and the circuit scale can be reduced.
Further, since the decoder and word line driver are shared by the erasure permission / inhibition information storage unit and the security information storage unit, the erasure permission / inhibition information storage unit and the security information storage unit are accessed simultaneously (in the same cycle). The reading of the security information from the security information storage unit and the writing of the deletion permission / prohibition information to the deletion permission / prohibition information storage unit according to the security information are performed simultaneously (in the same cycle). There is no need to perform a security information read operation from the security information storage unit prior to the writing of the erasure permission information to the erasure permission information storage unit. It is possible to shorten the time required for writing the erasure permission information to the erasure permission information storage section.

  Further, the method for controlling the nonvolatile memory device according to the present invention made to achieve the above-described object, from the security information storage unit according to the rewrite instruction of the erasure permission information stored in the erasure permission information storage unit, The method includes a step of reading security information corresponding to the erasure permission information and a step of controlling rewriting of the erasure permission information storage unit in accordance with the read security information.

  The non-volatile storage device control method according to the present invention performs the following two steps in response to a command to rewrite erase permission information stored in the erase permission information storage unit. First, security information corresponding to the erasure permission / inhibition information is read from the security information storage unit. Next, the step of controlling rewriting of the erasure permission / refusal information storage unit is performed within the same cycle in accordance with the read security information. Based on the read security information, the erasure permission information is rewritten in the erasure permission information storage unit.

  Thus, the security information corresponding to the target erasure permission / rejection information is confirmed in accordance with the erasure permission / rejection information rewrite command, and then rewriting to the erasure permission / rejection information storage unit is controlled. That is, a series of operations are performed according to one command (erase permission / rewrite information rewrite command). It is possible to shorten the time required for writing the erasure permission information to the erasure permission information storage section.

  According to the present invention, the erasure permission / inhibition information storage unit and the security information storage unit share the decoder and the word line driver, so that the security information is read from the security information storage unit, and the security information is read out. Writing of the erasure permission / prohibition information to the erasure permission / prohibition information storage unit is continuously performed within the same cycle. It is possible to provide a nonvolatile memory device and a control method therefor, in which the circuit scale is reduced and the time required for writing to the erasure permission / prohibition information storage unit is shortened.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the nonvolatile memory device according to the present invention will be described below in detail with reference to FIGS. It goes without saying that the embodiment described at the time of erasing can also be applied at the time of programming.

(First embodiment)
FIG. 1 is a diagram illustrating the operation of the nonvolatile memory device 1. The nonvolatile memory device 1 includes a first memory bank SRAM1, a second memory bank SRAM2, a third memory bank SRAM3, a first switch SW1, a second switch SW2, an SRAM1 control unit 8, and an SRAM3 control unit 9. And an erasure / rewrite control unit CNT and a nonvolatile storage unit NVRAM.

  First, the relationship between the first memory bank SRAM1, the second memory bank SRAM2, the third memory bank SRAM3, and the nonvolatile storage unit NVRAM will be described.

  The first memory bank SRAM1 manages whether or not the third memory bank can be rewritten, the second memory bank SRAM2 manages whether or not the first memory bank can be rewritten, and the third memory bank SRAM3 is non-volatile. Whether or not each sector of the volatile memory NVRAM can be erased / rewritten is managed.

  In the first memory bank SRAM1, management information that can be rewritten at any time is stored. However, the value stored in the corresponding address in the second memory bank SRAM2 is rewritten as being in a locked state (in this example, “1”). Can not do it.

  The second memory bank SRAM 2 stores management information that can be set only once (“1” in this example), and is set to a locked state (“1” in this example) unless the memory power supply is cut off or cold reset. The information thus obtained cannot be returned to unlock (in this example, “0”).

  In the third memory bank SRAM3, management information that can be rewritten at any time is stored. However, it is rewritten that the value stored in the corresponding address of the first memory bank SRAM1 is in the locked state ("1" in this example). Can not do it.

  Immediately after the power is turned on, all the first memory banks SRAM1 are set to the locked state “1”, and all the second memory banks SRAM2 are set to the unlocked state “0”.

  In FIG. 1, after the power is turned on, all the lock states “1” are stored in the first memory bank SRAM1, and each row in the third column and each row in the fourth column are in the lock state “1” in the second memory bank SRAM2. Is stored. In this state, write data to the first memory bank SRAM1 from outside the device (data in which each column in the first row and each column in the second row is “0”, each column in the third row and each column in the fourth row) Data of “1”) to the first memory bank SRAM1, each row of the third column and each row of the fourth column of the second memory bank SRAM2 are in a locked state, so that each row of the first column Only the data in each row of the second column is written into the first memory bank SRAM1. As a result, the unlock state “0” is stored only in the first row, first column, second row, first column, first row, second column, and second row, second column of the first memory bank SRAM1. Write control to the first memory bank SRAM1 at this time is performed by the SRAM1 control unit 8 and the first switch SW1, as will be described later.

In this state, when erasing the corresponding sector of the nonvolatile memory NVRAM by using NVRAM erase data from the outside of the device (data “E” for erasing each column of the second row and each column of the fourth row), Since the unlock state “0” is stored only in the first row, first column, second row, first column, first row, second column, and second row, second column of the first memory bank SRAM1, the third row Only the second row, first column and the second row, second column of the memory bank SRAM 3 are stored with a state “1” that can be erased / rewritten. Write control to the third memory bank SRAM 3 at this time is performed by the SRAM 3 control unit 9 and the second switch SW2, as will be described later.
As a result, only the second row, first column and the second row, second column are erased in the nonvolatile storage unit NVRAM.

  Next, the circuit operation of the nonvolatile memory device 1 will be described. FIG. 2 is a block diagram showing a configuration of the nonvolatile memory device 1. The nonvolatile memory device 1 includes three memory banks to which word lines are commonly connected, a first memory bank SRAM1, a second memory bank SRAM2, a third memory bank SRAM3, and a word decoder / X-SW including a word line driver. (2R), column decoder (2C), column switch / Y-SW (3), first write amplifier 5, second write amplifier 6, third write amplifier 7, first switch SW1, second switch SW2, SRAM1 control Unit 8, SRAM 3 control unit 9, first read amplifier 10, second read amplifier 11, third read amplifier 12, volatile storage unit 4, erase / rewrite control unit CNT, nonvolatile storage unit NVRAM, and volatile The memory storage rewrite control unit SRW and the command decoder CMD are provided.

  The command decoder CMD is connected to a group of control terminals outside the device, and various command signals as outputs are connected to the volatile storage unit rewrite control unit SRW and the erase / rewrite control unit CNT. The volatile storage unit rewrite control unit SRW is connected to the word decoder / X-SW (2R) and the column decoder (2C) by an SRAM active signal, and is connected to the first write amplifier 5, the second read amplifier 11, and the SRAM1 control unit 8. Is connected with the SRAM1 write mode signal, is connected with the second write amplifier 6 with the SRAM2 write mode signal, and is connected with the third write amplifier 7, the first read amplifier 10 and the SRAM3 control unit 9 with the SRAM1 write mode signal. Connected to the third read amplifier 12 by an SRAM3 read mode signal. From the erase / rewrite control unit CNT, an erase / rewrite control signal is connected to the volatile storage unit rewrite control unit SRW, and an erase / rewrite execution signal is connected to the NVRAM. From the third read amplifier 12, an erasure / rewrite acceptance signal is connected to the erasure / rewrite control unit CNT.

  In the first memory bank SRAM1, the memory cell selected by the word decoder / X-SW (2R) and activated in the word line WL is made conductive to the bit line BL1. The column switch / Y-SW (3) is selected by the column decoder (2C). The bit line BL1 selected by the column switch / Y-SW (3) is connected to the output terminal of the first write amplifier 5 via the first switch SW1, and is connected to the input terminal of the first read amplifier 10.

  In the second memory bank SRAM2, the memory cell selected by the word decoder / X-SW (2R) and activated in the word line WL is made conductive to the bit line BL2. The column switch / Y-SW (3) is selected by the column decoder (2C). The bit line BL2 selected by the column switch / Y-SW (3) is connected to the output terminal of the second write amplifier 6 and is connected to the input terminal of the second read amplifier 11. Note that the second memory bank SRAM2 is set so that once "1" is written as described later, the contents cannot be returned to "0" until the power is turned off.

  In the third memory bank SRAM3, the memory cell selected by the word decoder / X-SW (2R) and activated in the word line WL is made conductive to the bit line BL3. The column switch / Y-SW (3) is selected by the column decoder (2C). The bit line BL3 selected by the column switch / Y-SW (3) is connected to the output terminal of the third write amplifier 7 via the second switch SW2, and is connected to the input terminal of the third read amplifier 12. .

  The output terminal of the first read amplifier 10 is connected to the control terminal of the second switch SW2 via the SRAM 3 control unit 9. When the output signal of the first read amplifier 10 is at a low level, the second switch SW2 is turned on, and when it is at a high level, the second switch SW2 is turned off. When the output signal of the first read amplifier 10 is at a high level, external data is not written to the third memory bank SRAM3.

  The output terminal of the second read amplifier 11 is connected to the control terminal of the first switch SW1 via the SRAM1 control unit 8. When the output signal of the second read amplifier 11 is at a low level, the first switch SW1 is turned on. When the output signal is at a high level, the first switch SW1 is turned off. When the output signal of the second read amplifier 11 is at a high level, external data is not written to the first memory bank SRAM1.

  The erase / rewrite control unit CNT performs erase and rewrite operations of the nonvolatile storage unit NVRAM in accordance with the output value (erase / rewrite approval / denial signal) of the third read amplifier 12. Specifically, when the value “1” is written in the third memory bank SRAM 3, the erase / rewrite control unit CNT performs the erase and rewrite operations of the sector of the corresponding nonvolatile storage unit NVRAM. When “0” is written, the erase and rewrite operations of the sector of the corresponding nonvolatile memory NVRAM are not performed, so that the word decoder / X-SW, column decoder / Y− of the nonvolatile memory NVRAM are not performed. SW and an unillustrated erase / rewrite voltage generator are controlled.

  The command decoder CMD determines each access signal from the SRAM 1 to the SRAM 3 and controls the volatile storage unit rewrite control unit SRW. Further, the access signal to the NVRAM is discriminated and the erase / rewrite control unit CNT is controlled by the erase / rewrite mode signal. The erasing / rewriting control unit CNT includes an MCU that controls a plurality of processing steps (preprogramming, verifying, etc.) for erasing / rewriting. The MCU starts processing in response to an erasing / rewriting mode signal, and erase / rewrite acceptance / rejection. The erase / rewrite execution signal is controlled according to the signal. The volatile storage unit rewrite control unit SRW outputs an SRAM active signal and an SRAM3 read mode signal corresponding to the erase / rewrite control signal, and reads an erase / rewrite acceptance / rejection signal corresponding to the erase / rewrite sector of the NVRAM from the SRAM3. The volatile storage unit rewrite control unit SRW outputs an SRAM active signal, an SRAM1 write mode signal, an SRAM2 write mode signal, and an SRAM3 write mode signal corresponding to each access signal from the SRAM1 to the SRAM3. In response to an access signal to the SRAM 1, an SRAM 1 write mode signal is output, and the first write amplifier 5, the second read amplifier 11 and the SRAM 1 controller 8 are activated. When the SRAM active signal is activated, the SRAM 1 is rewritten in accordance with the first switch SW1 corresponding to the information of the SRAM 2 corresponding to the SRAM address signal and the I / O terminal signal. In response to an access signal to the SRAM 3, an SRAM 3 write mode signal is output, and the third write amplifier 7, the first write amplifier 5, and the SRAM 3 control unit 9 are activated. When the SRAM active signal is activated, the SRAM 3 is rewritten in accordance with the second switch SW2 corresponding to the information of the SRAM 1 corresponding to the SRAM address signal and the I / O terminal signal. In response to an access signal to the SRAM 2, an SRAM 2 write mode signal is output to activate the second write amplifier 6. When the SRAM active signal is activated, the SRAM 2 is rewritten according to the SRAM address signal and the I / O terminal signal. Incidentally, a second read amplifier activation signal (not shown) is input from the volatile storage unit rewrite control unit SRW to the second read amplifier 11 in response to the access signal to the SRAM 2, and the output of the second read amplifier 11 is the SRAM2 write mode. It is a logic signal indicating whether or not the signal is active. Thereby, the volatile memory unit rewrite control unit SRW prevents the bit of the SRAM address of the second memory bank SRAM 2 once written “1” from returning to “0” until the power is turned off. A function of controlling the second write amplifier 6 is provided.

  FIG. 3 is a timing chart showing the operation of each signal in the volatile storage unit 4. In the figure, WL is a signal of the word line WL, RA1 to RA3 are active signals of the first read amplifier 10 to the third read amplifier 12, BL1 to BL3 are signals of the bit line BL1 to bit line BL3, and WA1 to WA3 are the first write. The active signals SW1 and SW2 of the amplifiers 5 to 7 are signals indicating conduction / non-conduction of the first switch SW1 and the second switch SW2 (conduction at high level and non-conduction at low level).

First, a write mode to the third memory bank SRAM 3 will be described.
In (1), when the word line WL is active, the first read amplifier 10 is active, and the low level (unlock information; “0”) is read from the bit line BL1, the second switch SW2 is turned on. .

  In (2), when the second switch SW2 is turned on, a signal (NVRAM erase data) from the I / O is transmitted to the bit line BL3 in response to the activation of the third write amplifier 7, and the I / O Are written to the third memory bank SRAM3.

  In (3), when the word line WL is active, the first read amplifier 10 is active, and the high level (lock information; “1”) is read from the bit line BL1, the second switch SW2 is turned off. .

  In (4), since the first switch SW2 is non-conductive, the signal (NVRAM erase data) from the I / O is not transmitted to the bit line BL3 even when the third write amplifier 7 is active. For this reason, the signal from the I / O is not written in the third memory bank SRAM3.

Next, a write mode to the first memory bank SRAM1 will be described.
In (5), when the word line WL is active, the second read amplifier 11 is active, and the low level (unlock information; “0”) is read from the bit line BL2, the first switch SW1 is turned on. .

  In (6), when the first switch SW1 is turned on, a signal (SRAM1 write data) from the I / O is transmitted to the bit line BL1 in response to the activation of the first write amplifier 5, and the I / O Are written to the first memory bank SRAM1.

  In (7), when the word line WL becomes active, the second read amplifier 11 becomes active, and a high level (lock information; “1”) is read from the bit line BL2, the first switch SW1 is turned off. .

  In (8), since the first switch SW1 is non-conductive, the signal (SRAM1 write data) from the I / O is not transmitted to the bit line BL1 even when the first write amplifier 5 is active. For this reason, signals from the I / O are not written into the first memory bank SRAM1.

Next, a write mode (program to be erased or rewritten) to the nonvolatile storage unit NVRAM will be described. The erasure / rewrite control unit CNT controls the volatile storage unit 4 to obtain information of the third memory bank SRAM 3 in order to determine whether or not to execute the target sector during the NVRAM write mode.
In (9), when the word line WL becomes active and the third read amplifier 12 becomes active, the low level (lock information; “0”) is read from the bit line BL3.

  In (10), since the bit line BL3 is at the low level, the erase / rewrite execution signal for the target sector is not generated.

  In (11), when the third read amplifier 12 becomes active, a high level (unlock information; “1”) is read from the bit line BL3.

In (12), since the bit line BL3 is at the high level, an erase / rewrite execution signal for the target sector is generated.
In the write mode to the third memory bank SRAM3 and the write mode to the nonvolatile storage unit NVRAM, commands are input continuously from the outside of the device. That is, NVRAM erase data is continuously input from the outside of the device, and then an erase / rewrite command is issued from the outside of the device.

  In the volatile storage unit 4 according to the present embodiment, the first memory bank SRAM1 and the third memory bank SRAM3 are controlled by the same word line WL and the same column line. As a result, the circuit scale can be reduced because the word decoder, word line buffer, column decoder, column line buffer, etc. can be shared compared to the case where the word lines are individually configured for each memory bank. Can do.

  In the volatile storage unit 4 according to the present embodiment, the output signal of the first read amplifier 10 controls the second switch SW2. That is, writing to the third memory bank SRAM is controlled by the bit information value read from the first memory bank SRAM1. Since reading from the first memory bank SRAM1 and writing to the third memory bank SRAM3 are performed at the same timing (same cycle), compared to the operation of activating the word line WL twice, the third memory bank SRAM3 is read. Can be shortened.

  In the volatile storage unit 4 according to the present embodiment, the first memory bank SRAM1 and the second memory bank SRAM2 are controlled by the same word line WL and the same column line. As a result, the circuit scale can be reduced because the word decoder, word line buffer, column decoder, column line buffer, etc. can be shared compared to the case where the word lines are individually configured for each memory bank. Can do.

  Further, in the volatile storage unit 4 according to the present embodiment, the output signal of the second read amplifier 11 controls the first switch SW1. That is, the writing to the first memory bank SRAM1 is controlled by the bit information value read from the second memory bank SRAM2. Since reading from the second memory bank SRAM2 and writing to the first memory bank SRAM1 are performed at the same timing (same cycle), the first memory bank SRAM1 is compared with the operation of activating the word line WL twice. Write time can be shortened.

  Here, the first to third memory banks SRAM1 to SRAM3 are examples of an erasure permission information storage unit, a first security storage unit, and a second security storage unit, respectively. The SRAM 3 control unit 9 and the second switch SW2 are examples of the first control unit. The SRAM1 control unit 8 and the first switch SW1 are an example of a second control unit. The SRAM1 control unit 8 and the third switch SW3 are an example of a third control unit. Further, the erasure permission / inhibition information storage unit can be replaced with a program permission / rejection information storage unit, or both can be used together.

(Second Embodiment)
Hereinafter, a second embodiment of the nonvolatile memory device of the present invention will be described in detail with reference to FIG. 4 with reference to the drawings. A different part from 1st Embodiment is demonstrated and other than that is the same as 1st Embodiment.

  In FIG. 4, the second security information is read from the second security information storage unit in response to a second security information rewrite command, and the second security information storage unit is rewritten according to the read second security information. The 3rd control part to control is provided. The SRAM1 control unit 8 and the third switch SW3 are an example of a third control unit.

  In the second memory bank SRAM2, the memory cell selected by the word decoder / X-SW (2R) and activated in the word line WL is made conductive to the bit line BL2. The column switch / Y-SW (3) is selected by the column decoder (2C). The bit line BL2 selected by the column switch / Y-SW (3) is connected to the output terminal of the second write amplifier 6 via the third switch SW3 and is connected to the input terminal of the second read amplifier 11. The second memory bank SRAM2 is configured such that once "1" is written, the contents cannot be returned to "0" until the power is turned off, as in the first embodiment.

  The volatile storage unit rewrite control unit SRW is connected to the first write amplifier 5 by an SRAM1 write mode signal, and is connected to the second read amplifier 11 and the SRAM1 control unit 8 by an SRAM1 / 2 write mode signal. The second write amplifier 6 is connected by an SRAM2 write mode signal. The command decoder CMD determines an access signal to the SRAM 2 and controls the volatile storage unit rewrite control unit SRW. The volatile storage unit rewrite control unit SRW outputs the SRAM 1 write mode signal and the SRAM 1/2 write mode signal in response to the access signal to the SRAM 1, and the first write amplifier 5, the second read amplifier 11, and the SRAM 1 control unit 8. To activate. When the SRAM active signal is activated, the SRAM 1 is rewritten in accordance with the first switch SW1 corresponding to the information of the SRAM 2 corresponding to the SRAM address signal and the I / O terminal signal. The volatile storage unit rewrite control unit SRW outputs the SRAM 2 write mode signal and the SRAM 1/2 write mode signal in response to the access signal to the SRAM 2, and the second write amplifier 6, the second read amplifier 11, and the SRAM 1 control unit 8. To activate. When the SRAM active signal is activated, the SRAM 2 is rewritten according to the third switch SW3 corresponding to the information of the SRAM 2 corresponding to the SRAM address signal and the I / O terminal signal.

  Thereby, the volatile memory unit rewrite control unit SRW prevents the bit of the SRAM address of the second memory bank SRAM 2 once written “1” from returning to “0” until the power is turned off. A function of controlling the second write amplifier 6 is provided. Further, instead of the third switch SW3, the output control signal of the SRAM1 control unit 8 may control the SRAM2 write mode signal input to the second write amplifier 6.

  Note that the present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.

For example, in the present embodiment, the second switch SW2 is turned on when the bit line BL1 is at a low level, and the second switch SW2 is turned off when the bit line BL1 is at a high level. The present invention can also be applied to the case where the second switch SW2 is turned off when BL1 is at a low level and the second switch SW2 is turned on when the bit line BL1 is at a high level.
In this embodiment, the first switch SW1 is turned on when the bit line BL2 is at a low level, and the first switch SW1 is turned off when the bit line BL2 is at a high level. The present invention can also be applied to the case where the first switch SW1 becomes non-conductive when BL2 is at a low level and the first switch SW1 becomes conductive when the bit line BL2 is at a high level.
Furthermore, in the present embodiment, an example in which an erase / rewrite execution signal is not generated when the bit line BL3 is at a low level and an erase / rewrite execution signal is generated when the bit line BL3 is at a high level has been described. The present invention can also be applied to the case where the erase / rewrite execution signal is generated when the bit line BL3 is at the low level and the erase / rewrite execution signal is not generated when the bit line BL3 is at the high level.
Further, instead of the first switch SW1 and the second switch SW2, the output control signals of the SRAM1 control unit 8 and the SRAM3 control unit 9 are input to the first write amplifier 5 and the third write amplifier 7, respectively. And the SRAM3 write mode signal may be controlled.
In the embodiment, the first to third write amplifiers 5 to 7 and the first to third read amplifiers 10 to 12 are individually provided. However, the present application is not limited to this. By providing a configuration for switching paths, it is also possible to provide a set of amplifiers.
The nonvolatile storage device may be a RAM or a ROM.

It is a figure which shows operation | movement of a non-volatile memory | storage device. 1 is a block diagram showing a configuration of a nonvolatile memory device according to a first embodiment. Timing chart showing operation of each signal in volatile memory It is a block diagram which shows the structure of the non-volatile memory device concerning 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Nonvolatile memory | storage device SRAM1 1st memory bank SRAM2 2nd memory bank SRAM3 3rd memory bank 4 Volatile memory | storage part 5 1st write amplifier 6 2nd write amplifier 7 3rd write amplifier 8 SRAM1 control part 9 SRAM3 control part 10 1st 1 lead amplifier 11 2nd read amplifier 12 3rd read amplifier

Claims (12)

For each sector, an erasure permission / inhibition information storage unit for storing erasure permission / inhibition information indicating an erasure permission / inhibition state including a program of the nonvolatile memory cell;
A security information storage unit that stores security information related to rewriting of the deletion permission information storage unit for each of the deletion permission information,
A non-volatile storage device comprising: a decoder common to the erasure permission / inhibition information storage unit and the security information storage unit, wherein access to the erasure permission / inhibition information storage unit and the security information storage unit is performed simultaneously. The security information storage unit
A first security information storage unit that stores first security information for indicating a permission / refusal state of rewriting of the deletion permission / denial information storage unit for each of the deletion permission / denial information;
2. The nonvolatile memory according to claim 1, further comprising: a second security information storage unit that stores second security information that indicates a permission / refusal state of rewriting of the first security information storage unit for each erasure permission / inhibition information. Sex memory device.   The non-volatile storage device according to claim 2, wherein the number of times of writing to the second security information storage unit is one.   The non-volatile storage device according to claim 3, wherein the second security information storage unit is reset by power-off.   5. The erasure permission information storage unit and the security information storage unit or the first security information storage unit and the second security information storage unit include a common word line. The non-volatile memory device according to any one of the above.   6. The erasure permission information storage unit and the security information storage unit or the first security information storage unit and the second security information storage unit each include a common decoder. The nonvolatile memory device according to claim 1.   The security information corresponding to the erasure permission / inhibition information is read out from the security information storage section or from the first security information storage section in response to a rewrite instruction for the erasure permission / inhibition information stored in the erasure permission / inhibition information storage section. 7. The apparatus according to claim 1, further comprising a first control unit that reads the first security information corresponding to the erasure permission information and controls rewriting of the erasure permission information storage unit. Nonvolatile storage device.   In response to a rewrite command for the first security information stored in the first security information storage unit, the second security information corresponding to the first security information is read from the second security information storage unit, The nonvolatile storage device according to claim 2, further comprising a second control unit that controls rewriting of one security information storage unit.   A third control unit that reads out the second security information from the second security information storage unit and controls the rewriting of the second security information storage unit in response to the rewrite command of the second security information, The non-volatile storage device according to claim 2.   The erasure permission information storage unit and the security information storage unit or the first security information storage unit and the second security information storage unit are configured by volatile storage cells. 10. The non-volatile memory device according to at least any one of 9. A method for controlling a nonvolatile memory device according to claim 1, comprising:
In response to a rewrite command of the erasure permission / inhibition information stored in the erasure permission / inhibition information storage unit,
Reading the security information corresponding to the erasure permission / inhibition information from the security information storage unit;
And a step of controlling rewriting of the erasure permission / refusal information storage unit according to the read security information. A method for controlling a nonvolatile memory device according to claim 2,
In response to a rewrite command for the first security information stored in the first security information storage unit,
Reading the second security information corresponding to the first security information from the second security information storage unit;
And a step of controlling rewriting of the first security information storage unit according to the read second security information.

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