JP4540523B2 - Despreading device - Google Patents

Description

The present invention relates to a correlation circuit for spread spectrum communication used in a receiver of a spread spectrum communication system in mobile communication, wireless LAN, etc., and changes the number of received signal bits used for calculation according to the number of open channels and spreading factor, The present invention relates to a spread spectrum communication correlation circuit, a demodulation circuit, and a receiving apparatus capable of controlling the accuracy of a calculation result.

In a spread spectrum (SS) communication system generally used for mobile communication or wireless local area network (LAN), the transmission side performs narrowband modulation (primary modulation) on transmission data, and further spreads ( (Secondary modulation) is performed, and the data is transmitted by performing two-stage modulation. On the receiving side, the received data is despread and returned to the primary modulation, and then the baseband signal is generated by the detection circuit. Is going.

A correlation circuit for spread spectrum communication that outputs a correlation for demodulating a spectrum-spread received signal is composed of a despreading circuit and a demodulation circuit for a code division multiplexed modulation wave, specifically, spread spectrum communication. The correlation circuit uses a sliding correlator with the detected synchronization phase by performing synchronization acquisition, and performs correlation.

The configuration and operation of a spread correlator sliding correlator will be described with reference to FIG. The sliding correlator in FIG. 1 obtains a correlation with a code sequence on the reception side by shifting the code sequence used when spreading transmission data on the transmission side in units of one chip to despread the reception data. In the sliding correlator, the correlation with the received data can be obtained for the number of chips corresponding to the code sequence length.

The spread correlator sliding correlator includes an A / D converter 11, a multiplier 13, a PN (Pseudo-random Noise) code register 12, an adder 14, and a delay circuit 15.
Here, since it is necessary to reset the correlation value every time processing of received data for one symbol is completed, a flip-flop (Flip Flop) or register having a reset function is used for the delay circuit 15.

The analog signal spread and transmitted by the transmitter is received by the antenna of the receiver, then input to the A / D converter 11 and converted into digital received data.
Here, the chip rate of the analog signal is 4 Mcps, and the digital conversion in the A / D converter 11 is oversampling, so that multiple bits are output per bit of the same analog signal at 16 Mbps, which is usually four times that.

The received data converted into the digital signal of four times oversampling by the A / D converter 11 is output to the multiplier 13 bit by bit, and the multiplier 13 stores the PN (Pseudo-random Noise) stored in the PN code register 12. ) Multiplication with code, that is, despreading is performed. The PN code is the same code used for spreading at the transmitter.

The multiplier 13 multiplies the data of one sample per chip by the PN code, and does not use the remaining three samples of data. The PN code register 12 outputs the PN code to the multiplier 13 bit by bit at 4 Mbps.
The multiplication result of the multiplier 13 is output to the adder 14. The adder 14 adds the cumulative addition result and the multiplication result stored in the delay circuit 15 and outputs a new cumulative addition result as a correlation value and also to the delay circuit 15. The delay circuit 15 stores the input cumulative addition result.

When the cumulative addition of the multiplication results for one symbol is completed, the cumulative addition result is output from the adder 14 as a correlation value. Since the output result of the adder 14 is stored in the delay circuit 15, the same result can be obtained even if the correlation value is output from the delay circuit 15. When the correlation value for one symbol is output, the delay circuit 15 resets the stored cumulative addition result in preparation for calculating the correlation value of the next symbol.

Based on the correlation value output from the adder 14 in units of one symbol, the CDMA demodulation circuit further performs demodulation. The above is the operation of the sliding correlator for spread spectrum communication.
In the spread spectrum communication system, direct modulation may be used as secondary modulation. The above-described conventional spread correlator of the spread spectrum communication system can also be used as a complex type sliding correlator that outputs a correlation value with respect to orthogonally modulated received data.

と表される。（式１）より、復調信号の同相成分Ｄｉと直交成分Ｄｑはそれぞれ

と表される。（式３）及び（式４）のＤｉ、Ｄｑについて累加算を行い、両成分についての相関値を出力することが複素型スライディングコリレータの目的である。 A method for demodulating the reception data subjected to orthogonal modulation will be described below. The quadrature-modulated received data can be classified into an in-phase component and a quadrature component, respectively. Here, if the in-phase component is Ri, the quadrature component is Rq, the in-phase component of the spreading code is Ci, and the quadrature component is Cq, the demodulated signal D obtained by despreading is

It is expressed. From (Equation 1), the in-phase component Di and the quadrature component Dq of the demodulated signal are respectively

It is expressed. The purpose of the complex sliding correlator is to perform cumulative addition on Di and Dq in (Equation 3) and (Equation 4) and to output correlation values for both components.

FIG. 2 shows a configuration block diagram of a complex type sliding correlator that realizes the above-described received data demodulation method. In the complex type sliding correlator of FIG. 2, the CDMA modulated analog signal received by the antenna of the receiver is divided into an in-phase component and a quadrature component and input to A / D converters 21A and 21B, respectively. Here, the chip rate of the analog signal is 4 Mcps, and the digital conversion in the A / D converters 21A and 21B is oversampling, so that multiple bits are output per bit of the same analog signal at 16 Mbps, which is usually four times that.
The in-phase component and the quadrature component of the spread code are stored in the PN code register I22A and the PN code register Q22B, respectively.

In the complex type sliding correlator of FIG. 2, the digital reception data and the spread code output from the A / D converters 21A and 21B and the PN code registers 22A and 22B are input to the correlation calculation unit. In the correlation calculation unit, the digital reception data and the spread code are subjected to the calculations shown in the derivation equations (Equation 3) and (Equation 4) of the demodulated signal of each component by the multipliers 23A to 23D and the adders 24A and 24B. Correlation values for one symbol of the in-phase component and the quadrature component are respectively calculated by the accumulators 24C and 24D, and output as a correlation output I and a correlation output Q. The cumulative adder performs cumulative addition of one sample per chip and does not add the remaining three samples.

In the complex type sliding correlator of FIG. 2, a CDMA modulated analog signal is transmitted at a chip rate of 4 Mcps, and a 16 Mbps clock is input to each element of the complex type sliding correlator, thereby operating at a speed of 16 Mbps.
When demodulating a plurality of users and a plurality of paths, the PN code register and the correlation calculation unit are required for the number of users or the number of paths to be demodulated.

The configuration and operation of a conventional spread spectrum communication type despreading circuit will be described with reference to FIG. The CDMA modulated analog signal received by the receiver antenna is divided into an in-phase component and a quadrature component, and each is input to the A / D converter 31. In the figure, the in-phase component and the quadrature component are shown as one input. Here, the chip rate of the analog signal is 4 Mcps, and the digital conversion in the A / D converter 31 is oversampling, so that multiple bits are output per bit of the same analog signal at 16 Mbps, which is usually four times that.

The signed 15-bit received data output from the A / D converter 31 is output with the upper 8 bits cut out by the bit distributor 33 and the two systems obtained by cutting out the sign bit (MSB) + the lower 7 bits. To do.
The signal output from the bit distributor 33 is selected by the selectors 38A and 38B from either the upper 8 bits or the sign bit (MSB) + the lower 7 bits line and input to the correlation calculators 34A and 34B.

The in-phase component and the quadrature component of the despread codes of a plurality of users are stored in the PN code registers 32A and 32B, respectively, and input to the correlation calculators 34A and 34B. In FIG. 3, the in-phase component and the quadrature component of the despread code are represented by one figure.

In the correlation calculators 34A and 34B, the digital reception data and the spread code are subjected to the calculation shown in the derivation equations (Equation 3) and (Equation 4) of the demodulated signal of each component by the multiplier and the adder. Then, the correlation values for one symbol of the in-phase component and the quadrature component are respectively calculated and output as the correlation output I and the correlation output Q. In FIG. 3, the correlation output I and the correlation output Q are represented by one figure.

The outputs of the correlation calculators 34A and 34B are input to the bit shift calculators 35A and 35B, respectively. The bit shift calculators 35A and 35B output the result of arithmetic bit shift according to the information from the control unit to the adder 46.
The outputs of the bit shift calculators 35A and 35B are both input to the adder 36. The adder 36 adds the two calculation results and outputs the result.

The selector 39A selects one from the correlation calculator 34A, the adder 36, and the calculation result OFF input. Similarly, the selector 39B selects one from the correlation calculator 34B, the adder 36, and the calculation result OFF input. Are output as correlation calculation results. The control unit 37 outputs control signals to the selectors 38A, 38B, 39A, 39B, and the bit shift calculator, and controls them.

When acquiring a plurality of users or a plurality of paths, the control unit 37 selects the upper 8-bit line output from the bit distributor 33 by the selectors 38A and 38B. Further, the control unit 37 selects the output results of the correlation calculators 34A and 34B by the selectors 39A and 39B. By doing so, correlation results of a plurality of users or a plurality of paths are output as the correlation calculation results A and B, respectively.

Next, the operation when the number of users or the number of acquired paths is small, or when communication is performed at a rate with a small spreading factor and reception is performed with good characteristics will be described. In this case, the received data is calculated using all the 15-bit output from the A / D converter 31. In the control unit 37, the selector 38A selects the upper 8 bit line output from the bit distributor 33, and the selector 38B selects the code bit (MSB) + lower 7 bit line output from the bit distributor 33. .

In the correlation calculator 34A, the upper 8 bits are calculated, and in the correlation calculator 34B, the code bit (MSB) + the lower 7 bits are calculated. Since the outputs of the correlation calculators 34A and 34B are added later by the adder 36, the bit shift calculation is performed by the bit shift calculators 35A and 35B so as to be arranged at appropriate bit positions. The control unit 37 notifies and controls the bit shift computing units 35A and 35B as control values of the spread rate of the channel to be processed and the shift amount corresponding to the number of computation bits of the adder 36 in the subsequent stage.

The outputs of the bit shift calculators 35A and 35B are input to the adder 36 and added. In the control unit 37, the selector 39A selects the output of the adder 36 and outputs it as the correlation result A. The selector 39B selects OFF and does not output, or selects the output of the adder 36 and outputs it as the correlation result B. The operations of the selectors 39A and 39B may be reversed. In the control unit 37, the selector 39B selects the output of the adder 36 and outputs it as the correlation result B, and the selector 39A selects OFF and does not perform the output. The output of the device 36 may be selected and output as the correlation result A.

The selector 39A selects the output of the correlation calculator 34A and uses the upper 8 bits of the received data as the correlation calculation result A, and the selector 39B selects the output of the adder 36 and uses the received data 15 bits as the calculation result. Can also be output as the correlation calculation result B. The output can be changed by controlling the selectors 39A and 39B in the output stage according to the application to be used. In such a case, by using as many bits of the A / D converter output as possible, the calculation accuracy is improved and the characteristics are improved. Further, when communication is performed at a rate with a small spreading factor, the cumulative number of additions is reduced. Similarly, by using as many bits as possible of the output of the A / D converter, the calculation accuracy is improved and the characteristics are improved.

As described above, the correlation calculator shown in FIG. 2 of the prior art requires as many users or paths as to demodulate when demodulating multiple users and multiple paths. If the number of correlation calculators prepared in advance is small and the number of acquisition paths is small, there are unused correlation calculators.
The present invention has been made in view of the above circumstances, and the number of bits used for calculation is changed according to the number of users used, the number of acquired paths, and the reception rate (spreading rate) of users, An object of the present invention is to provide a spread spectrum communication type despreading circuit which can be processed in a time division manner by operating at high speed.

The present invention provides an A / D converter for converting an analog reception signal spectrum-spread by a plurality of types of spread signals into a digital reception signal, storage means for storing a despread code corresponding to each of the spread codes, A first selector that switches a spreading code stored in the storage means and outputs the time-division code; a bit distributor that distributes the digital reception signal to upper bits and MSBs and lower bits; and an output of the bit distributor A second selector for switching in a time-sharing manner, a correlation calculator for performing a correlation operation from a spreading code output from the first selector and a digital received signal output from the second selector, and the correlation An adder for adding the outputs of the computing unit;
, The circuit scale of the despreading device can be reduced and the calculation accuracy can be improved.

In the present invention, the second selector selects the first digital reception signal output from the bit distributor when the spreading factor is large and outputs it to the correlation calculator. When the spreading factor is small, the second selector selects the bit. the circuit scale of the despreading device by a despreading apparatus and outputs to the correlation calculator in a time division switch and a first digital received signal and the second digital received signal output from the distributor And the calculation accuracy can be improved. The present invention, correlation computing unit, the circuit scale of the despreading device by the despreaders you and performing a correlation operation at a multiple of the speed with respect to the operation speed of the A / D converter It can be reduced and the calculation accuracy can be improved.

  In the despreading device expected to increase the calculation accuracy and improve the characteristics of the present invention, the received data input to the correlation calculator is controlled, and the correlation calculator and the bit shift calculator are operated at twice the speed. The circuit scale can be reduced by controlling the selector, the bit shift arithmetic unit, and the adder with the control circuit.

Embodiments of the present invention will be described with reference to the drawings.
The function realizing means described below may be any circuit configuration or device configuration as long as it realizes the function, and part or all of the functions may be realized by software. Is possible. Furthermore, the function realizing means may be realized by a plurality of circuits, and the plurality of function realizing means may be realized by a single circuit.

One configuration example of the spread spectrum despreading circuit according to the embodiment of the present invention will be described with reference to FIG. The CDMA modulated analog signal received by the receiver antenna is divided into an in-phase component and a quadrature component, and each is input to the A / D converter 41. In FIG. 4, the in-phase component and the quadrature component are shown as one input. Here, the chip rate of the analog signal is 4 Mcps, and the digital conversion in the A / D converter 41 is oversampling, so that multiple bits are output per bit of the same analog signal at 16 Mbps, which is usually four times that.

The signed 15-bit received data output from the A / D converter 41 is output with the upper 8 bits cut out by the bit distributor 43 and the two systems obtained by cutting out the sign bit (MSB) + the lower 7 bits. To do.
The signal output from the bit distributor 43 is selected by the selector 48 as either the upper 8 bits or the sign bit (MSB) + lower 7 bits line and is input to the correlation calculator 44.
The in-phase component and the quadrature component of the despread codes of a plurality of users are stored in the PN code registers 42A and 42B, respectively, and one of them is selected by the selector 410 and input to the correlation calculator 44. In FIG. 4, the in-phase component and the quadrature component of the despread code are represented by one figure.

In the correlation calculator 44, the digital reception data and the spread code are subjected to the calculations shown in the derivation equations (Equation 3) and (Equation 4) of the demodulated signal of each component by the multiplier and the adder, and are further processed in phase by the accumulator. Correlation values for one symbol of the component and the orthogonal component are respectively calculated and output as a correlation output I and a correlation output Q. In FIG. 4, the correlation output I and the correlation output Q are represented by one figure. The correlation calculator 44 operates at a speed of 32 Mbps, which is twice as high as the operation speed of the A / D converter 41 in the previous stage, and is input by switching with the selector 48 and PN input by switching with the selector 410. Process code in a time-sharing manner. Here, the operation speed of the correlation calculator 44 is twice as high as the operation speed of the A / D converter 41, but it is a multiple of the operation speed of the A / D converter. You may make it operate | move by.

The output of the correlation calculator 44 subjected to the time division processing is input to the bit shift calculator 45. The bit shift computing unit 45 outputs the result of arithmetic bit shifting according to information from the control unit to the adder 46.
The adder 46 adds the operation result of the upper 8 bits and the operation result of the sign bit (MSB) + the lower 7 bits, which are alternately input from the bit shift operation unit in a time division manner, and outputs the result. The selector 49 selects one of the outputs from the correlation calculator 44 and the adder 46 and outputs it as a correlation calculation result. The control unit 47 outputs control signals to the selectors 48, 49, 410, the bit shift calculator 45, and the adder 46 to control each of them.

  When acquiring a plurality of users or a plurality of paths, the control unit 47 uses the selector 48 to select the upper 8-bit line output from the bit distributor 43. Further, the control unit 47 selects the output result of the correlation calculator 44 by the selector 49. By doing so, correlation results of a plurality of users or a plurality of paths are output in time division as a correlation calculation result.

Next, the operation when the number of users or the number of acquired paths is small, or when communication is performed at a rate with a small spreading factor and reception is performed with good characteristics will be described. In this case, the received data is calculated using all the 15-bit outputs from the A / D converter 41. In the control unit 47, the selector 48 selects the upper 8 bits line output from the bit distributor 43 and the code bit (MSB) + lower 7 bits line in a time division manner. In the correlation calculator 44, the upper 8 bits, the code bit (MSB) + the lower 7 bits are calculated in time division.

  Since the output of the correlation calculator 44 is added later by the adder 46, the bit shift calculator 45 performs bit shift calculation so that the data input in a time division manner are arranged at appropriate bit positions. The control unit 47 notifies the bit shift calculator 45 of the shift amount corresponding to the spreading factor of the channel to be processed and the number of calculation bits of the adder 46 in the subsequent stage as a control value for control. As the time division data input to the adder 46, the upper 8 bits correlation calculation result and the sign bit (MSB) + lower 7 bits correlation calculation result are alternately input, and the corresponding data are added and output. To do. The selector 49 selects the output of the adder 46 by the control unit 47 and outputs it as a correlation calculation result.

In the conventional despreading circuit, two correlation computing units and two bit shift computing units are prepared for high-order 8-bit processing and code bit (MSB) + low-order 7-bit processing, respectively. To realize a despreading circuit that reduces the circuit scale by controlling the selector and adder by controlling the selector and the adder in the spreading circuit by operating each of the correlation computing unit and the bit shift computing unit multiple times. Can do.

Configuration example of sliding correlator Configuration example of complex sliding correlator Configuration example of a conventional despreading circuit Configuration example of despreading circuit of the present invention

Explanation of symbols

41 ... A / D converter, 42 ... PN code register, 43 ... bit distributor, 44 ... correlation calculator, 45 ... bit shift calculator 46 ... adder, 47 ... control unit

Claims (1)

An A / D converter that converts an analog reception signal spectrum-spread by a plurality of types of spread signals into a 15-bit digital reception signal;
Storage means for storing a despread code corresponding to each of the spread codes;
A first selector that switches a spreading code stored in the storage means and outputs the spread code in a time-sharing manner;
A bit distributor that distributes the 15-bit digital received signal into an upper 8-bit first digital received signal and a code bit (MSB) + lower 7-bit second digital received signal;
A second selector that switches the output of the bit distributor and outputs in a time-sharing manner;
A correlation computing unit which performs a correlation operation from the digital reception signal output from the first selector and the spread code output the second selector,
A bit shift arithmetic unit for performing arithmetic bit shift on the output of the correlation arithmetic unit;
An adder for adding the outputs of the bit shift computing unit ;
A despreading device comprising :
When the spreading factor is large, the second selector selects the first 8-bit first digital reception signal output from the bit distributor, outputs the first digital reception signal to the correlation calculator, and correlates the output of the correlation calculator. If the spreading factor is small as a result of the calculation, the upper 8 bits of the first digital received signal and the code bit (MSB) + the lower 7 bits of the second digital received signal output from the bit distributor are switched The time-division output to the correlation calculator, the output of the correlation calculator is bit-shifted by the bit shift calculator, the output of the bit shift calculator is added by the adder, the output of the adder is A despreading device characterized by having a correlation calculation result.

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