JP4529571B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor.

Conventionally, in a field effect transistor (hereinafter referred to as “FET” as appropriate), the mobility of carriers is increased by selecting a material, particularly a material of a semiconductor portion that forms a channel, and a large on-current and a large switching frequency are obtained. (For example, Patent Document 1). Here, the “on-current” is an output current that flows through the channel when an appropriate gate voltage is applied to the gate electrode in order to cause the current to flow through the channel (that is, when it is on).
JP 2003-301116 A

However, the mobility that can be achieved by means of selecting semiconductor materials as has been done conventionally is insufficient. Therefore, it has been required to further improve the carrier mobility of the FET by another means to improve the on-current and the switching frequency. In particular, this is an important problem in an organic FET using an organic substance as a material for a semiconductor layer.
The present invention was devised in view of the above problems, and an object of the present invention is to provide a field effect transistor in which at least one of an on-current and a switching frequency is improved by improving carrier mobility. To do.

  The gist of the present invention is a field effect transistor comprising at least a semiconductor part and an insulating part, wherein the insulating part contains a substance having both ferroelectricity and ferromagnetism and a nonmagnetic substance. It exists in a transistor.

  According to the field effect transistor of the present invention, the mobility of carriers can be improved. This makes it possible to increase at least one of the on-current and the switching frequency of the field effect transistor.

Hereinafter, embodiments of the present invention will be described, but the present invention is not limited to the following embodiments, and can be arbitrarily modified and implemented without departing from the gist of the present invention.
[I. Overview]
The FET includes a source electrode, a drain electrode, a gate electrode, a semiconductor portion, and an insulating portion, and a channel is formed in the semiconductor portion between the source electrode and the drain electrode. The semiconductor portion is a portion where a channel is formed by a semiconductor. The channel is a portion where carriers generated when a voltage is applied to the gate electrode is distributed, and is usually formed along the source-drain direction. Further, many FETs such as a lateral FET and an electrostatic induction transistor (hereinafter referred to as “SIT” where appropriate) are configured by providing each component on a substrate.

The FET is based on the principle that the current between the source electrode and the drain electrode is generated by the contribution of channel carriers. In other words, current flows through the channel as carriers move between the source electrode and the drain electrode. The source-drain direction is
It is defined by the direction of a line segment that connects the shortest distances between the contact portion of the source electrode and the semiconductor portion and the contact portion of the drain electrode and the semiconductor portion.

Hereafter, each component of FET of this invention is demonstrated in detail.
[1. substrate]
As described above, in many FETs, components such as layers, members, and electrodes are provided on a substrate. In particular, it is preferable to use a substrate when an organic substance is used as the material of the semiconductor portion, because it is possible to manufacture an FET by a relatively low temperature process.

There is no restriction | limiting in particular about the material which forms a board | substrate, It can form with arbitrary materials. Specific examples of the substrate material include inorganic materials such as Si, SiO ₂ and metals, organic materials such as synthetic resins, and composite materials of inorganic materials and organic materials. Moreover, the material of a base material may be used individually by 1 type, and may use 2 or more types together by arbitrary combinations and a ratio. For example, it is possible to use a substrate having an insulating property by coating the surface of an inorganic substrate with an insulator such as a synthetic resin.

The shape of the substrate is also arbitrary, and various shapes such as a plate shape and a film shape can be used. However, from the viewpoint of flexibility, it is preferable to use a resin film for the substrate.
Furthermore, there is no restriction | limiting also about the dimension of a board | substrate, It can set arbitrarily according to the use.

  As described above, in the case of an FET such as a lateral FET, when an organic substance is used as the material of the semiconductor portion, it can be manufactured in a process at a relatively low temperature. Therefore, a plastic film can be used for the substrate, and there is an advantage that a device that is lightweight and excellent in flexibility and hard to break can be manufactured. Therefore, since a thin film flexible transistor can be manufactured, a wide range of applications such as a flexible active matrix liquid crystal display can be expected by using this as a switching element of each cell. .

Furthermore, the substrate may be formed as a laminate composed of a plurality of layers. In the case of a plurality of layers, the layers may be made of different materials.
By the way, there is a case where the characteristics of the FET can be improved by performing a predetermined surface treatment on the substrate. For example, the film quality of the film formed on the substrate may be improved by adjusting the degree of hydrophilicity or hydrophobicity of the substrate surface. In particular, when a semiconductor layer is formed as a semiconductor portion on a substrate, the characteristics of the semiconductor material vary greatly depending on the state of the film such as molecular orientation. By utilizing this, it is possible to improve the FET characteristics by controlling the molecular orientation at the interface between the substrate and the semiconductor layer by the surface treatment of the substrate.

Examples of such surface treatment include hydrophobization treatment with hexamethyldisilazane, cyclohexene, octadecyltrichlorosilane, etc., acid treatment with hydrochloric acid, sulfuric acid, acetic acid, etc., sodium hydroxide, potassium hydroxide, calcium hydroxide, ammonia, etc. Alkali treatment, ozone treatment, fluorination treatment, plasma treatment such as oxygen and argon, Langmuir-Blodgett film (LB film) formation process, other insulator and semiconductor thin film formation process, mechanical process, corona discharge, etc. For example.
[2. Gate electrode]
The gate electrode applies a gate voltage to the insulating portion, and on / off of the FET is controlled by the gate voltage applied from the gate electrode.

The material of the gate electrode is not particularly limited as long as it has conductivity, and any material can be used. For example, conductive materials such as metals, alloys, conductive polymers, and composite materials thereof can be used. Specific examples include metals such as platinum, gold, aluminum, chromium, nickel, copper, titanium, magnesium, calcium, barium, and sodium; conductive polymers such as polyaniline, polypyrrole, polythiophene, and polyacetylene; and hydrochloric acid Disperse carbon black and metal particles, including acids such as sulfuric acid and sulfonic acid, Lewis acids such as PF ₆ , AsF ₆ and FeCl ₃ , halogen atoms such as iodine, and metal atoms such as sodium potassium And conductive composite materials.

Note that the gate electrode may be formed using one type of material alone, or may be formed using two or more types of materials in any combination and ratio.
The shape of the gate electrode is arbitrary, but it is usually formed in a thin film shape in which the above materials are stacked. In this case, the thin film may have a single layer structure or a stacked structure in which two or more layers are stacked.

Furthermore, the dimensions of the gate electrode are also arbitrary. For example, the thickness is usually 1 nm or more, preferably 10 nm or more, and usually 100 nm or less, preferably 50 nm or less.
There is no limitation on a method for manufacturing the gate electrode, and various known methods can be arbitrarily used. For example, the gate electrode can be formed by depositing a material using a gate vacuum deposition method, a sputtering method, a coating method, a printing method, a sol-gel method, or the like.

  Further, in the case where the gate electrode is formed by film formation, it is preferable to perform patterning as necessary after forming the film so as to have a desired shape. Various known methods can be used as the patterning method. For example, photolithography using a combination of photoresist patterning and etching (wet etching with an etchant or dry etching with reactive plasma), inkjet printing, screen printing, offset A printing method such as printing and letterpress printing, a soft lithography method such as a microcontact printing method, and a method combining a plurality of these methods can be used. Alternatively, a pattern can be directly produced by irradiating an energy beam such as a laser or an electron beam to remove the material or changing the conductivity of the material. Further, a gate insulating film can be patterned around the gate electrode.

The gate electrode is insulated from the semiconductor portion. There is no limitation on the method of insulation, but it is optional. Usually, an insulating part is provided between the gate electrode and the semiconductor part to prevent carriers from entering and exiting. Specifically, it is preferable to use the insulating portion formed as a thin film as the insulating layer.
[3. Source electrode and drain electrode]
The source electrode is an electrode through which current flows from the outside through the wiring, and the drain electrode is an electrode that sends current through the wiring to the outside. When the carriers are holes, the carriers move from the source electrode to the drain electrode through the channel, so that an on-current flows between the source electrode and the drain electrode. Similarly, when the carrier is an electron, an on-current flows when the carrier moves from the drain electrode to the source electrode.

The material for the source electrode and the drain electrode is not particularly limited as long as it has conductivity, and any material can be used. For example, conductive materials such as metals, alloys, conductive polymers, and composite materials thereof can be used. Specific examples include the same materials as those exemplified as the material of the gate electrode.
Note that the source electrode and the drain electrode may be independently formed of one kind of material, or may be formed of two or more kinds of materials in any combination and ratio.

The shape of the source electrode and the drain electrode is arbitrary, but usually, the material is formed and used as an island-shaped structure thin film in which the material is formed in an island shape. In this case, the thin film may have a single layer structure or a stacked structure in which two or more layers are stacked.
Furthermore, although the dimensions of the source electrode and the drain electrode are arbitrary, for example, the thickness thereof is usually 1 nm or more, preferably 10 nm or more, and usually 100 nm or less, preferably 50 nm or less.

A source electrode and a drain electrode can be manufactured by any method, but can be manufactured in the same manner as a gate electrode, for example.
[4. Semiconductor Department]
(Constitution)
The semiconductor portion is a portion constituting a channel in which carriers move between the source electrode and the drain electrode, and is formed so as to connect the source electrode and the drain electrode.

There is no restriction | limiting in the semiconductor material which forms a semiconductor part, A well-known semiconductor material can be used arbitrarily. The semiconductor material may be organic or inorganic, but is preferably organic. This is because there are advantages such as that the FET can be manufactured by a simple and inexpensive manufacturing method, and that a flexible FET can be manufactured.
When the semiconductor material is an organic material, for example, condensed aromatic hydrocarbons such as naphthacene, pentanesene, pyrene, fullerene; oligomers such as α-sexithiophene; macrocyclic compounds such as phthalocyanine and porphyrin; α-sexithiophene, Oligothiophenes containing 4 or more thiophene rings typified by dialkylsexithiophene; a total of 4 or more thiophene rings, benzene rings, fluorene rings, naphthalene rings, anthracene rings, thiazole rings, thiadiazole rings, and benzothiazole rings Condensed thiophenes such as anthradithiophene, dibenzothienobisthiophene, α, α'-bis (dithieno [3,2-b ': 2', 3'-d] thiophene) and derivatives thereof; naphthalenetetracarboxylic anhydride , Naphthalenetetracarboxylic acid diimide, Aromatic carboxylic anhydrides such as rylenetetracarboxylic anhydride and perylenetetracarboxylic diimide and imidized products thereof; macrocyclic compounds such as copper phthalocyanine, perfluorocopper phthalocyanine, tetrabenzoporphyrin and metal salts thereof; polythiophene, polyfluorene Polythienylene vinylene, polyphenylene vinylene, polyphenylene, polyacetylene, polypyrrole, polyaniline and the like can be used.

Among these, those exhibiting self-organization such as regioregular polythiophene, and polymers exhibiting liquid crystallinity represented by polyfluorene and copolymers thereof are preferable.
Among organic semiconductor materials, pentacene, a compound having a porphyrin skeleton (porphyrin compound) and the like are preferable, and a compound having a porphyrin skeleton is more preferable. For example, the operational characteristics of a lateral FET, which is a type of FET, include carrier mobility μ and conductivity σ of the semiconductor part, capacitance of the gate insulating film, configuration of the lateral FET (distance and width between source and drain electrodes, gate insulation) The FET using a compound having a porphyrin skeleton is preferable because the carrier mobility μ and the on / off ratio can be increased.

  Among compounds having a porphyrin skeleton, particularly preferred are those having a structure represented by the following formula 1 or formula 2, for example.

In Formula 1 and Formula 2, Z ^ia and Z ^ib (i is an integer of 1 to 4) each independently represent a hydrogen atom, a hydroxyl group, a halogen atom, an amino group, a nitro group, or a monovalent organic group. .
Examples of monovalent organic groups that can be Z ^ia and Z ^ib include alkyl groups, alkoxy groups, mercapto groups (alkylthio groups), acyl groups, esters of carboxyl groups and C 1-10 alcohols, formyl groups, And a carbamoyl group.

When Z ^ia and Z ^ib are monovalent organic groups, the carbon number is usually 1 or more and usually 10 or less. Furthermore, these organic groups may have a substituent.
Further, when Z ^ia and Z ^ib are an amino group or a nitro group, the amino group or nitro group may be substituted with a hydrocarbon group such as an alkyl group. The number of carbon atoms of the hydrocarbon group substituted with the amino group or nitro group is usually 1 or more and 10 or less.

Further, when Z ^ia and Z ^ib are halogen atoms, specific examples thereof include fluorine, chlorine, bromine, iodine and the like.
Z ^ia and Z ^ib may combine to form a ring. Examples of the ring formed in this case include aromatic rings such as benzene ring, naphthalene ring and anthracene ring; heterocyclic rings such as pyridine ring, quinoline ring, furan ring and thiophene ring; non-aromatic rings such as cyclohexene Can be mentioned.

Furthermore, in said formula 1 and formula 2, R < ¹ > -R < ⁴ > represents a hydrogen atom, a halogen atom, or a monovalent organic group each independently. Examples of the organic group include an alkyl group, an aryl group, an alkoxy group, a mercapto group, an ester of a carboxyl group and an alcohol having 1 to 10 carbon atoms. Furthermore, these organic groups may have a substituent. When R ^{1 to} R ⁴ are halogen atoms, specific examples thereof include fluorine, chlorine, bromine and iodine.

  Examples of porphyrin compounds are given below. However, although a metal-free structure is illustrated here, even a metal salt corresponding to the following example or a molecule having a substituent can be used as a preferable organic semiconductor material. In addition, molecular structures with good symmetry are mainly exemplified, but an asymmetric structure based on a combination of partial structures can also be used. Further, the porphyrin compounds are not limited to these exemplified compounds.

On the other hand, examples of the inorganic semiconductor material include a single semiconductor and a compound semiconductor.
Examples of the single semiconductor include IV (B) group semiconductors such as Si and Ge, and those obtained by doping these single semiconductors with B or the like.
The compound semiconductors include III-V group compound semiconductors such as GaN, GaP, GaAs, InGaN, and InGaP; II-VI group semiconductors such as ZnTe and CdSe; chalcogen compounds such as FeS, Fe ₃ F ₄ , and CuS; magnetite And oxide semiconductors such as those obtained by doping these compound semiconductors.

In addition, a semiconductor material may be used individually by 1 type, and may use 2 or more types together by arbitrary combinations and a ratio.
Further, in addition to the semiconductor material, various additives may be mixed in the semiconductor portion in order to improve the characteristics or to impart other characteristics. Examples of the additive include an antioxidant.

Further, there is no particular limitation on the shape of the semiconductor portion, and any shape can be used as long as the source electrode and the drain electrode can be connected. However, the semiconductor part is usually configured as a semiconductor layer in which semiconductors are stacked.
When the semiconductor portion is formed as a semiconductor layer, the semiconductor layer may be formed from a single layer or may be formed from two or more layers.

  Furthermore, the thickness of the semiconductor layer is preferably as thin as possible within a range that can perform a necessary function. This is because the risk of increase in leakage current increases as the thickness of the semiconductor layer increases. The specific range of the thickness of the semiconductor layer is usually 1 nm or more, preferably 5 nm or more, more preferably 10 nm or more, and usually 10 μm or less, preferably 1 μm or less, more preferably 500 nm or less, most preferably Is 50 nm or less.

(Formation method)
There is no restriction | limiting about the formation method of a semiconductor part, It can form using a well-known method arbitrarily. Hereinafter, a method for forming a semiconductor layer will be described as an example of a method for forming a semiconductor portion.
There is no limitation on the method for forming the semiconductor layer, and any known method can be used. For example, the formation method in a vacuum process such as a sputtering method or a vacuum deposition method, or a solution process such as a coating method or a printing method. And the like. In addition, the formation method of these semiconductor layers may be performed individually by 1 type, and may be performed combining 2 or more types of methods suitably.

(Vacuum process)
Hereinafter, a method for obtaining a semiconductor layer by depositing a semiconductor material by a vacuum process will be described in detail. In film formation by a vacuum process, film formation is performed by attaching a semiconductor material to a substrate in a vacuum or reduced pressure environment.
For example, in the vacuum evaporation method, a semiconductor material is formed by heating and evaporating a semiconductor material in a vacuum and attaching the evaporated semiconductor material to a substrate.

In the vacuum deposition method, the pressure condition is usually 1 × 10 ⁻³ Torr (1.3 × 10 ⁻¹ Pa) or less, preferably 1 × 10 ⁻⁶ Torr (1.3 × 10 ⁻⁴ Pa) or less.
In addition, since the characteristics of the semiconductor layer, and hence the FET, vary depending on the substrate temperature, the substrate temperature is set to an optimum substrate temperature. Specifically, it is usually 0 ° C. or higher, preferably 10 ° C. or higher, and usually 200 ° C. or lower, preferably 50 ° C. or lower.

Further, although the deposition rate is arbitrary, it is usually 0.001 nm / s or more, preferably 0.01 nm / s or more, and usually 10 nm / s or less, preferably 1 nm / s or less.
Moreover, you may make it obtain a semiconductor layer by sputtering method, for example. In the sputtering method, instead of evaporating the semiconductor material by heating, ions such as accelerated argon collide with the semiconductor material target to strike out semiconductor material atoms and attach them to the substrate in the same manner as the vacuum evaporation method, A semiconductor layer is formed.

In general, when a relatively low molecular weight organic semiconductor material is used as a semiconductor material and when an inorganic semiconductor material is used, it is preferable to use such a vacuum process. In addition, although an expensive facility is required for the vacuum process, there is an advantage that a film forming property when the semiconductor layer is formed is good and a uniform film can be easily obtained.
(Solution process)
Next, a method for obtaining a semiconductor layer by depositing a semiconductor material by a solution process will be described in detail. In film formation by a solution process, a semiconductor material is dissolved in a solvent to form a solution, and the solution is applied onto a substrate to obtain a semiconductor layer.

There is no restriction | limiting in the solvent which melt | dissolves a semiconductor material, Arbitrary solvents can be used according to the kind etc. of semiconductor material.
Also, there are no restrictions on the application method. For example, coating methods (application methods) such as casting, spin coating, dipping, blade coating, wire bar coating, spray coating, ink jet printing, screen printing, etc. And printing methods such as offset printing and letterpress printing, and soft lithography methods such as a microcontact printing method. Moreover, these methods may be performed alone or in combination of two or more as appropriate.

Furthermore, as a technique similar to coating, a Langmuir-Blodgett method in which a monomolecular film of a semiconductor material formed on a water surface is transferred to a substrate and laminated, a liquid crystal or a melted semiconductor material is sandwiched between two substrates, or a capillary phenomenon And a method of introducing between two substrates.
When such a solution process is used, there is an advantage that a semiconductor layer having a large area can be easily manufactured with relatively inexpensive equipment.

  Among the materials for the semiconductor layer, organic compounds such as porphyrin compounds are formed by applying a solution obtained by dissolving the organic semiconductor material itself in a solvent to the substrate when forming the organic semiconductor layer by a solution process. The method using a precursor can be taken. That is, a precursor of an organic semiconductor material is dissolved in a solvent to prepare a precursor solution, this precursor solution is applied to a substrate, and the chemical structure of the precursor is changed on the substrate to obtain a final organic semiconductor material. This is a method for forming a semiconductor layer. This method is particularly useful when an organic semiconductor layer is formed by forming a film of a semiconductor layer material that is hardly soluble in a solvent by a solution process.

  Examples of the precursor include those having a bicyclo structure shown below. The two bonds of the bicyclo structure below and the benzene ring in which it is changed are bonds for linking to porphyrin or the like.

  As shown in the following reaction formula, this bicyclo structure is transformed into a benzene ring by dissociation of ethylene molecules by heating.

  Since the bicyclo structure is sterically bulky, its crystallinity is low. Therefore, the molecule having a bicyclo structure has good solubility, and when the solution is applied, it is easy to obtain a coating film with low crystallinity or amorphousness. In addition, when the bicyclo structure is changed to a benzene ring through a heating step, a molecular structure with good planarity is obtained, so that crystallinity is improved. Therefore, by utilizing a chemical change from a precursor having a bicyclo structure, even when an organic semiconductor layer is formed by a solution process using an organic semiconductor material having low solubility in a solvent, the organic semiconductor layer has better crystallinity. The resulting semiconductor layer can be obtained by coating. This heating step may also serve other purposes such as distilling off the coating solvent.

Specific examples of semiconductors suitable for a method using a precursor include, among porphyrin compounds, a compound in which a benzene ring is condensed with a pyrrole ring, a thiophene ring, or a furan ring called a benzoporphyrin is a bicyclo structure. Therefore, it is advantageous for forming a semiconductor layer by coating using the above method.
In addition, the solution process has an advantage that the thickness of the semiconductor layer can be increased by repeating the coating process and the drying process as many times as necessary. Furthermore, when forming a semiconductor layer using a precursor, if the coating process of the precursor solution and the chemical structure change process are repeated, the solubility of the precursor and the organic semiconductor material is different. There is also an advantage that a semiconductor layer can be stacked while not being dissolved in the precursor solution to form a thick film.

In general, according to a solution process, it is considered that a film forming property is not high and a semiconductor film having high crystallinity is difficult to obtain. However, the method using the precursor is preferable because a semiconductor film having high crystallinity and good characteristics can be obtained by a simple solution process.
An FET including a semiconductor layer formed in this manner has preferable characteristics of high carrier mobility and high on / off ratio. In addition, the method using the said precursor is not only a porphyrin compound, but is a method which can be widely applied to general organic materials.

When it is desired to control the crystal orientation of the semiconductor layer, the crystal orientation can be controlled by using a technique such as epitaxial growth or rubbing after coating. If the orientation of the semiconductor crystal is appropriately adjusted by these methods, the electrical resistivity of the channel can be reduced.
Further, the semiconductor portion may contain a small amount of impurities such as atoms, atomic groups, molecules, and polymers. The doping of impurities in the semiconductor portion in this way is referred to as doping, which can change the characteristics of the semiconductor portion and make it preferable.

As the impurities, known ones can be arbitrarily used depending on the characteristics of the semiconductor portion to be formed. Specific examples include acids such as oxygen, hydrogen, hydrochloric acid, sulfuric acid and sulfonic acid, Lewis acids such as PF ₆ , AsF ₅ and FeCl ₃ , halogen atoms such as iodine, metal atoms such as sodium and potassium, and the like. .
The doping method is also arbitrary. For example, the semiconductor portion may be brought into contact with an impurity gas, immersed in an impurity solution, or subjected to an electrochemical treatment.

  Further, the doping can be performed before or during the formation of the semiconductor portion, even after the semiconductor portion is not formed. For example, doping can be performed by mixing impurities at the time of synthesizing the semiconductor material before forming the semiconductor portion. In addition, when the semiconductor portion is formed by a vapor phase method such as sputtering or vapor deposition, doping can be performed by using a material in which an impurity to be doped is mixed in advance in a raw material such as a target or a source. Furthermore, when forming a semiconductor part by a solution process, doping may be performed by mixing impurities into a semiconductor material or a precursor solution, or using an impurity gas or solution at the stage of the precursor film. Is possible. In addition, when forming a semiconductor part by a vacuum process, impurities are co-deposited at the time of vapor deposition, impurities are mixed in the atmosphere of the vacuum process, and further, ions of the impurity are accelerated in the vacuum to collide with the semiconductor part. It is also possible to perform doping.

Various effects can be obtained as the effect of doping. Typical examples include a change in electrical conductivity due to an increase or decrease in carrier density, a change in carrier polarity (p-type or n-type), and Fermi. Examples include level changes.
Further, the characteristics of the semiconductor portion manufactured in this way can be further improved by post-processing. For example, the heat treatment can reduce distortion in the semiconductor portion that occurs during film formation and can improve characteristics. Furthermore, a change in characteristics due to oxidation or reduction can be induced by exposure to an oxidizing or reducing gas or liquid such as oxygen or hydrogen. This is used for the purpose of increasing or decreasing the carrier density in the semiconductor portion, for example. Other examples of post-processing include LB film formation processing, other insulator or semiconductor thin film formation processing, mechanical processing, and electrical processing such as corona discharge.

[5. Insulation part]
In the FET of the present invention, the insulating portion contains a material having both ferroelectricity and ferromagnetism (hereinafter sometimes referred to as “coexisting material”) and a nonmagnetic material.
Here, the term “ferroelectric” refers to the property of generating spontaneous electric polarization even when the external electric field is zero. Whether or not it has spontaneous electric polarization can be known as follows. First, the electric susceptibility χ _e is measured while changing the temperature T of the substance to be measured (target substance), and a 1 / χ _e -T plot (plot with 1 / χ _e and T as axes) is drawn. At this time, the 1 / χ _e -T plot is a straight line. If the straight line has an intercept in the region of T> 0 on the T axis, the target substance is said to have ferroelectricity. The temperature of this intercept is called the Curie temperature of the ferroelectric.

  In this connection, a substance having an electric dipole moment-electric field curve (dielectric polarization curve) having hysteresis exhibits a ferroelectric property, but an electric dipole moment-electric field curve (dielectric polarization curve) has hysteresis. In some cases, even a substance that does not have a ferroelectric substance exhibits ferroelectricity. Usually, it is desirable to use a substance that does not have hysteresis in the electric dipole moment-electric field curve (dielectric polarization curve) but exhibits ferroelectricity as the coexisting substance of the FET of the present invention.

Similarly, ferromagnetism is a property that causes spontaneous magnetization. Whether or not it has ferromagnetism can also be known in the same way as ferroelectricity. That is, the magnetic susceptibility χ _m is measured while changing the temperature T of the substance to be measured (target substance), and a 1 / χ _m -T plot (plot with 1 / χ _m and T as axes) is drawn. At this time, if the T> 0 region has an intercept, the target substance is said to have ferromagnetism. Further, the temperature of this intercept is called the Curie temperature of the ferromagnetic material.

In this connection, a substance whose magnetic dipole moment-magnetic field curve (magnetization curve) has hysteresis is a substance exhibiting ferromagnetism, but the magnetic dipole moment-magnetic field curve (magnetization curve) has hysteresis. Even a non-existing substance may be a substance exhibiting ferromagnetism. Usually, as with ferroelectricity, it is desirable to use, as the coexisting material of the FET of the present invention, a substance that does not have hysteresis in the magnetic dipole moment-magnetic field curve (magnetization curve) but exhibits ferromagnetism.

In order to use the coexisting material in the FET of the present invention, there is no particular limitation as long as it is a material having both ferroelectricity and ferromagnetism, and a known material can be arbitrarily used. Specific examples thereof include (BiFeO ₃ ) _x (BaTiO ₃ ) _1-x , (BiFeO ₃ ) _x (PbTiO ₃ ) _1-x , (PLZT) _x (BiFeO ₃ ) _{1-x, and the} like. Here, x is a number satisfying 0 ≦ x ≦ 1 independently. In addition, the PLZT, indicating that the _{Pb 1-klm La k Zr l} Ti m O 3. However, k, l, and m are numbers of 0 or more and 1 or less that satisfy k + 1 + m ≦ 1, respectively. Among these, it is preferable to use (PLZT) _x (BiFeO ₃ ) _1-x having transparency.

Moreover, the manufacturing method of the coexistence type material illustrated here is arbitrary, For example, it can manufacture by mixing starting materials, such as nitrate, and making it thermally decompose. Specifically, when (PLZT) _x (BiFeO ₃ ) _1-x is produced, Pb (NO ₃ ) ₂ , La (NO ₃ ) ₃ .6H ₂ O, ZrO (NO ₃ ) _2. 2H ₂ O, Ti [OCH (CH ₃ ) ₂ ] ₄ , Bi (NO ₃
) ₃ · 5H ₂ O, Fe (NO ₃ ) ₃ · 9H ₂ O are prepared. These starting materials are dissolved in a solvent such as an organic solvent, and applied in a film form to a place where an insulating portion is to be formed, for example, by spin coating. After evaporating the organic solvent, the reaction is carried out by heating with an electric furnace or the like. In this case, the reaction temperature is preferably maintained at about 600 ° C. Thereby, the thin film of a coexistence substance can be obtained as an insulating part. For details of the production method, Journal of Physics and Chemistry of Solids 64, 391 (2003) and the like can be referred to.

In addition, a coexistence type | system | group substance may be used individually by 1 type, and may use 2 or more types together by arbitrary combinations and a ratio.
A nonmagnetic material is a material that does not become ferromagnetic in the environment in which the FET is used. That is, a substance having no Curie temperature and a substance having a Curie temperature lower than the temperature of the environment in which the FET is used.

The nonmagnetic material is preferably a material that does not have electrical conductivity. This is to suppress an increase in leakage current in the insulating portion.
Non-magnetic substances include, for example, polymethyl methacrylate, polystyrene, polyvinyl phenol, polyimide, polycarbonate, polyester, polyvinyl alcohol, polyvinyl acetate, polyurethane, polysulfone, epoxy resin, phenol resin, and combinations of these. Polymers, oxides such as silicon dioxide, aluminum oxide and titanium oxide, ferroelectric oxides such as SrTiO ₃ and BaTiO ₃ , dielectrics such as nitrides such as silicon nitride, sulfides and fluorides can be used. .

A nonmagnetic substance may be used individually by 1 type, and may use 2 or more types together by arbitrary combinations and a ratio.
In addition to the coexisting materials and non-magnetic materials, other materials in the insulating part, as long as the properties are not impaired,
For example, a small amount of a substance having only ferromagnetism may be included.
Since the channel is formed in the semiconductor portion, the insulating portion is provided so as to be in direct contact with the semiconductor portion. When the semiconductor portion is composed of two or more members, it is preferable that the semiconductor portion is in direct contact with at least one of the members.

Furthermore, the shape of the insulating portion is also arbitrary, and can be formed in various shapes such as a thin film shape, a block shape, a plate shape, and a rod shape, but is usually formed in a thin film shape along the semiconductor portion. It is preferable. In this case, the thin film may have a single layer structure or a stacked structure in which two or more layers are stacked.
In addition, the dimensions of the insulating portion are arbitrary, but when it is formed in a thin film, for example, it is preferable that the insulating portion is thin as long as a necessary function can be achieved. The film thickness is usually 1 nm or more, preferably 5 nm or more, more preferably 10 nm or more, and usually 10 μm or less, preferably 1 μm or less, more preferably 500 nm or less. The thinner the film thickness, the larger the carrier injection effect can be obtained. However, if the film thickness is too thin, there is a risk of dielectric breakdown.

  There is no limitation on a method for manufacturing the insulating portion, and the insulating portion can be manufactured by any method. As a specific example, when the insulating portion is formed in a thin film shape, a coating method such as spin coating or blade coating, a printing method such as screen printing or inkjet, a vacuum deposition method, a sputtering method, or other alumite on aluminum. Thus, a thin film forming method such as a method of forming an oxide film on a metal can be used.

In addition, when forming each part in the order of the insulating part and the semiconductor part, in order to improve the crystal orientation and molecular orientation of the semiconductor material at the interface between the insulating part and the semiconductor part, a predetermined surface treatment is applied to the insulating part. It is preferable to do so. As an example of the surface treatment method, the same method as the surface treatment of the substrate can be given.
In the FET of the present invention, the number of insulating portions may be one, or two or more portions as long as the scope of the invention is satisfied. When it is layered, it may be one layer or may be composed of two or more layers.

As in the case where the substrate is subjected to the surface treatment, the insulating portion may be subjected to the surface treatment to improve the FET characteristics. As the surface treatment method, the same surface treatment as that of the substrate can be used.
For the purpose of increasing the effect of the FET of the present invention, the temperature of the usage environment of the FET may be kept lower or higher than room temperature as necessary. In particular, for the purpose of reducing carrier scattering due to lattice vibration, it is preferable to keep the temperature lower than room temperature.

Here, the GMR effect will be described.
When a voltage (gate voltage) is applied to the insulating portion of the FET of the present invention, carriers (electrons and / or holes) are induced inside the channel. When a voltage is applied between the source electrode and the drain electrode, induced carriers flow through the channel.
In general, carriers are affected by spin scattering due to a magnetic dipole moment. The carriers once subjected to spin scattering maintain their scattering history within the mean free path. If, while maintaining the history of scattering, then interacting with a magnetic dipole moment in the same direction as the magnetic dipole moment initially subjected to scattering, spin scattering is reduced. Therefore, the electrical resistivity of the part where carriers flow, such as metal and semiconductor, decreases. Here, when the inner product of the magnetic dipole moment contributing to the first scattering and the magnetic dipole moment contributing to the next scattering is the maximum (when the directions of the magnetic dipole moments are aligned with each other), the effect of spin scattering Decreases. This is realized by aligning the directions of the magnetic dipole moments in a material in which both a ferromagnetic material and a non-magnetic material exist. This effect is known as the Giant Magneto-Resistance (GMR) effect, and is described in Solid State Physics, 38 (9), 612 (2004), Annual Review of Materials Science, 25, 357 (1995), and the like.

In the FET of the present invention, a coexisting material is used for the insulating portion. In the coexisting material, the direction of the electric dipole moment is controlled at the same time as the direction of the electric dipole moment by an external field such as an electric field. Therefore, when a gate voltage is applied to the insulating portion, the electric dipole moments of the coexisting materials are aligned, and the directions of the magnetic dipole moments are aligned. On the other hand, carriers are induced in a portion of the semiconductor portion in contact with the insulating portion to form a channel. Carriers that flow in the channel (becomes carriers of output current (drain current)) are realized by an insulating part.
It is affected by spin scattering due to the presence of both ferromagnetic and non-magnetic materials. This is because a coexisting material that is also a ferromagnetic material is used. At this time, since the directions of the magnetic dipole moments of the coexisting materials are aligned with each other when the gate voltage is applied, the effect of carrier spin scattering is reduced. As a result, the mobility of the carrier increases.

The content of the coexisting material with respect to the insulating part is preferably 1% by volume or more, more preferably 10%.
Volume% or more. Moreover, Preferably it is 80 volume% or less, More preferably, it is 40 volume% or less. This is because if the distance is too small, the distance of carrier movement between spin scattering increases, and information on spin scattering cannot be maintained during movement. On the other hand, if it is too large, a continuous path between the coexisting material particles is formed, and the GMR effect is not exhibited. The content of the nonmagnetic substance with respect to the insulator part is preferably 100- (content of the coexisting substance with respect to the insulating part) (volume%). This is because the insulating portion other than the coexisting material is preferably made of a nonmagnetic material. The content of the coexisting material and the nonmagnetic material is determined by image processing of a TEM image. That is, the volume fraction is defined by raising the average area fraction in the TEM image of the part to the 3/2 power.

[7. Others]
In addition to the members described above, other members may be provided in the FET of the present invention.
For example, other layers can be provided between the respective portions of the FET (source electrode, drain electrode, semiconductor portion, ferromagnetic portion, gate electrode, and insulating portion) or on the outer surface of the FET as necessary. As an example of another layer, when a protective layer is formed on the semiconductor portion directly or via another layer, there is an advantage that the influence of outside air such as humidity can be minimized. In addition, there is an advantage that the electrical characteristics can be stabilized, for example, the on / off ratio of the FET is improved by the protective layer.

  The material of the protective layer is not particularly limited, and any material can be used depending on the purpose. For example, epoxy resin, acrylic resin such as polymethyl methacrylate, polyurethane, polyimide, polyvinyl alcohol, fluororesin, polyolefin, etc. Preferable examples include various resins, dielectric materials such as an inorganic oxide film and a nitride film, and the like, such as silicon oxide, aluminum oxide, and silicon nitride. Among these, it is particularly preferable to use a resin (polymer) having low oxygen and moisture permeability and water absorption.

  There is no limitation on the method for forming the protective layer, and various known methods can be arbitrarily used. However, when the protective layer is made of a resin, for example, a method in which a resin solution is applied and dried to form a resin film, a resin monomer is used. Examples thereof include a method of polymerizing after coating or vapor deposition. Further, post-treatment may be performed as appropriate after film formation. For example, cross-linking treatment may be performed after film formation. For example, when the protective layer is made of an inorganic material, for example, a formation method in a vacuum process such as a sputtering method or a vapor deposition method, or a formation method in a solution process typified by a sol-gel method can be used.

In addition, a wiring is usually connected to the source electrode, the drain electrode, and the gate electrode. The material of the wiring is arbitrary, but is usually made of substantially the same material as the source electrode, drain electrode, and gate electrode.
Furthermore, some materials that make up FETs, especially semiconductor materials used in the semiconductor part, generate charges by absorbing light. It is preferable to shield light (for example, a transistor portion). This is realized, for example, by forming a pattern with a low light transmittance (a so-called black matrix) in a desired region. For this pattern, a metal film such as chromium, aluminum, silver or gold, a resin film in which a pigment such as carbon black is dispersed, an organic dye film or the like is usually used.

Furthermore, the on / off ratio of the FET of the present invention is arbitrary. However, it is usually better as it is higher. Specifically, the on / off ratio is usually 800 or more, preferably 1000 or more. here,
The definition of the on / off ratio will be described. Drain voltage V _D (the voltage of the drain electrode to the source electrode) is fixed to -30 V, the gate voltage V _G, if the semiconductor layer is a p-type semiconductor,
Currents I _D (-50V) and I _D (+ 30V) flowing between the source and drain at -50V and + 30V are measured, and the on / off ratio is determined by these I _D (-50V) / I _D (+ 30V). Define. On the other hand, in the case of an n-type semiconductor, I _D (+50 V) and I _D (−30 V) are measured, and the on / off ratio is defined by I _D (+50 V) / I _D (−30 V).

[II. Horizontal FET]
Hereinafter, as an embodiment of the present invention, a case where the present invention is applied to a lateral FET which is an example of an FET will be described as an example and described in detail with reference to the drawings.
FIG. 1 is a longitudinal sectional view showing a main part of a lateral FET according to an embodiment of the present invention. In the lateral FET 10, a source electrode 12 and a drain electrode 13 are formed on a substrate 11 made of an insulator. Further, a semiconductor layer 15 is formed thereon as a semiconductor portion made of a semiconductor material, and an insulating layer 16 as an insulating portion is further formed thereon.
A gate electrode 17 is provided on the insulating layer 16, and a current flowing between the source electrode 12 and the drain electrode 13 is controlled by a gate voltage (input voltage) applied from the gate electrode 17. However, the gate electrode 17 is insulated from the semiconductor layer 15 by the insulating layer 16. In FIG. 1, wirings connected to the source electrode 12, the drain electrode 13, and the gate electrode 17 are not shown.

The insulating layer contains a coexisting material and a nonmagnetic material.
When a gate electrode is applied to the gate electrode 17 with this configuration, carriers are induced in the semiconductor layer 15 between the source electrode 12 and the drain electrode 13. That is, a channel is formed. At the same time, the directions of the magnetic moments of the coexisting substances in the insulating layer are aligned, and the mobility of carriers in the channel is increased. In the lateral FET, the channel thickness is usually about 5 nm to 50 nm.

The aspect of each component of the lateral FET is not limited to the configuration of the lateral FET 10 described above, and may be modified as described in the description of the outline of the FET of the present invention.
Furthermore, the configuration of the lateral FET is not limited to that described in the above embodiment, and the arrangement of each part can be arbitrarily set.
For example, as shown in FIG. 2A, a lateral FET 10 </ b> A may be configured in which a gate electrode 17 insulating layer 16, a source electrode 12 and a drain electrode 13, and a semiconductor layer 15 are arranged in this order on a substrate 11. In FIG. 2A, the same reference numerals as those in FIG. 1 denote the same parts.

Further, for example, a lateral FET is formed on the substrate 11 as shown in FIG.
7, the insulating layer 16, the semiconductor layer 15, and the lateral FET 10 </ b> B in which the source electrode 12 and the drain electrode 13 are arranged in this order. In FIG. 2B, the same reference numerals as those in FIGS. 1 and 2A denote the same parts.
Further, for example, the lateral FET may be configured as a lateral FET 10C in which a semiconductor layer 15, a source electrode 12 and a drain electrode 13, a coexisting insulating layer 16 and a gate electrode 17 are arranged in this order as shown in FIG. . In FIG. 2C, the same reference numerals as those in FIGS. 1, 2A, and 2B denote the same parts.
Further, in the configuration of each lateral FET described above, another member or layer may be provided.

[III. Static induction transistor]
Further, as another embodiment of the FET of the present invention, for example, an electrostatic induction transistor (SIT) can be cited. Hereinafter, this SIT will be described with reference to FIG.
In the lateral FETs 10, 10A to 10C, the source electrode 12 and the drain electrode 13 are the substrate 1
In the SIT, the gate electrode 17 is arranged at an appropriate position between the source electrode 12 and the drain electrode 13, while the current flow direction is perpendicular to the electric field induced by the gate electrode 17. Are arranged in a grid and the direction of the current is parallel to the electric field induced by the gate electrode 17 {see arrows in FIGS. 3A and 3B}.

    FIG. 3A is a cross-sectional view showing the main part of the SIT as one embodiment of the present invention. As shown in FIG. 3A, in SIT 20A, a source electrode 22, a semiconductor layer 23 as a semiconductor portion made of an organic semiconductor material, and a drain electrode 24 are laminated on a substrate 21 made of an insulator. . In addition, a plurality of gate electrodes 26 insulated from the semiconductor layer 23 are provided between the source electrode 22 and the drain electrode 24 in the semiconductor layer 23 by covering the entire peripheral surface with an insulating layer 25 as an insulating portion. It has been.

  In the SIT 20A having such a configuration, carriers are induced in the semiconductor layer when a gate breakdown voltage is applied. Since a voltage (source-drain voltage) is also applied between the source electrode and the drain electrode, the portion of the semiconductor layer 23 is moved from the source electrode 22 to the drain electrode 24 by the electric field generated by the source-drain voltage. Carriers move and current flows (indicated by arrows). At the same time, the magnetic moments of the coexisting substances contained in the insulating portion are aligned, and the electrical resistivity of the semiconductor layer is lowered.

In addition, the configuration of each component of the SIT is not limited to the configuration of the SIT 20A, and may be modified as described in the description of the outline of the FET of the present invention.
Further, as shown in FIG. 3B, the SIT 20 </ b> B may be provided so that the drain electrode 24 is closer to the substrate 21 than the source electrode 22. In FIG. 3B, the same reference numerals as those in FIG. 3A denote the same parts.

  In the SITs 20A and 20B, in order to allow current to flow between the gate electrodes 26 from the source electrode 22 to the drain electrode 24, the shape of the gate electrode 26 is a mesh shape, a stripe shape, a lattice shape, or the like. Thus, it is desirable to have a shape having a predetermined interval. At this time, the size of the gap between the gate electrodes 26 is arbitrary, but is usually preferably smaller than the distance between the source electrode 22 and the drain electrode 24 (corresponding to the thickness of the semiconductor layer 23 here). .

  In addition, the thickness of the gate electrode (that is, the size in the source-drain direction) is preferably large in a range thinner than the thickness of the semiconductor layer. This is because, in the interface between the insulator layer and the semiconductor layer, the projected component in the source-drain direction is increased, and the effect of increasing the mobility due to the uniform magnetic moment of the coexisting material is increased. The thickness of the gate electrode is usually 1/100 or more, preferably 1/10 or more, more preferably 1/2 or more, and most preferably 9/10 or more of the thickness of the semiconductor layer. Moreover, it is usually 99/100 or less.

  By the way, the channels of the SITs 20A and 20B as described above can have a larger cross-sectional area than the lateral FETs 10 and 10A to 10C. Here, the cross-sectional area of the channel is the total sum of the cross-sectional areas by a plane perpendicular to the source-drain direction of the channel region. Therefore, by adopting the SIT structure, a large number of carriers can be moved from the source electrode 22 to the drain electrode 24 or from the drain electrode 24 to the source electrode 22 at a time.

In SIT 20A and 20B, since the source electrode 22 and the drain electrode 24 are arranged vertically, the distance between the source electrode 22 and the drain electrode 24 can be reduced, and the response can be speeded up.
Accordingly, the SITs 20A and 20B are preferably applied to applications in which a large current flows or high-speed switching is performed.

Further, in the configuration of each SIT described above, different members and layers may be provided.
As mentioned above, although embodiment of this invention was described, this invention is not limited to the above embodiment, As mentioned above, in the range which does not deviate from the summary of this invention, it deform | transforms arbitrarily and can implement. it can.
For example, you may implement combining each structure mentioned above.

  Further, for example, the configuration of the present invention may be applied to an arbitrary FET other than a lateral FET or SIT.

  The FET of the present invention can be used, for example, in a wide industrial field using an electronic device. Specific examples include an active matrix of a display such as a liquid crystal display element, a polymer dispersed liquid crystal display element, electronic paper, an organic LED display element, an electrophoretic display element, an inorganic EL display element, and an electrochromic element. It can also be used for IC tags, IC chips, sensors and the like.

It is a longitudinal cross-sectional view which shows the principal part of lateral type FET which concerns on one Embodiment of this invention. (A)-(c) is a longitudinal cross-sectional view which shows the principal part of lateral type FET which concerns on one Embodiment of this invention. (A), (b) is a longitudinal cross-sectional view which shows the principal part of SIT which concerns on one Embodiment of this invention.

Explanation of symbols

10, 10A, 10B, 10C Horizontal FET
11, 21 Substrate 12, 22 Source electrode 13, 24 Drain electrode 15, 23 Semiconductor layer (semiconductor part)
16, 25 Insulating layer (insulating part)
17, 26 Gate electrodes 20A, 20B SIT

Claims (2)

At least the semiconductor part,
A field effect transistor comprising an insulating part,
The semiconductor material forming the semiconductor part is organic, and
A field effect transistor characterized in that the insulating portion contains a substance having both ferroelectricity and ferromagnetism and a nonmagnetic substance. At least the semiconductor part,
A method of manufacturing a field effect transistor comprising an insulating portion containing a substance having both ferroelectricity and ferromagnetism and a nonmagnetic substance,
The semiconductor material forming the semiconductor part is organic or inorganic, and
A method of manufacturing a field effect transistor, comprising a step of forming a semiconductor part by a solution process.

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