JP4521546B2 - Semiconductor integrated circuit device - Google Patents

Description

【数２】

(1)式で、左辺はクロックf0時のデータ数、右辺はクロックをf1に下げた場合に一スロットで処理できるデータ数を示す。式(2)は電圧の遷移にかかる時間Ttransとデータ無効期間tiの関係を示している。また、何スロットで周波数を変化させてよいかという条件Ntは、電力制約で決定される。電力制約は、各周波数における回路機能モジュールの動作電力Pf0、Pf1、電圧遷移にともなう電力Ptransと遷移時間Ttransから次式のように求められる。
【００４７】
【数３】

ここで、動作電力は待機時電力よりも充分大きいと仮定している。したがって、式(1)、(2)の条件がNt回おこった場合に周波数を下げて低電力動作に遷移する。電源遮断を行う条件は、電力制約とタイミング制約から考える。電力制約条件は、最低電源電圧における回路機能モジュールのリーク電力をPleakとした場合に次のようになる。
【００４８】
【数４】

【数５】

式(4)から求められた条件よりもデータ無効期間が長ければ式(5)を満たし、電源遮断を行う。このようにして、記憶テーブル回路は回路機能モジュールの消費電力を削減していく。データ量が増加して一スロット内で処理できなくなった場合には、データをバッファに蓄えつつクロックを最大周波数（f0）に戻し、再度同じ学習を繰り返す。図16において、式(1)、(2)の関係が満たされる場合、比較回路CMP161およびCMP162の出力、つまりアンド回路出力がダウン信号dwn161を出力する。この場合、記憶テーブル回路の出力である制御信号により、回路機能モジュールに供給される周波数および電圧条件を一段下げ、動作速度を下げるとともに消費電力を低下する。周波数最小になってもデータ無効期間が長いと式(5)が満たされて、シャットダウン信号sdwn161が出力され、回路機能モジュールは電源遮断となる。また、あるタイムスロットtmslot160でデータを処理しきれなくなり、データ無効信号flinv160の前に、次のタイムスロットtmslot161用データが到着してデータ有効信号flval161が発生してしまった場合には、error信号が出力され、周波数および電圧条件は最高速度性能の条件に戻る。
【００４９】
回路機能モジュールがある性能で動作している間に、データ量が増えてタイムスロット内で処理しきれなくなる場合、図１６のerr161信号が出力される。この時、処理しきれなかったデータについては、回路機能モジュールのデータ入力バッファに格納しておいたり、処理ミスとして一度データを捨ててあらためてデータを要求しなおすなどの対処をする。また、err161信号が出力された後の電源電圧、基板バイアス、クロック周波数の設定については、最高性能を与える設定に戻ってもよいし、現状より一つ上の性能設定に戻してもよい。
以上のようにして、本発明の記憶テーブル回路は、回路機能モジュールに与えられるデータ量を計測し学習することによって、回路機能モジュールが最適な性能を発揮できるように制御信号を生成する。
【００５０】
図18は、本発明の他の実施例を示す図である。
本発明は、回路機能モジュールCFM181、CFM182、クロック周波数制御回路CFC181、CFC182、電源電圧制御回路SVC181、SVC182、基板バイアス制御回路BBC181、BBC182、記憶テーブル回路MTC181、MTC182、バッファ回路BUF181、BUF182、バスBUS181、外部入力EXT181、性能測定回路PMC181、バス制御回路BSC181から構成される。回路機能モジュールCFM181はクロック周波数clk181、電源電圧vdd181、基板バイアスvbp181、vbn181を入力し、バッファ回路BUF181を介してデータ信号の入出力を行う。回路機能モジュールCFM182はクロック周波数clk182、電源電圧vdd182、基板バイアスvbp182、vbn182を入力し、バッファ回路BUF182を介してデータ信号の入出力を行う。クロック周波数制御回路CFC181、CFC182はそれぞれ、入力クロック信号clkin181を入力してクロック信号clk181、clk182を出力する。電源電圧制御回路SVC181、SVC182はそれぞれ、入力電圧vddin181を入力して電源電圧vdd181、vdd182を出力する。基板バイアス制御回路BBC181、BBC182はそれぞれ、入力電圧vddin181を入力して基板バイアスvbp181、vbn181およびvbp182、vbn182を出力する。記憶テーブル回路MTC181は、制御信号sig182を入力して、クロック周波数制御回路CFC181、電源電圧制御回路SVC181、基板バイアス制御回路BBC181を制御する。記憶テーブル回路MTC182は、制御信号sig183を入力して、クロック周波数制御回路CFC182、電源電圧制御回路SVC182、基板バイアス制御回路BBC182を制御する。バッファ回路BUF181、BUF182はそれぞれ、回路機能モジュールCFM181、CFM182とバスBUS181とのデータ入出力を中継し、データの保存を行う。バス回路BUS181は、外部入力EXT181、性能測定回路PMC181、バス制御回路BSC181、記憶テーブル回路MTC181、MTC182、バッファ回路BUF181、BUF182との間のデータ授受を中継する。
【００５１】
本発明に示されているように、回路機能モジュールが複数存在する場合のシステム構成は以下のようになる。各回路機能モジュールに対し、クロック周波数制御回路、電源電圧制御回路、基板バイアス制御回路、記憶テーブル回路、およびバッファ回路が各1つづつ配置される。バス配線、外部入力、性能測定回路、バス制御回路は、チップあるいはシステム1つにつき1セット配置される。また、入力電源と入力クロック信号は電圧値および周波数が一定の一種類の信号をチップに供給し、チップ内部で電圧や周波数を変換している。以上の構成により、チップ内の回路機能モジュール設計や、チップ全体のレイアウト設計が容易になり、設計期間の短縮や信頼性の向上をもたらす。また、各回路機能モジュール毎に最適なクロック周波数、電源電圧、基板バイアス制御を行うことで、チップ全体も最適化される。BSC181は、バスBUS181にどの回路機能モジュールなどモジュールからのデータをバス外部入力EXT181は、OS、アプリケーションソフトウェア、ミドルウェアなどが供給される。バス制御回路BSC181は、バスBUS181にどの回路機能モジュールにデータ信号入出力を許可するかを決定する。リクエスト信号req181を受け取ると、最適な条件となるようにアクノレッジ信号ack181を出力する。回路機能モジュール間のデータのやりとりについては、同期式、非同期式、データフロー式など、どのような方式でもよい。回路機能モジュール間の結合を実現するアーキテクチャに依存することなく、性能最適化、低電力化を果たすことができる。
【００５２】
図19は、チップテスト時のフローチャートを示す図である。
19Aでチップテストを開始する。19Bで、性能測定回路が測定する回路機能モジュールを選択する。19Cでは選択された回路機能モジュールにおいて、電源電圧制御回路および基板バイアス制御回路が回路機能モジュールの動作速度を最高にするような制御を行うよう、記憶テーブル回路が信号を出力する。19Dで、性能測定回路が測定する電圧種類（電源電圧、基板バイアス、など）を選択する。19Eにおいて電圧レベルが正しいかを判定し、正しくなければ19Fでその結果をログとして記憶し、19Dにもどる。19Eで電圧レベルが正しいと、19Gで電圧の遷移時間を計測する。19Hでは電圧種類の選択が全て終わっているかを判定し、まだ測定していない電圧種があれば19Dに戻る。全ての電圧種について測定が終われば、19Tにおいて最大遷移時間データを記憶テーブル回路に送る。19Cから19Tまでの作業は、アナログテストABST191作業になる。続いて、19Jにおいて、既に選ばれている回路機能モジュールにテストデータ（テストベクタ）を供給する。19Kで、出力データを検出し、回路機能モジュールのDC的な回路動作が正しいかどうかを判定する。動作が誤っていれば、19Lにおいてログを記憶し、19Jにもどる。19Kにおいて回路動作が正しい場合は、19Mですべてのテストベクタを終了したか判定する。終了していなければ19Jにもどり、終了していれば19Nへ進む。19Jから19Mまでの作業は、機能テストFBST191作業となる。19Nにおいては、電源電圧、基板バイアスの制御組合せを選択する。19Vでは、選択された制御組合せにおいて、回路機能モジュールの動作速度、すなわち遅延時間測定する。19Pで、測定結果データ信号を該当する回路機能モジュールの記憶テーブル回路に与える。
19Qで、制御組合せが全て終了したかを判定し、終了していれば19Rへ進み、終了していなければ19Nに戻る。19Nから19Qまでの作業は、タイミングテストTBST191作業となる。19Rにおいて、全ての回路機能モジュール選択が終了したかを判定。終了していなければ19Cにもどり、終了していれば19Sに進む。19Sにおいて、チップテストフローは終了する。
【００５３】
図20は、図19と同様チップテスト時のフローチャートを示す図である。図19との違いは、図20では回路機能モジュールにおける消費電力の測定を含んでいる点である。図19では、回路機能モジュールが消費する電力は、制御組合せに応じて既知であるとして、データ処理速度、すなわち遅延時間の測定のみを行う場合のフローチャートになっている。消費電力も未知である場合は、図20に従って測定する必要がある。図19との違いは、フローの20V、20Pにあたる箇所で、遅延時間を測定する際に消費電力も測定し、記憶テーブル回路に送る情報は遅延時間と消費電力の両方になっている。
【００５４】
図21は、バス制御回路の実施例を示す図である。
本発明は、インクリメントデクリメント回路INCDEC211、カウンタ回路CNT211、CN212、CNT213、CNT214、比較回路CMP211、セレクタ回路SEL211、エンコード回路ENC211、デコード回路DEC211から構成される。インクリメントデクリメント回路INCDEC211は、エンコーダ回路ENC211からの信号を入力して、カウンタのインクリメントまたはデクリメントを行う信号を出力する。カウンタ回路CNT211、CNT212、CNT213、CNT214はインクリメントデクリメント回路INCDEC211からの信号に応じてカウント値を変化させ、カウント値を比較回路CMP211に与える。デコード回路DEC211はリクエスト信号req211をデコードしてセレクタ回路SEL211を制御する。セレクタ回路SEL211は比較回路CMP211の出力をデコード回路211からの制御信号に応じてエンコード回路ENC211に伝え、エンコード回路はインクリメントデクリメント回路INCDEC211を制御する信号とアクノレッジ信号ack211を出力する。バス制御回路は、回路機能モジュールからリクエスト信号が届くと、アクノレッジ信号を返して、回路機能モジュールがバス上のデータとのやりとり（入出力）を行う権限を与える。リクエスト信号が同時に届いた場合、あるいは別の回路機能モジュールがバスを使用している最中にリクエスト信号が届いた場合に、回路機能モジュール間の優先度を調整する働きを行う。具体的には、バスの使用率が低い回路機能モジュールに優先度高くバスを使用させるようにする。全ての回路機能モジュールに該当するカウンタ回路をバス制御回路が所有し、ある回路機能モジュールからリクエスト信号req211が届くと、バス制御回路はその信号をデコード回路DEC211でデコードする。この時、該当する回路機能モジュールのカウント数が比較対象となる回路機能モジュールのカウント数よりも小さければ、エンコーダ回路ENC211を介してアクノレッジ信号ack211を戻し、該当する回路機能モジュールのバス使用を許可する。アクノレッジ信号を出した場合には、インクリメントデクリメント回路INCDEC211を用いて、各回路機能モジュールのカウント数を変化させる。アクノレッジ信号を出した回路機能モジュールについてはカウント数を１つインクリメントし、その他のモジュールは全てカウント数を１つデクリメントする。このようにして、回路機能モジュール同士のバス使用率を均一化する。
【００５５】
このようにバス制御回路を用いることで、図18における各回路機能モジュールが自律分散的に動作できるようになり、それにともなう本発明の低電力高性能化技術を有効に利用できる。
図22は、バス制御回路の他の実施例を示す図である。
【００５６】
本発明は、アドレスレジスタ回路ADR221、ADR222、ADR223、ADR224、ADR225を含むシフトレジスタ回路SRG221、セレクタ回路SEL221、デコーダ回路DEC221、エンコーダ回路ENC221から構成される。デコーダ回路DEC221はリクエスト信号req221をデコードしてセレクタ回路SEL221に伝える。セレクタ回路SEL221はデコーダ回路DEC221からの制御信号に応じてアドレスレジスタを選択する。エンコーダ回路ENC221は選択されたアドレスレジスタの信号をエンコードしてアック信号ack221として出力するとともに、シフトレジスタ回路SRG221内のアドレスレジスタを制御する。シフトレジスタ回路SRG221内のアドレスレジスタ回路は、チップ内の各回路機能モジュールに相当する。各アドレスレジスタの位置は、回路機能モジュールがバスを使用する頻度を示し、あまり使用頻度が高くない回路機能モジュールに対応するアドレスレジスタほど、図の上位置に配置される。リクエスト信号に応じてアクノレッジ信号ack221が出力されると、エンコーダ回路ENC221からの制御信号により、該当回路機能モジュールに対応する。
アドレスレジスタは、シフトレジスタ回路SRG221内で一番下位置に配置される。それ以外のアドレスレジスタは一段づつ上位に上がる。セレクタ回路は、リクエスト信号req221を受け取った時点でバスを使用予定の回路機能モジュールが複数ある場合、それらに対応するアドレスレジスタのうち一番上位置にあるレジスタに対応する、回路機能モジュールに対してアクノレッジ信号を出力する。この回路の場合も、図21と同様に回路機能モジュール同心のバス使用率を平均化する。
【００５７】
以上説明したように、本実施例によると次の効果がある。すなわち、高速かつ低消費電力で動作することが可能な半導体集積回路装置において、以下に示す課題を実現するCMOS回路及びそれで構成されたCMOS LSIチップならびに半導体集積回路装置を提供できる。すなわち、CMOS回路を構成するMOSトランジスタのクロック周波数、電源電圧、基板バイアスを自律分散的に、かつ自己学習的に制御するための性能測定回路と記憶テーブル回路を備えた構造を使用することで、以下の課題を解決する。
（１）マイクロプロセッサ等のCMOS回路で構成される半導体集積回路のチップ内回路規模や種類が複雑多岐にわたる場合でも、各回路モジュールは低電力高速化制御技術を意識せずに設計することが可能で、設計時間の短縮と信頼性向上が可能となる。
（２）マイクロプロセッサ等のチップにおいて既存の回路モジュールを利用する際やマルチプロセッサ化を行う際にも、低電力高速化制御技術を意識せずに使用して設計することが可能となり、設計時間の短縮と信頼性向上をもたらす。
（３）ASICのように回路モジュールを多様に組合せる場合でも、同様に低電力高速化制御技術を意識せずに設計可能で、設計時間短縮と信頼性向上を可能とする。
（４）低電力高速化制御技術を実現するために、あらかじめ各回路モジュールの性能を測定しておくため、チップテストの期間短縮を可能とする。
（５）チップ内の回路モジュール毎に最適なクロック周波数、電源電圧、基板バイアスの供給を可能とすることにより、プロセッサ等の動作において、「動作速度/消費電力性能」を最大にする。
【００５８】
【発明の効果】
以上のように、本発明によれば、CMOS回路を用いた半導体集積回路装置の設計の簡易化、テスト時間の短縮および低電力化が可能となる。
【図面の簡単な説明】
【図１】本発明の実施例の構成図。
【図２】クロック周波数制御回路の実施例の構成図。
【図３】クロック周波数制御回路の他の実施例の構成図。
【図４】電源電圧制御回路もしくは基板バイアス制御回路の実施例の構成図。
【図５】電源電圧制御回路もしくは基板バイアス制御回路の他の実施例の構成図。
【図６】本発明の性能測定回路の実施例の構成図。
【図７】性能測定回路の動作波形図。
【図８】本発明の性能測定回路の他の実施例の構成図。
【図９】本発明の性能測定回路の他の実施例の構成図。
【図１０】本発明の記憶テーブル回路のテーブル表の実施例。
【図１１】本発明の記憶テーブル回路のテーブル表の他の実施例。
【図１２】本発明の性能測定回路の他の実施例の構成図。
【図１３】本発明の性能測定回路の他の実施例の構成図。
【図１４】本発明の性能測定回路の他の実施例の構成図。
【図１５】本発明の性能測定回路の他の実施例の構成図。
【図１６】本発明の記憶テーブル回路の実施例の構成図。
【図１７】タイムスロットの概念を示す波形図。
【図１８】本発明の他の実施例の構成図。
【図１９】チップテスト時のフローチャート。
【図２０】チップテスト時の他のフローチャート。
【図２１】バス制御回路の実施例の構成図。
【図２２】バス制御回路の他の実施例の構成図。
【符号の説明】
ABST191，ABST201・・・アナログテスト、
ADC81，ADC91，ADC151・・・アナログデジタル変換回路、
ADR221，ADR222，ADR223，ADR224，ADR225・・・アドレスレジスタ回路、
AMP41，AMP91・・・増幅回路、
AND61，AND151・・・アンド回路、
ARB161・・・アービタ回路、
BBC11，BBC181，BBC182・・・基板バイアス制御回路、
BUF181，BUF182・・・バッファ回路、
BUS181バス、
BSC181・・・バス制御回路、
CAP31，CAP51・・・容量、
CFC11，CFC181，CFC182・・・クロック周波数制御回路、
CFM11，CFM61，CFM81，CFM91，CFM121，CFM131，CFM181，CFM182・・・回路機能モジュール、
CMP131，CMP151，CMP152，CMP161，CMP162，CMP211・・・比較回路、
CNT61，CNT151，CNT161，CNT162，CNT163，CNT211，CNT212，CNT213，CNT214・・・カウンタ回路、
DEC211，DEC221・・・デコード回路、
DFF21，DFF121，DFF151・・・D型フリップフロップ回路、
DID51，DID52・・・ダイオード、
DIV31・・・分周回路、
ENC211，ENC221・・・エンコード回路、
EXT181・・・外部入力、
FBST191，FBST201・・・機能テスト、
INCDEC211・・・インクリメントデクリメント回路、
INVAND61，INVAND151・・・インバータアンド回路、
LOG121・・・論理回路、
MTC11，MTC181，MTC182・・・記憶テーブル回路、
NMS31，NMS81・・・NMOSトランジスタ、
PFD31・・・位相周波数検出回路、
PMC11，PMC61，PMC81，PMC91，PMC121，PMC131，PMC141，PMC181・・・性能測定回路、
PMS31，PMS41・・・PMOSトランジスタ、
REG61，REG151，REG161，REG162・・・レジスタ回路、
RES31，RES91，RES92・・・抵抗、
ROS51・・・リング発振回路、
SEL21，SEL121，SEL151，SEL152，SEL211，SEL221・・・セレクタ回路、
SEN51・・・センサ回路、
SRG151，SRG221・・・シフトレジスタ回路、
SVC11，SVC181，SVC182・・・電源電圧制御回路、
TBST191，TBST201・・・タイミングテスト、
VCO31・・・電圧制御発振回路、
VRF41・・・参照電圧発生回路、
19A，19B，19C，19D，19E，19F，19G，19H，19J，19K，19L，19M，19N，19P，19Q，19R，19S，19T，19V，20A，20B，20C，20D，20E，20F，20G，20H，20J，20K，20L，20M，20N，20P，20Q，20R，20S，20T，20V・・・プロセス、
ack181，ack211，ack221・・・アクノレッジ信号、
bstin121，bstin131，bstin141，bstin151・・・テスト入力信号、
bstout121，bstout131，bstout141，bstout151，bstout152・・・テスト出力信号、
clk11，clk161，clk162，clk171，clk181，clk182・・・クロック信号、
clkin21，clkin181・・・入力クロック信号、
cmb101，cmb102，cmb103，cmb104，cmb105，cmb106，cmb111，cmb112，cmb113，cmb114，cmb115，cmb116・・・制御組合せ、
cntclk61，cntclk151，cntclk152・・・制御クロック信号、
dat181，dat182，dat183・・・データ信号、
datin61，datin121，datin122，datin123，datin124，datin125，datin161・・・データ入力信号、
datout61，datout121，datout122，datout123，datout124，datout125・・・データ出力信号、
dwn161・・・ダウン信号、
err161・・・エラー信号、
flag161・・・データフラグ信号、
flval160，flval161，flval162・・・データ有効信号、
flinv160，flinv161，flinv162・・・データ無効信号、
gnd31，gnd81・・・グランド電圧、
mescmd11，mescmd12・・・測定命令信号、
mesres11，mesres131・・・測定結果信号、
opcnt11，opcnt12，opcnt13・・・動作制御信号、
pfdat11・・・性能データ信号、
pwr101，pwr111・・・消費電力、
req61，req151，req181，req211，req221・・・リクエスト信号、
scnin121・・・スキャン入力信号、
scnout121・・・スキャン出力信号、
sdwn161・・・シャットダウン信号、
selcnt121，selcnt122・・・セレクタ回路制御信号、
sig21，sig22，sig23，sig24，sig25，sig31，sig32，sig41，sig51，sig61，sig62，sig63，sig81，sig91，sig92，sig131，sig151，sig152，sig153，sig154，sig155，sig156，sig181，sig182，sig183・・・制御信号、
t0，t1，t2，t3，t00，t01，t02，t03，t04，t05，t06・・・時間、
tim161・・・期間信号、
tmslot160，tmslot161，tmslot162・・・タイムスロット、
tpd101，tpd111・・・遅延時間、
vbn11，vbn181，vbn182・・・NMOSトランジスタ用基板バイアス、
vbp11，vbp181，vbp182・・・PMOSトランジスタ用基板バイアス、
vdd11，vdd91，vdd181，vdd182・・・電源電圧、
vddin31，vddin151，vddin181・・・入力電圧、
vmes151・・・被測定電圧、
vref81，vref91・・・参照電圧。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit device that simultaneously realizes high speed and low power consumption.
[0002]
[Prior art]
Semiconductor integrated circuit devices using CMOS circuits such as system LSIs have continued to increase in degree of integration and performance as devices such as MOS transistors are miniaturized and scaled. However, in recent years its growth has been slowing down. This is because the miniaturization is approaching the limit, and the sub-threshold leakage current, gate tunnel leakage current, junction leakage current, etc. of MOS transistors that have not been regarded as problems so far influence the power consumption of the chip. This is partly due to the fact that it has increased, or that there is a limit to the architectural method of increasing the number of pipeline stages and reducing the number of logic stages per stage. In particular, due to power consumption constraints, it will be difficult to achieve performance improvements that are in line with current trends. Further, as the degree of integration increases, the influence of wiring delay becomes enormous, and the design of a synchronous system becomes difficult. In the future, in order to further improve the performance of LSIs, not only devices and circuits but also architectures are required. As one solution, as described in Non-Patent Document 1 or Non-Patent Document 2, there is a system called multiprocessing or grid processing. These have a structure in which a large number of processors are formed on one chip, and are called chip multiprocessors (hereinafter referred to as CMP). In CMP, a normal synchronous system is used in processors, but an asynchronous (handshake) system or a data flow type processing system is adopted between processors. Each processor autonomously performs distributed control, and as a chip, all processors are integrated to efficiently process data. As a form of data processing, it is possible to perform different tasks simultaneously or to distribute the same tasks in parallel and to improve processing performance. CMP's autonomous decentralization not only solves the effects of signal wiring delays in high integration, but can also be expected to significantly reduce design man-hours.
[0003]
Even in an autonomous distributed semiconductor integrated circuit device represented by CMP, reduction in power is an important issue. Thermal countermeasures are also an important issue in CMP with high integration, and without realizing low power, it will be impossible to implement chips or packages. However, simply reducing the power supply voltage to reduce power consumption degrades chip performance, that is, data processing speed. In CMP, each processor or each IP functional module on the chip operates independently, so it is important to maximize the performance / power ratio of each functional module in order to increase the performance / power ratio of the entire chip. is there. As described in Non-Patent Document 3, the processor function module has a power supply voltage and a device (MOS transistor) threshold that minimize power consumption when the required processing performance (clock frequency) is uniquely determined. A combination of values is determined. By using the substrate bias, the threshold value of the device can be dynamically changed even during the operation of the processor. Therefore, by simultaneously controlling the power supply voltage and the substrate bias, it becomes possible to operate the functional module with the minimum power consumption according to the required performance, and the performance / power ratio of the functional module can be maximized. .
[0004]
[Non-Patent Document 1]
“The 34th Annual International Symposium on Proceedings of the 34 ^th Annual International Symposium on Microarchitecture) ”2001, p.40-51
[Non-Patent Document 2]
“2002 International Solid-State Circuits Conference Digest of Technical Papers” 2002, pp.196-197
[Non-Patent Document 3]
“2002 International Solid-State Circuits Conference Digest of Technical Papers” 2002, pp.58-59
[Non-Patent Document 4]
“2001 Symposium on VLSI Circuits Digest of Technical Papers” 2001, p.55-56
[0005]
[Problems to be solved by the invention]
In a semiconductor integrated circuit device using a CMOS circuit, it is possible to effectively improve data processing performance and reduce power consumption by controlling the clock frequency, power supply voltage, and substrate bias as described above. By finely adjusting the clock frequency according to the performance required for the circuit function module, power consumption can be reduced in proportion to the frequency. When the clock frequency is determined, the necessary power supply voltage and the threshold voltage of the MOS transistor constituting the CMOS circuit can be determined. Since the threshold voltage of the MOS transistor can be adjusted by the substrate bias, a plurality of combinations of the power supply voltage and the substrate bias for satisfying the required performance of the circuit function module can be taken. When the power supply voltage is lowered, the power consumption can be lowered in proportion to the square of the voltage. However, the voltage drop results in performance degradation. In order to maintain the performance when the voltage drops, it is necessary to lower the threshold voltage of the MOS transistor using the substrate bias. However, when the threshold voltage is lowered, the subthreshold leakage current of the transistor increases. The subthreshold leakage current increases exponentially as the threshold voltage decreases, and eventually becomes larger than the operating current during circuit operation, thereby increasing power consumption. Accordingly, there is only one combination that minimizes power consumption in the combination of the power supply voltage and the substrate bias that keeps the circuit performance constant. The optimum value of the power supply voltage / substrate bias differs depending on the type, scale, or operating frequency of the circuit function module. It also differs depending on the manufacturing process. Therefore, optimal design of complex low power control technology and many chip tests are required.
[0006]
By the way, as described above, in order to enhance the functions of the semiconductor integrated circuit device, it is necessary to arrange a large number of processors and functional modules on one chip to make a multiprocessor. In a multiprocessor, an increase in circuit scale leads to an increase in design period, an increase in test time, and an increase in redesign cost. In designing / manufacturing semiconductor integrated circuit chips, there are two possible ways to solve these problems. One is the reuse of design assets called IP (Intellectual Property). By reusing design data designed in the past as IP in the functional modules constituting the multiprocessor, the design period can be shortened. The other is the autonomous distributed functioning of multiprocessors. In the conventional centralized control system, the central control module that performs centralized control can be designed and designed only by looking through the entire chip. In this method, a function module cannot be easily added after design. On the other hand, in the distributed control method, each function module can perform its own control. Therefore, a function module that performs centralized control is not necessary, and a function module can be easily added. In addition, by providing each function module with an autonomous function, various functions can be realized simply by adding a similar function module. These IP-designed chips or autonomous decentralized chips are effective in shortening the design period and test time.
[0007]
However, if clock frequency / power supply voltage / substrate bias control is introduced in order to reduce the power consumption of such chips, optimal reuse for each IP, device, and functional module is required. It becomes impossible to shorten the time. Therefore, low power technology that supports IP design and autonomous distributed design is required. For example, a method described in Non-Patent Document 4 can be cited as a method for reducing power in an autonomous distributed manner. This method has a data invalid period measuring circuit and a power switch for shutting off the power, and cuts the power when the invalid period exceeds a certain time to reduce power. Each circuit function module has this function, and distributed control is achieved by measuring the invalid period for each function module. However, this method can only be used to shut off the power supply, and cannot cope with a method of improving the data processing performance / power consumption ratio during operation of the functional module by supplying the optimal clock frequency / power supply voltage / substrate bias. .
[0008]
Therefore, it automatically measures the data processing performance and power consumption of the circuit function module according to each combination of clock frequency / power supply voltage / substrate bias, and automatically measures the amount of data processing required for the circuit function module. , Always supply the optimal clock frequency / power supply voltage / substrate bias to the function module. By supplying the optimum conditions, it is possible to maximize the data processing performance / power consumption ratio of each functional module and improve the performance of the entire chip. In addition, since the power reduction in each functional module is performed autonomously and distributedly, it is possible to design functional modules without considering low power technology, resulting in shortened design time and chip test time. It becomes possible to realize a multiprocessor chip capable of shortening and dealing with variations in chip manufacturing.
[0009]
Therefore, the problems to be solved by the present invention are as follows. That is, in a semiconductor integrated circuit device formed by a functional module using a CMOS circuit, having a performance measurement circuit, a storage table circuit, a clock frequency control circuit, a power supply voltage control circuit, and a substrate bias control circuit, the following problems are solved. Resolve.
(1) In at least one functional module composed of CMOS circuits in a semiconductor integrated circuit device, the power consumption is minimized according to the data processing performance required for the functional module, that is, the performance / consumption of the functional module. It is possible to automatically control at least one of the clock frequency, power supply voltage, and substrate bias supplied to the functional module so that the power ratio is maximized, and the semiconductor integrated circuit device chip has high performance and low power consumption. Realize.
(2) In determining the clock frequency, power supply voltage, and substrate bias to be supplied to the functional module, it becomes possible to automatically perform optimum control according to the chip manufacturing process and usage environment, the amount of data received by the functional module, and the like. .
(3) Since the functional module can be designed and manufactured independently of the low power technology, the design period is shortened and the reliability is improved. Even when there are a plurality of functional modules and an autonomous distributed multiprocessor is formed, the low power technology can be easily adapted to the distributed control method.
(4) By incorporating the performance measurement circuit, the test time can be shortened, and by constantly monitoring the performance, it is possible to cope with performance variations between chips due to variations in the manufacturing process.
[0010]
[Means for Solving the Problems]
The main means presented in the present invention to solve the above problems are as follows.
The present invention includes a circuit function module, a clock frequency control circuit, a power supply voltage control circuit, a substrate bias control circuit, a performance measurement circuit, and a storage table circuit. The clock frequency control circuit receives a control signal from the storage table circuit and supplies a clock signal having a predetermined frequency to the circuit function module. The power supply voltage control circuit receives a control signal from the storage table circuit and supplies a predetermined power supply voltage to the circuit function module. The substrate bias control circuit receives a control signal from the storage table circuit and supplies a predetermined substrate bias to the circuit function module. The performance measurement circuit measures performance such as data processing speed and operation power consumption of the circuit function module, transmits the measurement data to the storage table circuit, and controls the storage table. The storage table circuit stores the performance measurement data of the circuit function module sent from the performance measurement circuit, and is optimal for the performance required for the circuit function module, the amount of data to be processed, or the environmental conditions during operation. The clock frequency, power supply voltage, and substrate bias are determined, and a control signal is transmitted to the clock frequency control circuit, power supply voltage control circuit, and substrate bias control circuit.
[0011]
The means of the present invention will be described in further detail below.
According to another embodiment of the present invention, the performance measuring circuit measures the data processing speed or the maximum operating frequency or the operating power consumption as the performance measurement of the circuit function module, and sends the measurement result to the storage table circuit. The storage table circuit stores the performance data obtained from the performance measurement circuit, and supplies the clock frequency, power supply voltage, and substrate bias that maximize the operation speed / power consumption ratio of the circuit function module according to the required performance. Therefore, a control signal is transmitted to the clock frequency control circuit, the power supply voltage control circuit, and the substrate bias conversion circuit.
[0012]
Further, according to another embodiment of the present invention, the performance measurement circuit performs the performance measurement of the operation speed and power consumption of the circuit function module described above at the time of chip inspection of the semiconductor integrated circuit.
[0013]
Furthermore, according to another embodiment of the present invention, the performance measuring circuit is configured to measure the function speed of the circuit function module and the clock supplied to the circuit function module in addition to the measurement of the operation speed and power consumption of the circuit function module. Includes circuits that measure and evaluate environmental conditions such as frequency, power supply voltage, and substrate bias.
[0014]
Further, according to another embodiment of the present invention, the performance measurement circuit can perform the minimum data processing speed (minimum operation speed) or the maximum data processing of the circuit function module in all combinations capable of supplying the clock frequency, the power supply voltage, and the substrate bias. Time, so-called critical path operating time is measured.
[0015]
Furthermore, according to another embodiment of the present invention, the performance measurement circuit is configured to operate the circuit module in the maximum operating current, the so-called worst current, and the stop time in all combinations capable of supplying the clock frequency, the power supply voltage, and the substrate bias. Measure the maximum leakage current.
[0016]
According to still another embodiment of the present invention, the performance measurement circuit measures and evaluates the frequency of the clock signal supplied to the circuit function module, the voltage level of the power supply voltage, and the voltage level of the substrate bias.
[0017]
Furthermore, according to another embodiment of the present invention, the storage table circuit measures the amount of data processed up to a certain point in time, determines the processing performance after a certain point based on the result, and the circuit Controls the clock frequency control circuit, power supply voltage control circuit, and substrate bias control circuit to maximize the operation speed / power consumption performance of the function module, and supplies the optimal clock signal, power supply voltage, and substrate bias to the circuit function module To do.
[0018]
Further, according to another embodiment of the present invention, the time during which data is continuously given to the circuit function module is set as the activation period, and the storage table circuit measures the data activation period to measure the data amount.
[0019]
Further, according to another embodiment of the present invention, the performance data stored in the storage table circuit is stored in the order in which the measured operation speed of the circuit function module is high or low, or in the order of high or low power consumption.
[0020]
Furthermore, according to another embodiment of the present invention, in a configuration in which a plurality of circuit function modules are arranged in a semiconductor integrated circuit chip, one performance measurement circuit is arranged on the chip, and a storage table circuit, a clock frequency control circuit, a power supply voltage are arranged. The control circuit and the substrate bias control circuit are arranged for each circuit function module.
[0021]
Furthermore, according to another embodiment of the present invention, in a configuration in which a plurality of circuit function modules are arranged in a semiconductor integrated circuit chip, a clock signal having one type of clock frequency and a power signal having one type of voltage are present throughout the chip. Distributed and supplied to each circuit function module. In each circuit function module, the clock frequency control circuit divides or multiplies the clock signal to supply the clock signal to the circuit function module, and the power supply voltage control circuit steps down or boosts the power supply signal. Then, the power supply voltage is supplied to the circuit function module, and the substrate bias control circuit steps down or boosts the power supply signal to supply the substrate bias to the circuit function module. The substrate bias supplies two kinds of voltages: a pMOS transistor bias and an nMOS transistor bias.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of the present invention.
The semiconductor integrated circuit device of the present invention includes a circuit function module CFM11 which is a semiconductor integrated circuit having a function of a microprocessor or the like composed of a CMOS circuit, a performance measuring circuit PMC11, a storage table circuit MTC11, a clock frequency control circuit CFC11, a power supply A voltage control circuit SVC11 and a substrate bias control circuit BBC11 are included. The circuit function module CFM11 receives the clock signal clk11, the power supply voltage vdd11, the PMOS transistor substrate bias vbp11, the NMOS transistor substrate bias vbn11, and the measurement command signal mescmd11, and outputs the measurement result signal mesres11. The performance measurement circuit PMC11 outputs measurement command signals mescmd11 and mescmd12, receives the measurement result signal mesres11, and outputs the result as the performance data signal pfdat11. The storage table circuit MTC11 receives the measurement command signal mescmd12 and the performance data signal pfdat11, and outputs operation control signals opcnt11, opcnt12, and opcnt13. The clock frequency control circuit CFC11 receives the operation control signal opcnt11 and outputs the clock signal clk11. The power supply voltage control circuit SVC11 receives the operation control signal opcnt12 and outputs the power supply voltage vdd11. The substrate bias control circuit BBC11 receives the operation control signal opcnt13, and outputs a PMOS transistor substrate bias vbp11 and an NMOS transistor substrate bias vbn11.
[0023]
The performance such as the data processing speed (or operation speed) or power consumption of the circuit function module CFM11, which is an integrated circuit composed of CMOS circuits, depends on the frequency of the clock signal clk11 supplied to the circuit function module CFM11 and the power supply voltage vdd11. It varies depending on the voltage and the voltages of the substrate biases vbp11 and vbn11. Therefore, by performing optimal control according to the amount of data to be processed by the circuit function module CFM11 or the required operation speed, the required processing performance can be satisfied with the minimum power consumption. That is, as described in Non-Patent Document 3, when the frequency of the clock signal clk11 is uniquely determined as the operation speed of the circuit function module CFM11, the power supply voltage vdd11 and the substrate bias vbp11 for satisfying the speed request, Although there are a plurality of voltage combinations of vbn11, it is also possible to uniquely determine the point at which the power consumption is minimum among the combinations. As a result, by supplying the optimal clock signal clk11, power supply voltage vdd11, substrate bias vbp11, vbn11, the circuit function module CFM11 can operate with the maximum operating speed / power consumption ratio, and it has high performance. Low power can be realized at the same time.
[0024]
In order to realize the above functions on a single chip, which is a semiconductor integrated circuit device such as a microprocessor composed of CMOS circuits, that is, optimal control of clock signal clk11, power supply voltage vdd11, substrate bias vbp11, vbn11 In this embodiment, the performance measurement circuit PMC11 measures performance such as the operation speed and power consumption of the circuit function module CFM11 in advance. First, a measurement command signal mescmd11 for measuring from the performance measurement circuit PMC11 is given to the circuit function module CFM11, and a measurement command signal mescmd12 is given to the storage table circuit MTC11. The storage table circuit MTC11 generates operation control signals opcnt11, opcnt12, and opcnt13 according to the measurement command signal mescd12, and controls the clock frequency control circuit CFC11, the power supply voltage control circuit SVC11, and the substrate bias control circuit BBC11, respectively. The clock frequency control circuit CFC11 outputs a clock signal clk11 having a frequency corresponding to the operation control signal opcnt11. The power supply voltage control circuit SVC11 outputs a power supply voltage vdd11 having a voltage corresponding to the operation control signal opcnt12. The substrate bias control circuit BBC11 outputs substrate biases vbp11 and vbn11 having voltages corresponding to the operation control signal opcnt13. The circuit function module CFM11 operates in accordance with the measurement command signal mescmd11 under the clock signal clk11, the power supply voltage vdd11, the substrate biases vbp11 and vbn11 supplied in this way, and performance measurement is performed. The measured performance data is given to the performance measurement circuit PMC11 as a measurement result signal mesres11. Further, the performance measurement circuit PMC11 stores the performance data as the measurement data in the storage table circuit as the performance data signal 11. The measurement of the performance related to the circuit function module CFM11 is performed at the frequency of the clock signal clk11 that can be generated by the clock frequency control circuit CFC11, the power supply voltage control circuit SVC11, and the substrate bias control circuit BBC11, the voltage of the power supply voltage vdd11, and the voltages of the substrate biases vbp11 and vbn11. All combinations are performed, and the entire performance data is stored in the storage table circuit MTC11. The storage table circuit includes a register, a memory, and a logic circuit. The memory table circuit MTC11 selects the clock signal clk11, power supply voltage vdd11, substrate bias vbp11, vbn11 that minimizes the power consumption among performance data that satisfies the operation speed required by the circuit function module. The operation control signals opcnt11, opcnt12, and opcnt13 are determined.
[0025]
As for the performance of the CMOS semiconductor integrated circuit chip, an error from a design value or a performance error occurs within a chip or between chips due to variations in manufacturing processes. This is called performance variation. The optimum values of the clock signal clk11, the power supply voltage vdd11, the substrate biases vbp11 and vbn11 can be obtained by simulation at the time of design, but cannot cope with performance variations due to the manufacturing process. In addition, performing design while obtaining optimum conditions during design complicates the design and extends the design period. As a result, the reliability of the chip is lowered. Therefore, as in the configuration of the present embodiment, the performance variation problem can be solved by measuring the performance of the circuit function module CFM11 with an actual chip and storing the data. Further, when designing the circuit function module CFM11, it is not necessary to consider these optimum controls, so that the design is facilitated, the design period is shortened, and the reliability is improved. Further, performing performance measurement means testing a chip, so that the test time of the chip can be shortened.
In the above description, one signal or one signal line in the drawing can transmit a set of a plurality of signals or information for a plurality of bits. The same applies to the following description.
[0026]
FIG. 2 is a diagram illustrating an embodiment of the clock frequency control circuit.
This clock frequency control circuit includes a D-type flip-flop circuit DFF21 and a selector circuit SEL21. The D-type flip-flop circuit DFF21 is connected in series and divides the input clock signal clkin21. The clock frequency of the input clock signal clikin21 is divided by 1/2 by the first-stage D-type flip-flop circuit output sig21 and divided by 1/4 by the second-stage D-type flip-flop circuit output sig22. The selector circuit SEL21 determines how many divided clock signals are output as clk11. The selector circuit SEL21 is controlled by an operation control signal opcnt11. In the case of the frequency division method of this embodiment, the divided clock signal output clk11 can be immediately output in one clock period when the operation control signal opcnt11 is supplied.
[0027]
FIG. 3 is a diagram showing another embodiment of the clock frequency control circuit.
The clock frequency control circuit includes a phase frequency detection circuit PFD31, a PMOS transistor PMS31, an NMOS transistor NMS31, a resistor RES31, a capacitor CAP31, a voltage controlled oscillation circuit VCO31, and a frequency divider circuit DIV31. This is a phase-locked rope circuit (hereinafter referred to as PLL) having a known circuit configuration. A clock signal clk11 obtained by multiplying the clock frequency with respect to the clock input signal clkin21 can be generated. The multiplication rate is determined by the frequency divider DIV31. If the frequency division is 1/2, the multiplication is doubled. If the frequency division is 1/3, the multiplication is 3 times. The operation control signal opcnt11 controls the frequency dividing rate of the frequency dividing circuit DIV31 and determines the frequency of the clock signal clk11.
[0028]
FIG. 4 is a diagram showing an embodiment of a power supply voltage control circuit or a substrate bias control circuit.
The power supply voltage control circuit includes a reference voltage generation circuit VRF41, an amplifier circuit AMP41, and a PMOS transistor PMS41. The output voltage signal sig41 of the reference voltage generation circuit VRF41 is controlled by the operation control signal opcnt11, and the output power supply voltage vdd11 changes. This is a known circuit configuration called a series regulator. In addition, a circuit configuration of a switching regulator system may be used. The reference voltage generation circuit VRF41 can be configured by, for example, a resistor divider circuit, a band gap reference circuit, a MOS transistor threshold voltage use circuit, or the like. The input voltage vddin31 is stepped down to generate the output voltage vdd11. This embodiment can also be used as a substrate bias control circuit. In the case of the substrate bias control circuit, two types of output voltages, vbp11 and vbn11, are required, so two circuits of this embodiment are used.
[0029]
FIG. 5 is a diagram showing another embodiment of the power supply voltage control circuit or the substrate bias control circuit.
The power supply voltage control circuit includes a ring oscillation circuit ROS51, a sensor circuit SEN51, a capacitor CAP51, and diodes DID51 and DID52. This circuit can be used when boosting the output voltage vdd11 above the input voltage vddin31 or generating a negative voltage. The configuration is the same as that of a known charge pump circuit. The output voltage vdd11 is determined by the operation control signal opcnt11 controlling the sensor circuit SEN51. When the output reaches a voltage greater than (or less than) the set value, the sensor circuit SEN51 supplies the signal sig51, stops the operation of the ring oscillation circuit ROS51, and determines the output voltage vdd11. Alternatively, a circuit configuration in which a plurality of stages of charge pump circuits are connected in series and the operation control signal opcnt11 determines which stage of output is selected as the output voltage vdd11 may be employed. The diode DID51 can be formed by using a layer such as a direct diffusion layer in a CMOS manufacturing process, or by using a MOS transistor.
[0030]
FIG. 6 is a diagram showing an embodiment of the performance measuring circuit of the present invention, which is in the PMC 11 of FIG.
The performance measuring circuit PMC61 of the present invention is composed of an inverter AND circuit INVAND61, an AND circuit AND61, a register circuit REG61, and a counter circuit CNT61. The inverter AND circuit INVAND61 receives the request signal req61 and the measurement result signal mesres11 and outputs a signal sig61. The AND circuit AND61 receives the signal sig61 and the control clock signal cntclk61 and outputs the signal sig62. The counter circuit CNT61 receives the signals sig61 and sig62 and outputs a signal sig63. The register circuit REG61 receives the signals sig61 and sig63 and outputs a performance data signal pfdat11. The circuit function module CFM61 receives the request signal req61 as the measurement command signal mescmd11, inputs the data input signal datin61 for performance measurement, and outputs the data output signal datout61 as the measurement result signal mesres11. The present invention is a method for detecting the data processing speed or circuit operation speed of the circuit function module CFM61 as performance.
[0031]
The operation waveform of the present invention is shown in FIG. In advance, the data input signal datin61 is supplied to the circuit function module CFM61 before time t1. The request signal req61 is asserted at time t1, and the measurement command signal mescmd11 is also asserted, and the circuit function module CFM61 starts processing the data input signal datin61. When the circuit function module finishes the data processing, the data output signal datout61 is asserted at time t2. This time (t2-t1) is a delay time indicating the data processing speed or circuit operation speed of the circuit function module CFM61. The data output signal datout61 is given to the performance measurement circuit PMC61 as a measurement result signal mesres11. In the performance measurement circuit PMC61, the control signal sig61 is asserted only between the times t1 and t2, and the counter circuit CNT61 measures the length of this assertion period using the control clock signal cntclk61. When the control signal sig61 is negated at time t2, the value measured by the counter circuit CNT61 is stored in the register circuit REG61 and output as the performance data signal pfdat11. A value obtained by dividing the performance data signal pfdat11 by the frequency of the control clock signal cntclk61 corresponds to a delay time required for data processing of the circuit function module CFM61.
[0032]
FIG. 8 is a diagram showing another embodiment of the performance measuring circuit of the present invention.
The performance measurement circuit PMC81 according to the present invention includes an NMOS transistor NMS81 and an analog / digital conversion circuit ADC81. For example, a virtual ground voltage line of the circuit function module CFM81 is connected to the control signal sig81 of the performance measurement circuit PMC81. The NMOS transistor NMS81 connects the reference voltage vref81 to the gate, the ground voltage gnd81 to the source, and the control signal sig81 to the drain. The analog-to-digital conversion circuit inputs the control signal sig81 and outputs the performance data signal pfdat11. During normal operation, the reference voltage vref81 is at the maximum input voltage level or the supply voltage level to the circuit function module CFM81, and the control signal sig81 and the ground voltage gnd81 are at the same potential. In this state, the circuit function module CFM81 processes the data input signal datin81. When measuring the power of the circuit function module CFM81, the reference voltage vref81 is set to a value lower than the maximum input voltage level and higher than the ground voltage level as necessary. In such a state, data for measuring power is given to the circuit function module CFM81 as the data input signal datin81, and measurement is started with the measurement command signal mescmd11. Since the power consumption until the measurement result signal mesres11 is output depends on the voltage level of the control signal sig81, when that level is converted by the analog-to-digital converter circuit ADC81, the digital value at that time becomes the power consumption of the circuit function module CFM81. Equivalent to. This power consumption data is output as the performance data signal pfdat11. A PMOS transistor can be used for the NMOS transistor part. In addition, the connection part between the circuit function module and the performance measurement circuit and the power measurement part have the same effect not on the ground voltage line of the circuit function module but on the power supply voltage line.
[0033]
FIG. 9 is a diagram showing another embodiment of the performance measuring circuit of the present invention.
The performance measuring circuit PMC91 according to the present invention includes an amplifier circuit AMP91, resistors RES91 and RES92, and an analog / digital conversion circuit ADC91. The amplifier circuit AMP91 receives the power supply voltage vdd91 and the reference voltage vref91 supplied to the circuit function module CFM91, and outputs a signal sig91. The resistor RES91 is inserted between the power source vdd91 and the signal sig91, and the resistor RES92 is inserted between the signals sig91 and sig92. The analog-digital conversion circuit inputs the signal sig92 and outputs the performance data signal pfdat11. By combining the amplifier circuit AMP91 and the resistors RES91 and RES92 as shown in FIG. 9, a voltage depending on the current flowing in the power supply vdd91 appears in the signal sig92. The analog-to-digital conversion circuit ADC91 converts this voltage into a digital signal, and the current consumption is output to the performance data pfdat11 as a digital signal. The circuit function module CFM91 at the time of performance measurement has the same function as the CFM81 in FIG.
[0034]
In addition, the connection part between the circuit function module and the performance measurement circuit and the power measurement part have the same effect not in the power supply voltage line of the circuit function module but in the ground voltage line.
[0035]
FIG. 10 is a diagram showing an example of a table of the storage table circuit of the present invention.
The storage table circuit of the present invention is composed of storage elements such as flip-flop circuits and static random access memory circuits. The memory table circuit is arranged for each circuit function module and stores data on power consumption pwr101 and delay time tpd101 of the circuit function module for all combinations of power supply voltage vdd11 and substrate bias vbp11, vbn11 that can be supplied to each circuit function module. To do. In the example of FIG. 10, 1.2V, 1.0V, and 0.8V are given as the power supply voltage vdd11, and two kinds of voltages such as vbp11 = vdd11 or vbp11 = vdd11 / 2 are given as the substrate bias vbp11, and as the substrate bias vbn11 Is given two voltages, vbn11 = 0 or vbn11 = vdd11 / 2. Therefore, there are six control combinations: cmb101, cmb102, cmb103, cmb104, cmb105, and cmb106. For each combination, performance such as the operation speed and power consumption of the circuit function module is measured using a performance measurement circuit as shown in the embodiments of FIGS. 6, 8, and 9, and the measurement result is obtained from the performance data pfdat11. As shown in FIG. 1, it is given to the storage table circuit MTC11, and a table as shown in FIG. 10 is created in the storage table circuit. In this figure, for example, in the case of the control combination cmb101, the power consumption pwr101 of a certain circuit function module is 3.5 mW, and the delay time tpd101 is 3.1 ns. When the performance required for the circuit module is determined, the optimum combination of power supply voltage vdd11, substrate bias vbp11, vbn11 is determined from this table, and each control signal is sent to the frequency control circuit, power supply voltage control circuit, and substrate bias control circuit. give. For example, when the performance required for the circuit function module is 250 MHz with a clock signal, the delay time required for data processing may be 4 ns or less, so the control combination cmb102 is selected.
As the number of combinations of the power supply voltage vdd11, the substrate biases vbp11 and vbn11, or the number of divisions of each voltage increases, it becomes possible to select a condition for performing an operation close to the ideal minimum power consumption.
[0036]
In the table of FIG. 10, the delay times tpd101 are arranged in ascending order. However, when the power consumption pwr101 is rearranged in the descending order, the voltage combinations corresponding to cmb104 and cmb105 are switched among the control combinations in FIG. 10 as shown in FIG. By rearranging in this way, for example, when selecting a voltage combination with a delay time of 7 ns or less in order to achieve a certain circuit operation speed, when the control combination is searched in the direction from cmb116 to cmb111, cmb115 is determined. can do. If searching in the direction of the control combination cmb106 to cmb101 in the table of FIG. 10, cmb105 is determined. The cmb 105 has a power consumption of 0.8 mW, which is larger than the 0.6 mW of the cmb 115. Therefore, it is possible to select a control combination that maximizes the operation speed / power consumption ratio by rearranging the data as shown in FIG. In order to perform the rearrangement as shown in FIG. 11, the data of the power consumption pwr111 and the delay time tpd111 are sequentially compared by the comparison circuit and then stored in the storage table circuit, or when the data is used after being stored in the storage table circuit. The size may be compared with a comparison circuit.
[0037]
FIG. 12 is a diagram showing another embodiment of the performance measurement circuit of the present invention.
The circuit function module CFM121 of the present invention includes a selector circuit SEL121, a D-type flip-flop circuit DFF121, and a logic circuit LOG121. During normal data processing operation, data such as data input signals datin121, datin122, datin123, datin124, datin125, etc. are input to the circuit function module CFM121, input to the D-type flip-flop via the selector circuit, and then the actual data processing operation. The data is supplied to a logic circuit LOG121 that performs data processing. Data obtained as a result of calculation by the logic circuit LOG121 is output from the circuit function module CFM121 to the outside as data output signals datout121, datout122, datout123, datout124, and datout125 via a selector circuit and a D-type flip-flop circuit. When the performance measurement circuit PMC121 is used at the time of chip testing, it is necessary to perform the operation function test, so-called function test, in addition to measuring the performance of the circuit function module CFM121 by means of FIG. 6, FIG. 8, FIG. There is. The circuit configuration of the portion corresponding to this function test is the configuration shown in FIG. The performance measurement circuit PMC121 gives selector circuit control signals selcnt121 and selcnt122 to the selector circuit in the circuit function module CFM121, stops connection with the data input signal and data output signal, and uses the scan input signal scnin121 for performance measurement. Are sequentially applied using a selector circuit and a D-type flip-flop circuit in the circuit function module. Similarly, the output data signal is returned to the performance measuring circuit PMC121 as the sequential scan output signal scnout121 using the selector circuit and the D-type flip-flop circuit. The test data signal is taken in from the outside of the performance measurement circuit PMC121 as the test input signal bstin121, and the result of the function test is output as the test output signal bstout121. The aforementioned so-called scan test method in the circuit function module CFM 121 is a known technique. In the present invention, the performance measurement circuit PMC121 that measures the performance of the circuit function module also performs the scan test together with the performance measurement by inputting and outputting the control signal for the scan test. As a result, the scan test and the performance are performed during the chip test. Both tests can be performed. Therefore, the test time is shortened. Further, since performance tests are performed for each chip and further for each circuit function module, it is possible to cope with variations in performance due to manufacturing processes.
[0038]
FIG. 13 is a diagram showing another embodiment of the performance measurement circuit of the present invention.
The circuit function module CFM131 of the present invention includes a selector circuit SEL121, a D-type flip-flop circuit DFF121, and a logic circuit LOG121, like the circuit function module CFM121 in FIG. The data input signals datin121 to datin125 and the scan input signal scnin121 are selected by the selector circuit control signal selcnt121, and the data output signals datout121 to datout125 and the scan output signal scnout121 are selected by the selector circuit control signal selcnt122. The difference from the circuit function module CFM121 is that the data output of the logic circuit LOG121 is directly output as the measurement result signal mesres131. The performance measurement circuit PMC131 of the present invention includes an inverter AND circuit INVAND61, an AND circuit AND61, a comparison circuit CMP131, a register circuit REG61, and a counter circuit CNT61.
[0039]
The present invention is one of the embodiments for measuring the circuit operation module CFM131 operation speed, the circuit operation delay time indicating the data processing speed using the performance measurement circuit PMC131, and using the scan test technique shown in FIG. Yes. Further, using the measurement result signal mesres131 output from the circuit function module CFM131, the performance measurement circuit PMC131 measures the delay time of the circuit function module CFM131 by the same mechanism as the performance measurement circuit PMC61 in FIG. Specifically, the test input signal bstin131 is supplied to the circuit function module CFM131 using the selector control signal selcnt121 and the scan input signal scnin121. At the moment when the request signal req61 is asserted, the logic circuit LOG121 starts a data processing operation in the CFM 131 of the circuit function module, and in the performance measurement circuit PMC131, the counter circuit CNT61 measures time according to the control clock signal cntclk61. When the logic circuit LOG121 finishes the processing and the output data is determined, it is given to the comparison circuit CMP131 as the measurement result signal mesres131. When the measurement result signal mesres131 indicates a correct result, the comparison circuit outputs the control signal sig131, the measurement of the counter circuit CNT61 is stopped, and the measurement value is given to the register circuit REG61. The output pfdat11 represents the delay time of the circuit function module CFM131. For example, if data using a critical path is given as input data as the test input signal bstin 131, the measured delay time becomes the critical path delay of the corresponding circuit function module CFM 131, that is, the worst (maximum) delay time.
[0040]
FIG. 14 is a diagram showing another embodiment of the performance measuring circuit of the present invention.
The circuit function module CFM121 of the present invention has the same configuration as the scan test technology of the circuit function module in FIG. 12, and the performance measurement circuit PMC141 of the present invention has a power consumption measurement function as shown in FIG. 8 or FIG. Have. The ground level of the circuit function module becomes a pseudo ground line and is connected to the control signal sig81 of the performance measuring circuit PMC141. The performance measurement circuit PMC141 measures the worst (maximum) power of the circuit function module CFM121, for example, by supplying data from the test input signal bstin141 so that the corresponding circuit function module CFM121 operates at the maximum power consumption.
[0041]
FIG. 15 is a diagram showing another embodiment of the performance measuring circuit of the present invention.
The performance measurement circuit of the present invention includes a shift register circuit SRG151, selector circuits SEL151 and SEL152, an analog / digital conversion circuit ADC151, a comparison circuit CMP151 and CMP152, a D-type flip-flop circuit DFF151, an inverter AND circuit INVAND151, an AND circuit AND151, and a register circuit REG151. The counter circuit CNT151. The shift register circuit SRG151 receives the test input signal bstin151 and the control clock signal cntclk151 and outputs the control signal sig151. The selector circuit SEL151 inputs a voltage signal such as a power supply voltage or a substrate bias as the voltage to be measured vmes151, selects and outputs a voltage to be measured. The analog-to-digital conversion circuit ADC151 receives the voltage to be measured selected by the selector circuit SEL151, converts the voltage level into a digital value, and outputs a control signal sig152. The comparison circuit CMP151 compares the control signals sig151 and sig152 to determine whether they match, and outputs the control signal sig153. The D-type flip-flop circuit receives the request signal req151 and the input voltage vddin151 and outputs a control signal sig154. The inverter AND circuit INVAND151, the AND circuit AND151, the register circuit REG151, and the counter circuit CNT151 have the same configuration as the performance measurement circuit PMC61 in FIG. The selector circuit SEL152 selects which of the control signal sig152 and the test output signal bstout152 that is the register circuit output is transmitted to the comparison circuit CMP152. The comparison circuit CMP152 determines whether the output signal from the selector circuit SEL152 is the same as or different from the output signal sig151 from the shift register circuit SRG151, and outputs it as the test output signal bstout151.
[0042]
The performance measurement circuit of the present invention measures whether the power supply voltage and the substrate bias voltage supplied to the circuit function module are supplied at the correct level, and the transition time when the power supply voltage and the substrate bias change. And measure whether it is as designed. First, the shift register circuit SRG151 takes the test input signal bstin151 according to the control clock signal cntclk151 and outputs it as a signal sig151. The power supply voltage and the substrate bias are connected to the voltage to be measured vmes151, and the selector circuit SEL151 selects which voltage to measure. The analog-digital conversion circuit ADC151 digitizes the applied voltage level and outputs it as a signal sig152. The voltage level applied to the voltage to be measured vmes151 becomes the signal sig152, and the signal sig151 is compared with the comparison circuit CMP152 to observe whether a correct voltage level is generated, and the result is output as the test output signal bstout151. When the request signal req151 is asserted, the counter circuit CNT151 starts measuring time. At the same time, the supplied power supply voltage or the substrate bias starts to change in each circuit function module. The corresponding voltage level is digitized and given by the signal sig152. When this value becomes equal to the desired signal sig151, the comparison circuit CMP151 asserts the output signal sig153, and the measurement of the counter circuit CNT151 stops. During this time, the time measured by the counter circuit CNT151 corresponds to the voltage level transition time. The measurement result is stored in the register circuit REG151 and output as the test output signal bstout152. Further, the comparison circuit CMP152 determines whether it is equal to the design value by comparing with the signal sig151. In this way, the voltage level and voltage transition time supplied to the circuit function module are measured.
[0043]
FIG. 16 is a diagram showing an embodiment of the storage table circuit of the present invention.
The present invention measures the amount of data supplied to a self-learning function unit, that is, a circuit function module in a storage table circuit, and predicts the performance of the circuit function module that will be required in the future. 1 shows a circuit for generating a control signal to a circuit function module, a clock frequency conversion circuit, a power supply voltage conversion circuit, and a substrate bias control circuit based on the performance data stored in FIG.
[0044]
The storage table circuit of the present invention includes an arbiter circuit ARB161, counter circuits CNT161, CNT162, and CNT163, register circuits REG161 and REG162, comparison circuits CMP161 and CMP162, an AND circuit, and an inverter circuit. The signal input to the storage table circuit is shown by the waveform in FIG. The data input signal datin161 to the circuit function module has a data valid period (shaded line in the figure) and an invalid period, and data is given during the valid period. The time obtained by combining one data valid period and invalid period is called time slots tmslot160, tmslot161, and tmslot162. The data flag signal flag161 changes its value during this time slot, generates a data valid signal flval160, flval161, flval162 in the data valid period in each time slot, and data invalid signals flinv160, flinv161, flinv162 in the data invalid period Is generated. Therefore, the rise of the data valid signal means the start of the data valid period, and the assertion of the data invalid signal means the end of the data valid period. In the storage table circuit of FIG. 16, at the start of operation of the circuit function module, the storage table circuit selects control of conditions indicating the maximum speed, such as maximum frequency and maximum power supply voltage. After that, as the actual data processing progresses, the technique is to reduce the performance and reduce the power.
[0045]
Specifically, in a certain time slot tmslot161, the data valid period, that is, the time between the data valid signal flval161 and the data invalid signal flinv161 is tv, the invalid period, that is, the data invalid signal flinv161 and the data valid signal of the next time slot tmslot162 Let ti be the time between flval162. The amount of data in this time slot is measured every Nt times. First, supply the clock signal clk161 (frequency f0) with the maximum clock frequency, and if the data processing performance of the circuit function module is sufficient, the clock frequency is lowered to the clock signal clk162 with f0, and the power is reduced. . At this time, the power supply voltage and the substrate bias are simultaneously changed according to the control combination of the storage table circuit. If the data invalid period ti continues for a certain time Tsd or more under the minimum power condition, the power supply is shut off. When the power is shut off, a power switch composed of a MOS transistor is incorporated in the power supply voltage control circuit shown in FIGS. In addition, during the data invalid period, the clock signal supply to the circuit function module is stopped (for example, in the clock frequency control circuit, the output clock frequency is set to 0 or the output is gated using an AND circuit). This further reduces power. The conditions for reducing the clock frequency from f0 to f1 are as follows.
[0046]
[Expression 1]

[Expression 2]

In equation (1), the left side indicates the number of data at the clock f0, and the right side indicates the number of data that can be processed in one slot when the clock is lowered to f1. Equation (2) shows the relationship between the time Ttrans required for voltage transition and the data invalid period ti. In addition, the condition Nt for how many slots the frequency can be changed is determined by the power constraint. The power constraint is obtained from the operating power Pf0 and Pf1 of the circuit function module at each frequency, the power Ptrans associated with the voltage transition, and the transition time Ttrans as follows.
[0047]
[Equation 3]

Here, it is assumed that the operating power is sufficiently larger than the standby power. Therefore, when the conditions of the expressions (1) and (2) occur Nt times, the frequency is lowered and a transition is made to low power operation. The conditions for shutting off the power are considered from the power constraints and timing constraints. The power constraint condition is as follows when the leakage power of the circuit function module at the minimum power supply voltage is Pleak.
[0048]
[Expression 4]

[Equation 5]

If the data invalid period is longer than the condition obtained from equation (4), equation (5) is satisfied and the power is shut off. In this way, the storage table circuit reduces the power consumption of the circuit function module. When the amount of data increases and processing cannot be performed in one slot, the clock is returned to the maximum frequency (f0) while storing data in the buffer, and the same learning is repeated again. In FIG. 16, when the relations of the expressions (1) and (2) are satisfied, the outputs of the comparison circuits CMP161 and CMP162, that is, the AND circuit output, outputs the down signal dwn161. In this case, the frequency and voltage conditions supplied to the circuit function module are lowered by one step by the control signal that is the output of the storage table circuit, thereby reducing the operation speed and power consumption. If the data invalid period is long even when the frequency is minimized, the expression (5) is satisfied, the shutdown signal sdwn161 is output, and the circuit function module is shut off. In addition, if the data cannot be processed completely in a certain time slot tmslot160 and the data for the next time slot tmslot161 arrives before the data invalid signal flinv160 and the data valid signal flval161 is generated, an error signal is generated. The frequency and voltage conditions are returned to the maximum speed performance conditions.
[0049]
When the circuit function module is operating at a certain performance and the amount of data increases and cannot be processed within the time slot, the err161 signal of FIG. 16 is output. At this time, the data that could not be processed is stored in the data input buffer of the circuit function module, or the data is discarded as a processing error and the data is requested again. In addition, the setting of the power supply voltage, the substrate bias, and the clock frequency after the err161 signal is output may be returned to the setting that gives the highest performance or may be returned to the performance setting that is one level higher than the current state.
As described above, the storage table circuit of the present invention generates a control signal so that the circuit function module can exhibit optimum performance by measuring and learning the amount of data given to the circuit function module.
[0050]
FIG. 18 is a diagram showing another embodiment of the present invention.
The present invention includes circuit function modules CFM181 and CFM182, clock frequency control circuits CFC181 and CFC182, power supply voltage control circuits SVC181 and SVC182, substrate bias control circuits BBC181 and BBC182, storage table circuits MTC181 and MTC182, buffer circuits BUF181 and BUF182, bus BUS181 , An external input EXT181, a performance measurement circuit PMC181, and a bus control circuit BSC181. The circuit function module CFM 181 receives the clock frequency clk 181, the power supply voltage vdd 181, the substrate biases vbp 181 and vbn 181, and inputs / outputs data signals via the buffer circuit BUF 181. The circuit function module CFM 182 receives the clock frequency clk 182, the power supply voltage vdd 182, the substrate biases vbp 182 and vbn 182, and inputs / outputs data signals via the buffer circuit BUF 182. Each of the clock frequency control circuits CFC181 and CFC182 receives the input clock signal clkin181 and outputs the clock signals clk181 and clk182. The power supply voltage control circuits SVC181 and SVC182 receive the input voltage vddin181 and output the power supply voltages vdd181 and vdd182, respectively. Substrate bias control circuits BBC181 and BBC182 receive input voltage vddin181 and output substrate biases vbp181 and vbn181 and vbp182 and vbn182, respectively. The storage table circuit MTC181 receives the control signal sig182 and controls the clock frequency control circuit CFC181, the power supply voltage control circuit SVC181, and the substrate bias control circuit BBC181. The storage table circuit MTC182 receives the control signal sig183 and controls the clock frequency control circuit CFC182, the power supply voltage control circuit SVC182, and the substrate bias control circuit BBC182. The buffer circuits BUF181 and BUF182 relay data input / output between the circuit function modules CFM181 and CFM182 and the bus BUS181 to store data. The bus circuit BUS181 relays data exchange with the external input EXT181, performance measurement circuit PMC181, bus control circuit BSC181, storage table circuits MTC181 and MTC182, buffer circuits BUF181 and BUF182.
[0051]
As shown in the present invention, the system configuration when there are a plurality of circuit function modules is as follows. One clock frequency control circuit, one power supply voltage control circuit, one substrate bias control circuit, one storage table circuit, and one buffer circuit are arranged for each circuit function module. One set of bus wiring, external input, performance measurement circuit, and bus control circuit is arranged for each chip or system. In addition, the input power supply and the input clock signal supply a single type of signal having a constant voltage value and frequency to the chip, and convert the voltage and frequency inside the chip. With the above configuration, the circuit function module design in the chip and the layout design of the entire chip are facilitated, and the design period is shortened and the reliability is improved. In addition, the entire chip is optimized by controlling the optimal clock frequency, power supply voltage, and substrate bias for each circuit function module. The BSC 181 supplies data from modules such as which circuit function modules to the bus BUS 181. The bus external input EXT 181 is supplied with OS, application software, middleware and the like. The bus control circuit BSC181 determines to which circuit function module the bus BUS181 is permitted to input / output data signals. When the request signal req181 is received, the acknowledge signal ack181 is output so as to satisfy the optimum condition. As for the exchange of data between the circuit function modules, any method such as a synchronous method, an asynchronous method, a data flow method, or the like may be used. Performance optimization and low power consumption can be achieved without depending on the architecture for realizing coupling between circuit function modules.
[0052]
FIG. 19 is a diagram showing a flowchart at the time of a chip test.
Start chip test at 19A. In 19B, the circuit function module to be measured by the performance measurement circuit is selected. In 19C, in the selected circuit function module, the storage table circuit outputs a signal so that the power supply voltage control circuit and the substrate bias control circuit perform control so as to maximize the operation speed of the circuit function module. In 19D, select the voltage type (power supply voltage, substrate bias, etc.) that the performance measurement circuit measures. In 19E, it is determined whether the voltage level is correct. If it is not correct, the result is stored as a log in 19F and the process returns to 19D. If the voltage level is correct at 19E, measure the voltage transition time at 19G. In 19H, it is determined whether all voltage types have been selected. If there is a voltage type that has not yet been measured, the process returns to 19D. When all voltage types have been measured, the maximum transition time data is sent to the storage table circuit at 19T. The work from 19C to 19T becomes the analog test ABST191 work. Subsequently, in 19J, test data (test vector) is supplied to the already selected circuit function module. At 19K, output data is detected and it is determined whether the DC function of the circuit function module is correct. If the operation is wrong, the log is memorized in 19L and it returns to 19J. If the circuit operation is correct at 19K, it is determined at 19M whether all test vectors have been completed. If it is not finished, return to 19J, and if it is finished, proceed to 19N. The work from 19J to 19M is the function test FBST191 work. In 19N, the control combination of the power supply voltage and the substrate bias is selected. At 19V, the operation speed of the circuit function module, that is, the delay time is measured in the selected control combination. At 19P, the measurement result data signal is applied to the storage table circuit of the corresponding circuit function module.
In 19Q, it is determined whether all control combinations are completed. If completed, the process proceeds to 19R, and if not completed, the process returns to 19N. The work from 19N to 19Q is the work of timing test TBST191. In 19R, determine whether all circuit function modules have been selected. If not completed, return to 19C, and if completed, proceed to 19S. In 19S, the chip test flow ends.
[0053]
FIG. 20 is a view showing a flowchart at the time of the chip test as in FIG. The difference from FIG. 19 is that FIG. 20 includes the measurement of power consumption in the circuit function module. In FIG. 19, the power consumed by the circuit function module is assumed to be known in accordance with the control combination, and the flowchart shows a case where only the measurement of the data processing speed, that is, the delay time is performed. When the power consumption is unknown, it is necessary to measure according to FIG. The difference from FIG. 19 is that the power consumption is also measured when measuring the delay time at the location corresponding to 20V and 20P in the flow, and the information sent to the storage table circuit is both the delay time and the power consumption.
[0054]
FIG. 21 is a diagram illustrating an example of the bus control circuit.
The present invention includes an increment decrement circuit INCDEC211, counter circuits CNT211, CN212, CNT213 and CNT214, a comparison circuit CMP211, a selector circuit SEL211, an encode circuit ENC211, and a decode circuit DEC211. The increment / decrement circuit INCDEC211 receives the signal from the encoder circuit ENC211 and outputs a signal for incrementing or decrementing the counter. The counter circuits CNT211, CNT212, CNT213, and CNT214 change the count value according to the signal from the increment decrement circuit INCDEC211 and give the count value to the comparison circuit CMP211. The decode circuit DEC211 decodes the request signal req211 and controls the selector circuit SEL211. The selector circuit SEL211 transmits the output of the comparison circuit CMP211 to the encode circuit ENC211 according to the control signal from the decode circuit 211, and the encode circuit outputs a signal for controlling the increment decrement circuit INCDEC211 and the acknowledge signal ack211. When a request signal arrives from the circuit function module, the bus control circuit returns an acknowledge signal and gives the authority for the circuit function module to exchange (input / output) data on the bus. When request signals arrive at the same time, or when a request signal arrives while another circuit function module is using the bus, it works to adjust the priority between the circuit function modules. Specifically, a circuit function module with a low bus usage rate is made to use the bus with high priority. The bus control circuit owns counter circuits corresponding to all circuit function modules. When a request signal req211 arrives from a certain circuit function module, the bus control circuit decodes the signal by the decode circuit DEC211. At this time, if the count number of the corresponding circuit function module is smaller than the count number of the circuit function module to be compared, the acknowledge signal ack211 is returned via the encoder circuit ENC211 and the bus use of the corresponding circuit function module is permitted. . When an acknowledge signal is issued, the count number of each circuit function module is changed using the increment decrement circuit INCDEC211. The circuit function module that issued the acknowledge signal increments the count number by one, and all other modules decrement the count number by one. In this way, the bus usage rate among the circuit function modules is made uniform.
[0055]
By using the bus control circuit in this way, each circuit function module in FIG. 18 can operate autonomously and distributedly, and the low power and high performance technology of the present invention can be used effectively.
FIG. 22 is a diagram showing another embodiment of the bus control circuit.
[0056]
The present invention includes a shift register circuit SRG221 including address register circuits ADR221, ADR222, ADR223, ADR224, and ADR225, a selector circuit SEL221, a decoder circuit DEC221, and an encoder circuit ENC221. The decoder circuit DEC221 decodes the request signal req221 and transmits it to the selector circuit SEL221. The selector circuit SEL221 selects an address register in accordance with a control signal from the decoder circuit DEC221. The encoder circuit ENC221 encodes the signal of the selected address register and outputs it as an ACK signal ack221, and controls the address register in the shift register circuit SRG221. The address register circuit in the shift register circuit SRG221 corresponds to each circuit function module in the chip. The position of each address register indicates the frequency with which the circuit function module uses the bus. The address registers corresponding to the circuit function modules that are not frequently used are arranged at the upper position in the figure. When the acknowledge signal ack221 is output in response to the request signal, it corresponds to the corresponding circuit function module by the control signal from the encoder circuit ENC221.
The address register is arranged at the lowest position in the shift register circuit SRG221. The other address registers go up one step at a time. When there are a plurality of circuit function modules scheduled to use the bus at the time of receiving the request signal req221, the selector circuit selects the circuit function module corresponding to the register at the top position among the corresponding address registers. Outputs an acknowledge signal. In the case of this circuit as well, the bus utilization rate of circuit function modules concentric is averaged as in FIG.
[0057]
As described above, according to this embodiment, the following effects are obtained. That is, in a semiconductor integrated circuit device that can operate at high speed and with low power consumption, a CMOS circuit that realizes the following problems, a CMOS LSI chip constituted by the CMOS circuit, and a semiconductor integrated circuit device can be provided. That is, by using a structure including a performance measurement circuit and a storage table circuit for controlling the clock frequency, power supply voltage, and substrate bias of the MOS transistor constituting the CMOS circuit autonomously and in a self-learning manner, The following issues are solved.
(1) Even when the circuit scale and type of semiconductor integrated circuits composed of CMOS circuits such as microprocessors are complex and diverse, each circuit module can be designed without being aware of low-power and high-speed control technology. Thus, the design time can be shortened and the reliability can be improved.
(2) When using an existing circuit module in a chip such as a microprocessor or when using a multiprocessor, it is possible to design without using the low-power and high-speed control technology. Shortening and improving reliability.
(3) Even when various circuit modules are combined like ASIC, it is possible to design without considering the low-power and high-speed control technology, and it is possible to shorten the design time and improve the reliability.
(4) Since the performance of each circuit module is measured in advance in order to realize the low-power and high-speed control technology, the chip test period can be shortened.
(5) Maximizing the “operation speed / power consumption performance” in the operation of the processor or the like by enabling the supply of the optimum clock frequency, power supply voltage, and substrate bias for each circuit module in the chip.
[0058]
【The invention's effect】
As described above, according to the present invention, it is possible to simplify the design of a semiconductor integrated circuit device using a CMOS circuit, reduce the test time, and reduce the power consumption.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of the present invention.
FIG. 2 is a configuration diagram of an embodiment of a clock frequency control circuit.
FIG. 3 is a configuration diagram of another embodiment of a clock frequency control circuit.
FIG. 4 is a configuration diagram of an embodiment of a power supply voltage control circuit or a substrate bias control circuit.
FIG. 5 is a configuration diagram of another embodiment of a power supply voltage control circuit or a substrate bias control circuit.
FIG. 6 is a configuration diagram of an embodiment of a performance measurement circuit according to the present invention.
FIG. 7 is an operation waveform diagram of the performance measurement circuit.
FIG. 8 is a configuration diagram of another embodiment of the performance measuring circuit of the present invention.
FIG. 9 is a configuration diagram of another embodiment of the performance measuring circuit of the present invention.
FIG. 10 shows an example of a table of the storage table circuit of the present invention.
FIG. 11 shows another embodiment of the table of the storage table circuit of the present invention.
FIG. 12 is a configuration diagram of another embodiment of the performance measuring circuit of the present invention.
FIG. 13 is a configuration diagram of another embodiment of the performance measuring circuit of the present invention.
FIG. 14 is a configuration diagram of another embodiment of the performance measurement circuit of the present invention.
FIG. 15 is a configuration diagram of another embodiment of the performance measuring circuit of the present invention.
FIG. 16 is a configuration diagram of an embodiment of a storage table circuit of the present invention.
FIG. 17 is a waveform diagram showing the concept of a time slot.
FIG. 18 is a configuration diagram of another embodiment of the present invention.
FIG. 19 is a flowchart at the time of a chip test.
FIG. 20 is another flowchart at the time of a chip test.
FIG. 21 is a configuration diagram of an embodiment of a bus control circuit.
FIG. 22 is a configuration diagram of another embodiment of the bus control circuit.
[Explanation of symbols]
ABST191, ABST201 ・ ・ ・ Analog test,
ADC81, ADC91, ADC151 ... Analog to digital converter,
ADR221, ADR222, ADR223, ADR224, ADR225 ... Address register circuit,
AMP41, AMP91 ・ ・ ・ Amplifier circuit,
AND61, AND151 ... AND circuit,
ARB161 ・ ・ ・ Arbiter circuit,
BBC11, BBC181, BBC182 ... Substrate bias control circuit,
BUF181, BUF182 ・ ・ ・ Buffer circuit,
BUS181 bus,
BSC181 ・ ・ ・ Bus control circuit,
CAP31, CAP51 ... capacity
CFC11, CFC181, CFC182 ... clock frequency control circuit,
CFM11, CFM61, CFM81, CFM91, CFM121, CFM131, CFM181, CFM182 ... Circuit function module,
CMP131, CMP151, CMP152, CMP161, CMP162, CMP211 ... comparison circuit,
CNT61, CNT151, CNT161, CNT162, CNT163, CNT211, CNT212, CNT213, CNT214 ... counter circuit,
DEC211, DEC221 ... decode circuit,
DFF21, DFF121, DFF151 ... D-type flip-flop circuit,
DID51, DID52 ・ ・ ・ Diodes,
DIV31 ... frequency divider,
ENC211, ENC221 ... encoding circuit,
EXT181 ... External input,
FBST191, FBST201 ・ ・ ・ Function test,
INCDEC211 ・ ・ ・ Increment decrement circuit,
INVAND61, INVAND151 ・ ・ ・ Inverter and circuit,
LOG121 ・ ・ ・ Logic circuit,
MTC11, MTC181, MTC182 ... Storage table circuit,
NMS31, NMS81 ... NMOS transistors,
PFD31 ・ ・ ・ Phase frequency detection circuit,
PMC11, PMC61, PMC81, PMC91, PMC121, PMC131, PMC141, PMC181 ... Performance measurement circuit,
PMS31, PMS41 ... PMOS transistors,
REG61, REG151, REG161, REG162 ... register circuit,
RES31, RES91, RES92 ・ ・ ・ resistance,
ROS51 ・ ・ ・ Ring oscillation circuit,
SEL21, SEL121, SEL151, SEL152, SEL211, SEL221 ... selector circuit,
SEN51 ・ ・ ・ Sensor circuit,
SRG151, SRG221 ... shift register circuit,
SVC11, SVC181, SVC182 ... Power supply voltage control circuit,
TBST191, TBST201 ・ ・ ・ Timing test,
VCO31 ・ ・ ・ Voltage controlled oscillator circuit,
VRF41 ・ ・ ・ Reference voltage generation circuit,
19A, 19B, 19C, 19D, 19E, 19F, 19G, 19H, 19J, 19K, 19L, 19M, 19N, 19P, 19Q, 19R, 19S, 19T, 19V, 20A, 20B, 20C, 20D, 20E, 20F, 20G, 20H, 20J, 20K, 20L, 20M, 20N, 20P, 20Q, 20R, 20S, 20T, 20V ... Process,
ack181, ack211, ack221 ... Acknowledgment signal,
bstin121, bstin131, bstin141, bstin151 ... test input signal,
bstout121, bstout131, bstout141, bstout151, bstout152 ... test output signal,
clk11, clk161, clk162, clk171, clk181, clk182 ... clock signal,
clkin21, clkin181 ・ ・ ・ Input clock signal,
cmb101, cmb102, cmb103, cmb104, cmb105, cmb106, cmb111, cmb112, cmb113, cmb114, cmb115, cmb116 ... control combination,
cntclk61, cntclk151, cntclk152 ... control clock signal,
dat181, dat182, dat183 ... data signals,
datin61, datin121, datin122, datin123, datin124, datin125, datin161 ... data input signal,
datout61, datout121, datout122, datout123, datout124, datout125 ... Data output signal,
dwn161 ・ ・ ・ Down signal,
err161 ・ ・ ・ Error signal,
flag161: Data flag signal,
flval160, flval161, flval162 ... Data valid signal,
flinv160, flinv161, flinv162 ... Data invalid signal,
gnd31, gnd81 ・ ・ ・ Ground voltage,
mescmd11, mescmd12 ... Measurement command signal,
mesres11, mesres131 ・ ・ ・ Measurement result signal,
opcnt11, opcnt12, opcnt13 ... operation control signals,
pfdat11 ・ ・ ・ Performance data signal,
pwr101, pwr111 ・ ・ ・ Power consumption,
req61, req151, req181, req211, req221 ... request signal,
scnin121 ・ ・ ・ Scan input signal,
scnout121 ・ ・ ・ Scan output signal,
sdwn161 ・ ・ ・ Shutdown signal,
selcnt121, selcnt122 ... selector circuit control signal,
sig21, sig22, sig23, sig24, sig25, sig31, sig32, sig41, sig51, sig61, sig62, sig63, sig81, sig91, sig92, sig131, sig151, sig152, sig153, sig154, sig155, sig156, sig181, 183 ··Control signal,
t0, t1, t2, t3, t00, t01, t02, t03, t04, t05, t06 ... time,
tim161 ・ ・ ・ period signal,
tmslot160, tmslot161, tmslot162 ... Time slot,
tpd101, tpd111 ... delay time,
vbn11, vbn181, vbn182 ... NMOS transistor substrate bias,
vbp11, vbp181, vbp182 ... PMOS transistor substrate bias,
vdd11, vdd91, vdd181, vdd182 ... power supply voltage,
vddin31, vddin151, vddin181 ... input voltage,
vmes151 ・ ・ ・ Measured voltage,
vref81, vref91: Reference voltage.

Claims (14)

In the semiconductor integrated circuit chip,
A circuit function module having at least one data processing function;
A clock frequency control circuit for controlling a clock signal frequency supplied to the circuit function module;
A power supply voltage control circuit for supplying a power supply voltage to the circuit function module;
A substrate bias control circuit for supplying a substrate bias to the circuit function module;
A performance measuring circuit and a storage table circuit for controlling the clock frequency, power supply voltage, and substrate bias of the MOS transistors constituting the semiconductor integrated circuit autonomously and in a self-learning manner;
The storage table circuit is based on the storage data stored in the storage table according to the type and amount of data to be processed by the circuit function module or according to the environmental conditions under which the circuit function module operates. A semiconductor integrated circuit device characterized by controlling at least one of the clock frequency control circuit, the power supply voltage control circuit, or the substrate bias control circuit so as to satisfy the performance of a given circuit function module. In the semiconductor integrated circuit chip,
A circuit function module having at least one data processing function;
A clock frequency control circuit for controlling a clock signal frequency supplied to the circuit function module;
A power supply voltage control circuit for supplying a power supply voltage to the circuit function module;
A substrate bias control circuit for supplying a substrate bias to the circuit function module;
A performance measuring circuit and a storage table circuit for controlling the clock frequency, power supply voltage, and substrate bias of the MOS transistors constituting the semiconductor integrated circuit autonomously and in a self-learning manner;
The performance measurement circuit measures at least one of power consumption or data processing time of the circuit function module at the time of performance inspection before shipment of the semiconductor integrated circuit chip, and the measurement result is stored in the storage table in the storage table circuit. Remember
The storage table circuit determines a combination of a power supply voltage and a substrate bias based on the storage table so as to satisfy performance required for the circuit function module during operation of the circuit function module, and the clock frequency control circuit or the A semiconductor integrated circuit device, wherein a control signal is applied to at least one of a power supply voltage control circuit and the substrate bias control circuit. The performance measurement circuit measures the power consumption or data processing time of the circuit function module and stores the measurement result in the storage table circuit,
The storage table circuit controls at least one of the clock frequency control circuit, the power supply voltage control circuit, or the substrate bias control circuit so that a ratio of data processing time to power consumption of the circuit function module is maximized. The semiconductor integrated circuit device according to claim 1 or 2.   3. The semiconductor integrated circuit device according to claim 1, wherein the performance measuring circuit includes a function test circuit and an environmental condition evaluation circuit for the semiconductor integrated circuit chip.   3. The semiconductor integrated circuit according to claim 1, wherein the performance measuring circuit measures a minimum data processing time or a maximum data processing time in all given clock frequency conditions, power supply voltage conditions, or substrate bias conditions. apparatus.   3. The performance measuring circuit measures a maximum current consumption during operation and a maximum leakage current during stop of the circuit function module at all given clock frequencies or power supply voltages or substrate bias conditions. A semiconductor integrated circuit device according to 1.   The said performance measurement circuit measures at least 1 of the frequency level of the clock signal supplied to the said circuit function module, the voltage level of a power supply voltage, or the voltage level of a substrate bias, The Claim 1 or 2 characterized by the above-mentioned. Semiconductor integrated circuit device.   The storage table circuit predicts a data amount to be processed in the future from a data amount processed in the past by the circuit function module and maximizes the performance of the circuit function module or the power supply voltage control. 3. The semiconductor integrated circuit device according to claim 1, wherein at least one of the circuit and the substrate bias control circuit is controlled.   3. The semiconductor integrated circuit device according to claim 1, wherein the storage table circuit measures, as a data amount, a time during which data supply to the circuit function module is activated.   3. The semiconductor integrated circuit device according to claim 1, wherein the storage table circuit measures a change amount of data supplied to the circuit function module as a data amount.   3. The storage table circuit stores performance data in the order of short or long data processing time of the circuit function module, or in order of small or large power consumption. Semiconductor integrated circuit device. When there are a plurality of the circuit function modules in the semiconductor integrated circuit chip,
One of the performance measurement circuits is provided in the semiconductor integrated circuit chip,
3. The semiconductor integrated circuit device according to claim 1, wherein the storage table circuit, the clock frequency control circuit, the power supply voltage control circuit, and the substrate bias control circuit are provided for each circuit function module. . When there are a plurality of the circuit function modules in the semiconductor integrated circuit chip,
One bus control circuit is provided, and the bus control circuit measures the number of times the circuit function module uses the bus, and the circuit function module is less frequently used when two or more circuit function modules use the bus simultaneously. 3. The semiconductor integrated circuit device according to claim 1, wherein the bus is used preferentially. In the semiconductor integrated circuit chip, a clock signal having one type of clock frequency and a power signal having one type of voltage are supplied to each circuit function module, and each circuit function module is supplied with the clock frequency control circuit. Divide or multiply the clock signal to supply the clock signal to the circuit function module,
The power supply voltage control circuit steps down or boosts a given power supply signal to supply a power supply voltage to the circuit function module,
3. The semiconductor according to claim 1, wherein the substrate bias control circuit supplies a substrate bias for a pMOS transistor and a substrate bias for an nMOS transistor to the circuit function module by stepping down or boosting an applied power supply signal. Integrated circuit device.

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