JP4512059B2 - Recording method and apparatus for optical disk - Google Patents

Description

  The present invention relates to a technique for recording information on an optical disc in which an auxiliary signal indicating the physical position of a signal track is preformatted in an area different from the signal track, and in particular, records information at a discontinuous recording position on the signal track. The present invention relates to an optical disc recording method and apparatus.

On an optical disc such as a normal compact disc (hereinafter referred to as CD) and a digital versatile disc (hereinafter referred to as “DVD”), signal tracks on which information is recorded are formed in a spiral or concentric form. Has been.
Also, auxiliary signals have been preformatted on the optical disc so that signal tracks can be accessed randomly. This auxiliary signal divides the signal track into unit storage areas of a certain size and indicates the physical positions of these unit storage areas.

  The auxiliary signal is preformatted on the optical disk by two methods, a hard sector method and a soft sector method. According to the former hard sector method, auxiliary signals are preformatted on an optical disc by forming embossed pits in a partial area of a signal track of the optical disc. In this way, on the optical disc (10) on which the auxiliary signal is preformatted, as shown in FIG. 1, concentric or spiral signal tracks (12) are divided into sectors (14) having a fixed length. Each of these sectors (14) includes a sector identification signal section (16) and a main information signal section (18). The sector identification signal section 16 includes a synchronization pattern, an address mark, a track number, and a sector number, and is used as an auxiliary signal that indicates a boundary portion with an adjacent sector and also indicates a physical position of the sector. User information is recorded in the main information signal section (18). Since the hard sector type auxiliary signal occupies a part of the signal track in which user information is recorded, the recording capacity of the optical disk is reduced.

  The recording signal of the optical disk can be enlarged by arranging the latter auxiliary signal of the soft sector system in a wobble area other than the signal track of the optical disk. As shown in FIG. 2, the optical disk on which the auxiliary signal is preformatted in this soft sector method has a groove (22) (hereinafter referred to as a groove track) formed in a spiral or concentric form from the center to the outer periphery of the optical disk. ) Are bent at a constant cycle, and lands (20) (hereinafter referred to as mountain tracks) are arranged between the tracks (22) of these grooves. The auxiliary signal is preformatted in a bent portion (hereinafter referred to as a “wobble area”) on both sides of the groove track (22).

  Such a user information block recorded on a signal track of an optical disc preformatted with a soft sector type auxiliary signal is composed of a user block identification unit and a user block information unit. The user block identification unit includes a synchronization pattern, an address mark, a track number, a block number, and the like as in the case of the hard sector type auxiliary signal. The user block identification unit configured as described above indicates the physical position of the signal track of the optical disc during reproduction. Accordingly, the soft sector type auxiliary signal is mainly used when user information is recorded on the optical disc.

  The auxiliary signal is preformatted on the optical disc in a form synchronized with a clock signal of a predetermined cycle in order to express the transmission speed of user information, that is, the recording speed and the reproducing speed. In other words, the auxiliary signal preformatted on the optical disc includes a clock signal of a certain cycle. The clock signal included in each of the user block identification unit and the hard sector type sector identification signal unit has the same cycle as that of the user information bit, but the clock signal included in the soft sector type auxiliary signal is a bit of the user information. Has a relatively large cycle. That is, the reference clock signal included in the soft sector type auxiliary signal has a lower frequency than the bit of the user information. As a result, the phase of the clock signal recorded on the signal track can change abruptly in an optical disc on which a soft sector type auxiliary signal has been preformatted. When the phase of the clock signal changes abruptly in this way, the optical disc playback apparatus plays back the clock signal having a cycle different from the bit of the user information, so among the user information blocks recorded on the signal track, etc. Some user information blocks will not be played correctly. Such a phenomenon occurs from a recording position (hereinafter referred to as “discontinuous recording position”) on the signal track of the optical disc on which user information is recorded discontinuously in time, and on the signal track of the optical disc. As the number of information files to be recorded increases, the problem occurs more frequently. That is, the discontinuous recording position is determined when the second information file is recorded from an arbitrary position after an arbitrary time after the first information file is recorded over an arbitrary intermediate position from the start position of the signal track. Occurs when new information is overwritten at an arbitrary position in the recorded signal track.

  As shown in FIG. 3, the first user information is recorded in the section (S1) from the left side of the signal track (20 or 22) of the optical disc to the arbitrary point (DCP), and after the next arbitrary period has passed, If the second user information is recorded in the right direction from the point (DCP, that is, the discontinuous recording position), the phase of the recording clock recorded in the signal track (20 or 22) is discontinuous as shown in FIG. 4A. It changes abruptly at the recording position (DCP). This is because the recording clock recorded on the signal track (20 or 22) of the optical disc is generated based on the reference clock signal included in the soft sector type auxiliary signal. This recording clock has a large cycle during a period corresponding to a certain interval from the discontinuous recording position (DCP) as shown in FIG. 4B by the optical disk reproducing apparatus, or corresponds to a certain interval from the discontinuous recording position (DCP) as shown in FIG. 4C. During the period, it is regenerated to have a small cycle. Thus, since the recording clock signal recorded in a certain section from the discontinuous recording position (DCP) on the signal track (20 or 22) is reproduced so as to have a large or small cycle, the user information recorded in that section is recorded. Will not play correctly.

  In order to prevent such an error in the user information at the discontinuous recording position on the signal track of the optical disc, it is called a “variable frequency oscillation (hereinafter referred to as“ VFO ”) signal” at the discontinuous recording position. A method to add clock stabilization information was proposed. Since this clock stabilization information is normally recorded over one sector section from the discontinuous recording position, the signal track of the optical disk is unnecessarily consumed. As a result, the method of adding clock stabilization information has the disadvantage that the recording capacity of the optical disk is significantly reduced as the number of discontinuous recording positions on the signal track of the optical disk increases.

  Accordingly, an object of the present invention is to provide an optical disc capable of recording user information at discontinuous recording positions on a signal track of the optical disc so that the user information is stably reproduced and the recording capacity of the optical disc is increased. It is to provide a recording method and apparatus.

In order to achieve the above object, an optical disk recording method according to the present invention provides auxiliary synchronization in which a signal track of an optical recording medium is divided into unit blocks from an auxiliary signal preformatted on either side of the signal track of the optical recording medium. A step of detecting a signal, and based on the detected auxiliary synchronization signal, clock stabilization information and a user information block including user information and following the clock stabilization information are discontinuous in the signal track of the optical recording medium. A step of recording is provided in a part of the unit block adjacent to the recording position, and the clock stabilization information is recorded with a deviation from the discontinuous recording position .

In this case, the clock stabilization information is recorded while being shifted so as to create a space between the discontinuous recording positions.
The method further includes the step of sequentially recording the next user information block in subsequent unit blocks arranged subsequent to the unit block adjacent to the discontinuous recording position.
The user information block includes auxiliary address information indicating the physical position of the unit block.
The clock stabilization information and the user information block are recorded according to a reference clock synchronized with a frequency derived from the auxiliary signal .

Still another optical disk recording method according to the present invention includes clock stabilization information and user information, and a user information block following the clock stabilization information is adjacent to a discontinuous recording position in a signal track of the optical recording medium. A step of recording in a part of the unit block. In the optical recording medium, the auxiliary signal for dividing the unit block is preformatted on either side of the signal track, and the clock stabilization information is shifted from the discontinuous recording position. And is recorded .

Here, the method further includes a step of sequentially recording the next user information block in subsequent unit blocks arranged subsequent to the unit block adjacent to the discontinuous recording position.
The user information block includes auxiliary address information indicating a physical position of the unit block.
The clock stabilization information and the user information block are recorded according to the frequency of the reference clock synchronized with the frequency derived from the auxiliary signal .

An apparatus for recording data on an optical recording medium according to the present invention records information on a signal track of the optical recording medium or reads an auxiliary signal preformatted on either side of the signal track of the optical recording medium. An optical pickup configured, and an auxiliary signal decoder coupled to the optical pickup and configured to reconstruct an auxiliary synchronization signal dividing the signal track of the optical recording medium into unit blocks from the auxiliary signal; The optical pickup is controlled based on the auxiliary synchronization signal, and the clock stabilization information and the user information block including the user information and following the clock stabilization information are adjacent to the discontinuous recording position in the signal track of the optical recording medium. And a controller configured to record in a unit block, and the clock stabilization information is not recorded from the recording position. It is characterized in that it is recorded.

Here, the controller is configured to control the optical pickup and record the clock stabilization information in such a manner that there is a space between the clock stabilization information and the discontinuous recording position. .
The recording information processing unit may further include a recording information processing unit configured to form a user information block including auxiliary address information indicating a physical position of the unit block.
The controller controls the optical pickup, and is configured to record the clock stabilization information and the user information block in accordance with a reference clock synchronized with a frequency derived from the auxiliary signal .

Still another data recording apparatus according to the present invention includes an optical pickup configured to record information on a signal track of an optical recording medium or to read an auxiliary signal preformatted on either side of the signal track, and an optical pickup And a carrier signal detector configured to detect an auxiliary signal transmitted from the optical pickup and dividing the signal track into unit blocks, and controls the optical pickup based on the detected auxiliary signal, and a clock A controller configured to record the stabilization information and the user information block including the user information and following the clock stabilization information in a unit block adjacent to the discontinuous recording position of the signal track, Controls the optical pickup and records clock stabilization information at a position shifted from the discontinuous recording position. Characterized in that it is configured to.

In this case, a recording information processing unit configured to form a user information block is further provided, and the user information block includes auxiliary address information indicating a physical position of the unit block.
Further, the controller is configured to control the optical pickup and record the clock stabilization information and the user information in accordance with the frequency of the reference clock synchronized with the frequency derived from the auxiliary signal. .

An optical recording medium according to the present invention includes an auxiliary synchronization signal that divides a signal track into unit blocks, and is recorded in an auxiliary signal preformatted on the recording medium and a unit block adjacent to a discontinuous recording position of the signal track. The clock stabilization information and the user information block are recorded, and the clock stabilization information is recorded at a position shifted from the recording position .

In this case, the clock stabilization information is recorded in the unit block so that a space is formed between the clock stabilization information and the discontinuous recording position.
Further, the user information block includes auxiliary address information indicating a physical position of the unit block .

Still another optical recording medium according to the present invention is preformatted on either side of a signal track of the recording medium, an auxiliary signal for dividing the signal track into unit blocks, and a unit adjacent to a discontinuous recording position of the signal track. It has a clock stabilization information and user information block recorded in the block, and the clock stabilization information is recorded at a position deviated from the discontinuous recording position .

In this case, the user information block includes auxiliary address information indicating the physical position of the unit block .

[Action]
With the above configuration, in the present invention, the clock stabilization information is recorded together with the user information in the unit block section adjacent to the discontinuous recording position on the signal track of the optical disc on which the auxiliary signal is preformatted on either side of the signal track. The As a result, the user information recorded in the block section adjacent to the discontinuous recording position on the signal track is reproduced stably, and the recording capacity of the optical disc is increased. In the present invention, a margin section is selectively generated between the discontinuous recording position on the signal track of the optical disc and the clock stabilization information by the phase relationship between the reproduction synchronization signal and the auxiliary synchronization signal included in the auxiliary signal. To be. As a result, the clock stabilization information is recorded in the block section adjacent to the discontinuous recording position so as to be synchronized with the reproduction synchronization signal. The present invention also keeps the recording capacity of the optical disk constant by recording information on the optical disk only when the reference clock is synchronized with the auxiliary clock included in the auxiliary signal, and minimizes the occurrence of errors. Turn into.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS.
FIG. 5 illustrates an optical disk recording apparatus according to an embodiment of the present invention. In FIG. 5, an optical disk recording apparatus includes a spindle motor (26) that rotates an optical disk (24), a servo unit (30) connected to an optical pickup (28), and a motor drive unit connected to the spindle motor (26). is equipped with a (32). The optical pickup (28) irradiates one main light beam (MB) and two auxiliary light beams (SB1, SB2) onto the groove track (22) of the optical disk (24) as shown in FIG. Information is recorded with the light beam (MB), and the auxiliary signal preformatted with the auxiliary light beams (SB1, SB2) is read. The optical pickup (28) is located between the laser diode (LD) and the photodetector (PD) and splits the laser light beam between the optical disc (24) and the beam splitter (BS). The objective lens (OL) installed in is provided. The objective lens (OL) condenses the laser light beam traveling from the beam splitter (BS) toward the optical disc (24). The beam splitter (BS) allows the laser light beam from the laser diode (LD) to irradiate the surface of the optical disk (24) via the objective lens (OL) and reflects the light reflected by the optical disk (24). The light beam travels toward the photodetector (PD) through the sensor lens (SL). The sensor lens (SL) focuses the light beam traveling from the beam splitter (BS) toward the photodetector (PD) and adjusts the focal point by the astigmatism method . The light beam generated by the laser diode (LD) is separated into three light beams (MB, SB1, SB2) by a diffraction grating (GT). Then, the light beams (MB, SB1, SB2) separated by the diffraction grating (GT) pass through the beam splitter (BS) and are tracked in the groove of the optical disc (24) by the objective lens (OL) as shown in FIG. Focused on (22). The light beam (MB, SB1, SB2) reflected by the track (22) in the groove of the optical disk (24) passes through the objective lens (OL) and the beam splitter (BS) and is detected by the sensor lens (SL). Condensed on the surface of PD). The photodetector (PD) converts the auxiliary light beams (SB1, SB2) into electrical signals. The servo unit (30) drives the actuator (ACT) in the optical pickup (28) by an electrical signal from the photodetector (PD) to perform focusing servo, tracking servo, and the like. On the other hand, the motor drive unit (32) adjusts the rotation speed of the spindle motor (26) according to a signal from the servo unit (30).

  The optical disk recording apparatus further includes a carrier signal detector (34) and an auxiliary signal decoder (36) connected in series to the photodetector (PD) of the optical pickup (28). The carrier signal detector (34) detects the carrier signal (Pc) from the electrical signal from the photodetector (PD), and the auxiliary signal decoder (36) detects the auxiliary address (PAdd) and the auxiliary signal from the carrier signal (Pc). The clock (PCLK) and the auxiliary synchronization signal (PYre) as shown in FIG. 6 are decoded. The auxiliary synchronization signal (PYre) divides the signal track (20 or 22) of the optical disc (24) into unit blocks of a certain size, and the auxiliary address (PAdd) indicates the physical position of each unit block. In addition, the optical disk recording apparatus according to the embodiment of the present invention includes a reference synchronization signal generator (38) that inputs an auxiliary synchronization signal (PYre) from an auxiliary signal decoder (36), and stabilization information from a reference clock generator (40). A pseudo synchronous signal generator (42) for inputting a control signal (CVFO) and a VFO signal generator (44) for generating a VFO signal using a reference clock (SCLK) from the reference clock generator (40) are provided. A reference synchronization signal generator (38) generates a reference synchronization signal (SYre) phase-synchronized with the auxiliary synchronization signal (PYre). The reference clock generator (40) generates a reference clock (SCLK) as shown in FIG. 6 whose phase and frequency are synchronized with the auxiliary clock (PCLK) from the auxiliary signal decoder (36). The frequency of the reference clock (SCLK) increases from N times the auxiliary clock (PCLK) to M times the auxiliary clock for a certain period from the start of recording. After this fixed period has elapsed, the frequency of the reference clock (SCLK) again decreases from M times the auxiliary clock (PCLK) to N times the auxiliary clock (PCLK). More specifically, the reference clock (SCLK) corresponds to a section from the discontinuous recording position (DCP) to the position on the signal track (20 or 22) of the optical disc (24) where the recording of the VFO signal is completed. During the period, the frequency changes from M times the auxiliary clock (PCLK) to N times the auxiliary clock (PCLK). After this VFO signal is recorded, the reference clock (SCLK) is a period corresponding to a section from the end position of the section in which the VFO signal is recorded to the end position of the unit block adjacent to the discontinuous recording position (DCP) or a fixed time The frequency gradually decreases from M times to N times the auxiliary clock (PCLK) during a period corresponding to several unit blocks. The reference clock generator (40) is stabilized by using the recording start signal (WRsta) as shown in FIG. 6 from the control unit (50) and the auxiliary synchronization signal (PYre) from the auxiliary signal decoder (36). An information control signal (CVFO) is generated. This stabilization information control signal (CVFO) is generated on the signal track (20 or 22) of the optical disc (24) in which the phase of the clock signal recorded on the signal track (20 or 22) of the optical disc (24) changes rapidly. A VFO signal can be inserted at a discontinuous recording position (DCP). The stabilization information control signal (CVFO) is a signal track of the optical disc (24) as shown in FIG. 6 so that the VFO signal is recorded in a part of the unit block adjacent to the discontinuous recording position (DCP). It has a pulse with a considerably shorter width than the unit block (20 or 22). Further, the reference clock generator 40 has a specific logic (for example, when the reference clock (SCLK) has a frequency in a certain range of multiples, that is, in a range from N times to M times, compared to the auxiliary clock (PCLK). A locking signal (LK) having a high logic) can be generated. The pseudo synchronization signal generator (42) maintains a specific logic (for example, high logic) for a certain period from the end point (for example, the falling edge) of the stabilization information control signal (CVFO). ). This pseudo sync signal (PSre) has a pulse of a specific logic that is narrower than the reference sync signal. For this purpose, the pseudo synchronization signal generator (42) can include a monostable multivibrator.

  Further, the optical disk recording apparatus has a recording information processing unit (46) for inputting user information, and selects a VFO signal from the VFO signal generator (44) and a recording signal from the recording information processing unit (46). In addition, a control switch (SW1) for supplying to the light controller (48) is provided. The recording information processing unit (46) generates user block information by dividing user information by a certain size, and at the head of this user block information, the auxiliary address (PAdd) from the auxiliary signal decoder (36) and pseudo-synchronization The pseudo synchronization signal (PSre) from the signal generator (42) or the reference synchronization signal (SYre) from the reference synchronization signal generator (38) is added to form a user information block. The recording information processing section (46) supplies user information as a recording signal to the control switch (SW1) in accordance with the reference clock (SCLK) from the reference clock generator (40). The user information block including the pseudo-synchronization signal (PSre) is transmitted by the reference clock (SCLK) having a frequency M times that of the auxiliary clock (PCLK), whereby the signal track (20 or 20) of the optical disc (24) is transmitted together with the VFO signal. 22) Recorded in one unit block. That is, the user information block including the pseudo synchronization signal (PSre) has a shorter cycle than the user information block including the reference synchronization signal (SYre) by being temporally compressed. The control switch (SW1) selectively transmits the VFO signal and the recording signal to the optical controller (48) according to the logic state of the stabilization information control signal (CVFO) from the reference clock generator (40). This will be described in detail. The control switch (SW1) is configured such that when the stabilization information control signal (CVFO) maintains a specific logic (ie, high logic), the VFO signal from the VFO signal generator (44). To the light controller (48). On the other hand, when the stabilization information control signal (CVFO) maintains the base logic (for example, low logic), the recording signal from the recording information processing unit (46) is transmitted to the optical controller (48). To do. The optical controller (48) intermittently connects the laser diode (LD) according to the logical value of the output signal of the control switch (SW1), and the user information block is the signal track of the optical disk (24), ie, the mountain track (20) or groove To be recorded on the track (22). At this time, the unit block adjacent to the discontinuous recording position (DCP) of the signal track (20 or 22), that is, the arbitrary portion on the signal track (20 or 22) where the forefront portion of the user information is recorded at the start of recording As shown in FIG. 6, a pseudo synchronization signal (PSre) block identification code and user block information are sequentially recorded in the unit block as well as a VFO signal which is clock stabilization information. On the other hand, a reference sync signal (SYre) block identification code and user block information are recorded in each block section distant from the discontinuous recording position (DCP).

Finally, the control unit (50) controls the operation of the servo unit (30) and the motor drive unit (32), and also controls the operation mode of the light controller (48). The control unit 50 generates a recording start signal (WRsta) having a pulse of a specific logic (for example, high logic) at the start of recording. This recording start signal (WRsta) is supplied to the reference clock generator (40), and VFO which is clock stabilization information from a recording discontinuity point on the signal track (20 or 22) on the optical disk (24) to a certain interval. Allow the signal to be recorded.
Further, the control unit 50 can input a locking signal LK from the reference clock generator 40. The controller (50) selectively enables the recording operation of the light controller (48) according to the logic state of the locking signal (LK). The control unit 50 keeps the recording density of the optical disc 24 constant so that the light controller 48 executes the recording operation only when the locking signal LK maintains a specific logic (for example, high logic). To prevent the occurrence of errors.

FIG. 7 is a block diagram showing in detail the reference clock generator (40) shown in FIG. In FIG. 7, a reference clock generator (40) includes a frequency divider (54) for inputting a reference clock (SCLK) from a voltage controlled oscillator (52) via a first AND gate (62), and the frequency divider. A phase comparator (56) for inputting the output signal of (54) and a frequency comparator (58) are provided. The first AND gate 62 switches the reference clock (SCLK) supplied from the voltage controlled oscillator 52 to the frequency divider 54 by the stabilization information control signal CVFO. The first AND gate 62 prevents the reference clock SCLK from the voltage controlled oscillator 52 from being supplied to the frequency divider 54 when the stabilization information control signal CVFO maintains a high logic. That is, the first AND gate 62 supplies a low logic low signal to the frequency divider 54. As a result, a logic signal of low logic or high logic is also generated in the frequency divider (54). At this time, since the phase comparator (56) compares the phase of the auxiliary clock (PCLK) from the auxiliary signal decoder (36) shown in FIG. 5 with the logic signal from the frequency divider (54), it rapidly increases. A phase error signal having a voltage signal is supplied to an integrator (60). The frequency comparator (58) that compares the frequency of the logic signal from the frequency divider (54) with the auxiliary clock (PCLK) also supplies a frequency error signal having a voltage signal that increases rapidly to the integrator (60).
The integrator (60) integrates the phase error signal from the phase comparator (56) and the frequency error signal from the frequency comparator (58), respectively, and removes the noise signal of the high frequency component contained in these signals. Based on the integrated phase error signal and frequency error signal from the integrator 60, the voltage controlled oscillator 52 changes the frequency of the reference clock SCLK from N times the auxiliary clock PCLK to M times the auxiliary clock PCLK. To suddenly increase. As a result, the frequency of the reference clock (SCLK) suddenly increases from N to M times the auxiliary clock (PCLK) at the rising edge of the clock stabilization information control signal (CVFO), and then the clock stabilization information control signal (CVFO). The auxiliary clock (PCLK) is maintained at M times until the falling edge is designated. On the other hand, when the stabilization information control signal (CVFO) maintains low logic, the first AND gate 62 is supplied with the reference clock SCLK from the voltage controlled oscillator 52 to the frequency divider 54. To. In this case, the frequency divider (54) divides the reference clock (SCLK) from the first AND gate (62) by N. At this time, the phase comparator (56) generates a phase error signal having a voltage signal that is gradually reduced by the phase difference between the auxiliary clock (PCLK) and the divided clock signal from the frequency divider (54). To do. Similarly, the frequency comparator 58 generates a frequency error signal whose voltage gradually decreases due to the difference in frequency between the clock signal from the frequency divider 54 and the auxiliary clock PCLK. Then, the voltage controlled oscillator (52) that inputs the phase error signal and the frequency error signal via the integrator (60) changes the frequency of the reference clock (SCLK) from M times the auxiliary clock (PCLK) to the auxiliary clock (PCLK). Gradually lowers to N times. Accordingly, the frequency of the reference clock (SCLK) is set for a certain period from the falling edge of the clock stabilization information control signal (CVFO) (for example, the signal track (20, 22) in which the clock stabilization information (CVFO) is recorded). During the period from the end position of the upper section to the end position of the unit block where the clock stabilization information is recorded, the auxiliary clock (PCLK) gradually decreases from M times to N times. In addition, this reference clock (SCLK) is supplied to the VFO signal generator (44) and the recording information processing unit (46) shown in FIG. Further, when the divided reference clock signal has a frequency difference within a certain range compared to the auxiliary clock (PCLK), that is, the reference clock (SCLK) has a frequency N times or M times that of the auxiliary clock (PCLK). The frequency comparator 58 generates a locking signal (LK) having a specific logic (eg, high logic). This locking signal (LK) is supplied to the control unit (50) shown in FIG.

  The reference clock generator (40) includes a first latch (64) for inputting a recording start signal (WRsta) from the control unit (50) shown in FIG. 5, and an auxiliary signal decoder (36) shown in FIG. Is further provided with a NAND gate (66) for inputting an auxiliary synchronization signal (PYre). The first latch 64 outputs a high logic output signal to its output terminal (Q) when a specific logic (ie, high logic) recording start signal (WRsta) is input to its set terminal (S). appear. The NAND gate 66 performs a NAND operation on the output signal of the first latch 64 and the auxiliary synchronization signal PYre, and selectively toggles the second latch 68 based on the result. That is, the NAND gate 66 generates a low logic pulse only when both the output signal of the first latch 64 and the auxiliary synchronization signal PYre maintain high logic. The second latch (68) changes the logic signal on its output terminal (Q) from the low logic to the high logic from the rising edge of the low logic pulse from the NAND gate (66). The first and second latches 64 and 68 are initialized by a base logic (ie, low logic) stabilization information control signal (CVFO) applied at its reset terminal (R).

  The reference clock generator (40) has a second AND gate (70) for inputting the reference clock (SCLK) from the voltage controlled oscillator (52), and a counter (72) for inputting the output signal of the second latch (68). And an inverter (74) for inputting a carry signal from the counter (72). The second AND gate 70 receives the reference clock SCLK from the voltage controlled oscillator 52 only when the stabilization information control signal CVFO is maintained at a specific logic (ie, high logic). Transmit to the terminal (CLK). The counter 72 adds and counts with the reference clock (SCLK) supplied from the second AND gate (70) while the logic signal of high logic is applied from the second latch (68) to its reset terminal (R). . The counter 72 generates a high logic carry signal when the count value reaches “K”. Further, after generating the carry signal, the counter (72) stops the counting operation by a low logic signal supplied from the second latch (68) to its reset terminal (R). The inverter (74) inverts the carry signal from the counter (72), and uses the inverted carry signal as a stabilization information control signal (CVFO), the first and second AND gates (62, 70), the first and second This is supplied to the latch (64, 68), the control switch (SW1) and the pseudo synchronization signal generator (42) shown in FIG. As a result, the second latch 68, the second AND gate 70, the counter 72, and the inverter 74 have a certain width from the falling edge of the first auxiliary synchronization signal PYre at the start of recording. It performs the function of a monostable pulse generator that generates a stabilized information control signal (CVFO) having a high logic pulse.

  FIG. 8 illustrates a block of an optical disk recording apparatus according to another embodiment of the present invention. The optical disk recording apparatus according to another embodiment shown in FIG. 8 is different from the optical disk recording apparatus shown in FIG. 5 in the second control switch (SW1) connected between the control switch (SW1) and the optical controller (48). SW2) is further provided. In addition, an optical disk recording apparatus according to another embodiment includes an adaptive reference clock generator (76) instead of the reference clock generator (40) shown in FIG.

This adaptive reference clock generator (76) generates a reference clock ( SCLK ) as shown in FIG. 9 in the same manner as the reference clock generator (40) shown in FIG. 5, and records the reference clock ( SCLK ) as recorded information. The data is supplied to the processing unit (46) and the VFO signal generator (44). As shown in FIG. 9, the adaptive reference clock generator (76) generates a recording start signal (WRsta), and then generates a margin control signal (SY) sequentially arranged from the falling edge of the first auxiliary synchronization signal (PYre). Cspc) and a stabilization information control signal (CVFO). By this margin control signal (Cspc), the second control switch (SW2) selectively connects the recording information processing unit (46) to the light controller (48), thereby causing the signal track (20 or 22) of the optical disc (24). ) So that a blank section where no information is recorded is generated. This blank section is located between the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disc (24) and the clock stabilization information section. That is, in the block section adjacent to the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disk (24), the blank section (SPC), VFO signal (VFO), and pseudo-synchronization as shown in FIG. A signal (PSre), a block identification signal, and user block information are recorded.

  An optical disk recording apparatus according to another embodiment of the present invention reproduces an output signal of a photodetector (PD) in an optical pickup (28) and generates a reproduction synchronization signal (RYre) as an adaptive reference clock generator (76). A reproduction signal processing unit (51) that supplies the signal to the computer may be further provided. In this case, the adaptive reference clock generator (76) changes the logical state of the blank control signal (Cspc) according to the phase relationship between the reproduction synchronization signal (RYre) and the auxiliary synchronization signal (PYre). As shown in FIGS. 10 and 11, the adaptive reference clock generator (76) generates a blank control signal (Cspc) as the base logic (ie, when the phase of the reproduction synchronization signal (SYre) is faster than the auxiliary synchronization signal (PYre)). , Low logic) is maintained so that no blank section appears on the signal track (20 or 22) of the optical disc (24). That is, the unit block adjacent to the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disc (24) has a VFO signal (VFO), a pseudo synchronization signal (PSre), a block identification signal, and user block information. Is recorded. On the other hand, as shown in FIG. 12, when the phase of the reproduction synchronization signal (RYre) is later than the auxiliary synchronization signal (PYre), the adaptive reference clock generator (76) uses the margin control signal (Cspc) as the auxiliary synchronization signal (PYre). From the falling edge to the rising edge of the reproduction synchronization signal (RYre), a high logic is set to generate a blank section on the signal track (20 or 22) of the optical disk (24). That is, the unit block adjacent to the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disc (24) has a blank section (SPC), VFO signal (VFO), and pseudo sync signal as shown in FIG. (PSre), a block identification signal and user block information are recorded.

FIG. 13 is a circuit diagram showing in detail the first embodiment of the adaptive reference clock generator (76) shown in FIG. 13, the adaptive reference clock generator 76 is connected in series between the NANAD gate 66 and the second latch 68 when compared with the reference clock generator 40 shown in FIG. 3 latch (78), second counter (84) and second inverter (86), and a second frequency divider connected in series between the clock terminal (CLK) of the voltage controlled oscillator (52) and the second counter (84) (80) and a third AND gate (82).
The adaptive reference clock generator (76) is stabilized by the reference clock (SCLK) from the voltage controlled oscillator (52) and the first inverter (74) instead of the first AND gate (62) shown in FIG. A fourth AND gate (88) for inputting the information control signal (CVFO) and the margin control signal (Cspc) from the second inverter (86) is provided.

The third latch (78) changes the logic signal on its output terminal (Q) from low logic to high logic at the rising edge of the output signal of the NAND gate (66). That is, after the recording start signal (WRsta) is generated as shown in FIG. 9, the third latch 78 generates a high logic output signal in response to the falling edge instruction of the auxiliary synchronization signal (PYre) input first. become. The second frequency divider (80) divides the reference clock (SCLK) from the voltage controlled oscillator (52) by N and supplies the divided reference clock to the third AND gate (82). The third AND gate 82 is a divided reference from the second divider 80 only while the margin control signal (Cspc) as shown in FIG. 9 maintains a specific logic (ie, high logic). The clock is transmitted to the clock terminal (CLK) of the second counter (84).
The second counter (84) is added by the divided reference clock from the third AND gate (82) while a high logic signal is applied from the third latch (78) to its reset terminal (R). Count. The second counter 84 generates a high logic carry signal when the count value reaches "L". Also, after the second counter 84 generates a carry signal, the count operation is stopped by a low logic signal supplied from the third latch 78 to its own reset terminal R. . The second inverter (86) inverts the carry signal from the second counter (84), and uses the inverted carry signal as the margin control signal (Cspc), the third and fourth AND gates (82, 88), the third latch. (78) and the second control switch (SW2) as shown in FIG. As a result, the third latch 78, the third AND gate 82, the second counter 84, and the second inverter 86 start from the falling edge of the first auxiliary synchronization signal (PYre) at the start of recording. It performs the function of a monostable pulse generator that generates a margin control signal (Cspc) having a high logic pulse of a certain width. Based on the margin control signal (Cspc), the second latch 68 determines the generation point of the stabilization information control signal (CVFO). That is, the second latch 68 starts the count operation of the first counter 72 from the falling edge of the margin control signal Cspc from the second inverter 86, and then the first latch 74 receives the signal from the first inverter 74. By initializing with the low logic stabilization information control signal (CVFO), the stabilization information control signal (CVFO) has a high logic with a certain width from the falling edge of the margin control signal (Cspc) as shown in FIG. To.

  On the other hand, the fourth AND gate 88 is supplied with a reference clock (SCLK) supplied from the voltage controlled oscillator 52 to the first frequency divider 54 by the margin control signal (Cspc) and the stabilization information control signal (CVFO). Switch. The fourth AND gate 88 is a reference clock (SCLK) from the voltage controlled oscillator 52 when any one of the margin control signal (Cspc) and the stabilization information control signal (CVFO) maintains a high logic. Is not supplied to the first frequency divider (54). That is, the fourth AND gate 88 is configured such that the reference clock (SCLK) is supplied to the first frequency divider 54 during the period when the margin signal and the VFO signal are recorded on the signal track 20 or 22 of the optical disc 24. Do not supply. In contrast, when the margin control signal (Cspc) and the stabilization information control signal (CVFO) maintain low logic, the fourth AND gate (88) receives the reference clock (SCLK) from the voltage controlled oscillator (52). The first frequency divider (54) is supplied.

  The second and third latches (68, 78), the third and fourth AND gates (82, 88), the frequency divider (80), the second counter (86) and the second inverter (86) other than the adaptive type The description of the operation of the remaining components of the reference clock generator (76) is the same as in FIG.

FIG. 14 is a circuit diagram showing in detail the second embodiment of the adaptive reference clock generator (76) shown in FIG. The adaptive reference clock generator (76) shown in FIG. 14 is the same as the adaptive reference clock generator (76) shown in FIG. 13 except that the fourth AND gate (88) is replaced with a clock adjuster (90). Has a circuit configuration. This clock (90) is a reference clock for a certain period from the time when the margin control signal (Cspc) is enabled (for example, the period corresponding to the section from the discontinuous recording point to the point where one unit block is completed). The frequency of (SCLK) is kept constant at M times the auxiliary clock (PCLK). For this purpose, the clock adjuster 90 performs a constant cycle during a period corresponding to one unit block after the margin control signal Cspc from the second inverter 86 is changed from low logic to high logic. The reference clock (SCLK) transmitted from the voltage controlled oscillator (52) to the first frequency divider (54) is removed one by one.
In this case, the phase error signal generated from the phase comparator (56) and the frequency error generated from the frequency (58) increase once and then decrease every fixed cycle. Then, the voltage controlled oscillator (52) responding to the phase error signal and the frequency error signal adjusts the phase and frequency of the reference clock (SCLK) so that the phase of the reference clock (SCLK) matches the phase of the auxiliary clock (PCLK). In addition, the frequency of the reference clock (SCLK) is kept constant at M times that of the auxiliary clock (PCLK). On the contrary, when the margin control signal (Cspc) and the stabilization information control signal (CVFO) maintain the base logic (low logic), the clock adjuster (90) generates the reference clock (SCLK) from the voltage controlled oscillator (52). Is transmitted to the first frequency divider (54) as it is to maintain the frequency of the reference clock (SCLK) constant at N times the auxiliary clock (PCLK).

FIG. 15 is a circuit diagram illustrating in detail the clock adjuster 90 shown in FIG.
In FIG. 15, the clock adjuster (90) is an OR gate for inputting the stabilization information control signal (CVFO) and the margin control signal (Cspc) from the first and second inverters (74, 86) shown in FIG. 92) and a fifth AND gate (94), a third frequency divider (96) and an exclusive OR (hereinafter referred to as “hereinafter referred to as“ the reference clock (SCLK) ”from the voltage controlled oscillator (52) shown in FIG. A gate (98) is provided. The OR gate 92 ORs the stabilization information control signal (CVFO) and the margin control signal (Cspc) and generates a pulse signal that maintains the high logic during the high logic period of the two signals. The fifth AND gate (94) transmits the reference clock (SCLK) to the clock terminal (CLK) of the third counter (100) while the output signal of the OR gate (92) maintains a high logic. The third counter (100) counts the number of clock signals supplied to its clock terminal (CLK) from the fifth AND gate (94). On the other hand, the third frequency divider (96) divides the reference clock (SCLK) by a constant frequency division ratio (for example, 4), and the frequency-divided reference clock is passed through the sixth AND gate (102). Supply to 4 counter (104). The fourth counter (104) counts the divided reference clock number from the sixth AND gate (102). The count value of the third counter (100) and the count value of the fourth counter (104) are compared by a comparator (106). When the two count values are the same, the comparator (106) supplies a high logic comparison signal to the sixth AND gate (102), so that the reference clock divided from the third divider (96) is supplied. The fourth counter (104) and the XOR gate (98) are not supplied. That is, the sixth AND gate (102) uses the XOR gate (the divided reference clock) from the start of recording until the count value of the fourth counter (104) becomes the same as the count value of the third counter (100). 98). The XOR gate (98) inverts the phase of the reference clock (SCLK) by 180 ° every time the frequency-divided reference clock from the sixth AND gate (102) maintains a high logic, thereby causing the XOR gate (98) shown in FIG. One cycle of the reference clock is eliminated from the reference clock (SCLK) supplied to the one-frequency divider (54). The frequency division ratio of the third frequency divider (96) includes a period corresponding to the combination of the high logic width of the margin control signal (Cspc) and the high logic width of the stabilization information control signal (CVFO), and the period of the unit block. Determined by the ratio of

  FIG. 16 is a circuit diagram showing in detail the third embodiment of the adaptive reference clock generator (76) shown in FIG. The adaptive reference clock generator (76) includes a first frequency divider (54) for inputting the reference clock (SCLK) from the voltage controlled oscillator (52) via the first AND gate (108), and a first frequency divider. A phase comparator (56) for inputting an output signal of the frequency divider (54) and a frequency comparator (58) are provided. The first AND gate (108) switches the reference clock (SCLK) according to a switching control signal. The first AND gate (108) prevents the reference clock (SCLK) from the voltage controlled oscillator (52) from being supplied to the first frequency divider (54) when the switching control signal maintains a high logic. That is, the first AND gate 108 supplies a low logic signal to the first frequency divider 54. As a result, a logic signal of low logic or high logic is also generated in the first frequency divider (54). At this time, since the phase comparator (56) compares the phase of the auxiliary clock (PCLK) from the auxiliary signal decoder (36) shown in FIG. 8 with the logic signal from the first frequency divider (54), it rapidly increases. A phase error signal having a voltage signal is supplied to an integrator (60). The frequency comparator (58) that compares the frequency of the logical signal from the first frequency divider (54) with the auxiliary clock (PCLK) also supplies a frequency error signal having a voltage signal that rapidly increases to the integrator (60). The integrator (60) integrates the phase error signal from the phase comparator (56) and the frequency error signal from the frequency comparator (58), respectively, and removes the high frequency component noise signal contained in these signals. Based on the integrated phase error signal and frequency error signal from the integrator 60, the voltage controlled oscillator 52 changes the frequency of the reference clock SCLK from N times the auxiliary clock PCLK to M times the auxiliary clock PCLK. To suddenly increase. As a result, the frequency of the reference clock (SCLK) rapidly increases from N times to M times the auxiliary clock (PCLK) at the rising edge of the switching control signal, and then increases to M of the auxiliary clock (PCLK) until the falling edge of the switching control signal. To keep the fold. When the switching control signal maintains low logic, the first AND gate (108) supplies the reference clock (SCLK) from the voltage controlled oscillator (52) to the first frequency divider (54). In this case, the first frequency divider (54) divides the reference clock (SCLK) from the first AND gate (108) by N. At this time, the phase comparator 56 outputs a phase error signal having a voltage signal that gradually decreases due to the phase difference between the auxiliary clock PCLK and the divided clock signal from the first frequency divider 54. appear. Similarly, the frequency comparator (58) also generates a frequency error signal whose voltage gradually decreases due to the frequency difference between the clock signal from the first frequency divider (54) and the auxiliary clock (PCLK). Then, the voltage controlled oscillator (52) that inputs the phase error signal and the frequency error signal via the integrator (60) changes the frequency of the reference clock (SCLK) from M times the auxiliary clock (PCLK) to the auxiliary clock (PCLK). Gradually lower to N times. Thus, the frequency of the reference clock (SCLK) is set for a certain period from the falling edge of the switching control signal (that is, the position on the signal track (20 or 22) where the recording of the clock stabilization information ends) (for example, the clock). The period gradually decreases from M times to N times the auxiliary clock (PCLK) during a period corresponding to a section up to the end position of the unit block in which the stabilization information is recorded. The recording clock (SCLK) is supplied to the VFO signal generator (44) and the recording information processing unit (46) shown in FIG. Further, the frequency comparator 58 is configured such that the divided reference clock has a certain frequency difference compared to the auxiliary clock (PCLK), that is, the reference clock (SCLK) is N times or more than the auxiliary clock (PCLK). When the frequency is M times, a locking signal (LK) having a specific logic (for example, high logic) is generated. This locking signal (LK) is supplied to the control unit (50) shown in FIG.

  The adaptive reference clock generator (76) includes a first latch (110) for inputting a recording start signal (WRsta) as shown in FIGS. 10 to 12 from the controller (50) shown in FIG. A NAND gate (112) for inputting the auxiliary synchronization signal (PYre) from the auxiliary signal decoder (36) shown in FIG. 8, and a reproduction synchronization signal (RYre) from the reproduction signal processing unit (51) shown in FIG. The second AND gate 116 is further provided. The first latch (110) outputs a high logic output signal to its output terminal (Q) when a specific logic (ie, high logic) recording start signal (WRsta) is input to its set terminal (S). appear. The NAND gate 112 performs an NAND operation on the output signal of the first latch 110 and the auxiliary synchronization signal PYre and selectively toggles the second latch 114 based on the result. The NAND gate 112 generates a low logic pulse when the output signal of the first latch 110 and the auxiliary synchronization signal PYre maintain a high logic. The second latch (114) changes the signal on its output terminal (Q) from low logic to high logic at the rising edge of the low logic pulse from the NAND gate (112). On the other hand, the second AND gate 116 performs an AND operation on the output signal of the first latch 110 and the reproduction synchronization signal RYre, and the output signal of the first latch 110 maintains the high logic, that is, recording starts. At this time, the reproduction synchronization signal (RYre) is passed only when the first user information block is recorded on the signal track (20 or 22) of the optical disc (24).

  The adaptive reference clock generator (76) includes a second frequency divider (118) connected in series to the voltage controlled oscillator (52), a third AND gate (120), a first counter (122), and a first counter (122). 1 inverter (124). The second frequency divider (118) divides the reference clock (SCLK) from the voltage controlled oscillator (52) into a constant frequency division ratio (N), and the frequency-divided reference clock is converted into a third AND gate (120). To supply. The third AND gate 120 receives the frequency-divided reference clock from the second frequency divider 118 while the margin control signal Cspc maintains a specific logic (ie, high logic). To the clock terminal. The first counter 122 is driven by the divided reference clock supplied from the third AND gate 120 while a high logic signal is applied from the second latch 114 to its reset terminal R. Add and count. The first counter 122 generates a high logic carry signal when the count value reaches “L”. In addition, after the first counter 122 generates a carry signal, the count operation is stopped by a low logic signal supplied to the reset terminal R from the second latch 114. As another method, the first counter 122 receives a low logic reproduction synchronization signal (RYre) from the second AND gate 116, that is, at the end of the first reproduction synchronization signal (RYre). Specific logic (eg, high logic) can be generated. Accordingly, whether the carry signal generated from the first counter 122 maintains only a high logic or is a certain width from the end of the auxiliary synchronization signal (PYre), that is, smaller than N × L reference clock cycles? Or it has a base logic (eg, low logic) pulse of the same width. The first inverter 124 inverts the carry signal from the first counter 122, and uses the inverted signal as a margin control signal (Cspc) as the third AND gate 120 and the second control shown in FIG. Supply to the switch (SW2). This margin control signal (Cspc) generates a pulse of a specific logic (ie, high logic) depending on the operation mode of the first counter (122), that is, the phase relationship between the reproduction synchronization signal (RYre) and the auxiliary synchronization signal (PYre). You will have selectively. The margin control signal (Cspc) maintains the base logic (ie, low logic) when the auxiliary synchronization signal (PYre) is terminated after the reproduction synchronization signal (RYre) is terminated as shown in FIGS. In this case, no blank section is generated in the signal track (20 or 22) of the optical disc (24). On the other hand, when the reproduction synchronization signal (RYre) ends later than the end point of the auxiliary synchronization signal (PYre) as shown in FIG. 12, the margin control signal (Cspc) has a pulse of specific logic. At this time, the pulse of the margin control signal (Cspc) has a width corresponding to a period from the end point of the auxiliary synchronization signal (PYre) to the end point of the reproduction synchronization signal (RYre). Thus, when a specific logic pulse is present in the margin control signal (Cspc), a margin section (SPC) corresponding to the width of the specific logic pulse is generated on the signal track (20 or 22) of the optical disc (24). Will come to be.

  Further, the adaptive reference clock generator (76) is connected in series to the fourth AND gate (126) and the third latch (128) connected in series to the output terminal of the second AND gate (116), and to the voltage controlled oscillator (52). The fifth AND gate 130, the second counter 132, and the second inverter 134 are provided. The fourth AND gate (126) performs an AND operation on the margin control signal (Cspc) from the first inverter (124) and the output signal of the second AND gate (116), and the third latch (128) is selectively selected based on the result. Toggle. The fourth AND gate 126 is a falling edge of the margin control signal (Cspc), that is, the end point of the margin control signal (Cspc) or the falling edge of the output signal of the second AND gate 116, that is, the first reproduction synchronization signal ( At the end of (RYre), the third latch (128) is toggled. At this time, the output signal of the third latch 128 changes from low logic to high logic. The fifth AND gate (130) receives the reference clock (SCLK) from the voltage controlled oscillator (52) for the second counter (132) only while the stabilization information control signal (CVFO) maintains a specific logic (ie, high logic). To the clock terminal (CLK). The second counter 132 is a reference clock (SCLK) supplied from the fifth AND gate 130 while a high logic signal is applied from the third latch 128 to its reset terminal R. The addition is counted by. The second counter 132 generates a high logic carry signal when the count value reaches “K”. After generating the carry signal, the second counter 132 stops the counting operation by a low logic signal supplied from the third latch 128 to its reset terminal R. The second inverter 134 inverts the carry signal from the second counter 132 and uses the inverted carry signal as a stabilization information control signal (CVFO) as a fifth AND gate 130 and a third latch 128. And supplied to the first control switch (SW1) and the pseudo synchronization signal generator (42) shown in FIG. When the margin control signal (Cspc) includes a specific logic pulse as shown in FIG. 12, the stabilization information control signal (CVFO) has a specific logic for a certain period from the end of the margin control signal (Cspc). (For example, high logic) is maintained. On the other hand, when the margin control signal (Cspc) does not include a specific logic pulse as shown in FIGS. 10 and 11, the stabilization information control signal (CVFO) is the falling edge of the first reproduction synchronization signal (RYre), That is, the high logic is maintained for a certain period from the end point. Then, the third latch 128 is initialized by a base logic (ie, low logic) stabilization information control signal (CVFO) applied to its reset terminal (R).

  The adaptive reference clock generator (76) includes a fourth latch (138) toggled by an output signal of the first NAND gate (112), and an OR gate (136) for inputting a stabilization information control signal (CVFO). A third inverter (140) is provided. The OR gate 136 performs an OR operation on the margin control signal (Cspc) and the stabilization information control signal (CVFO), and initializes the output signal of the second latch (114) based on the calculated result. The fourth latch (138) is the same as the second latch (114), and the rising edge of the low logic pulse from the first NAND gate (112), that is, the end of the first auxiliary synchronization signal (PYre) at the start of recording. The signal on its output terminal (Q) is changed from low logic to high logic from the time point. The fourth latch 138 supplies its output signal as a switching control signal to the first AND gate 108 and the second NAND gate 144. The third inverter 140 inverts the stabilization information control signal (CVFO) and applies the inverted stabilization information control signal to the toggle terminal (T) of the fifth latch 142. The fifth latch 142 is supplied to the toggle terminal T from the third inverter 140 and is inverted. The rising edge of the stabilization information control signal, that is, the end point of the stabilization information control signal CVFO. Generates a logic signal of high logic at its output terminal (Q). The output signal of the fifth latch (142) is supplied to the first latch (110) and the second NAND gate (144). The second NAND gate 144 performs an AND operation on the output signal of the first latch 110, the output signal of the fourth latch 138, and the output signal of the fifth latch 142 to generate a low logic pulse. The output signals of the first, fourth and fifth latches (110, 138, 142) are initialized by the low logic pulse from the second NAND gate (144). As a result, the output signal of the first latch (110) maintains the high logic from the rising edge of the recording start signal (WRsta), that is, from the recording start time to the falling edge of the stabilization information control signal (CVFO). The switching control signal generated from the fourth latch 138 is a falling edge of the auxiliary synchronization signal (PYre), that is, a falling edge of the stabilization information control signal (CVFO) from the end point, that is, the stabilization information control signal (CVFO). High logic is maintained until the end of). On the other hand, the output signal of the fifth latch 142 has a high logic pulse form because the fifth latch 142 forms a circulation loop with the second NAND gate 144. The first AND gate (108) switches the reference clock (SCLK) supplied from the voltage controlled oscillator (52) to the first frequency divider (54) according to the switching control signal. The first AND gate (108) prevents the reference clock (SCLK) from the voltage controlled oscillator (52) from being supplied to the variable frequency divider (54) when the switching control signal maintains a high logic. When the switching control signal maintains low logic, the reference clock (SCLK) from the first AND gate (108) voltage controlled oscillator (52) is supplied to the variable frequency divider (54).

  FIG. 17 is a circuit diagram showing in detail the fourth embodiment of the adaptive reference clock generator (76) shown in FIG. The adaptive reference clock generator (76) shown in FIG. 17 is the adaptive reference clock generator of the third embodiment shown in FIG. 16, except that the first AND gate (108) is replaced with a clock adjuster (146). The circuit configuration is the same as that of the vessel (76). The clock adjuster (146) has a reference clock (SCLK) for a certain period from when the switching control signal is enabled (for example, during a period from a discontinuous recording position (DCP) to a point where one unit block is terminated). ) Is maintained at a constant M times the auxiliary clock (PCLK). For this purpose, the clock controller 146 changes the voltage control oscillator (52) every fixed cycle while the switching control signal from the fourth latch (138) changes from low logic to high logic and then hits one unit block. ) To the first frequency divider 54 are removed one by one. In this case, the phase error signal generated by the phase comparator (56) and the frequency error signal generated by the frequency comparator (58) are increased once every fixed cycle and then decreased. Then, the voltage controlled oscillator (52) responding to the phase error signal and the frequency error signal adjusts the phase and frequency of the reference clock (SCLK) so that the phase of the reference clock (SCLK) becomes the phase of the auxiliary clock (PCLK). In addition, the frequency of the reference clock (SCLK) is maintained at a constant M times that of the auxiliary clock (PCLK). Then, the clock adjuster (146) removes the OR gate (92) for inputting the stabilization information control signal (CVFO) and the margin control signal (Cspc) from the circuit elements of the clock adjuster (90) shown in FIG. Instead, it can be realized by supplying the switching control signal from the fourth latch (138) in FIG.

[The invention's effect]
As described above, in the present invention, the clock stabilization information is recorded together with the user information in the block section adjacent to the discontinuous recording position on the signal track of the optical disc in which the auxiliary signal is preformatted in a different area from the signal track. The As a result, the user information recorded in the block section adjacent to the discontinuous recording position on the signal track is reproduced stably, and the recording capacity of the optical disc increases.

  Further, according to the present invention, a margin section is selectively generated between the discontinuous recording position on the signal track of the optical disc and the clock stabilization information by the phase relationship between the reproduction synchronization signal and the auxiliary synchronization signal included in the auxiliary signal. Is done. As a result, the clock stabilization information is recorded in the block section adjacent to the discontinuous recording position so as to be synchronized with the reproduction synchronization signal.

  In addition, the present invention records information on the optical disk only when the reference clock is synchronized with the auxiliary clock included in the auxiliary signal, thereby keeping the recording capacity of the optical disk constant and minimizing the occurrence of errors. Can be

1 is a diagram schematically illustrating an optical disc on which a hard sector type auxiliary signal is pre-formatted. 1 is a diagram schematically illustrating an optical disc on which a soft sector type auxiliary signal is pre-formatted. 3 shows a state where information is recorded discontinuously on the signal track of the optical disc shown in FIG. FIG. 4 shows a clock signal recorded on the signal track shown in FIG. 3 and a reproduced state of the clock signal. 1 is a block diagram of an optical disc recording apparatus according to an embodiment of the present invention. FIG. 6 is an output waveform diagram for each portion shown in FIG. 5. FIG. 6 is a detailed circuit diagram of the reference clock generator shown in FIG. 5. It is a block diagram of the optical disk recording device by other embodiment of this invention. FIG. 9 is an output waveform diagram of each part illustrated in FIG. 8. FIG. 9 is an output waveform diagram of each part illustrated in FIG. 8. FIG. 9 is an output waveform diagram of each part illustrated in FIG. 8. FIG. 9 is an output waveform diagram of each part illustrated in FIG. 8. FIG. 9 is a detailed circuit diagram of the first embodiment of the adaptive reference clock generator shown in FIG. 8. FIG. 9 is a detailed circuit diagram of a second embodiment of the adaptive reference clock generator shown in FIG. 8. FIG. 15 is a detailed circuit diagram of the variable phase delay device illustrated in FIG. 14. FIG. 9 is a detailed circuit diagram of a third embodiment of the adaptive reference clock generator shown in FIG. 8. FIG. 9 is a detailed circuit diagram of a fourth embodiment of the adaptive reference clock generator shown in FIG. 8.

Explanation of symbols

10, 24 ... optical disc, 12 ... signal track,
14 .... sector, 16 .... sector identification signal part,
18 .... main information signal part, 20 .... mountain track,
22 ······· Tracks of grooves · 26 ····· Spindle motor,
28... Optical pickup 30... Servo unit 32... Motor drive unit 34.
36... Auxiliary signal decoder, 38... Reference sync signal generator,
40... Reference clock generator, 42... Pseudo sync signal generator,
44... VFO signal generator, 46...
48 .... Light controller, 50 .... Control part,
51... Reproduction signal processing unit 52... Voltage controlled oscillator
54... First frequency divider 56... Phase comparator
58... Frequency comparator 60... Integrator 62, 108.
64, 110... The first latch,
66, 112... NAND gate,
68, 114... Second latch,
70, 116... Second AND gate,
72, 122... First counter,
74, 124 ... the first inverter,
76... Adaptive reference clock generator,
78, 128... Third latch, 80, 118... Second divider,
82, 120 .... Third AND gate,
84, 132 ... the second counter,
86, 134... Second inverter,
88, 126... 4th AND gate,
90, 146... Clock adjuster,
92... OR gate,
94, 130 .... 5th AND gate,
96 ..... 3rd frequency divider, 98 .... XOR gate,
100 ... 3rd counter, 102 ... 6th AND gate,
104 ······· fourth counter 106 ······ Comparator
138... 4th latch, 140... 3rd inverter,
142 ... 5th latch

Claims (21)

A recording method for recording data on an optical recording medium,
Detecting an auxiliary synchronization signal for dividing the signal track of the optical recording medium into unit blocks from the auxiliary signal preformatted on either side of the signal track of the optical recording medium;
Based on the detected auxiliary synchronization signal, clock stabilization information and a user information block including user information and succeeding the clock stabilization information are adjacent to a discontinuous recording position in the signal track of the optical recording medium. A step of recording in a part of the unit block
The clock stabilization information is recorded with a deviation from the discontinuous recording position.   2. The recording method according to claim 1, wherein the clock stabilization information is recorded while being shifted so that a space is formed between the clock stabilization information and the discontinuous recording position.   2. The recording method according to claim 1, further comprising the step of sequentially recording the next user information block in subsequent unit blocks arranged following the unit block adjacent to the discontinuous recording position.   The recording method according to claim 1 or 2, wherein the user information block includes auxiliary address information indicating a physical position of the unit block.   3. The recording method according to claim 1, wherein the clock stabilization information and the user information block are recorded in accordance with a reference clock synchronized with a frequency derived from the auxiliary signal. Recording the clock stabilization information and the user information block including the user information and following the clock stabilization information in a part of the unit block adjacent to the discontinuous recording position in the signal track of the optical recording medium. ,
In the optical recording medium, an auxiliary signal for dividing into unit blocks is preformatted on either side of the signal track,
A recording method for recording data on an optical recording medium, wherein the clock stabilization information is recorded while being shifted from the discontinuous recording position.   7. The recording method according to claim 6, further comprising a step of sequentially recording next user information blocks in subsequent unit blocks arranged subsequent to the unit blocks adjacent to the discontinuous recording position.   The recording method according to claim 6, wherein the user information block includes auxiliary address information indicating a physical position of the unit block.   9. The recording method according to claim 6, wherein the clock stabilization information and the user information block are recorded in accordance with a frequency of a reference clock synchronized with a frequency derived from the auxiliary signal. An apparatus for recording data on an optical recording medium,
An optical pickup configured to record information on a signal track of the optical recording medium, or to read an auxiliary signal preformatted on either side of the signal track of the optical recording medium;
An auxiliary signal decoder coupled to the optical pickup and configured to reconstruct an auxiliary synchronization signal dividing the signal track of the optical recording medium into unit blocks from the auxiliary signal;
Based on the reconstructed auxiliary synchronization signal, the optical pickup is controlled, and clock stabilization information and a user information block that includes user information and follows the clock stabilization information are signaled from the optical recording medium. A controller configured to record in a unit block adjacent to a discontinuous recording position in a track, and
The clock stabilization information is recorded while being shifted from the discontinuous recording position.   The controller is configured to control the optical pickup to record the clock stabilization information in such a manner that a space exists between the clock stabilization information and the discontinuous recording position. The apparatus according to claim 10.   The apparatus according to claim 10 or 11, further comprising a recording information processing unit configured to form the user information block including auxiliary address information indicating a physical position of the unit block.   The controller is configured to control the optical pickup and record clock stabilization information and a user information block in accordance with a reference clock synchronized with a frequency derived from the auxiliary signal. Item 12. The apparatus according to Item 10 or 11. An optical pickup configured to record information on a signal track of an optical recording medium, or to read an auxiliary signal preformatted on either side of the signal track;
A carrier signal detector coupled to the optical pickup, configured to detect the auxiliary signal transmitted from the optical pickup and dividing the signal track into unit blocks;
Based on the detected auxiliary signal, the optical pickup is controlled, and clock stabilization information and a user information block including user information and following the clock stabilization information are recorded at discontinuous recording positions of the signal track. And a controller configured to record in a unit block adjacent to
An apparatus for recording data on an optical recording medium, wherein the controller is configured to control the optical pickup to record the clock stabilization information at a position shifted from the discontinuous recording position. .   15. The apparatus according to claim 14, further comprising a recording information processing unit configured to form the user information block, wherein the user information block includes auxiliary address information indicating a physical position of the unit block. .   The controller is configured to control the optical pickup to record the clock stabilization information and the user information in accordance with a frequency of a reference clock synchronized to a frequency derived from the auxiliary signal. Or the apparatus of 15. An auxiliary sync signal that divides the signal track into unit blocks and preformatted on either side of the signal track of the recording medium;
Clock stabilization information and user information block recorded in a unit block adjacent to a discontinuous recording position of the signal track, and
It said clock stabilization information optical recording medium, characterized in Tei Rukoto recorded at a position shifted from the discontinuous recording position. Said clock stabilization information, the clock stabilization information to the optical recording medium according to claim 17, wherein Tei Rukoto recorded in said unit block to allow a space between the discontinuous recording position.   The optical recording medium according to claim 17 or 18, wherein the user information block includes auxiliary address information indicating a physical position of the unit block. An auxiliary signal preformatted on either side of the signal track of the optical recording medium and dividing the signal track into unit blocks;
Clock stabilization information and user information block recorded in a unit block adjacent to a discontinuous recording position of the signal track, and
It said clock stabilization information optical recording medium, characterized in Tei Rukoto recorded at a position shifted from the discontinuous recording position.   21. The optical recording medium according to claim 20, wherein the user information block includes auxiliary address information indicating a physical position of the unit block.

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