JP4512028B2 - Transmitter - Google Patents

Description

  The present invention relates to a transmitting device used for, for example, a mobile phone or the like that collects sound with a plurality of microphones and processes a transmitted sound signal.

  The transmitters represented by mobile phones have been dramatically improved in functionality, and have been used in ways that were previously unthinkable. For example, a videophone function or the like requires a call mode in which conversation is performed while viewing the image with the transmitter device away from the mouth. For example, as shown in FIG. 19 (Non-Patent Document 1), a technique for suppressing three-dimensional noise by providing three microphones in a mobile phone 180 has been studied for the purpose of adapting to such a call style. Non-Patent Document 1 compares the size of the same frequency component on the spectrum with a spatial filter formed by combining the outputs of three microphones, and selectively selects the spectrum component that satisfies the condition, so It is related with the technique which suppresses the disturbance sound from the right-and-left both sides and the front of a person.

As described above, many directivity controls using a plurality of microphones are known not only for portable devices but also for fixed transmitters. In either case, an analog signal from a microphone is converted into a digital signal (Analog to Digital Conversion, hereinafter referred to as A / D conversion), and audio processing is performed by a CPU (IC chip).
Adaptation of a sound source separation method using a spatial filter and band selection to a cellular phone (Autumn Research Meeting of the Acoustical Society of Japan 2005.9.27)

  Conventionally, however, an analog signal from a microphone is transmitted as it is to a CPU that performs audio processing as an analog signal. A mobile phone or the like is a lump of electromagnetic noise because various functions are mounted at high density. Among them, there are various frequency signals such as the system clock frequency that controls the entire radio function and the frequency (common, segment) of the control signal for the display panel. These various frequency signals are mounted at high density and at the same time Is considerably flowing, and the power supply current becomes large. The noise of the frequency and the power supply current noise often have an influence on the transmission line of an inevitable voice system (microphone and receiver), which is inevitably long due to the convenience of component arrangement. In addition, this influence on the voice system is immediately recognized as noise by the user, which is a problem in terminal design.

In order to increase the noise margin of the microphone signal, a method of performing A / D conversion near the microphone, converting it to a digital signal and transmitting it to the CPU is also conceivable, but as soon as the microphone signal is converted into a digital signal. In addition, there is a problem that the number of wires increases because the signal is converted into a signal of 8 bits to 16 bits, for example. In addition to the case where various functions are mounted in high density as described above, for example, in a transmitter using a plurality of microphones fixedly arranged in a relatively wide space, there is a problem of the influence of external noise and an increase in the number of wirings. was there.
The present invention has been made in view of such points, and by performing A / D conversion with ΣΔ oversampled low amplitude encoding, the noise margin is improved without increasing the number of wirings, and then directing is performed. An object of the present invention is to provide a transmitter capable of performing sex control.

The transmitter of the present invention includes a plurality of microphones that output digital signals based on oversampled low amplitude resolution encoding, a delay / gain setting unit having control values for delay processing and gain processing, and the digital signal as input. is a 1bit signal processing unit for performing directivity control by the delay processing and gain processing based on the control value for at least one of that de Ijitaru signal, it adds the digital signal which the 1bit signal processing section outputs A digital processing unit including an addition processing unit that converts the summation signal into one analog voltage value and an A / D conversion processing unit that converts the summation signal into a digital signal.

According to the transmitter of the present invention, the analog output signal of the microphone can be transmitted with a small number of signal lines digitized by oversampled low-amplitude coding, so that the noise margin can be improved with a small number of wires. I can do it. In addition, since the low-amplitude coded digital signal can be easily subjected to delay control and gain control, ambient noise can be suppressed with a simple configuration, and call quality can be improved.
In addition, the output of the digital processing unit of the present invention can be input to the A / D conversion input of an off-the-shelf voice processing IC chip equipped with an A / D converter, and the ambient noise can be reduced in a very simple and inexpensive manner. Repression is possible.

Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same components are denoted by the same reference numerals, and the description will not be repeated.
[Basic configuration of the present invention]
FIG. 1 shows an example of the appearance of the transmitter of the present invention. FIG. 1 is a foldable mobile phone, for example, and shows the front in an open state. A display panel 12 and a receiver 14 are disposed on the upper case 10 side. In the lower case 16, a keyboard 18 and a cursor key 19, microphones A and B are arranged at both ends of the short side of the upper case side of the lower case 16, and a microphone C is arranged at the central portion of the opposite end. A signal line is derived from each of the microphones A, B, and C, and a microphone output is output to these signal lines as a digital signal subjected to oversampled low amplitude encoding. As described above, since the audio device is arranged at the end of the case (housing), the wiring from there is also long.

  FIG. 2 shows an example of a ΣΔ1-bit A / D converter 20 (hereinafter, ΣΔ is omitted) that converts the analog signals output from the microphones A, B, and C into digital signals near the microphones, and the operation thereof will be briefly described. The 1-bit A / D converter 20 includes a subtractor J, an analog integrator K, and a quantizer L. When the subtractor J subtracts the analog input from the output of the quantizer L and the analog input changes in the increasing direction, the quantizer L outputs a positive pulse. When the analog input changes in the decreasing direction, the quantizer L outputs a negative pulse. When the analog input value does not change, the quantizer L alternately outputs positive and negative pulses. By setting the sampling frequency (pulse interval) to about 2 to 3 MHz, the analog input signal waveform can be faithfully A / D converted.

FIG. 3 shows an example of the functional configuration of the transmitter of the present invention. The 1-bit encoded signals A, B, and C (1-bit digital signals) of the microphones A, B, and C digitized into pulse trains by the oversampled 1-bit A / D converter shown in FIG. To the 1-bit signal processing unit 31.
In order to perform directivity control for each of the 1-bit encoded signals A, B, and C from the microphone, the 1-bit signal processing unit 31 adds delay and weighting to each 1-bit encoded signal A, B, and C (what is weighting)? Addition is performed based on the set value from the delay / gain setting unit 32.

The pulse trains from the microphones to which the delay and gain are added in the 1-bit signal processing unit 31 are added in the addition processing unit 33a of the addition digital processing unit 33 and converted into one analog voltage value. The one analog voltage value is converted into, for example, a PCM (Pulse Code Modulation, hereinafter abbreviated as PCM) signal having an amplitude of 16 bits and 8 KHz in an A / D conversion processing unit 32b built in the audio processing IC 34 (corresponding to the CPU described above). Converted.
The audio signal converted into the PCM signal is subjected to processing such as compression and recognition in the audio encoding transmission processing unit 35. This voice processing IC corresponds to a baseband IC if it is a mobile phone, for example.

The 1-bit encoded signals A, B, and C from the microphone may be input to the 1-bit signal processing unit 31 via the selection switch 36 that is switched on / off by the control signal from the delay / gain setting unit 32. Good. For example, if the 1-bit encoded signal A is separated by the selection switch 36, the sensitivity to the sound of the sound source coming from the microphone A side can be lowered.
Of course, it is an extreme directivity control method to cut off the signal from the microphone by the selection switch 36. Normally, the 1-bit signal processing unit 31 performs the process for each 1-bit encoded signal A, B, C. Then, directivity control is performed by performing control for adding delay and processing for adding gain.

Assume that the amount of delay and gain for the 1-bit encoded signals A, B, and C from the microphones A, B, and C input to the 1-bit signal processing unit 31 are the same, and the speaker of the mobile phone 1 bit encoded signals A, B, and C are signals having the same timing and the same amplitude.
For example, if the delay amount of the 1-bit encoded signal A from the microphone A is increased more than the 1-bit encoded signal B from the microphone B, the sound wave that reaches the lower case 16 of the mobile phone from a certain position is delayed on the microphone A side. Processed. In this case, even if the speaker speaks from the front direction of the lower case 16 as described above, it seems that the sound source is generated from the microphone B side by an amount corresponding to the delay time. Further, if a gain is added to the 1-bit encoded signal B, the tendency can be further emphasized. Conversely, this means that the directivity of the microphone of the mobile phone is directed to the microphone B side.

By utilizing this principle, in the embodiment shown in FIG. 1, since microphones are arranged at both ends of the short side of the lower case 16, each of the 1-bit encoded signals A, B, and C from each microphone is provided. By performing delay addition control and gain addition control, it is possible to rotate the overall sound collection directivity characteristic of the microphones A, B, and C by 360 °.
A control value for controlling the directivity is set in the delay / gain setting unit 32. The control value may be given to the directivity control means 32a in advance. For example, when the cursor key 19 side is set to the 12 o'clock position of the timepiece dial and the position of the microphone C is set to the 6 o'clock position, the control value can be easily set to the 9 o'clock direction, the 3 o'clock direction, or the like. .

Alternatively, the output signal of the digital processing unit 30 may be fed back and the control amount may be adaptively generated in the adaptive control unit 37. Alternatively, the control amount may be generated by directly evaluating the signal from each microphone, and the 1-bit signal processing unit 31 may be controlled by the control amount. As for this control method, various methods have been studied and known as shown in Non-Patent Document 1, and a description thereof will be omitted here.
In the transmitter of the present invention, since the output signal of each microphone is digitized by oversampled low amplitude encoding, the control can be easily performed. Hereinafter, an embodiment of the control method will be shown and the operation will be described.
The A / D conversion processing unit 33b constituting the addition digital processing unit 33 has been described using an A / D converter built in the audio processing IC 34, but the present invention is not necessarily limited to this configuration. When realizing the transmitter of the present invention by using a voice processing IC that does not include an A / D converter, or a voice processing IC that does not ensure the required accuracy with the built-in A / D converter. As shown in FIG. 3, the addition digital processing unit 33 may be provided outside the audio processing IC 34, as the addition processing unit 33 a and the A / D conversion processing unit 33 b are indicated by broken lines.

Whether the built-in A / D converter is used or provided externally is a design matter determined based on hardware conditions and required specifications. In general, the use of the built-in A / D converter can realize the transmitter of the present invention at low cost.
Since the output signal of the addition processing unit 33a shown in FIG. 3 is an analog signal of an oversampled, for example, directivity-controlled acoustic signal, the signal is directly connected to the acoustic regenerator 38 as indicated by a broken line ( It is also possible to realize a sound regenerator by using an amplifier (if necessary).

[First embodiment]
[Example 1]
FIG. 4 shows a first embodiment of the 1-bit signal processing apparatus 30 according to the present invention. FIG. 4 shows an embodiment in which delay control and gain control are performed on two 1-bit encoded signals A and B. A 1-bit encoded signal A which is a digital signal of a pulse train is input to a 1-channel 1-bit signal processing unit (hereinafter abbreviated as 1Ch signal processing unit) 40a, and a 1-bit encoded signal A is input to a 2Ch signal processing unit 40b. Each of the Ch signal processing units 40a and 40b includes a series connection of variable delay devices 41a and 41b and variable width ternary converters 42a and 42b. The amount of delay added to the 1-bit encoded signal by the variable delay devices 41a and 41b varies depending on the delay control signals 30da and 30db from the delay / gain setting unit 32 shown in FIG.

Further, the gain added by the variable width ternary converters 42a and 42b to the output signals of the variable delay devices 41a and 41b varies depending on the gain control signals 30ga and 30gb. The output signals of the Ch signal processing units 40a and 40b are converted into one voltage value by the analog addition smoother 43 and transmitted to the A / D conversion processing unit 33b.
The variable delay devices 41a and 41b are simply delayed by an input digital signal using a flip-flop (hereinafter referred to as FF) or a shift register configured by connecting FFs in series. It is the same as the delay device. Therefore, the description is omitted.

In the present invention, since the output signal of the microphone is digitized by oversampled low amplitude encoding, the gain control method can be easily configured with respect to the prior art. In the first embodiment shown in FIG. 4, the positive polarity pulse generated when the analog output signal output from the microphone changes in the increasing direction and the negative polarity pulse generated when the analog output signal changes in the decreasing direction. The pulse width is changed according to the control amount.
When it is desired to increase the gain, the pulse width is widened. Conversely, when the gain is desired to be decreased, the pulse width is narrowed. As a result, it is possible to control the level of one voltage value output from the analog addition smoother 43.

Thus, gain control can be realized with a very simple configuration. FIG. 5 shows a more specific example of the first embodiment shown in FIG. The 1-bit encoded signals A and B are input to the 1Ch and 2Ch signal processing units 40a and 40b, respectively. Since the 2Ch signal processing unit 40b is exactly the same as the configuration of 40a, a detailed configuration is omitted. The explanation will be given only for the 1Ch side.
The positive and negative pulse train digital signals to which the delay is added in the variable delay device 41a is input to the ± distributor 50 constituting the variable width ternary converter 40a. The ± distributor 50 is composed of, for example, two operational amplifiers (hereinafter abbreviated as OP), and distributes positive and negative pulses and converts them into positive pulses.

The operation will now be described with reference to FIG. 6 which is an operation time chart of FIG. The output signal of the variable delay device 41a obtained by adding a delay to the 1-bit encoded signal A is, for example, a pulse train composed of positive and negative pulses as shown in FIG. The positive polarity pulse is directly connected to the clock terminal C of the delay type FF (hereinafter referred to as DFF) 51a as the positive polarity pulse at OP1. The negative pulse is inverted by OP2 and connected to the clock terminal C of the DFF 51b.
Since the D terminal of the DFF 51a is connected to the potential of the positive power supply, the Q terminal of the DFF 51a becomes logic level 1 (the voltage level of the positive power supply, hereinafter referred to as “1”) at the falling timing of the positive pulse 61. . When the Q terminal of the DFF 51a is “1” and the next positive pulse 62 arrives, a pulse 52a ₋₁ is generated in the AND gate 52a that takes the logical product of the output terminal of OP1 and the Q terminal of the DFF 51a.

Since the output terminal of the AND gate 52a is connected to the set terminal (hereinafter abbreviated as S) of the RS latch, the Q output of the RS latch is "1" as soon as the pulse 52a- ₁ is generated. become. When the Q output of the RS latch is set to “1”, the gate 55a connected to the clock terminal C of the preset counter 56a that determines the pulse width of the positive pulse opens, and starts counting with the frequency signal f1. The frequency signal f1 is a frequency signal supplied from the output port terminal of the audio processing IC 34, for example, and is a frequency signal faster than the 1-bit encoded signals A and B. The specific value is determined by the resolution of gain control performed by the Ch signal processing unit.

Immediately before the preset counter 56a starts counting with the frequency signal f1, the one-shot pulse generator 57a generates a preset pulse 58a having a narrow time width at the moment when the pulse 52a- ₁ rises. When the preset pulse 58a is generated, the preset circuit 59a sets the gain control signal 30ga from the delay / gain setting unit 32 to the preset counter 56a.
In the example of FIG. 5, the preset counter 56a is, for example, an octal binary counter, and a 3-bit gain control signal 30ga is set by a preset pulse 58a. Such an operation can be realized by setting the frequency of the frequency signal f2 that determines the pulse width of the preset pulse generated by the one-shot pulse generator 57a higher than the frequency signal f1. Similarly to the frequency signal f1, the frequency signal f2 is a frequency signal supplied from an output port terminal of the audio processing IC 34, for example.

For example, if the gain control signal 30ga is a binary number 8, the preset counter 56a generates eight carry signals by counting eight frequency signals f1. The Q terminal for generating the carry signal of the preset counter 56a is connected to the reset (Reset, hereinafter abbreviated as R) terminal of the RS latch, so that it becomes "1" at the rising edge of the pulse 52a- ₁ . The output signal of the Q terminal of the RS latch 54a changes to “0” (logic level 0, negative voltage of the power supply) by the carry signal of the preset counter 56a.
The Q output terminal of the RS latch 54a that changes the pulse width according to the value of the gain control signal 30ga is connected to the non-inverting input + of OP3. In OP3, since the inverting input terminal − is connected to the ground potential which is an intermediate potential between the positive power source and the negative power source, the positive polarity pulse having the pulse width generated at the Q output terminal of the RS latch 54a is added. To 33a.

  OP3 outputs the positive pulse to the addition processing unit 33a only when it is generated continuously with the pulses 61 and 62 at the output of the ± distributor 50 as shown in FIG. As shown in FIG. 6, after the pulse 62, for example, when a negative pulse is generated at the output of OP2, the AND gate 53a that takes the logical product of the Q terminal of the DFF 51a and the output terminal of OP2 immediately resets the DFF 51a. Therefore, the Q terminal of the RS latch 54a reset by the preset counter 56a remains "0" even when the next positive pulse 64 comes.

The same applies to the negative pulse, and the Q terminal of the DFF 51b that has become “1” at the rising timing of the negative pulse 63 is the pulse that follows the negative pulse 63 is the positive pulse 64. This is because the AND gate 53a taking the logical product of the Q terminal and the output terminal of OP1 immediately resets the DFF 51a.
The Q terminal of the DFF 51 b reset by the positive pulse 64 becomes “1” at the falling timing of the next negative pulse 65. When the negative terminal pulse 66 is continuously generated while the Q terminal of the DFF 51b is “1”, a pulse 52b ₋₁ is generated in the AND gate 52b that performs an AND operation between the output terminal of OP2 and the Q terminal of the DFF 51b.

When the pulse 52b- ₁ is generated, the Q terminal of the RS latch 54b is set to "1". The pulse width set to “1” varies depending on the value of the gain control signal 30ga from the delay / gain setting unit 32, which is exactly the same as the above-described operation. Therefore, the reference numeral of the configuration on the negative pulse side is represented as b, and the same number is the same and the description is omitted. For example, 56b is written for the preset counter 56a on the positive pulse side.
Since the negative pulse whose pulse width is changed by the negative pulse gain control signal 30ga is input to the inverting input terminal − of OP4, it is the same width as the pulse width generated at the Q terminal of the RS latch 54b, and the ground potential. The negative polarity pulse having a lower negative voltage is output to the addition processing unit 33a.

  The addition processing unit 33a is a known addition circuit using OP5, and the output voltage Vo can be expressed by Vo = − (Vp / R1 + Vm / R2) Rf. Rf is a feedback resistor connected between the inverting input terminal-and the output terminal of OP5. For example, by setting R1 connected between the output terminal of OP3 and the inverting input terminal of OP5 and R2 connected between the output terminal of OP4 and the inverting input terminal of OP5 to the same value, The smoothing capacitor 60 connected between the output terminal of OP5 and the ground potential can be charged with the result of weighting (increasing gain) the positive and negative pulses by the gain control signal 30ga from the gain setting unit 32.

As described above, when the positive pulse continues, the positive pulse Vp is output to the smoothing capacitor 59 when the positive pulse and the negative pulse are alternately generated. When the negative pulse continues, the negative pulse Vm is supplied. I can do it. Accordingly, the smoothing capacitor 60 can be charged with the voltage resulting from the gain control performed by the gain control signal 30ga from the delay / gain setting unit 32.
The description of the 1-bit encoded signal B side is omitted because it is the same operation, but as shown in FIG. 5, the positive pulse Vp2 and the negative pulse Vm2 of the 2Ch signal processing unit 40b are respectively connected through resistors R3 and R4. By connecting to the inverting input terminal − of OP5, the result of delay / gain control of the output signal of the different microphone B can be charged to one smoothing capacitor 60.

The voltage of the smoothing capacitor 60 is converted into, for example, a 16-bit, 8 KHz PCM signal by the A / D converter 33b, and the voice encoding transmission processing unit 35 performs voice processing.
Thus, according to the transmitter of the present invention, directivity control of a plurality of microphones can be performed with a relatively simple configuration. Furthermore, since the output of the microphone is transmitted after being digitized by oversampled low-amplitude coding near the microphone, the noise margin can be improved.

[Example 2]
FIG. 7 shows a second embodiment which is another embodiment of the 1-bit signal processing device 30 of the present invention. In the second embodiment shown in FIG. 7, gain control is performed with variable amplitude as compared to the first embodiment shown in FIG. 4. The only difference from the first embodiment is that the gain control is composed of variable amplitude converters 71a and 71b. Other configurations are exactly the same.
FIG. 8 shows an example of a gain control method using variable amplitude, and its operation will be described. An AND gate 52a that generates a positive pulse is connected to a non-inverting input terminal + of OP3, and an output terminal of an AND gate 52b that generates a negative pulse is connected to an inverting input terminal-of OP4.
Since the second embodiment performs gain control by varying the amplitude, there is no configuration for varying the pulse width in the first embodiment. Instead, a new configuration is added between the outputs of OP3 and OP4 and the inverting input terminal of OP5.

The output voltage levels of OP3 and OP4 in the second embodiment are set, for example, to a fraction of the absolute value of both positive and negative power supplies. The pulse widths of the positive and negative pulses are the same values as the 1-bit encoded signals A and B. The positive pulse Vp suppressed to a fraction of the power supply voltage is connected to one input terminal of the analog switches 80a, 81a, 82a, 83a. In the analog switches 80a to 83a, the control terminal C is "1" and the other output terminal and the input terminal are connected with a low resistance, and the control terminal C is "0" and open, that is, the resistance between the input and output is low. It is an element that becomes infinite.
Between the other output terminal of the analog switch 80a and the non-inverting input terminal − of OP5, a resistor R84a, between the analog switch 81a, a resistor R85a, between the analog switch 82a, a resistor R86a, an analog switch A resistor R87a is connected to 83a.

The control terminal C of each analog switch 80a to 83a is connected with the decoded signal of the decoder 88 that converts, for example, a 2-bit gain control signal 30ga, which is a control signal from the delay / gain setting unit 32, into four control signals. ing.
When the 2-bit gain control signal 30ga is binary 0 _B (B is Binary), the D0 output terminal of the decoder 88 becomes "1". D1 when the 1 _B is, D2 when the _{2 B} becomes the D3 is "1" when the _{3 B.}
The D0 terminal of the decoder 88 is connected to the control terminal C of the analog switch 80a, D1 is connected to the control terminal C of the analog switch 81a, D2 is connected to 82a, and D3 is connected to the control terminal C of 83a.

In this state, the resistance R84a is set to the same value as the feedback resistance Rf, the resistance R85a is set to 1/2 of Rf, the resistance R86a is set to 1/4 of Rf, and the resistance R87a is set to 1/8 of Rf. . Then, as described above, the output voltage Vo of the addition processing unit 33a formed of the addition circuit can be expressed by the relationship Vo = − (Vp / R1 + Vm / R2) Rf. Therefore, when the 2-bit gain control signal 30ga is 0 _B , smoothing is performed. The output voltage Vo of the OP5 that charges the capacitor 59 is 1 time the positive polarity pulse Vp, 2 times when the gain control signal 30ga is 1 _B , 4 times when the gain control signal 30ga is 2 _B , and 3 times the gain control signal 30ga. _{When B,} the amplitude can be changed to 4 times.
Since the negative pulse side has exactly the same configuration, the reference symbol is represented by b, and the same components are designated by the same numbers, and the description thereof is omitted. As described above, according to the transmitter of the present invention, gain control by variable pulse amplitude can be performed with a very simple configuration.

[Example 3]
FIG. 9 shows a third embodiment which is another embodiment of the 1-bit signal processing device 30 of the present invention. In the third embodiment shown in FIG. 9, gain control is performed by a pulse counter with respect to the first embodiment shown in FIG.
As apparent from the above description, the 1-bit encoded signals A and B are digital signals based on pulse trains. Therefore, the output signal of the microphone can be converted into a PCM signal by counting the pulse trains for a certain period of time. Is possible.
In the first and second embodiments, a part of the analog circuit using OP is used, but by doing so, the present invention can be configured entirely by digital circuits. The difference from the second embodiment is that the gain control is changed to the variable frequency converters 91a and 91b and the analog addition smoother 43 of the first and second embodiments is replaced with a pulse counter smoother 92.

Others are the same, and the number of positive and negative pulses generated for one pulse signal to which delay is added by the variable delay devices 41a and 41b is determined by the gain control signal from the delay / gain setting unit 32. The pulse is changed and counted by a pulse counter smoother 92 which is an up / down counter for a predetermined time.
The pulse counter smoother 92 counts the pulse train of the 1-bit encoded signal for a certain period of time, and converts it into a digital signal having a 16-bit amplitude, for example. That is, the output is converted into a 16-bit PCM signal. The reason why the PCM signal is fed back by the feedback line 92a is to prevent a count value from being biased when the monotonous increase or decrease is caused and the count range becomes too large. For example, an operation of manipulating the count value at a constant rate is performed such that a count value of, for example, 1/10 of the monotonically increasing amount is subtracted.

FIG. 10 shows a functional configuration example in which the third embodiment of FIG. 9 is made more specific, and the operation will be described. The digital processing unit 30 receives a 1-bit encoded signal A from the microphone A and a 1-bit encoded signal B from the microphone B. Hereinafter, the description on the 1-bit encoded signal B side is the same as that on the 1-bit encoded signal A side, and therefore will be omitted.
The 1-bit encoded signal A is added with a delay based on the delay control signal 30da from the delay / gain setting unit 32 in the variable delay device 41a, and is transmitted to the ± distributor 50a. The ± distributor 50a has the same configuration as the ± distributor 50 composed of OP1 and OP2 shown in FIG. 5, and distributes the 1-bit encoded signal A to the positive pulse and the negative pulse.
The positive pulse distributed by the ± distributor 50a is connected to the + input terminal of the frequency variable device 100a, and the negative pulse is connected to the − input terminal. The ± distributor 50a includes a simple combinational logic circuit including the decoder 88 and gate shown in FIG. For example, when the 2-bit gain control signal 30ga from the delay / gain setting section 32 is binary 0 _B (B is binary, binary), the D0 output terminal of the decoder 88 becomes "1". D1 when the 1 _B is, D2 when the _{2 B} becomes the D3 is "1" when the _{3 B.} The frequency variable device 100a can be configured with each decode terminal (output terminal) of the decoder 88 already described in FIG. 8 and a simple gate.

Since it is a simple configuration, the description will be made without particularly illustrating. For example, if the logical product of the D0 output terminal of the decoder 88 and fa which is the same frequency signal as the positive and negative pulses is taken, one positive pulse Vp or negative pulse Vm is generated for one positive and negative pulse. It can be made.
When the frequency signal obtained by ANDing with each output terminal of the decoder 88 is doubled with respect to the frequency of the positive / negative pulse, it is two with respect to one positive / negative pulse, and when it is quadrupled, one positive / negative pulse. In contrast, four positive pulses Vp or negative pulses Vm can be generated. Similarly, the positive pulse Vp2 and the negative pulse Vm2 are generated on the 1-bit encoded signal B side.

  The OR of the Vp of the frequency variable device 100a and the Vp2 of the frequency variable device 100b on the signal B side is taken by the OR gate 101, and the output signal is input to the upcount input terminal U of the U / D counter 92. Similarly, the OR of the outputs Vm and Vm2 of each frequency generator on the negative pulse side is taken by the OR gate 102 and inputted to the downcount input terminal D of the U / D counter 92. By doing so, it is possible to convert a digital signal of a pulse train, which is an oversampled low amplitude resolution encoded signal whose gain is controlled by the frequency of pulse generation, to a PCM signal by the U / D counter 92.

Note that the timings of the positive and negative pulses Vp and Vm output from the frequency variable devices 100a and 100b, respectively, and Vp2 and Vm2 must be different. At exactly the same timing, the U / D counter 92 cannot accurately count. Shifting the timing can be realized by a simple logic circuit, and is not specifically illustrated. Also, the specific configuration of the U / D counter 92 is a general counter and is not specifically illustrated and described.
As described above, the gain control of the transmitter of the present invention can be performed with all digital circuits. An example in which the gain control method of the present invention is realized by varying the pulse width in the first embodiment, varying the pulse amplitude in the second embodiment, and varying the frequency of the number of pulses in the third embodiment is shown. In any configuration, the analog output signal of the microphone is converted into a digital signal composed of a pulse train by oversampled low amplitude encoding, and then the delay control and gain control are performed, so that the conversion to the conventional PCM signal is performed. Since it can be realized with a simple configuration, directivity control of a plurality of microphones can be easily realized.

  The first to third embodiments described above are examples for showing that the gain control of the present invention can be performed by variable pulse width, variable pulse amplitude, and variable pulse frequency. This invention is not limited. A digital signal composed of a pulse train by oversampled low amplitude coding is subjected to gain control by any of variable pulse width, variable pulse amplitude, variable pulse frequency, and directivity control of a plurality of microphones is all of the present invention. It is included in the technical idea.

[Example 4]
The above-described embodiment has been described by using an example in which digital signals obtained by over-sampling and low-amplitude encoding of signals from a plurality of microphones are transmitted by separate wires. It can be easily understood that reducing such wiring reduces the number of places affected by noise, which is advantageous for improving the noise margin.

  A plurality of wires for transmitting the 1-bit encoded signal can be made into one by time-division-multiplexing the signal, and an example thereof is shown in FIG. Analog signals from the microphones A and B are input to the 1-bit A / D converters 110a and 110b of the multiplexing unit 110, respectively. The 1-bit A / D converter 110a is sampled with a sampling clock α which is a frequency signal of about 2 MHz, for example. The 1-bit A / D converter 110b is sampled with a signal obtained by inverting the sampling clock α. FIG. 12 shows an operation time chart of FIG. When the sampling clock α is “1”, the 1-bit A / D converter 110a is activated, and when it is “0”, the 1-bit A / D converter 110b is activated. That is, the 1-bit A / D converters 110a and 110b are activated alternately with a duty of 50%.

Therefore, the signals of the microphones A and B are alternately transmitted to the common signal line 111 that is the output signal line of the OR gate 110C that takes the logical sum of the output signals of both. The common signal line 111 is connected to the D terminals of the DFFs 112a and 112b constituting the separation unit 112.
By making the clock signal C of the DFF 112a an α × β signal with the frequency signal β that is a frequency twice the sampling clock α, the DFF 112a holds the signal on the common signal line 111 at the rising timing. At the rise timing of the α × β signal, since the 1-bit A / D converter 110a connected to the microphone A is activated, the DFF 112a holds the digital signal output on the microphone A side.

By setting the clock signal C of the DFF 112b to α￣ × β (the symbol A￣ means inversion of A), the DFF 112b holds the signal on the common signal line 111 at the rising timing. Since the 1-bit A / D converter 110b connected to the microphone B is activated at the rising timing of the α￣ × β signal, the DFF 112b holds the digital signal output on the microphone B side. The separated digital signals can be handled as 1-bit encoded signals A and B, respectively.
Since multiplexing and demultiplexing can be easily performed in this way, wiring necessary for a 1-bit A / D converter can be combined into one. As a result, since the number of wirings can be reduced, the noise margin can be improved, and since the number of wirings can be reduced, it is possible to obtain a cost reduction effect by reducing the number of parts and assembly steps.

The concept of FIG. 11 can be applied to a case where a larger number of microphones are fixedly arranged in a relatively wide space. An example is shown in FIG. FIG. 12 shows an example in which a transmitter according to the present invention is incorporated in a curtain 120 attached to a window or the like of a room. A large number of elements 122 a to 122 n each composed of a microphone and a 1-bit A / D converter are distributed and arranged on the entire surface of the curtain 120 hung on the curtain rail 121, and these elements are connected by a common signal line 123. Other control lines 124 indicated by broken lines are wired along the common signal line 123. The other control lines 124 include, for example, a power supply line that supplies power to each element and a sampling clock α.
Even in such a case, according to the transmitter of the present invention, it is possible to reduce the number of wires and improve the noise margin.

[Second Embodiment]
In the first embodiment described above, the description has been given with the 1-bit encoded signal digitized by the 1-bit A / D converter. However, it is well known that an A / D converter based on the ΣΔ oversample low amplitude resolution encoding technique can increase the number of bits to about 3 bits. When amplitude accuracy is required, a case of 2 bits or 3 bits is also assumed. In that case, control values for delay control and gain control may be set according to the weight of each bit. The embodiment is shown below as a 2-bit example.

[Example 1]
FIG. 13 shows a first embodiment in which the gain of an encoded signal digitized by 2-bit A / D conversion is controlled by a variable width converter. Since the signals from the microphones A and B are sent as 2-bit encoded signals, the Ch signal processing units 40a and 40b described with reference to FIG. 4 can control the lower-order encoded signals according to the bit weights. 1 bit A / D conversion is provided with two variable delays and variable width converters 41a0 and variable width converters 42a0, and a high-order encoded signal is controlled by a variable delay unit 41a1 and variable width converter 42a1. This is different from the embodiment of FIG.

  The output pulse width of the upper variable width ternary variable converter 42a1 is originally designed to be doubled with respect to the output of the variable width ternary converter 42a0 which outputs the lower weight pulse of the bit weight. In addition, the gain amount is also controlled by changing the pulse width. In other words, the width of the pulse that can be varied by controlling the amount of gain can be halved with respect to the pulse width of the upper bit variable converter 42a1. The upper digit pulse width may be controlled to be twice (2 Ws) the lower digit pulse width Ws. Other operations are the same as those in FIG. 4 described above. Changing the pulse width to twice can be realized by simply changing the specific example shown in FIG. 5, and therefore no specific example is shown.

[Example 2]
FIG. 14 shows an example in which 2-bit weighting is performed with amplitude and gain control is performed with variable pulse width. The amplitude 2h of the variable width ternary converters 130a1 and 131b1 that perform gain control of the upper digits of the digital signals A and B is twice the amplitude h of the variable width ternary converters 130a0 and 131b0 that perform gain control of the lower digits. The amplitude is set. In this state, gain control is performed by varying the pulse width according to the gain control signal.

[Example 3]
FIG. 15 shows an example in which all weights in weighted addition processing of encoded signals digitized by 2-bit A / D conversion are distinguished by amplitude control. The variable amplitude converters 71a and 71b shown in FIG. 7 for explaining the case of 1-bit A / D conversion are different from those shown in FIG. 15 in that they are replaced with variable amplitude quaternary converters 140a and 140b that output 2-bit weights. That is, in FIG. 8 illustrating the specific operation of FIG. 7, the outputs of OP3 and OP4 that generate the positive polarity pulse and the negative polarity pulse are binary values of “1” and “0”, but are variable. The amplitude quaternary converters 140a and 140b generate positive and negative pulses having four values “00”, “01”, “10”, and “11”. In this way, it is possible to cope with the increase in the number of bits.

[Example 4]
FIG. 16 shows an example in which 2-bit weighting is adjusted by the frequency of pulses. The upper digit has a frequency twice that of the lower bit. The variable frequency converters 91a and 91b in FIG. 9 for explaining the case of 1-bit A / D are the same as the lower bit variable frequency converters 150a0 and 150b0, the upper bit variable frequency converters 150a1 and 150b1 in FIG. The difference is that it is composed of two variable frequency converters. The upper bit variable frequency converters 150a1 and 150b1 are designed so as to generate twice as many pulses as the lower bit variable frequency converters 150a0 and 150b0. The output signal may be input to the pulse counter smoother 92 via an OR gate having an increased input terminal as shown in FIG.

[Example 5]
FIG. 17 summarizes the upper and lower digits, obtains a count value for each, and then doubles the upper digits to add them to the lower digits. For the higher order digital signal A, variable delay devices 41a1, 41b1 and variable frequency converters 91a1, 91b1 are connected in series, and for digital signal B, variable delay devices 41a0, 41b0 and variable frequency converters 91a0, 91b0 are also connected. Connected in series.

The output signals of the upper digit variable frequency converters 91a1 and 91b1 are counted by the upper digit pulse counter smoother 92a, and the lower digit variable frequency converters 91a0 and 91b0 are output by the lower digit pulse counter smoother. The counter 92b counts. The PCM signal of the pulse counter smoother 92a for the upper digit is doubled by the doubler 160 (simple 1-bit shift) and added to the PCM signal of the pulse counter smoother 92b for the lower digit by the adder 161. The PCM signal output from the adder 161 becomes the directivity-controlled audio data.
In this way, it is possible to configure the upper and lower digits separately.

As described above, the transmitter of the present invention can cope with the increase in the number of bits.
The above-described embodiments have been described in the form of performing speech encoding transmission processing in the speech processing IC 34 after all have been converted into one PCM signal. However, delay / gain control may be performed after a plurality of microphones and respective digital signals are converted into PCM signals. An example is shown in FIG.

  The example shown in FIG. 18 implements the present invention by inputting a digital signal obtained by over-sampled low-amplitude coding of a microphone analog signal directly to a port of an audio processing IC or the like that does not have an existing A / D converter. It is. A feature of this configuration is that it can be configured with an off-the-shelf IC and no special hardware is required. That is, the digital signal of the pulse train input to the IC port is counted by software and converted into a PCM signal, and then the delay / gain control is performed by the digital signal processing unit 171.

The figure which shows an example of the external appearance of the transmitter of this invention. The figure which shows an example of (SIGMA) (DELTA) 1bit A / D converter. The figure which shows the function structural example of the transmitter of this invention. The figure which shows Example 1 of the 1-bit signal processing apparatus 30 of this invention. The figure which shows the function structural example which made Example 1 of FIG. 4 more concrete. The figure which shows the operation | movement time chart of the function structure of FIG. The figure which shows Example 2 of the 1-bit signal processing apparatus 30 of this invention. FIG. 6 is a diagram illustrating an example of a gain control method using variable amplitude according to the second embodiment. The figure which shows Example 3 of the 1-bit signal processing apparatus 30 of this invention. FIG. 10 is a diagram illustrating a functional configuration example that is a more specific example of the third embodiment. FIG. 11A is a diagram illustrating a functional configuration of a fourth embodiment in which a plurality of wirings are time-division multiplexed into one. FIG.11 (b) is a figure which shows the operation | movement time chart of Fig.11 (a). The figure which shows the example by which many microphones were fixedly arrange | positioned in the comparatively wide space. The figure which shows Example 1 which carries out gain control of the encoding signal digitized by 2 bit A / D conversion with a variable width converter. The figure which shows Example 2 which carries out gain control of the encoding signal digitized by 2 bit A / D conversion with a variable width converter. The figure which shows Example 3 which carries out gain control of the encoding signal digitized by 2 bit A / D conversion with a variable width converter. The figure which shows Example 4 of this invention which adjusts 2-bit weighting with the frequency of a pulse. The figure which shows Example 5 of this invention which adjusts 2-bit weighting with the frequency of a pulse. The figure which shows the example which implements this invention using the existing audio | voice processing IC etc. FIG. The figure which shows the technique which provides three microphones in a mobile telephone and suppresses an interference sound.

Claims (11)

A plurality of microphones for outputting digital signals based on oversampled low amplitude resolution encoding;
A delay / gain setting unit having control values for delay processing and gain processing, and the digital signal are input, and directivity control by delay processing and gain processing based on the control value is performed on at least one of the digital signals. A 1-bit signal processing unit to perform , an addition processing unit that adds the digital signals output from the 1-bit signal processing unit and converts them to an addition signal that is one analog voltage value, and an A / that converts the addition signal to a digital signal A digital processing unit including a D conversion processing unit;
A transmission device characterized by comprising: A plurality of microphones that output a multi-bit digital signal based on oversampled low amplitude resolution encoding;
A delay / gain setting unit having control values for delay processing and gain processing;
For each weight of the plurality of bits, a ch signal processing unit including a variable delay unit that performs delay processing based on the control value and a variable gain unit that performs gain processing, and an output signal of the ch signal processing unit is selectively added. An addition processing unit, an A / D conversion processing unit for converting an output signal of the addition processing unit into a digital signal,
A transmission device characterized by comprising: The transmitter according to claim 1,
The above-mentioned digital processing unit is a processing unit in which the delay amount, gain amount, and selection of a digital signal are set in advance. The transmitter according to claim 1,
A transmission apparatus comprising a delay / gain setting unit for setting a delay amount, a gain amount, and selection of a digital signal for the digital processing unit. The transmitter according to claim 1,
A directivity control means for controlling the total sound directivity characteristics of the plurality of microphones by controlling the delay amount, the gain amount, and the selection of the digital signal based on the output signal and input signal of the digital processing unit. A transmission device. In the transmitter according to any one of claims 1 and 3 to 5,
The digital processing unit includes a 1-bit signal processing unit that performs delay processing and gain processing with variable pulse width for each bit of the digital signal, and an addition processing unit that adds the output signals of the 1-bit signal processing unit. Transmitter device characterized by In the transmitter according to any one of claims 1 and 3 to 5,
The digital processing unit includes a 1-bit signal processing unit that performs delay processing and gain processing with variable pulse amplitude for each bit of the digital signal, and an addition processing unit that adds the output signals of the 1-bit signal processing unit. Transmitter device characterized by In the transmitter according to any one of claims 1 and 3 to 5,
The digital processing unit is
A variable delay device that performs delay processing based on the control value for each bit of the digital signal; a distributor that distributes the digital signal output from the variable delay device to positive and negative pulses; and the positive and negative pulses A frequency variable unit that performs gain processing by changing the frequency of occurrence of the positive pulse and the negative pulse based on the control value as an input, and a 1-bit signal processing unit,
And characterized by including the and configured pulse counter smoothing unit in the U / D counter for outputting a P CM signal counts between the positive pulse and the negative pulse a fixed time in which the 1-bit signal processing section outputs To send a device. In the transmitter according to any one of claims 1 and 3 to 8,
The digital output signal of the plurality of digital microphones are transmitted time-division multiplexed into a set of common signal lines, transmission apparatus according to claim Rukoto is input to the digital signal processing unit. In the transmitter according to any one of claims 1 and 3 to 9,
The transmission apparatus according to claim 1, wherein the gain processing unit of the digital processing unit changes the gain control amount for each bit of the digital signal in accordance with the weight of the bit. In any of the transmitters according to claims 1 to 7 and claims 9 and 10,
A transmitter according to claim 1, wherein the addition signal is input to a sound regenerator.

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