JP4492066B2 - Electro-optical device and electronic apparatus using the same - Google Patents

Description

  The present invention relates to an electro-optical device provided with a plurality of complementary circuits having different driving voltages on the same substrate, and an electronic apparatus using the electro-optical device.

  In an electro-optical device such as an active matrix liquid crystal device or an organic electroluminescence display device, a plurality of thin film transistors (field effect transistors / hereinafter referred to as TFTs (Thin)) are provided as active elements for pixel switching on a substrate holding an electro-optical material. A drive circuit TFT that constitutes a drive circuit may be formed on the same substrate. Such an electro-optical device is an electro-optical device with a built-in drive circuit. It is called.

  In such a drive circuit, as shown in FIGS. 12A and 12B, an N-channel TFT and a P-channel TFT constitute a complementary circuit. In such a complementary circuit, the operation speed is high. A configuration in which the absolute value of the threshold voltage of the TFT is as close to 0 V as possible from the viewpoint of reduction in power consumption and power consumption, a configuration in which the threshold voltages of the N-channel TFT and the P-channel TFT are as equal as possible, N A configuration has been proposed in which variations in threshold voltages of channel TFTs and P channel TFTs are reduced (see, for example, Patent Document 1).

  In addition, in the electro-optical device with a built-in driving circuit, the pixel switching TFT is required to have a small off-current, and the driving circuit TFT is required to have a large on-current. It has also been proposed that the transistor characteristics be different from those of the TFT for use (see, for example, Patent Document 2).

  Further, it has been proposed to provide a transistor with a four-terminal structure in order to control the threshold value or achieve both on-current and off-current (see, for example, Patent Document 3).

  Here, the driving voltage of the complementary circuit is defined by the maximum potential difference between a plurality of power supplies and signals input to the circuit. Conventionally, a threshold voltage for turning on / off an electro-optical material such as a liquid crystal or an IC It is determined by external factors such as the output signal level. In general, a control input signal output from an IC, that is, a clock signal or a start pulse signal has a relatively small voltage amplitude of about 1V to 5V. In addition, since the power consumption of the circuit is proportional to the square of the drive voltage, it is preferable to drive the circuit at as low a voltage as possible. Therefore, in a logic circuit such as a shift register, it is desirable to set the drive voltage to a low voltage as long as the TFT characteristics allow. However, the higher the frequency (high-speed operation) of the circuit, the higher the driving voltage is required. Further, in order to switch the alignment state of the liquid crystal between the black level and the white level, a potential difference of about 3 V to 5 V is necessary, and since the polarity needs to be inverted, the total width of the voltage amplitude is about 6 V to 10 V. The amplitude of the signal applied to the scan bus line needs to be higher than that in consideration of the threshold voltage of the pixel switching transistor. Therefore, when the scanning line driving circuit and the data line driving circuit are compared, it is originally preferable that the driving voltage is low in the data line driving circuit and the driving voltage is high in the scanning line driving circuit.

However, in the past, the TFT characteristics were originally low, the circuits that could be built were limited, and the drive voltage of the circuit was mostly determined by the TFT characteristics, so changing the drive voltage depending on the circuit in this way was not very common. It was.
JP-A-7-273349 JP-A-9-266316 JP 2001-51292 A

  Conventionally, since the threshold voltage of the TFT is generally high and it is difficult to lower the voltage of the complementary circuit, the entire display device has to be driven at 8V to 12V. For this reason, the balance between the drive voltage of the built-in peripheral circuit and the voltage applied to the display portion is secured to some extent, so that the absolute value of the threshold voltage of the TFT can be set as much as possible from the viewpoint of reducing power consumption and holding capacity. Only studies have been made such as bringing the threshold voltage close to 0 V or setting the threshold voltage to a different value between the pixel switching TFT and the driving circuit TFT. However, in recent years, the technology for crystallizing the polysilicon film and the technology for forming the gate insulating film have improved, and it has become possible to manufacture a TFT with a low threshold voltage, and the drive voltage of the built-in peripheral circuit and the voltage applied to the display unit are reduced. The balance is greatly losing.

  In other words, the peripheral logic circuit can be driven at a voltage of 7 V or less, and it is expected that the drive voltage will further decrease from the viewpoint of reducing current consumption. However, since there is a threshold voltage of the electro-optic material, the voltage applied to the display portion cannot be kept below a certain level, and there is a tendency that circuits with greatly different driving voltages are mixed depending on the circuit. Moreover, if many circuits are further integrated on the same substrate toward the SOP in the future, the driving voltage will inevitably become different depending on the circuit. For example, a circuit driven at a high frequency requires a higher driving voltage because an on-state current of the transistor is required, and a low frequency circuit has a circumstance that it is desired to operate at a low driving voltage in order to reduce power consumption.

  Under such circumstances, when the entire electro-optical device is composed of TFTs having a low threshold voltage, there is a problem that a malfunction occurs in a complementary circuit having a high drive voltage. This point will be described with reference to the drawings.

  When the inverter is configured by a complementary circuit as shown in FIG. 12A and used at a driving voltage of 10 V, the output signal OUT is ideal as the input signal IN is periodically switched between a high level and a low level. Specifically, as shown in FIG. However, in an actual circuit, as shown in FIG. 13B, the input signal IN does not rise or fall sharply due to the influence of wiring resistance and parasitic capacitance, but with a gentle gradient. Change. Therefore, when the threshold voltage of the N-channel TFT is about + 1V to + 3V and the threshold voltage of the P-channel TFT is about -1V to -3V, for example, each is + 2V and -2V. In the case where there is, a period during which the input voltage IN is between (high level side power supply voltage + threshold voltage of P-channel TFT) and (low level side power supply voltage + N channel type TFT threshold voltage), that is, 2V In the interval of ˜8 V, an inversion layer is formed in the channel in both the N-channel TFT and the P-channel TFT, and both TFTs are in a low resistance state. For this reason, the output signal OUT takes an intermediate voltage between the high level and the low level, which causes a problem that a malfunction or malfunction is caused in the circuit.

  In the CMOS clocked inverter as shown in FIG. 12B, when the threshold voltages of the N-channel TFT and the P-channel TFT are +2 V and −2 V, respectively, the clock signal CLK is 5 V due to signal delay. When the inverted signal CLKX has a moment of 5V, the clocked inverter shown in FIG. 12B and the clocked inverter in which CLK and CLKX are switched with respect to FIG. Therefore, there is a problem that the signal selection operation and the latch operation are not performed correctly. Such a problem also applies to the complementary transmission gate.

  In view of the above problems, the object of the present invention is to improve the stability of the operation of the complementary circuit by optimizing the threshold voltage of the field effect transistor constituting the complementary circuit in accordance with the driving voltage. And an electro-optical device including the same.

In order to solve the above problems, in the present invention, a field effect transistor for pixel switching corresponding to each of a plurality of pixels arranged in a matrix on a substrate for holding an electro-optic material, And a field effect transistor for a driving circuit that constitutes a driving circuit for driving a plurality of pixels. The plurality of field effect transistors are defined by a signal input and a maximum voltage difference between power supplies. In an electro-optical device including an N-channel field effect transistor and a P-channel field effect transistor that form a first complementary circuit and a second complementary circuit having different driving voltages,
The N-channel field effect transistor and the P-channel field effect transistor are configured as a four-terminal structure including a back gate, and
A back gate potential defined by an average value of potentials applied between a back gate and a source of the N-channel field effect transistor having the four-terminal structure, and a back gate of the P-channel field effect transistor having the four-terminal structure; -When the back gate potential defined by the average value of the potential applied between the sources is Vb-Nch and Vb-Pch, respectively.
The back-gate potential Vb-Nch and the back-gate potential Vb-Pch are different in the four-terminal N-channel field effect transistor and the four-terminal P-channel field effect transistor that constitute the same complementary circuit. ,And,
In the first complementary circuit and the second complementary circuit, the back gate potential Vb-Nch of the N-channel field effect transistor having the 4-terminal structure or the back-gate potential of the P-channel field effect transistor having the 4-terminal structure is used. It is characterized in that at least one of the gate potentials Vb-Pch is different.

  In the present specification, complementary circuits having different driving voltages are referred to as a first complementary circuit and a second complementary circuit, and do not mean that the number of complementary circuits is limited to two. Further, this does not mean that all field effect transistors on the electro-optical device have four terminals.

In the present invention, the minimum value of the gate voltage when the inversion layer is formed in the channel with the back gate short-circuited to the source potential in the N-channel field effect transistor having the 4-terminal structure, When the maximum value of the gate voltage when the inversion layer is formed in the channel with the back gate short-circuited to the source potential in the P-channel field effect transistor is Vth-Nch and Vth-Pch, respectively.
In at least one complementary circuit of the first complementary circuit and the second complementary circuit, the following equation | ((Vth−Nch) − (Vb−Nch)) − ((Vth−Pch) − (Vb -Pch)) |
It is preferable that the value Vth-d (absolute value of the threshold voltage difference in the state controlled by the back gate) obtained by the above is in the range of 0.25 to 1 times the driving voltage of the complementary circuit. . Thus, the absolute value of the difference between the threshold voltage in the state controlled by the back gate of the N-channel field effect transistor and the threshold voltage in the state controlled by the back gate of the P-channel field effect transistor is When the drive voltage is optimized, the balance between the drive voltage and the threshold voltage can be ensured even when the threshold voltage of the field-effect transistor is lowered. Can be prevented.

  In the present invention, in at least one complementary circuit of the first complementary circuit and the second complementary circuit, the value Vth-d is 0.5 to 1 times the drive voltage of the complementary circuit. It is preferable that it is the range of these.

In the present invention, at least one complementary circuit of the first complementary circuit and the second complementary circuit is
| ((Vth−Nch) − (Vb−Nch)) + ((Vth−Pch) − (Vb−Pch)) |
It is preferable that the value obtained in (1) is not more than 1/4 times the driving voltage of the complementary circuit.

  In the present invention, when the threshold voltages Vth-Nch and Vth-Pch vary, an inversion layer is formed in the channel with the back gate short-circuited to the source potential in the N-channel field effect transistor having the four-terminal structure. The minimum value of the gate voltage when formed, and the maximum value of the gate voltage when the inversion layer is formed in the channel in the state where the back gate is short-circuited with the source potential in the P-channel field effect transistor having the four-terminal structure. The values are preferably Vth-Nch and Vth-Pch, respectively. Thus, a desired effect can be obtained even when the threshold voltage of the transistor varies in the circuit.

  According to the present invention, in at least one complementary circuit of the first complementary circuit and the second complementary circuit, the value Vth-d is a driving voltage of the first complementary circuit and the second complementary circuit. Even when applied to an electro-optical device having a value less than or equal to half the maximum value, the balance between the drive voltage and the absolute sum Vth-d of the threshold voltage is ensured, so that the occurrence of malfunction can be prevented. Therefore, when the present invention is applied to an electro-optical device using such a field effect transistor having a low threshold voltage, the effect is particularly remarkable.

  In the present invention, ((Vth−Nch) − (Vb−Nch)) is a positive value in at least one complementary circuit of the first complementary circuit and the second complementary circuit, and ((Vth -Pch)-(Vb-Pch)) is preferably a negative value. With this configuration, the level of current (leakage current) when the gate voltage is 0 V can be reduced. For this reason, in at least one of the complementary circuits, it is preferable that Vb−Nch is a positive value and Vb−Pch is a negative value.

  In the above invention, the configuration is defined using the threshold voltage in the physical sense as a parameter, but it may be defined as a circuit operation.

That is, according to the present invention, when the predetermined constant voltage Vds-Nch is applied between the drain and the source in a state where the back gate is short-circuited with the source potential in the N-channel field effect transistor having the four-terminal structure, With the gate voltage when the value obtained by dividing the resistance between the sources by the channel width becomes a predetermined value Ron-off, and in the state where the back gate is short-circuited to the source potential in the P-channel field effect transistor having the 4-terminal structure, The gate voltages when the value obtained by dividing the drain-source resistance by the channel width when the predetermined constant voltage Vds-Pch is applied between the drain and the source becomes the predetermined value Ron-off are Von-off-Nch and When Von-off-Pch
In at least one complementary circuit of the first complementary circuit and the second complementary circuit, the following formula | ((Von-off-Nch)-(Vb-Nch))-((Von-off-Pch )-(Vb-Pch)) |
Von-off-d (the absolute value of the difference in threshold voltage on the circuit operation surface in the state controlled by the back gate) obtained from 0.25 to 1 times the drive voltage of the complementary circuit It is preferable that it is the range of these. Thus, the absolute value of the difference between the threshold voltage in the state controlled by the back gate of the N-channel field effect transistor and the threshold voltage in the state controlled by the back gate of the P-channel field effect transistor is When the drive voltage is optimized, the balance between the drive voltage and the threshold voltage can be ensured even when the threshold voltage of the field-effect transistor is lowered. Can be prevented.

  In the present invention, in at least one complementary circuit of the first complementary circuit and the second complementary circuit, the value Von-off-d is from 0.5 times the driving voltage of the complementary circuit. It is preferable that the range is 1 times.

In the present invention, in at least one complementary circuit of the first complementary circuit and the second complementary circuit, the following expression | ((Von-off-Nch) − (Vb−Nch)) + ((Von -off-Pch)-(Vb-Pch)) |
Is preferably ¼ times or less the driving voltage of the complementary circuit.

  According to the present invention, in at least one of the first complementary circuit and the second complementary circuit, the value Von-off-d is equal to that of the first complementary circuit and the second complementary circuit. Even when applied to an electro-optical device that is less than half of the maximum value of the drive voltage, the balance between the drive voltage and the value Von-off-d in terms of circuit operation is ensured, so that the occurrence of malfunction can be prevented. . Therefore, when the present invention is applied to an electro-optical device using such a field effect transistor having a low threshold voltage, the effect is particularly remarkable.

  In the present invention, ((Von-off-Nch)-(Vb-Nch)) is a positive value in at least one of the first complementary circuit and the second complementary circuit, (Von-off-Pch)-(Vb-Pch)) is preferably a negative value. With this configuration, the level of current (leakage current) when the gate voltage is 0V can be reduced. For this reason, in at least one of the complementary circuits, it is preferable that Vb−Nch is a positive value and Vb−Pch is a negative value.

  In the present invention, when threshold voltages Von-off-Nch and Von-off-Pch vary in terms of circuit operation, the back gate is short-circuited to the source potential in the N-channel field effect transistor having the four-terminal structure. In this state, the minimum value of the gate voltage when the value obtained by dividing the drain-source resistance by the channel width when the predetermined constant voltage Vds-Nch is applied between the drain and the source becomes the predetermined value Ron-off. And a drain-source resistance when a predetermined constant voltage Vds-Pch is applied between the drain and the source in a state where the back gate is short-circuited with the source potential in the P-channel field effect transistor having the four-terminal structure. It is preferable that the maximum value of the gate voltage when the value divided by the channel width becomes a predetermined value Ron-off is Von-off-Nch and Von-off-Pch, respectively. Thus, a desired effect can be obtained even when the threshold voltage of the transistor varies in the circuit.

  In the present invention, the predetermined constant voltage Vds-Nch is from + 1V to + 20V, the predetermined constant voltage Vds-Pch is from -1V to -20V, and the predetermined value Ron-off is from 1 MΩ / μm. It is preferably 1 GΩ / μm.

  In the present invention, the first complementary circuit and the second complementary circuit are configured in the drive circuit, for example. However, in the pixel, a field effect transistor for pixel switching may constitute a complementary circuit. In such a case, one complementary circuit of the first complementary circuit and the second complementary circuit is The present invention may be applied to the case where the pixel is configured and the other complementary circuit is configured as a drive circuit.

  In the present invention, in at least one complementary circuit of the first complementary circuit and the second complementary circuit, the drive voltage is not more than half of the maximum value of the drive voltage.

  In the present invention, the field effect transistor is, for example, a thin film transistor whose active layer is made of polycrystalline silicon.

  In the present invention, the electro-optical material is, for example, a liquid crystal held between the electro-optical device substrate and a counter substrate.

  In the present invention, the electro-optical material is, for example, an organic electroluminescent material that constitutes a light-emitting element on the electro-optical device substrate.

  An electro-optical device to which the present invention is applied is used in an electronic apparatus such as a mobile phone or a mobile computer.

  In the present invention, in the first and second complementary circuits having different driving voltages, an N-channel field effect transistor and a P-channel field effect transistor are provided with four terminals having a back gate for threshold voltage control. Since the structure and the back gate potential of each field effect transistor are optimized, the threshold voltage in the state controlled by the back gate of the N channel field effect transistor and the P channel field effect transistor are obtained. The absolute value of the difference between the threshold voltages in the state controlled by the back gate can be made appropriate in accordance with the drive voltage and optimized. For this reason, in order to achieve high-speed operation and low power consumption, even when the threshold voltage of the field effect transistor is reduced, the balance between the drive voltage and the threshold voltage is not achieved in each complementary circuit. Therefore, no malfunction occurs in the complementary circuit. In particular, in an electro-optical device, although there is no space in spite of driving a large number of pixels, the wiring and the like are considerably miniaturized. When used in a direct-view display, the input signal waveform is likely to be distorted due to RC delay because the device itself is large and the wiring length becomes long. Even in such a case, the complementary circuit malfunctions. Does not occur. Therefore, in the electro-optical device, high reliability can be ensured even when the number of pixels is increased, the screen is enlarged, the operation speed is increased, and the power consumption is reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1]
A specific configuration of an active matrix liquid crystal device (electro-optical device) with a built-in driving circuit to which the present invention is applied will be described later. A TFT array for holding liquid crystal as an electro-optical material between a counter substrate and a counter substrate. On the substrate (active matrix substrate), along with the pixel switching TFTs, drive circuit TFTs constituting the drive circuit are formed in the peripheral region of the element substrate. In this type of driving circuit, a scanning line driving circuit and a data line driving circuit including a shift resistor are constituted by a complementary circuit (hereinafter referred to as a CMOS circuit) including an N-channel TFT and a P-channel TFT. Here, the drive circuit includes CMOS circuits having different drive voltages. For example, the data line driving circuit includes a CMOS circuit having a driving voltage of 12V, and the scanning line driving circuit includes a CMOS circuit having a driving voltage of 5V. Conventionally, an apparatus having such a configuration is manufactured so as to reduce the threshold voltage in accordance with a scanning line driving circuit having a low driving voltage (5V), and this is a data line driving circuit having a high driving voltage (12V). This was a cause of malfunction.

  Under such a technical background, the present invention is characterized in that a TFT having an appropriate threshold voltage corresponding to the driving voltage is used for each CMOS circuit, and details thereof will be described below.

(Relationship between threshold voltage and driving voltage of TFT)
1A and 1B are explanatory diagrams of an inverter circuit using a CMOS circuit to which the present invention is applied and a clocked inverter circuit, respectively. In the following description, CMOS circuits having different driving voltages are referred to as a first CMOS circuit and a second CMOS circuit. Here, “first” and “second” mean that the drive voltages are different, and that there are not only two types of CMOS circuits but also three or more types of CMOS circuits. .

  In the present invention, first, as shown in FIGS. 1A and 1B, a first CMOS circuit and a second CMOS circuit which are different in input voltage and drive voltage defined by the maximum voltage difference between power supplies. N-channel TFTs and P-channel TFTs constituting the four-terminal structure having a threshold voltage control back gate, each of which has a threshold control signal line 111, A predetermined back gate potential is applied from 112. In the following description, the potential applied to the back gate is assumed to be fixed (DC), but some signal may be applied to assist various driving operations.

  The back gate potential, which is an average value of the potential applied to the back gate of the N-channel TFT having the four-terminal structure, is Vb-Nch, and the potential applied to the back gate of the P-channel TFT having the four-terminal structure is When the average back gate potential is Vb-Pch, the back gate potential Vb-Nch and the back gate are the same for the four-terminal N-channel TFT and the four-terminal P-channel TFT constituting the same CMOS circuit. The potential Vb-Pch is made different.

  Further, the back gate potential Vb-Nch of the N-channel TFT having the 4-terminal structure is different between the first CMOS circuit and the second CMOS circuit, and the back gate potential Vb-Pch of the P-channel TFT having the 4-terminal structure is different. Are different configurations.

  Here, the back gate potential Vb-Nch of the N-channel TFT is set to a negative potential, and the back gate potential Vb-Pch of the P-channel TFT is set to a positive potential.

Further, a gate voltage (physical threshold voltage in a state not controlled by the back gate) when an inversion layer is formed in the channel in a state where the back gate is short-circuited with the source potential in an N-channel TFT having a four-terminal structure, And a gate voltage (physical threshold voltage in a state not controlled by the back gate) when an inversion layer is formed in the channel in a state where the back gate is short-circuited with the source potential in a P-channel TFT having a 4-terminal structure. When Vth-Nch and Vth-Pch, the CMOS circuit of at least one of the first CMOS circuit and the second CMOS circuit, in this embodiment, the CMOS of both the first CMOS circuit and the second CMOS circuit In the circuit, the following formula | ((Vth-Nch)-(Vb-Nch))-((Vth-Pch)-(Vb-Pch)) |
Vth-d (absolute value of the threshold voltage difference in a state controlled by the back gate of the TFT / hereinafter, simply referred to as “absolute value of the threshold voltage difference”) obtained by For example, the voltage is set in the range of 0.25 to 1 time, preferably in the range of 0.5 to 1 time.

  For example, when the driving voltage of the first CMOS circuit is 5V, the absolute value Vth-d of the threshold voltage difference between TFTs constituting the CMOS circuit is in the range of 1.25V to 5V, preferably 2. It is in the range of 5V-5V. On the other hand, when the driving voltage of the second CMOS circuit is, for example, 12V, the absolute value Vth-d of the threshold voltage difference is in the range of 3V to 12V, preferably in the range of 6V to 12V. . That is, in the case of adopting a preferable configuration, the absolute value (Vth-d) of the difference between the threshold voltages of the transistors constituting the first CMOS circuit and the TFTs constituting the second CMOS circuit must be different. Must not. For example, ((Vth−Nch) − (Vb−Nch)) and ((Vth−Pch) − (Vb−Pch)) in the first CMOS circuit are + 2V and −2V, respectively, (( Vth−Nch) − (Vb−Nch)) and ((Vth−Pch) − (Vb−Pch)) may be set to + 5V and −5V, respectively. More specifically, if the threshold voltages of the TFTs in the first CMOS circuit and the second CMOS circuit are substantially the same, and Vth−Nch = 1.5V and Vth−Pch = −1.5V. The back gate voltages of the first CMOS circuit are Vb-Nch = -0.5V and Vb-Pch = + 0.5V, respectively, and the back gate voltages of the second CMOS circuit are Vb-Nch = -3.5V and Vb, respectively. -Pch = + 3.5V may be set.

  In this way, if the absolute value Vth-d of the threshold voltage difference is optimized in correspondence with the driving voltage of each CMOS circuit, malfunction of the driving circuit can be prevented. That is, when an inverter is configured by a CMOS circuit as shown in FIG. 1A, the waveform of the input signal IN is distorted and rises due to the influence of wiring resistance and parasitic capacitance, as shown in FIG. When the absolute value Vth-d of the threshold voltage difference is made equal to the power supply voltage even when the fall is not steep, for example, the drive voltage, the threshold voltage after control of the N-channel TFT ((Vth-Nch ) − (Vb−Nch)) and the threshold voltage (Vth−Pch) − (Vb−Pch)) after the control of the P-channel TFT are 10 V, +5 V, and −5 V, respectively, The absolute value Vth-d of the threshold voltage difference is equal to the driving voltage of the CMOS circuit, and the N-channel TFT and the P-channel TFT are not simultaneously turned on or off, as shown in FIG. I want to stand up It can fall to obtain a sharp output waveform.

  Here, as the absolute value Vth-d of the threshold voltage difference is closer to the driving voltage of the CMOS circuit, malfunction can be prevented. However, the absolute value Vth-d of the threshold voltage difference is less than that of the CMOS circuit. When the driving voltage is exceeded, there is a timing without output when both TFTs are OFF, and an on-current cannot be sufficiently secured, which is also not preferable. Therefore, the absolute value Vth-d of the threshold voltage difference may be set to a level slightly lower than the driving voltage of the CMOS circuit.

  In addition, since there is always a variation in threshold voltage in each TFT, the N-channel type with the back gate short-circuited to the source potential is used to obtain the absolute value Vth-d of the difference in threshold voltage. The minimum value of the threshold voltage at which the inversion layer is formed in the channel of the TFT, and the maximum value of the threshold voltage at which the inversion layer is formed in the channel of the P-channel TFT with the back gate shorted to the source potential Are Vth-Nch and Vth-Pch, respectively, and using these values, the absolute value Vth-d of the threshold voltage difference is preferably obtained.

  The allowable range of the absolute value Vth-d of the threshold voltage difference becomes narrower as the gradient of the input signal IN is larger. That is, the time that the input signal IN takes between (high level side driving voltage + threshold value of the P-channel TFT) and (low level side driving voltage + threshold value of the N channel type TFT) causes malfunction. It should be shorter than time. Here, since the slope of the input signal IN is inversely proportional to the wiring relaxation time τ = RC (R: wiring resistance, C: parasitic capacitance), the wiring length, wiring material, film thickness / dielectric constant of the interlayer insulating film It depends on etc. In this embodiment, the absolute value Vth-d of the threshold voltage difference is calculated with respect to the driving voltage of the CMOS circuit based on the result of waveform measurement performed on the element substrate of the liquid crystal device using low-temperature polysilicon. The range is 0.25 times to 1 time, preferably 0.5 times to 1 time.

  Therefore, it can be seen from the above setting that the effect of the present invention is remarkable when the ratio of the absolute value Vth-d of the threshold voltage difference between the circuits is more than twice different. Therefore, according to this embodiment, even when the driving voltage includes two or more CMOS circuits than other CMOS circuits, malfunction of the voltage side circuit can be prevented by controlling the threshold voltage by the back gate. Further, according to this embodiment, in at least one of the first CMOS circuit and the second CMOS circuit, the absolute value Vth-d of the threshold voltage difference is equal to the driving voltage of the other CMOS circuit. Even in the case of half or more, since the balance between the drive voltage and the absolute value Vth-d of the difference between the threshold voltages is ensured for each CMOS circuit, the occurrence of malfunction can be prevented. Therefore, when the present invention is applied to an electro-optical device using such a TFT having a low threshold voltage, the effect is remarkable.

  Furthermore, since a large number of pixels are arranged in a matrix as in an electro-optical device, even when the input signal IN is distorted and rises or falls easily due to the influence of wiring resistance and parasitic capacitance. In this embodiment, since the relationship between the threshold voltage of the TFT and the drive voltage is optimized, no malfunction of the CMOS circuit occurs.

(Balance of threshold voltage between TFTs)
From the viewpoint of preventing malfunction in the CMOS circuit configured as described above, the absolute value of the threshold voltage after the control of the N-channel TFT and the absolute value of the threshold voltage after the control of the P-channel TFT are obtained. It is preferable that the difference from the value is small. Specifically, according to the inventors' measurements,
| ((Vth−Nch) − (Vb−Nch)) + ((Vth−Pch) − (Vb−Pch)) |
Is preferably 1/4 times or less the driving voltage of the CMOS circuit, it is possible to reliably prevent malfunction.

  In at least one of the first CMOS circuit and the second CMOS circuit, the threshold voltage ((Vth−Nch) − (Vb−Nch)) after the control of the N-channel TFT is set. If it is a positive value and the threshold voltage ((Vth−Pch) − (Vb−Pch)) of the P-channel TFT is a negative value, leakage current in a steady state can be surely prevented. It is preferable that Vb-Nch is negative and Vb-Pch is positive.

(Effect of this embodiment)
As described above, in the electro-optical device of this embodiment, in the first and second CMOS circuits having different driving voltages, the N-channel TFT and the P-channel TFT are used as the back gate for controlling the threshold voltage. Since it has a four-terminal structure and the back gate potential has been optimized for each TFT, the threshold voltage in the state controlled by the back gate of the N-channel TFT and the back gate of the P-channel TFT are controlled. In this state, the absolute value of the difference between the threshold voltages can be made different in accordance with the driving voltage and can be optimized. For example, the data line driving circuit includes a CMOS circuit having a driving voltage of 12V, and the scanning line driving circuit includes a CMOS circuit having a driving voltage of 5V. In order to secure a balance with the absolute value Vth-d of the threshold voltage difference, for example, the average value of the back gate voltage applied to the TFT constituting the shift register of the scanning line driving circuit is Vb−Nch = −0 .5V and Vb-Pch = + 0.5V, and the average value of the back gate voltage applied to the transmission gate portion of the data line driving circuit is Vb-Nch = -3.5V and Vb-Pch = + 3.5V. Therefore, the occurrence of malfunction can be prevented. Therefore, even when the threshold voltage of the TFT is lowered to achieve high-speed operation (in this embodiment, Nth channel Vth = 1.5 V, P channel Vth = −1.5 V), Even when the driving voltage of the CMOS circuit is made different in response to various demands, the balance between the driving voltage and the absolute value Vth-d of the threshold voltage difference is ensured in each CMOS circuit. Therefore, the occurrence of malfunction can be prevented. In addition, as the number of pixels increases, there is no room for space and the wiring has been made very fine. As a result, the wiring width is narrow, although the drive frequency is high, or the display area is enlarged. Even when the signal waveform is distorted due to a long period of time, the balance between the drive voltage and the absolute value Vth-d of the difference between the threshold voltages is secured, so that the occurrence of malfunction can be prevented. .

[Embodiment 2]
FIG. 2 is an explanatory diagram of the threshold voltage Von-off in terms of the circuit operation of the TFT. FIG. 3 is a graph showing the correspondence between the threshold voltage Von-off on the circuit operation surface of the TFT and the physical threshold voltage Vth based on the formation of the inversion layer.

  In the above configuration, the relationship between the driving voltage of the CMOS circuit and the configuration of the TFT is defined by the threshold voltage (Vth) which is a physical parameter of the TFT. The threshold voltage (Vth) of a physical TFT refers to a gate voltage at which an inversion layer is formed in the channel. There are various methods for experimental determination, and the simplest means is, for example, a saturation region The drain-source current Ids of (Vgs−Vth <Vds) is measured, and when the square root of Ids is plotted on the vertical axis and Vgs is plotted on the horizontal axis, the maximum value of Vgs at which the straight line in contact with the curve intersects the horizontal axis is represented by Vth. There are ways to do it. In the above, Vgs means a gate-source voltage.

  However, particularly in the case of a polysilicon thin film TFT, it is difficult to obtain the threshold voltage Vth experimentally with high accuracy, and the result often varies depending on the method. Therefore, the relationship between the driving voltage and the driving voltage may be defined by using the on / off threshold voltage Von-off in terms of circuit operation as a simple parameter instead of the threshold voltage (Vth).

  In the active matrix type liquid crystal device with a built-in driving circuit of this embodiment, a driving circuit is formed on the element substrate (active matrix substrate) together with pixel switching TFTs in the peripheral region of the element substrate as in the first embodiment. A driving circuit TFT is formed. In the driving circuit, a plurality of CMOS circuits each including an N-channel TFT and a P-channel TFT are configured. The plurality of CMOS circuits are defined by a maximum voltage difference between an input signal and a power source. A first CMOS circuit and a second CMOS circuit having different driving voltages are included.

  In the liquid crystal device having such a structure, in this embodiment, as in the first embodiment, the threshold values of the N-channel TFT and the P-channel TFT constituting the first CMOS circuit and the second CMOS circuit are the threshold values. The four-terminal structure is provided with a back gate for controlling the value voltage.

  The back gate potential applied to the back gate of the N-channel TFT having the four-terminal structure is Vb-Nch, and the back gate potential applied to the back gate of the P-channel TFT having the four-terminal structure is Vb-Pch. In this case, the back-gate potential Vb-Nch and the back-gate potential Vb-Pch are made different between the 4-terminal N-channel TFT and the 4-terminal P-channel TFT constituting the same CMOS circuit.

  In the first CMOS circuit and the second CMOS circuit, the back gate potential Vb-Nch of the four-terminal structure N-channel TFT is set, and the back gate potential Vb-Pch of the four-terminal structure P-channel TFT is set. Make it different.

  Here, the back gate potential Vb-Nch of the N-channel TFT is set to a negative potential, and the back gate potential Vb-Pch of the P-channel TFT is set to a positive potential.

Further, in the Vgs-Ids characteristics of the TFT when the drain-source voltage (Vds) shown in FIG. 2 is fixed to a constant value, the back gate is short-circuited to the source potential in the N-channel TFT having a four-terminal structure. In this state, when a predetermined constant voltage Vds-Nch is applied between the drain and the source, the gate voltage when the value obtained by dividing the drain-source resistance by the channel width becomes the predetermined value Ron-off, and a four-terminal structure A value obtained by dividing the drain-source resistance by the channel width when a predetermined constant voltage Vds-Pch is applied between the drain and the source in a state where the back gate is short-circuited with the source potential in the P-channel TFT of When the gate voltages when the value Ron-off is Von-off-Nch and Von-off-Pch, respectively,
In at least one of the first CMOS circuit and the second CMOS circuit, in this embodiment, both the first CMOS circuit and the second CMOS circuit, the following expression | ((Von-off-Nch )-(Vb-Nch))-((Von-off-Pch)-(Vb-Pch)) |
Von-off-d (the absolute value of the difference in threshold voltage on the circuit operation surface in a state controlled by the back gate of the TFT / below, simply “the difference in threshold voltage on the circuit operation surface”) The threshold in terms of the circuit operation so that the absolute value of the input voltage is in the range of 0.25 times to 1 time, preferably in the range of 0.5 times to 1 time, with respect to the driving voltage of the CMOS circuit. The value voltage has been optimized.

  For example, when the driving voltage of the first CMOS circuit is 5 V, for example, the absolute value Von-off-d of the threshold voltage difference on the circuit operation surface of the TFT constituting the CMOS circuit is 1.25 V to It is in the range of 5V, preferably in the range of 2.5V to 5V. On the other hand, when the driving voltage of the second CMOS circuit is 12 V, for example, the absolute value Von-off-d of the difference in threshold voltage on the circuit operation operation side of the TFT constituting the CMOS circuit is It is in the range of 3V to 12V, preferably in the range of 6V to 12V.

  Here, the threshold voltage Von-off in terms of circuit operation is a constant drain-source resistance (Rds) per TFT channel width when the drain-source voltage (Vds) is fixed to a constant value. It means the gate voltage that becomes the value. The constant values of the drain-source voltage (Vds) and the drain-source resistance (Rds) vary depending on the circuit drive frequency and channel length, but are CMOS digital logic circuits formed by low-temperature polysilicon TFTs on a glass substrate. In this case, it is appropriate to set the Ron-off value from about 1 MΩ / μm to about 1 GΩ / μm, the Vds values from 1 to 20 V, and Pch from −1 to −20 V. For example, the threshold voltage Von-off in terms of circuit operation is shown in FIG. 3 when the drain-source resistance (Rds) is constant (Rds˜1 MΩ / μm) or large (Rds˜). As shown in the graph plotting the measurement results of a plurality of TFTs for each of about 1 GΩ / μm, it has been confirmed that there is a sufficient correlation with the physical threshold voltage Vth.

  Therefore, as in the present embodiment, by setting the absolute value Von-off-d of the threshold voltage difference in the circuit operation operation as described above, for example, the drive voltage ratio is more than twice. Malfunctions in different CMOS circuits can be prevented. Further, according to the present embodiment, in at least one of the first CMOS circuit and the second CMOS circuit, the absolute value Von-off-d of the threshold voltage difference on the circuit operation surface is different. Even when the driving voltage is less than half the driving voltage of the circuit, the same effects as those of the first embodiment can be obtained, such as prevention of malfunction.

  In each TFT, there is always a variation in threshold voltage on the circuit operation surface. Therefore, in this embodiment, the absolute value Von-off-d of the threshold voltage difference on the circuit operation surface is obtained. The value obtained by dividing the drain-source resistance by the channel width when a predetermined constant voltage Vds-Nch is applied between the drain and source while the back gate of the N-channel TFT is short-circuited to the source potential is a predetermined value. When a predetermined constant voltage Vds-Pch is applied between the drain and the source in a state where the back gate is short-circuited to the source potential with a P-channel TFT and the minimum value of the gate voltage when the value Ron-off is The maximum gate voltage when the drain-source resistance divided by the channel width becomes a predetermined value Ron-off is used as Von-off-Nch and Von-off-Pch, respectively. Noshiki It is preferable that the absolute value Von-off-d of the difference between the value voltage.

From the standpoint of preventing malfunction, the absolute value of the threshold voltage in the circuit operation state in the controlled state of the N-channel TFT and the circuit operation surface in the controlled state of the P-channel TFT. It is preferable that the difference from the absolute value of the threshold voltage is small. That is,
| ((Von-off-Nch)-(Vb-Nch)) + ((Von-off-Pch)-(Vb-Pch)) |
Is preferably equal to or less than 1/4 times the driving voltage of the CMOS circuit.

[Specific configuration of electro-optical device]
(overall structure)
FIG. 4 is a plan view of the electro-optical device to which the present invention is applied as viewed from the side of the counter substrate together with the components formed thereon, and FIG. It is H 'sectional drawing. FIG. 6 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels formed in a matrix to constitute an image display region of the electro-optical device.

  In FIG. 4, the electro-optical device 100 of this embodiment is an active matrix type liquid crystal device, and a sealing material 107 is provided on the TFT array substrate 10 along the edge of the counter substrate 20. A data line driving circuit 101 and a mounting terminal 102 (signal input terminal) are provided along one side of the TFT array substrate 10 in a region outside the sealing material 107, and the scanning line driving circuit 104 is adjacent to the one side. It is formed along two sides. Furthermore, a plurality of wirings 105 are provided on the remaining side of the TFT array substrate 10 to connect between the scanning line driving circuits 104 provided on both sides of the image display area 10a. In some cases, a precharge circuit or an inspection circuit is provided. Further, at least one corner portion of the counter substrate 20 is formed with a vertical conductive material 106 for electrical conduction between the TFT array substrate 10 and the counter substrate 20.

  As shown in FIG. 5, the counter substrate 20 having substantially the same contour as the sealing material 107 shown in FIG. 4 is fixed to the TFT array substrate 10 by this sealing material 107. The sealing material 107 is an adhesive made of a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the counter substrate 20 around them.

  As will be described in detail later, pixel electrodes 9 a are formed in a matrix on the TFT array substrate 10. On the other hand, a frame 108 made of a light-shielding material is formed in the inner area of the sealing material 107 on the counter substrate 20, and the inner side is an image display area 10 a. Further, a light shielding film 23 called a black matrix or a black stripe is formed in a region facing vertical and horizontal boundary regions of pixel electrodes (described later) formed on the TFT array substrate 10, and on the upper layer side thereof, A counter electrode 21 made of an ITO film is formed.

  In FIG. 6, in the image display region 10a of the electro-optical device 100, a pixel electrode 9a and a pixel switching TFT 30 for controlling the pixel electrode 9a are formed in each of a plurality of pixels formed in a matrix. The data line 6 a for supplying a pixel signal is electrically connected to the source of the TFT 30. Pixel signals S1, S2,... Sn written to the data line 6a are supplied line-sequentially in this order. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,... Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the pixel signal S1, S2,... Sn supplied from the data line 6a is turned on by turning on the TFT 30 as a switching element for a certain period. Are written in each pixel at a predetermined timing. Thus, the pixel signals S1, S2,... Sn at a predetermined level written to the liquid crystal through the pixel electrode 9a are constant with the counter electrode 21 (see FIG. 5) formed on the counter substrate 20. Hold for a period.

  Here, in order to prevent the held pixel signal from leaking, a storage capacitor 70 (capacitor) may be added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 holds the voltage of the pixel electrode 9a for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. As a result, the charge retention characteristics are improved, and an electro-optical device capable of performing display with a high contrast ratio can be realized. As a method of forming the storage capacitor 70, there is either a case where it is formed between the capacitor line 3b, which is a wiring for forming a capacitor, or a case where it is formed between the storage line 70 and the preceding scanning line 3a. Also good.

  In the electro-optical device 100 configured as described above, the data line driving circuit 101 includes a shift register 101a, a level shifter 101b, and a video signal transmission gate unit 101c. The shift register 101a and the video signal transmission gate unit 101c And a CMOS circuit including a driving circuit TFT described later. Here, the drive voltage of the CMOS circuit of the shift register 101a is 8V, the drive voltage of the CMOS circuit of the video signal transmission gate unit 101c is 12V, and the drive voltages are different. Therefore, the level shifter 101b performs a level shift from 8V to 12V.

  The scanning line driver circuit 104 includes a shift register 104a and a level shifter 104b. The shift register 104a includes a CMOS circuit including a driver circuit TFT described later. Here, the driving voltage of the CMOS circuit of the shift register 104a is 5V, and the level shifter 104b performs a level shift from 5V to 12V.

  As described above, in the data line driving circuit 101 and the scanning line driving circuit 104, the driving voltages of the CMOS circuits used in the shift register 101a, the video signal transmission gate unit 101c, and the shift register 104a are 8V, 12V, and 5V, respectively. Therefore, in the present embodiment, as described in the first and second embodiments, the TFT constituting the shift register 101a, the video signal transmission gate unit 101c, and the shift register 104a has a back gate for threshold voltage control. In addition to the four-terminal structure provided, and by applying a predetermined back gate potential to the back gate by the threshold voltage control signal lines 73 and 74, the threshold voltage suitable for the driving voltage of each CMOS circuit is adapted. Configure to operate on voltage.

(Pixel configuration)
7A and 7B are plan views of adjacent pixels on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed, and electro-optics at a position corresponding to the AA ′ line. It is explanatory drawing which shows a cross section when an apparatus is cut | disconnected. In these drawings, the scales are different for each layer and each member so that each layer and each member can be recognized on the drawing.

  7A and 7B, on the TFT array substrate 10 of the electro-optical device 100, a plurality of transparent pixel electrodes 9a (regions surrounded by dotted lines) are formed in a matrix for each pixel. Data lines 6a (shown by alternate long and short dash lines), scanning lines 3a (shown by solid lines), and capacitor lines 3b (shown by solid lines) are formed along the vertical and horizontal boundary regions of the electrodes 9a.

  The base of the TFT array substrate 10 is made of a transparent substrate 10b such as a quartz substrate or a heat resistant glass plate, and the base of the counter substrate 20 is made of a transparent substrate 20b such as a quartz substrate or a heat resistant glass plate. A pixel electrode 9 a is formed on the TFT array substrate 10, and an alignment film 16 made of a polyimide film or the like subjected to a predetermined alignment process such as a rubbing process is formed on the upper side. The pixel electrode 9a is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is formed by performing a rubbing process on an organic film such as a polyimide film. In the counter substrate 20, an alignment film 22 made of a polyimide film is also formed on the upper layer side of the counter electrode 21, and this alignment film 22 is also a film obtained by rubbing the polyimide film.

  The TFT array substrate 10 has a base insulating film 11 formed on the surface of the transparent substrate 10b, and a three-terminal structure that controls switching of the pixel electrodes 9a at positions adjacent to the pixel electrodes 9a on the surface side. The pixel switching TFT 30 is formed.

  As shown in FIG. 7, in the semiconductor film 1a, a channel region 1a ′ in which a channel is formed by an electric field from the scanning line 3a, a high concentration source region 1d, and a high concentration drain region 1e are formed. A gate insulating film 2 for insulating the semiconductor film 1a and the scanning line 3a is formed on the upper side of the semiconductor film 1a.

  Interlayer insulating films 4 and 7 made of a silicon oxide film are formed on the surface side of the TFT 30 thus configured. A data line 6 a is formed on the surface of the interlayer insulating film 4, and the data line 6 a is electrically connected to the high concentration source region 1 d through a contact hole 5 formed in the interlayer insulating film 4. A pixel electrode 9 a made of an ITO film is formed on the surface of the interlayer insulating film 7. The pixel electrode 9 a is electrically connected to the drain electrode 6 b through a contact hole 7 a formed in the interlayer insulating film 7, and the drain electrode 6 b is a contact hole formed in the interlayer insulating film 4 and the gate insulating film 2. 8 is electrically connected to the high-concentration drain region 1e. An alignment film 16 made of a polyimide film is formed on the surface side of the pixel electrode 9a.

  Further, the extension portion 1f (lower electrode) extending from the high-concentration drain region 1e has a capacitance in the same layer as the scanning line 3a through an insulating film (dielectric film) formed simultaneously with the gate insulating film 2a. The storage capacitor 70 is configured by the line 3b facing as an upper electrode.

  In this embodiment, a single gate structure is used in which only one gate electrode (scanning line 3a) of the TFT 30 is disposed between the source and drain regions. However, two or more gate electrodes may be disposed between these gate electrodes. Good. At this time, the same signal is applied to each gate electrode. If the TFT 30 is configured with dual gates (double gates) or more than triple gates in this manner, leakage current at the junction between the channel and the source-drain region can be prevented, and the current during OFF can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-current can be further reduced and a stable switching element can be obtained.

  In FIG. 7B, in the counter substrate 20, a light shielding film 23 called a black matrix or a black stripe is formed in a region facing the vertical and horizontal boundary regions of the pixel electrode 9 a formed on the TFT array substrate 10. A counter electrode 21 made of an ITO film is formed on the upper layer side. Further, an alignment film 22 made of a polyimide film is formed on the upper layer side of the counter electrode 21, and this alignment film 22 is a film obtained by rubbing the polyimide film.

  The TFT array substrate 10 and the counter substrate 20 thus configured are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, and the sealing material 53 (see FIG. 4 and FIG. 4) is disposed between these substrates. A liquid crystal 50 as an electro-optic material is sealed and sandwiched in a space surrounded by (see FIG. 5). The liquid crystal 50 takes a predetermined alignment state by the alignment film in a state where an electric field from the pixel electrode 9a is not applied. The liquid crystal 50 is made of, for example, one or a mixture of several types of nematic liquid crystals.

(Configuration of peripheral circuit)
4 and 6 again, in the electro-optical device 100 according to the present embodiment, the data line driving circuit 101 and the scanning line driving circuit 104 are provided on the surface side of the TFT array substrate 10 by using the peripheral area of the image display area 10a. Is formed. The data line driving circuit 101 and the scanning line driving circuit 104 are basically constituted by an N-channel TFT and a P-channel TFT shown in FIGS.

  8 and 9 are plan views showing the configuration of a complementary inverter circuit using TFTs constituting peripheral circuits such as the scanning line driving circuit 104 and the data line driving circuit 101, and the TFTs constituting this inverter circuit are shown in FIG. It is sectional drawing when cut | disconnecting by a 'line.

  In FIG. 8 and FIG. 9, the TFT constituting the peripheral circuit is configured as a CMOS TFT composed of a P-channel TFT 80 and an N-channel TFT 90. The semiconductor film 60 (the outline is indicated by a dotted line in FIG. 8) constituting the TFTs 80 and 90 for the drive circuit is formed in an island shape on the surface of the base insulating film 11 of the transparent substrate 10b.

  The high potential lines 71 and the low potential lines 72 are electrically connected to the source regions of the semiconductor film 60 through the contact holes 63 and 64, respectively, in the TFTs 80 and 90. The input wiring 66 is connected to the common gate electrode 65, and the output wiring 67 is electrically connected to the drain region of the semiconductor film 60 via the contact holes 68 and 69.

  Interlayer insulating films 4 and 5 and gate insulating film 2 are also formed in such a peripheral circuit region. Further, the TFTs 80 and 90 for the driving circuit have an LDD structure, and on both sides of the channel regions 81 and 91, a source region composed of the high concentration source regions 82 and 92 and the low concentration source regions 83 and 93, and a high A drain region comprising the concentration drain regions 84 and 94 and the low concentration drain regions 85 and 95.

  Further, in this embodiment, in both the P-channel TFT 80 and the N-channel TFT 90, the back gate gate insulating film 12 and the threshold voltage control back gate are provided below the channel regions 81 and 91. 76 and 77, and predetermined back gate potentials are applied to the back gates 76 and 77 from the threshold voltage control signal lines 73 and 74, respectively.

  Accordingly, the back gate potentials Vb-Nch and Vb-Pch applied to the back gates 76 and 77 of the TFTs 80 and 90 are set to optimum values for each CMOS circuit, as described in the first and second embodiments. The threshold voltages of the TFTs 80 and 90 can be optimized.

[Other embodiments]
In the above embodiment, the CMOS circuit formed in the scanning line driving circuit and the data line driving circuit has been described as an example of the first CMOS circuit and the second CMOS circuit having different driving voltages. In some cases, the TFTs constitute a CMOS circuit. In such a case, one of the first CMOS circuit and the second CMOS circuit may be used for pixel switching, and the other CMOS circuit may be used for the drive circuit.

  In the above embodiment, an active matrix liquid crystal device with a built-in driving circuit is described as an example of an electro-optical device. However, an electro-optical device using an electro-optical material other than liquid crystal, for example, referring to FIG. The present invention may be applied to the manufacture of a TFT array substrate used in the organic electroluminescence display device described in 1), or a thin film semiconductor device other than an electro-optical device.

  The present invention is not limited to the above-described embodiment, and may be applied to a TFT using amorphous silicon, or may be applied to the case where an electro-optical device is formed on a silicon wafer instead of an insulating substrate. Also, as a built-in circuit form, not only a simple circuit such as a shift register, but also a built-in DAC circuit or decoder circuit for digital / analog conversion of a video signal, or a graphic memory, and a sophisticated circuit such as a CPU are incorporated. You may do it. In addition, not all CMOS circuits are formed with a four-terminal structure transistor, but only a part of the CMOS circuit may be a four-terminal structure transistor. Good.

  FIG. 10 is a block diagram of an active matrix type electro-optical device using a charge injection type organic thin film electroluminescence element.

  The electro-optical device 100p shown in FIG. 10 is an active matrix type that drives and controls a light emitting element such as an EL (electroluminescence) element or an LED (light emitting diode) element that emits light when a driving current flows through an organic semiconductor film. Since all of the light-emitting elements that are display devices and are used in this type of electro-optical device self-emit, there is an advantage that a backlight is not required and that the viewing angle dependency is small.

  In the electro-optical device 100p shown here, on the TFT array substrate 10p, a plurality of scanning lines 3p, a plurality of data lines 6p extending in a direction intersecting with the extending direction of the scanning lines 3p, and these A plurality of common power supply lines 23p parallel to the data lines 6p and a pixel region 15p corresponding to the intersection of the data lines 6p and the scanning lines 3p are configured. For the data line 6p, a data side driving circuit 101p including a shift register, a level shifter, a video line, and an analog switch is configured. A scanning side drive circuit 104p including a shift register and a level shifter is configured for the scanning line 3p.

  Each pixel region 15p holds a first TFT 31p to which a scanning signal is supplied to the gate electrode via the scanning line 3p, and an image signal supplied from the data line 6p via the first TFT 31p. A storage capacitor 33p to be connected, a second TFT 32p (thin film semiconductor element) to which an image signal held by the storage capacitor 33p is supplied to the gate electrode, and a common power supply line 23p through the second TFT 32p. Thus, a light emitting element 40p into which a driving current flows from the common power supply line 23p is configured.

  Also in the TFT array substrate 10p of the electro-optical device 100p, the driving voltage is applied to the data side driving circuit 101p including the shift register, the level shifter, the video line, and the analog switch, and the scanning side driving circuit 104p including the shift register and the level shifter. Different CMOS circuits are formed by TFTs. Accordingly, even in the electro-optical device 100p, the TFT constituting the CMOS circuit has a four-terminal structure including a back gate for controlling the threshold voltage, and the back gate potential applied to the back gate is optimal for each CMOS circuit. By setting the value, the threshold voltage of the TFT may be optimized as described in the first and second embodiments.

[Application to electronic devices]
Next, an example of an electronic apparatus including the electro-optical devices 100 and 100p to which the present invention is applied will be described with reference to FIGS.

  11A and 11B are an explanatory diagram of a mobile personal computer as an example of an electronic apparatus using the electro-optical device according to the present invention, and an explanatory diagram of a mobile phone, respectively.

  Examples of the electronic apparatus on which the electro-optical device to which the present invention is applied include a projection type liquid crystal display device (liquid crystal projector), a multimedia-compatible personal computer (PC), an engineering work station (EWS), a pager, or a portable device. Examples include a telephone, a word processor, a television, a viewfinder type or a monitor direct-view type video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, a touch panel, and the like. For example, as shown in FIG. 11A, the personal computer 180 includes a main body 182 provided with a keyboard 181 and a display unit 183. The display unit 183 includes the electro-optical devices 100 and 100p described above. As shown in FIG. 11B, the mobile phone 190 includes a plurality of operation buttons 191 and a display unit including the electro-optical devices 100 and 100p described above.

  As described above, according to the present invention, in the first and second complementary circuits having different driving voltages, the N-channel field effect transistor and the P-channel field effect transistor are connected to the threshold voltage control back. Since the four-terminal structure including the gate is used and the back gate potential is optimized by making each field effect transistor different, the threshold voltage in the state controlled by the back gate of the N channel field effect transistor, and P The absolute value of the difference between the threshold voltages in the state controlled by the back gate of the channel field effect transistor can be made different in accordance with the driving voltage and can be optimized. For this reason, in order to achieve high-speed operation and low power consumption, even when the threshold voltage of the field effect transistor is reduced, the balance between the drive voltage and the threshold voltage is not achieved in each complementary circuit. Therefore, no malfunction occurs in the complementary circuit. Therefore, in the electro-optical device, high reliability can be ensured even when the number of pixels is increased, the operation speed is increased, and the power consumption is reduced.

(A) and (B) are explanatory diagrams of an inverter circuit using a CMOS circuit to which the present invention is applied and a clocked inverter circuit, respectively. It is explanatory drawing of threshold voltage Von-off in the circuit operation | movement surface of TFT. It is a graph which shows a response | compatibility with the threshold voltage Von-off in the circuit operation surface in TFT, and the physical threshold voltage Vth based on formation of an inversion layer. 1 is a plan view of a liquid crystal device (electro-optical device) to which the present invention is applied as viewed from the side of a counter substrate together with components formed thereon. It is HH 'sectional drawing of FIG. FIG. 5 is an equivalent circuit diagram of various elements and wirings formed in a plurality of pixels arranged in a matrix in the image display region of the electro-optical device shown in FIG. 4. FIGS. 4A and 4B are plan views showing the configuration of each pixel formed on the TFT array substrate in the electro-optical device shown in FIG. 4 and the electro-optical device cut at a position corresponding to the line AA ′. It is sectional drawing when doing. FIG. 5 is a plan view of a circuit formed in a peripheral area of an image display area of the electro-optical device shown in FIG. 4. It is B-B 'sectional drawing of FIG. It is a block diagram of an active matrix type electro-optical device using a charge injection type organic thin film electroluminescence element. 1A and 1B are an explanatory diagram showing a mobile personal computer as an embodiment of an electronic apparatus using an electro-optical device according to the present invention, and an explanatory diagram of a mobile phone, respectively. (A) and (B) are explanatory diagrams of an inverter circuit using a conventional CMOS circuit and a clocked inverter circuit, respectively. (A), (B), and (C) are waveform diagrams showing the relationship between an input signal and an output signal for a CMOS circuit, respectively.

Explanation of symbols

3a scanning line, 3b capacitance line, 6a data line, 9a pixel electrode, 10, 10p TFT array substrate (thin film semiconductor device), 30, 31p, 32p, 80, 90 TFT (field effect transistor), 73, 74, 111 , 112 Threshold voltage control signal line, 76, 77 Back gate, 100, 100p Electro-optical device

Claims (10)

A field effect transistor for switching pixels corresponding to each of a plurality of pixels arranged in a matrix and a drive circuit for driving the plurality of pixels are formed on a substrate for holding an electro-optical material. And a field effect transistor for the driving circuit is formed,
The plurality of field effect transistors include N-channel field effect transistors constituting a first complementary circuit and a second complementary circuit having different driving voltages defined by the input signal and the maximum voltage difference between power supplies. And an electro-optical device including a P-channel field effect transistor,
The N-channel field effect transistor and the P-channel field effect transistor are configured as a four-terminal structure including a back gate for threshold voltage control,
A back gate potential defined by an average value of potentials applied between a back gate and a source of the N-channel field effect transistor having the four-terminal structure, and a back gate of the P-channel field effect transistor having the four-terminal structure; -When the back gate potential defined by the average value of the potential applied between the sources is Vb-Nch and Vb-Pch, respectively.
The back-gate potential Vb-Nch and the back-gate potential Vb-Pch are different in the four-terminal N-channel field effect transistor and the four-terminal P-channel field effect transistor that constitute the same complementary circuit. ,And,
In the first complementary circuit and the second complementary circuit, the back gate potential Vb-Nch of the N-channel field effect transistor having the 4-terminal structure or the back-gate potential of the P-channel field effect transistor having the 4-terminal structure is used. An electro-optical device, wherein at least one of gate potentials Vb-Pch is different. 2. The minimum value of a gate voltage when an inversion layer is formed in a channel in a state where a back gate is short-circuited with a source potential in the N-channel field effect transistor having the 4-terminal structure, and the 4-terminal structure. When the maximum value of the gate voltage is Vth-Nch and Vth-Pch when the inversion layer is formed in the channel with the back gate short-circuited to the source potential in the P-channel field effect transistor of FIG.
In at least one complementary circuit of the first complementary circuit and the second complementary circuit, the following equation | ((Vth−Nch) − (Vb−Nch)) − ((Vth−Pch) − (Vb -Pch)) |
The electro-optical device is characterized in that the value Vth-d obtained in (1) is in the range of 0.25 to 1 times the drive voltage of the complementary circuit.   3. In at least one of the first complementary circuit and the second complementary circuit according to claim 2, the value Vth-d is 0.5 times to 1 with respect to the driving voltage of the complementary circuit. An electro-optical device characterized in that the range is double. The complementary circuit of claim 2 or 3, wherein at least one of the first complementary circuit and the second complementary circuit is
| ((Vth−Nch) − (Vb−Nch)) + ((Vth−Pch) − (Vb−Pch)) |
The electro-optical device is characterized in that the value obtained in (1) is not more than 1/4 times the driving voltage of the complementary circuit. In any one of claims 1 to 4, wherein at least one of the complementary circuit of the first complementary circuit and the second complementary circuit, the back gate potential of the N-channel type field effect transistor of the four-terminal structure Vb An electro-optical device, wherein -Nch is a negative potential, and the back gate potential Vb-Pch of the four-channel P-channel field effect transistor is a positive potential. In any one of claims 1 to 5, wherein the first complementary circuit and the second complementary circuit to an electro-optical device, characterized in that one has also been configured to the drive circuit. In any one of claims 1 to 6, wherein the field effect transistor, an electro-optical device, wherein the active layer is a thin film transistor made of polycrystalline silicon. In any one of claims 1 to 7, wherein the electro-optical material, an electro-optical device, wherein the a liquid crystal held between the electro-optical device substrate and the counter substrate. In any one of claims 1 to 8, wherein the electro-optical material, an electro-optical device, characterized in that the organic electroluminescent material constituting the light-emitting element in the electro-optical device substrate. An electronic apparatus using the electro-optical device defined in any one of claims 1 to 9 .

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