JP4488688B2 - Wiring substrate for display device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board used in a display device such as a liquid crystal display device and a manufacturing method thereof. In particular, the present invention relates to a wiring board provided with a thick resin film.
[0002]
[Prior art]
2. Description of the Related Art In recent years, flat display devices have been actively developed as display devices that can replace CRT displays. In particular, liquid crystal display devices have attracted attention because of their advantages such as light weight, thinness, and low power consumption. In particular, an active matrix type liquid crystal display device in which a switch element is electrically connected to each pixel electrode can realize a good display image without crosstalk between adjacent pixels, and is therefore a mainstream of liquid crystal display devices. Yes.
[0003]
In the following, a light transmissive active matrix liquid crystal display device using a TFT (Thin Film Transistor) as a switching element will be described as an example.
[0004]
An active matrix type liquid crystal display device is formed by holding a liquid crystal layer between an array substrate and a counter substrate via an alignment film. In an array substrate, on a transparent insulating substrate such as glass or quartz, a plurality of signal lines and a plurality of scanning lines are arranged in a lattice shape with an insulating film interposed therebetween, and in an area corresponding to each square of the lattice. A pixel electrode made of a transparent conductive material such as ITO (Indium-Tin-Oxide) is disposed. A TFT as a switching element having a function of electrically separating the on-pixel and the off-pixel and holding a video signal to the on-pixel is disposed at each intersection portion of the lattice. The gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to the pixel electrode.
[0005]
The counter substrate includes a counter electrode made of ITO on a transparent insulating substrate such as glass, and a color filter layer if a color display is realized.
[0006]
At the outer periphery of the display area of the liquid crystal display device, the array substrate protrudes from the counter substrate to form a shelf-like connection area. The connection pads arranged in this connection area and the terminals for inputting from the external drive system And are connected. Further, a sealing material is disposed between the edge portion of the counter substrate and the array substrate to seal the four circumferences of the liquid crystal layer.
[0007]
In reducing the manufacturing cost of such an active matrix liquid crystal display device, there is a problem that the number of steps for manufacturing the array substrate is large, and therefore the cost ratio of the array substrate is high.
[0008]
Therefore, in Japanese Patent Laid-Open No. 9-160076, the pixel electrode is arranged in the uppermost layer, and along with this, the semiconductor film and the like are patterned together with the signal line, source and drain electrodes based on the same mask pattern. Later, it has been proposed to simultaneously produce a contact hole for a source electrode for connecting a source electrode and a pixel electrode, and an outer peripheral contact hole for exposing a connection end of a signal line or a scanning line. Thereby, productivity can be improved with a small number of masks, and the manufacturing yield is not reduced.
[0009]
Here, in order to create the outer peripheral contact hole for exposing the connection end of the scanning line, it is necessary to penetrate not only the interlayer insulating film but also the gate insulating film. Therefore, wet etching using BHF or the like has been performed so that a gate insulating film including a silicon oxide layer and an interlayer insulating film made of a silicon nitride film can be simultaneously penetrated (Japanese Patent Laid-Open No. 2000-267595).
[0010]
On the other hand, in such an array substrate, it is required to improve the aperture ratio of the pixel portion so as to improve the utilization efficiency of backlight light. In addition, when used in a reflective flat display device, it is required to improve the effective reflectance of light by increasing the area ratio of the pixel electrode.
[0011]
Therefore, in recent years, in order to improve the pixel aperture ratio and the light reflectance, the pixel electrode is arranged on the wiring pattern of the array substrate or the upper layer of the TFT through the insulating thick resin film, and the outer edge of the pixel electrode is arranged. Is superimposed on the signal line and the scanning line. The thick resin film is generally composed of a low dielectric constant organic resin having a thickness of 1 to 10 μm, typically 2 to 4 μm. Between the pixel electrode and the signal line and the like stacked therethrough, It is possible to sufficiently reduce the possibility of occurrence of electric capacity and short circuit.
[0012]
Conventionally, the light shielding film is on the counter substrate or the array substrate, and not only the location of the TFT, but also the interval between the edge of the pixel electrode and the signal line, and the edge of the pixel electrode and the scanning line. It was also provided at the place covering the gap between the two. This absorbs misalignment between the pattern of the pixel electrode and the pattern of the signal line or the scan line while sufficiently preventing an undesired electric capacity or short circuit due to the overlap of the pixel electrode and the signal line or the scan line, This was necessary to reliably prevent light leakage from the interval.
[0013]
With the configuration in which the thick resin film is arranged, loss of the pixel opening due to the alignment margin can be eliminated, so that the pixel aperture ratio can be greatly improved.
[0014]
In particular, in an array substrate used in a reflective liquid crystal display device, a reflective pixel electrode made of aluminum (Al) or the like is formed on the uppermost layer of the array pattern, and this reflective electrode layer and a lower wiring layer are formed. A thick resin film is disposed between the two. This thick resin film makes it possible to arrange the reflective pixel electrode so that the edge of the reflective pixel electrode covers the scanning line, the signal line, and the TFT, thereby improving the pixel electrode area and improving the light utilization efficiency. It is. By interposing the thick resin film, an increase in parasitic capacitance due to superposition is prevented. In addition, the thick resin film generally serves as a flattening film for making the height of the pixel electrode uniform from the surface of the insulating substrate and making the thickness of the liquid crystal layer uniform.
[0015]
[Problems to be solved by the invention]
Recently, as the required performance of a display device in a portable information terminal or a mobile phone has improved, use of a display device of a type called a transflective type or a transflective type has been studied. This comprises a transparent conductive film (such as ITO) having light transparency and a reflective electrode having light reflectivity in one pixel electrode, and in a bright environment such as sunlight, a reflective electrode plate Display is performed by reflection of external light at the (reflective pixel electrode portion), and display is performed by backlight light passing through the transparent conductive film portion, that is, the transparent electrode portion, in a dark environment.
[0016]
In such a transflective display device, two types of conductive layers are required to form pixel electrodes, and it is necessary to perform patterning on each of them. Therefore, a patterning process (PEP: Photo Engraving Process) is increased by one as compared with the case of producing a reflective liquid crystal display device that is not a transflective type. The number of mask patterns required increases as the number of patterning steps increases, and the number of steps of resist resin coating, development, etching, resist stripping, and cleaning increases, resulting in an increase in process burden and manufacturing cost. .
[0017]
In order to reduce the number of patterning steps, for example, it is conceivable to form a contact hole that penetrates the gate insulating film or the like using the pattern of the thick resin film as it is as a mask. A contact hole having a shape aligned with the contact hole of the thick resin film is provided in the gate insulating film or the like.
[0018]
However, in this case, due to side etching or the like of the gate insulating film, an overhang portion is generated, which causes a discontinuous portion (so-called “step break”) in the conductive film covering the contact hole. was there.
[0019]
The present invention has been made in view of the above problems, and in a display device and a manufacturing method thereof, an apparatus capable of improving manufacturing efficiency and reducing manufacturing cost and process burden without causing connection failure and the like, and A method is provided.
[0020]
[Means for Solving the Problems]
The array substrate of the present invention includes a first conductive layer pattern formed on the substrate, a first insulating film disposed on the first conductive layer pattern and having an opening corresponding to the pattern, A second insulating film having a diameter larger than the opening of the first insulating film and having a contact hole whose inner wall is covered with the second conductive layer; and formed on the second conductive layer, via the contact hole A third conductive layer connected to the first conductive layer is provided, and an upper end of the opening of the first insulating film and an opening of the second conductive layer have the same shape.
[0021]
For example, the first conductive layer pattern on the insulating substrate, the gate insulating film covering the first conductive layer pattern, and the second conductive layer pattern formed on the first conductive layer pattern, and scanning lines arranged substantially in parallel, A multilayer wiring pattern including signal lines arranged substantially orthogonal to each other through the gate insulating film, switching elements provided in the vicinity of the intersections of the scanning lines and the signal lines, and a thickness covering the multilayer wiring pattern At least one of an insulating resin film having a thickness of 1 μm or more, a pattern of the third conductive layer and the pattern of the fourth conductive layer disposed on the resin film, and the pattern of the third and fourth conductive layers A pixel electrode arranged in a matrix in a pixel region, a first contact hole that penetrates the resin film and the gate insulating film and partially exposes a pattern of the first conductive layer, and the resin And the second contact hole that partially exposes the pattern of the second conductive layer, wherein the first and second contact holes are substantially entirely composed of the pattern of the fourth conductive layer including the bottom surface. The first contact hole is provided with a perforated pattern made of the third conductive layer, in which a region from the bottom surface to the upper edge of the end surface of the gate insulating film is omitted.
[0022]
With the above configuration, the number of patterning steps can be reduced, thereby improving the manufacturing efficiency and reducing the manufacturing cost and the process burden.
[0023]
When an insulating film made of a non-resin material such as an interlayer insulating film is interposed between the laminated wiring pattern and the resin film, the perforated pattern of the first contact hole is formed from the bottom surface to the insulating film. The area that reaches the upper edge of the end face of this is omitted.
[0024]
In the method for manufacturing an array substrate of the present invention, for example, a pattern of a first conductive layer, a gate insulating film covering the first conductive layer, and a pattern of a second conductive layer formed thereon are formed on an insulating substrate. Thus, the scanning lines arranged substantially in parallel, the signal lines arranged so as to be substantially orthogonal to the scanning lines via the gate insulating film, and the switching elements provided near the intersections of the scanning lines and the signal lines And forming an insulating resin film having a thickness of 1 μm or more covering the laminated wiring pattern and an upper contact hole penetrating the photosensitive resin by applying, exposing and developing the photosensitive resin. Forming a lower contact hole that exposes the pattern of the first conductive layer within the contour of the upper contact hole by etching, and on the resin film, And forming a pattern of the fourth conductive layer, and at this time, providing a pixel electrode made of at least one of the conductive layers corresponding to each of the switching elements. And after forming the resin film and the upper contact hole, depositing the third conductive layer, and forming a resist pattern having an opening inside the lower edge of the inner wall of each upper contact hole; and A first etching for patterning the third conductive layer along a resist pattern, and subsequently an etching solution is applied through the opening under the resist pattern, and the gate etching is performed under a condition that a side etching dimension is smaller than the predetermined dimension. By removing the insulating film, the inner wall surface after the side etching is placed in front of the lower contact hole. Second etching formed so as to be located inside the lower edge of the inner wall of the upper layer contact hole, and further, the third conductivity projecting to the opening of the resist pattern along the lower surface of the resist pattern. A third etching for removing the eaves-like portion by applying an etching solution to the eaves-like portion of the layer from the back side through the lower layer contact hole, and then removing the resist pattern and then removing the resist pattern. 4 conductive layer deposition and patterning.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
<Example 1>
The array substrate of Example 1 and the method for manufacturing the same will be described with reference to FIGS.
[0026]
FIG. 1 is a schematic process diagram with partial lamination sectional views for explaining the main part of the manufacturing method of the embodiment. FIG. 2 is a schematic plan view of the array substrate 10 of the embodiment. FIGS. 3 and 4 are stacked structures of a pixel portion and a peripheral portion of the display panel 100 including the array substrate 10 of the embodiment, respectively. Indicates.
[0027]
First, the configuration of the array substrate 10 will be described with reference to FIGS.
[0028]
As shown in FIGS. 2 to 3, near the intersection of the lower scanning line 11 and the upper signal line 31, signal input from the signal line 31 to the pixel electrode 6 is performed according to the pulse voltage applied to the scanning line 11. A TFT 9 for switching is disposed. The gate electrode 11 a of the TFT 9 is formed by an extending portion from the scanning line 11, and the drain electrode 32 of the TFT 9 is formed by an extending portion of the signal line 31. The source electrode 33 of the TFT 9 is electrically connected to the pixel electrode 6 through a contact hole 53 that penetrates the translucent thick resin film 5.
[0029]
The pixel electrode 6 is disposed in a grid-like area (pixel dot area) defined by the scanning line 11 and the signal line 31 so as to be electrically insulated from each other, covers substantially the entire area, and has both edges. Is superimposed on the signal line 31. Each pixel electrode 6 is made of metal, in this case, one reflective pixel electrode 73 and a transparent pixel electrode 63a, 63b and 63c having optical transparency such as ITO. The transparent pixel electrodes 63a, 63b, and 63c are arranged at positions corresponding to the three window-shaped openings of the reflective pixel electrode 73, and the inner edge of the window-shaped opening of the reflective pixel electrode and the outer edges of the transparent pixel electrodes 63a, 63b, and 63c. The parts are directly superposed and are connected to each other.
[0030]
The reflective pixel electrode 73 is formed with a concavo-convex pattern to improve the light scattering property.
[0031]
The translucent thick resin film 5 is made of, for example, an insulating resin material having a thickness of 1 μm or more and a low dielectric constant. In particular, it is made of a photosensitive curable organic resin material such as an acrylic resin. The thick resin film 5 covers almost the entire surface of the array substrate except for the locations where the connection pads 14 are arranged and the locations of the upper contact holes 51 to 53.
[0032]
Near the center of the pixel dot, in the region covered by the reflective pixel electrode 73, the auxiliary capacitance line wide portion 12 a made of the same material as the scanning line and the auxiliary capacitance extension portion 35 extending from the source electrode 33. And the auxiliary capacitance of the pixel electrode 6 is formed.
[0033]
As shown in FIGS. 2 and 4, the connection pads 14 are arranged in the extraction region 54 of the thick resin film 5 at the peripheral edge for connection. The connection pad 14 is made of the same material in the same process as the scanning line 11, the pad wiring 14 a extending from the connection pad 14 to the inside of the substrate, the contact holes 41, 51, 52, and the bridge shape covering them. The conductive film 71 is electrically connected to the tip 31 a of the signal line 31. Here, at the end of the pad wiring 14 a, a lower contact hole 41 that penetrates the gate insulating film 15 is disposed at the bottom of the upper contact hole 51 that penetrates the thick resin film 5. On the other hand, only the upper layer contact hole 52 penetrating the thick resin film 5 is disposed at the tip 31a of the signal line.
[0034]
FIG. 1 shows a process of forming a lower layer contact hole 41 at an end portion of the pad wiring 14a on the inner side of the substrate. The outline of this process is as follows.
[0035]
First, a resist pattern 8 is provided on the pattern of the thick resin film 5. The resist pattern 8 is provided with an opening 81 having a smaller diameter than the upper contact hole 51 passing through the thick resin film 5.
[0036]
Under this resist pattern 8, the following three stages of wet etching (1) to (3) are performed. Subsequently, the step (4) of forming the bridge-like conductive film 71 is performed.
[0037]
(1) First etching (ITO pattern formation; 5PEP (1), FIG. 7)
The a-ITO film is patterned along the contour of the resist pattern 8 with an oxalic acid solution that etches only the a-ITO film. As a result, an ITO film pattern 61 ′ that covers the upper contact hole 51 and the vicinity thereof except for the inside of the opening 81 is formed.
[0038]
At the same time, transparent pixel electrodes 63a, 63b and 63c are formed in the pixel region.
[0039]
(2) Second etching (through hole formation; 5 PEP (2))
The gate insulating film 15 made of silicon oxide or the like is etched with a wet etching solution, and a lower contact hole 41 penetrating the gate insulating film 15 is formed. In this etching, side etching is large, and the formed lower contact hole 41 has a considerably larger diameter than the opening 81 of the resist pattern 8. Therefore, in the region between the lower edge of the opening 81 and the upper edge of the lower layer contact hole 41, an “eave-like portion” 6a in which the ITO film protrudes inward is formed.
[0040]
(3) Third etching (back etching of ITO; 5 PEP (3), FIG. 8)
Again, using the aqueous oxalic acid solution, the “eave portion” 6a is removed. At this time, an etching solution acts from the back side of the resist pattern 8 through the lower layer contact hole 41 formed by the second etching. That is, “back etching” is performed.
[0041]
As a result of the series of patterning, a perforated ITO film patch 61 from which the lower contact hole 41 is omitted is formed.
[0042]
Thereafter, the resist pattern 8 is peeled off, washed, and the a-ITO film is annealed (crystallization by heating).
[0043]
(4) Formation of the uppermost metal pattern (6PEP, FIG. 9)
After a laminated film (Mo / Al) of a molybdenum metal film and an aluminum metal film is deposited, further resist application, exposure using a photomask, and development are performed. Then, a bridge-like conductive film 71 is formed by etching to cover a region from the location of the lower layer contact hole 41 and the upper layer contact hole 51 connected thereto to the adjacent upper layer contact hole 52. At this time, the reflective pixel electrode 73 is formed in the pixel region.
[0044]
Next, the manufacturing process of the array substrate 10 will be described in detail with reference to FIGS.
[0045]
When the array substrate 10 is manufactured, each large-sized original substrate (for example, 550 mm X 650 mm) is used for each liquid crystal display device for each region having a predetermined dimension (for example, a diagonal dimension of 2.2 inches). Wiring / film formation pattern is formed. Similarly, after being bonded together with the original substrate for the counter substrate created in a large format through a sealing material and a spacer, a cell structure corresponding to each liquid crystal display device is cut out.
[0046]
(1) First patterning (Figure 5)
A molybdenum-tungsten alloy film (MoW film) is deposited on the glass substrate 18 by sputtering to a thickness of 230 nm. Then, by patterning using the first photomask, 176 scanning lines 11, gate electrodes 11a composed of the extended portions, and scanning lines 11 are formed for each rectangular area having a diagonal size of 2.2 inches (56 mm). And approximately the same number of auxiliary capacitance lines (Cs wirings) 12 are formed. In the example shown in the figure, the auxiliary capacitance line 12 is arranged approximately in the middle of the adjacent scanning line 11, and for each pixel dot, a single substantially square-shaped wide portion 12 a is avoided by avoiding the vicinity of the arrangement position of the signal line 31. Forming.
[0047]
At the same time, the connection pad 14 and the pad wiring 14a extending from the connection pad 14 are formed at the peripheral portion.
[0048]
(2) Second patterning (Figure 6)
First, a 350 nm thick silicon oxide film (SiOx film) that forms the first gate insulating film 15a is deposited. After the surface is treated with hydrofluoric acid, 40 nm to 50 nm silicon nitride film (SiNx film) forming the second gate insulating film 15b and 50 nm thick amorphous silicon (a-Si) for forming the semiconductor film 36 of the TFT 9 are formed. : H) and a silicon nitride film (SiNx film) having a film thickness of 200 nm for forming the channel protection film 21 and the like of the TFT 9 are continuously formed without being exposed to the atmosphere (FIG. 3).
[0049]
After the resist layer is applied, a channel protective film 21 is formed on each gate electrode 11a by a backside exposure technique using a pattern such as the scanning line 11 obtained by the first patterning as a mask.
[0050]
(3) Third patterning (Figure 6)
After the exposed surface of the amorphous silicon (a-Si: H) layer is treated with hydrofluoric acid so that a good ohmic contact can be obtained, a phosphorus-doped amorphous silicon (50 nm thick) for forming the low-resistance semiconductor film 37 ( n ⁺ a-Si: H) layer is deposited by the CVD method similar to the above (FIG. 3).
[0051]
Thereafter, a three-layer metal film (Mo / Al / Mo) composed of a bottom Mo layer having a thickness of 25 nm, an Al layer having a thickness of 250 nm, and a top Mo layer having a thickness of 50 nm is deposited by sputtering.
[0052]
Then, after exposing and developing the resist using a third photomask, the a-Si: H layer, n ⁺ The a-Si: H layer and the three-layer metal film (Mo / Al / Mo) are patterned at once. By this third patterning, 220 × 3 signal lines 31, a drain electrode 32 extending from each signal line 31, a source electrode 33, and a rectangular area having a diagonal dimension of 2.2 inches (56 mm) are provided. Create
[0053]
At the same time, an auxiliary capacity extension portion (Cs pattern) 35 that slightly protrudes from the outer peripheral edge of the wide portion 12 a is disposed so as to substantially overlap the wide portion 12 a of the auxiliary capacitance line 12. The auxiliary capacitor extension portion 35 is a rectangular pattern further extended from a straight line 33 a extending from the source electrode 33 along the signal line 31.
[0054]
(4) Fourth patterning
On the multilayer film pattern obtained as described above, a positive photosensitive curable resin liquid made of an acrylic resin is uniformly applied by a coater so that the film thickness after drying becomes 2 μm. Then, after performing an exposure operation as described below, development, ultraviolet irradiation, post-baking, and cleaning operations are performed. The ultraviolet irradiation is an operation for improving the light transmittance of the thick resin film 5 by reducing unreacted portions in the thick resin film 5.
[0055]
In the exposure operation, strong exposure is performed at the positions where the upper contact holes 51 to 53 are provided and the extraction area 54 for the connection pad, and weak exposure is performed at the positions where the recess 56 is provided in the reflective pixel electrode area. (See FIGS. 2-3).
[0056]
For example, it is possible to prepare two photomasks, and perform strong exposure under one photomask and weak exposure under the other photomask. This “strong exposure” and “weak exposure” can be performed by appropriately adjusting the accumulated exposure amount of effective light rays by adjusting the exposure intensity and the exposure time.
[0057]
The upper contact holes 51 to 53 and the pad punching region 54 penetrating the thick resin film 5 are formed at the place where the “strong exposure” has been received. The place where the “weak exposure” has been received has a depth of, for example, 1 μm. A concave portion 56 having a thickness is formed.
[0058]
By providing a large number of concave portions 56 in the region where the reflective pixel electrode 73 is disposed, an uneven pattern for providing the reflective pixel electrode 73 with a light scattering function is formed.
[0059]
In the illustrated example, the thick resin film 5 functions as a flattening film that makes the thickness of the liquid crystal layer substantially uniform when assembled in a liquid crystal display device, and allows the pixel electrodes to be overlaid on signal lines and the like. By doing so, it plays a role of improving the light utilization efficiency.
[0060]
In the above description, it has been described that the thick resin film 5 is formed of a positive photosensitive resin. However, a negative photosensitive resin can also be used. In this case, a region where no exposure is performed and a region where strong exposure is performed are interchanged, but a region where weak exposure is performed is exactly the same.
[0061]
Further, in the above description, instead of using two photomasks, a step is provided in the integrated exposure amount by using a photomask having a mesh pattern in a predetermined region, that is, by adopting so-called halftone patterning. You can also.
[0062]
(5) Fifth patterning (FIGS. 7-8 and FIG. 1)
After depositing 40-nm thick a-ITO as a transparent conductive layer, resist coating, exposure and development are performed. Then, under this resist pattern 8, the following three-stage etching operation is performed. The resist pattern 8 has an opening at the location of the upper contact hole 51. At the end portion of the pad wiring 14 a, the size of the opening 81 is slightly smaller than the inner diameter (that is, the bottom surface diameter) of the upper contact hole 51.
[0063]
(5-1) Formation of ITO pattern (Figure 7)
First, the a-ITO film other than the portions covered with the resist pattern 8 is removed by processing for about 50 seconds at 45 ° C. using an aqueous oxalic acid solution as an etching solution. That is, a pattern of an a-ITO film having a shape along the resist pattern 8 is created.
[0064]
As a result, three substantially rectangular patterns 63a, 63b, and 63c forming the transmissive pixel electrode 63 are formed for each pixel dot.
[0065]
At the same time, at the peripheral edge of the array substrate, an ITO film pattern 61 ′ having a small hole and a larger hole is formed so as to cover the wall surfaces of the pair of upper contact holes 51. At the same time, a pad coating ITO layer 64 ′ is formed so as to cover the connection pad 14 except for the central linear region.
[0066]
(5-2) Through hole formation (upper part of Fig. 1)
Next, a buffered hydrofluoric acid (BHF, hydrogen fluoride-ammonium fluoride buffer solution is used as an etchant, for example, at a temperature of 28 ° C. for 120 seconds by a spray method, thereby forming the scanning line 11 (gate line) simultaneously. The gate insulating film 15 is removed in the region of the bottom surface of the upper contact hole 51 so as to expose the upper surface of the pad wiring 14a that has been formed in. The buffered hydrofluoric acid is, for example, 6% hydrogen fluoride and 30%. The etching time is set so that side etching does not become excessive, and the inner wall surface of the lower contact hole 41 to be formed forms a tapered surface with an inclination of about 45 °. .
[0067]
As shown in the upper part of FIG. 1, considerable side etching occurs in the gate insulating film 15 during wet etching for forming a through hole. Therefore, the inner diameter D1 (bottom diameter) of the opening 81 of the resist pattern 8 is slightly marginal to the dimension d of the side etching on both sides than the inner diameter D2 of the bottom of the corresponding upper contact holes 51 to 53 of the resin film. The size is set smaller by adding That is, D1 = D2-2 (d + m). The margin m is about 2 μm in the specific example of this embodiment.
[0068]
This margin m takes into account some variation in the conditions of side etching, and the upper edge of the lower contact hole 41 penetrating the gate insulating film 15 corresponds to the upper layer contact hole 51 penetrating the thick resin film 5, respectively. It is set so that it is always inside the lower edge (bottom edge). This is to prevent the conductive layer covering the wall surface of the contact hole from causing a so-called “step break” due to the formation of the overhang portion.
[0069]
(5-3) Back etching of a-ITO (middle of Fig. 1 and Fig. 8)
Again, using an aqueous oxalic acid solution as an etchant, for example, by treating at 45 ° C. for 15 seconds, the “eave-like portion” 6 a of a-ITO resulting from side etching of the gate insulating film 15 is removed. As schematically shown in the middle part of FIG. 1, etching caused by the etching solution flowing to the back side of the resist pattern 8, that is, “back etching” is performed.
[0070]
After the back etching is completed, the resist pattern 8 is peeled off, and after cleaning, annealing for crystallizing a-ITO is performed.
[0071]
After the back etching, the inner edge of the patch-like ITO film covering the vicinity of the contact hole 51 is located in a shelf-like region between the upper edge of the lower layer contact hole 41 and the lower edge of the upper layer contact hole 51. Then, as a result of removing the lower contact hole 41 and the exposed portion of the connection pad 14 from the ITO film pattern 61 ′ and the pad covering ITO layer 64 ′, the ITO film patch 61 and the connection pad 14 of one hole are formed at the peripheral portion. A bordered ITO film patch 64 is formed to surround the exposed portion.
[0072]
(6) Sixth patterning (bottom of FIGS. 8 and 1)
A laminated film (Mo / Al) composed of a molybdenum metal film with a thickness of 50 nm and an aluminum metal film with a thickness of 50 nm thereon is deposited by sputtering. Thereafter, after forming a resist pattern using a photomask, the bridge-like conductive film 71 covering the pair of adjacent lower layer contact holes 41 and 42, the pad coating portion 74, and the large size of each pixel dot are formed by wet etching patterning. A reflective pixel electrode 73 covering the portion is created.
[0073]
In each pixel dot, the reflective pixel electrode 73 has transmissive openings 73a, 73b, and 73c so as to expose portions other than the peripheral portions of the previously formed transmissive pixel electrodes 63a, 63b, and 63c. Further, the pixel electrodes 63a, 63b, and 63c are electrically connected to each other by being overlapped with the peripheral portions of the transmissive pixel electrodes 63a, 63b, and 63c.
[0074]
The reflective pixel electrode 73 also covers the portion of the TFT 9 and is directly connected to the source electrode 33 through the contact holes 43 and 53 on the source electrode 33 to be conductive. Further, the reflection pixel electrode 73 has an edge along the signal line 31 overlapped with both edges of the signal line 31 with the thick resin film 5 interposed therebetween.
[0075]
In this manner, the array substrate 10 in the state of a large original substrate is completed.
[0076]
The original substrate of the counter substrate 102 combined with this is (i) formation of a light shielding layer pattern (black matrix) 108, (ii) red (R), blue (B), and green (G) colors for each pixel dot. It is formed through the steps of forming the filter layer 109, (iii) forming columnar spacers, and (iv) forming an ITO film forming the counter electrode 107.
[0077]
Thereafter, a sealing material 105 is applied to any one of the original substrates, and is subjected to pressure bonding and curing. After the cell structure is cut out by scribing, the display panel 100 main body is created by injecting the liquid crystal material 103 and sealing the injection port, and then the liquid crystal display through the mounting of the TCP and drive circuit board and the assembly of the backlight device The device is completed.
[0078]
Although not shown in FIGS. 3 to 4, an alignment film for determining the alignment of the liquid crystal material in contact with the outermost layer on the liquid crystal side of the array substrate 10 and the counter substrate 102 is a resin made of polyimide (PI) or the like. It is formed by the film formation and the subsequent rubbing process. A polarizing plate 104 is attached to the outer surface side of the array substrate 10 and the counter substrate 102.
[0079]
<Comparative Example 1>
Next, a manufacturing method of a comparative example will be described with reference to FIG.
[0080]
In the array substrate manufacturing method of the comparative example, the pattern of the thick resin film 5 was used as a mask to pattern the gate insulating film on the lower layer side. In order to collectively etch the silicon oxide film or the silicon oxynitride film, buffered hydrofluoric acid was used as in the above example.
[0081]
As a result, as shown in the upper part of FIG. 10, due to side etching, the lower edge of the upper contact hole 51 protrudes from the upper edge of the lower contact hole 41 to the inside of the contact hole, An overhang covering the edge was formed all around. Therefore, when the metal film 71 ′ covering the upper and lower contact holes 51, 41 is provided, a “step break” 71 a is generated in the metal film 71 ′.
[0082]
<Example 2>
The array substrate of Example 2 and the manufacturing method thereof will be described with reference to FIGS.
[0083]
FIG. 11 is a schematic process diagram 1 according to a partially laminated cross-sectional view 1 for explaining a main part of the manufacturing method of the second embodiment. FIG. 12 is a schematic plan view of the array substrate 10 ′ according to the second embodiment. FIGS. 13 and 14 respectively illustrate pixel portions of the display panel 100 ′ including the array substrate 10 ′ according to the second embodiment. The laminated structure of a peripheral part is shown.
[0084]
First, the configuration of the array substrate 10 ′ will be described with reference to FIGS.
[0085]
In the pixel portion, as shown in FIGS. 12 to 13, the interlayer insulating film 4 is superimposed on the light-transmitting thick resin film 5 from below in the same configuration as in the first embodiment (thick type). The structure further includes an interlayer insulating film 4 between the resin film 5 and the gate insulating film 15), and the source electrode 33 of the TFT 9 is formed through contact holes 43 and 53 that penetrate the interlayer insulating film 4 and the light-transmitting thick resin film 5. The pixel electrode 6 is electrically connected. In addition, a donut-shaped ITO film 62 with a hole is formed in the contact holes 43 and 53.
[0086]
As shown in FIGS. 12 and 14, in the peripheral portion, in the same configuration as in the first embodiment, the tip portion 31a of each signal line 31 and the inside of the substrate from the connection pad 14 are configured as follows. A bridge-like conductive film 71 formed at the same time as the pixel electrode covers the entire arrangement region of the contact holes 41, 42, 51, 52 at a connection point with the pad wiring 14 a extending to the edge.
[0087]
FIG. 11 shows a process of forming the lower layer contact hole 41 at the end of the substrate inside the pad wiring 14a. The outline of this process is as follows.
[0088]
First, a resist pattern 8 is provided on the pattern of the thick resin film 5. The resist pattern 8 is provided with an opening 81 having a smaller diameter than the upper contact hole 51 passing through the thick resin film 5.
[0089]
Under this resist pattern 8, the following three stages of wet etching (1) to (3) are performed. Subsequently, the step (4) of forming the bridge-like conductive film 71 is performed.
[0090]
(1) First etching (formation of ITO pattern; 5PEP (1), FIG. 17)
The a-ITO film is patterned along the contour of the resist pattern 8 with an oxalic acid solution that etches only the a-ITO film. Thereby, an ITO film pattern 61 ′ covering the upper contact hole 51 and the vicinity thereof is formed.
[0091]
At the same time, transparent pixel electrodes 63a, 63b and 63c are formed in the pixel region.
[0092]
(2) Second etching (through hole formation; 5 PEP (2))
The interlayer insulating film 4 made of silicon nitride and the gate insulating film 15 made of silicon oxide are etched by one wet etching solution, and a lower contact hole 41 penetrating the insulating films 4 and 15 is formed. In this etching, side etching is large, and the formed lower contact hole 41 has a considerably larger diameter than the opening 81 of the resist pattern 8. For this reason, in the region between the lower edge of the opening 81 and the upper edge of the lower layer contact hole 41, an “eave-like portion” in which the ITO film protrudes inward is formed.
[0093]
At the same time, a contact hole 43 exposing the source electrode 33 is formed in the interlayer insulating film 4 in the pixel region.
[0094]
(3) Third etching (back etching of ITO; 5 PEP (3), FIG. 18)
Again, using the aqueous oxalic acid solution, the “eave portion” 6a is removed. At this time, an etching solution acts from the back side of the resist pattern 8 through the lower layer contact hole 41 formed by the second etching. That is, “back etching” is performed.
[0095]
As a result of the series of patterning, a perforated ITO film patch 61 from which the lower contact hole 41 is omitted is formed.
[0096]
Thereafter, the resist pattern 8 is peeled off, washed, and the a-ITO film is annealed (crystallization by heating).
[0097]
(4) Formation of uppermost metal pattern (6PEP, FIG. 19)
After a laminated film (Mo / Al) of a molybdenum metal film and an aluminum metal film is deposited, further resist application, exposure using a photomask, and development are performed. Then, a bridge-like conductive film 71 is formed by etching to cover a region from the lower contact hole 41 shown in FIG. 11 to the adjacent lower contact hole 42 (FIG. 19). At this time, the reflective pixel electrode 73 is formed in the pixel region.
[0098]
Next, the manufacturing process of the array substrate 10 ′ will be described in detail with reference to FIGS.
[0099]
When manufacturing the array substrate 10 ′, each large-sized original substrate (for example, 550 mm × 650 mm) is used for each liquid crystal display device for each region having a predetermined dimension (for example, a diagonal dimension of 2.2 inches). A wiring / film-forming pattern for forming is formed. Similarly, after being bonded together with the original substrate for the counter substrate created in a large format through a sealing material and a spacer, a cell structure corresponding to each liquid crystal display device is cut out.
[0100]
(1) First patterning (Figure 15)
A molybdenum-tungsten alloy film (MoW film) is deposited on the glass substrate 18 by sputtering to a thickness of 230 nm. Then, by patterning using the first photomask, 176 scanning lines 11, gate electrodes 11 a composed of extending portions, and scanning lines 11 are formed for each rectangular region having a diagonal size of 2.2 inches (56 mm). And approximately the same number of auxiliary capacitance lines 12 are formed. In the illustrated example, the auxiliary capacitance line 12 is arranged approximately in the middle of the two scanning lines 11, and for each pixel dot, avoids the vicinity of the position where the signal line 31 is arranged, and one wide portion 12a having a substantially square shape. Is forming.
[0101]
At the same time, the connection pad 14 and the pad wiring 14a extending from the connection pad 14 are formed at the peripheral portion.
[0102]
(2) Second patterning (Fig. 16)
First, a 350 nm-thick silicon oxide / silicon nitride film (SiONx film) that forms the gate insulating film 15 is deposited. After the surface is treated with hydrofluoric acid, a 50 nm thick amorphous silicon (a-Si: H) layer for forming the semiconductor film 36 of the TFT 9, and a film for forming the channel protective film 21 of the TFT 9 and the like A silicon nitride film (SiNx film) having a thickness of 200 nm is continuously formed without being exposed to the atmosphere (FIG. 13).
[0103]
After the resist layer is applied, a channel protective film 21 is formed on each gate electrode 11a by a backside exposure technique using a pattern such as the scanning line 11 obtained by the first patterning as a mask.
[0104]
(3) Third patterning (Fig. 16)
After the exposed surface of the amorphous silicon (a-Si: H) layer is treated with hydrofluoric acid so that a good ohmic contact can be obtained, a phosphorus-doped amorphous silicon (50 nm thick) for forming the low-resistance semiconductor film 37 ( n ⁺ The a-Si: H) layer is deposited by the CVD method similar to the above (FIG. 13).
[0105]
Thereafter, a three-layer metal film (Mo / Al / Mo) composed of a bottom Mo layer having a thickness of 25 nm, an Al layer having a thickness of 250 nm, and a top Mo layer having a thickness of 50 nm is deposited by sputtering.
[0106]
Then, after exposing and developing the resist using a third photomask, the a-Si: H layer, n ⁺ The a-Si: H layer and the three-layer metal film (Mo / Al / Mo) are patterned at once. By this third patterning, 220 × 3 signal lines 31, a drain electrode 32 extending from each signal line 31, a source electrode 33, and a rectangular area having a diagonal dimension of 2.2 inches (56 mm) are provided. Create
[0107]
At the same time, an auxiliary capacity extending portion 35 protruding slightly from the outer peripheral edge of the wide portion 12a is disposed so as to substantially overlap the wide portion 12a of the auxiliary capacity line 12. The auxiliary capacitor extension portion 35 is a rectangular pattern further extended from a straight line 33 a extending from the source electrode 33 along the signal line 31.
[0108]
(4) Fourth patterning
An interlayer insulating film 4 made of a silicon nitride film having a thickness of 50 nm is deposited on the multilayer film pattern obtained as described above.
[0109]
Subsequently, a positive photosensitive curable resin liquid made of an acrylic resin is uniformly applied by a coater so that the film thickness after drying becomes 2 μm. Then, after performing an exposure operation as described below, development, ultraviolet irradiation, post-baking, and cleaning operations are performed. The ultraviolet irradiation is an operation for improving the light transmittance of the thick resin film 5 by reducing unreacted portions in the thick resin film 5.
[0110]
In the exposure operation, strong exposure is performed at the positions where the upper contact holes 51 to 53 are provided and the extraction area 54 for the connection pad, and weak exposure is performed at the positions where the recess 56 is provided in the reflective pixel electrode area. (See FIGS. 12-13).
[0111]
As described in the first embodiment, it is possible to use a negative photosensitive resin, and instead of using two photomasks, a photomask having a mesh pattern in a predetermined area is used to achieve an integrated exposure amount. A step can also be provided.
[0112]
(5) Fifth patterning (FIGS. 17 to 8 and FIG. 11)
After depositing 40-nm thick a-ITO as a transparent conductive layer, resist coating, exposure and development are performed. Then, under this resist pattern 8, the following three-stage etching operation is performed. The resist pattern 8 has openings 81 at the upper contact holes 51 to 53, and the dimensions of the openings 81 are slightly smaller than the inner diameter (that is, the diameter of the bottom surface) of the corresponding contact hole.
[0113]
(5-1) Formation of ITO pattern (Figure 17)
First, the a-ITO film other than the portions covered with the resist pattern 8 is removed by processing for about 50 seconds at 45 ° C. using an aqueous oxalic acid solution as an etching solution. That is, a pattern of an a-ITO film having a shape along the resist pattern 8 is created.
[0114]
As a result, three substantially rectangular patterns 63a, 63b, and 63c forming the transmissive pixel electrode 63 are formed for each pixel dot. Further, an ITO film pattern 62 ′ having a small hole is formed so as to cover the contact hole 53 at the source electrode 33 except for its central portion.
[0115]
At the same time, an ITO film pattern 61 ′ having small holes is formed on the peripheral edge of the array substrate so as to cover the pair of upper layer contact holes 51 to 52 except for the center of each contact hole. At the same time, a pad coating ITO layer 64 ′ is formed so as to cover the connection pad 14 except for the central linear region.
[0116]
(5-2) Through-hole formation (upper part of Fig. 11)
Next, an upper layer contact that penetrates the thick resin film 5 by treating with buffered hydrofluoric acid (BHF, hydrogen fluoride-ammonium fluoride buffer) as an etchant at, for example, 28 ° C. for 120 seconds by a spray method. In the region of the bottom surface of the holes 51 to 53, only the insulating films 4 and 15 or the interlayer insulating film 4 are removed to expose the underlying metal layer. The buffered hydrofluoric acid contains, for example, 6% hydrogen fluoride and 30% ammonium fluoride. The etching time is set so that side etching does not become excessive, and the inner wall surfaces of the lower contact holes 41 to 43 to be formed have a tapered surface with an inclination of about 45 °.
[0117]
As shown in the upper part of FIG. 11, the gate insulating film 15 and the interlayer insulating film 4 are simultaneously formed within the bottom contour of the upper contact hole 51 at the end of the pad wiring 14 a extending from the connection pad 14 to the inside of the substrate. Removed. That is, a pad wiring lower layer contact hole 41 that penetrates the insulating films 15 and 4 and exposes the inner end portion of the pad wiring 14a is formed.
[0118]
Further, at the position of the end portion 31a of the signal line 31 adjacent thereto, the interlayer insulating film 4 is removed inside the upper layer contact hole 52, and the signal line end lower layer contact hole exposing the end portion 31a of the signal line. 42 is created. At the same time, in each pixel dot, a source lower layer contact hole 43 that penetrates the interlayer insulating film 4 and exposes the source electrode 33 is formed.
[0119]
As shown in the upper part of FIG. 11, considerable side etching occurs in the insulating films 15 and 4 during the wet etching for forming the through hole. Therefore, the inner diameter D1 (bottom diameter) of the opening 81 of the resist pattern 8 is slightly marginal to the dimension d of the side etching on both sides than the inner diameter D2 of the bottom of the corresponding upper contact holes 51 to 53 of the resin film. The size is set smaller by adding That is, D1 = D2-2 (d + m). In a specific example, the margin m is about 2 μm.
[0120]
The margin m is an upper layer contact that penetrates the thick resin film 5 corresponding to the upper edges of the lower layer contact holes 41 to 43 that penetrate the insulating films 15 and 4 in consideration of some variations in side etching conditions. It is set so as to be always inside the lower edge (bottom edge) of the holes 51 to 53. This is to prevent the conductive layer covering the wall surface of the contact hole from causing a so-called “step break” due to the formation of the overhang portion.
[0121]
Note that when a hydrofluoric acid-based etching solution such as buffered hydrofluoric acid is used, the side etching speed is generally much higher in the interlayer insulating film 4 made of a silicon nitride film than in the gate insulating film 15, and thus the gate insulating film 15 The wall surface of the lower contact hole 41 penetrating through can be easily formed into a forward taper shape, that is, a gentle upward slope shape.
[0122]
(5-3) Back etching of a-ITO (middle of FIG. 11 and FIG. 18)
Again, using an aqueous oxalic acid solution as an etchant, for example, by treating at 45 ° C. for 15 seconds, the “eave-like portion” 6a of a-ITO resulting from the side etching of the insulating films 15 and 4 is removed. As schematically shown in the middle part of FIG. 11, etching caused by the etching solution flowing into the back side of the resist pattern 8, that is, “back etching” is performed.
[0123]
After the back etching is completed, the resist pattern 8 is peeled off, and after cleaning, annealing for crystallizing a-ITO is performed.
[0124]
After the back etching, the inner edge of the patch-like ITO film covering the vicinity of the contact holes 51 to 53 is in the shelf area between the upper edge of the lower contact holes 41 to 43 and the lower edge of the upper contact hole. To position. Then, as a result of removing the portions of the lower layer contact holes 41 to 43 from the ITO film patterns 61 ′ to 62 ′, the ITO film patch 61 having two holes is formed at the peripheral portion, and a hole-like donut shape is formed on the source electrode 33. The ITO film patch 62 is formed. A perforated ITO film patch 64 is formed so as to surround the exposed portion of the connection pad 14.
[0125]
(6) Sixth patterning (bottom of FIGS. 18 and 11)
A laminated film (Mo / Al) composed of a molybdenum metal film with a thickness of 50 nm and an aluminum metal film with a thickness of 50 nm thereon is deposited by sputtering. Thereafter, after forming a resist pattern using a photomask, the bridge-like conductive film 71 covering the pair of adjacent lower layer contact holes 41 and 42, the pad coating portion 74, and the large size of each pixel dot are formed by wet etching patterning. A reflective pixel electrode 73 covering the portion is created.
[0126]
In each pixel dot, the reflective pixel electrode 73 has transmissive openings 73a, 73b, and 73c so as to expose portions other than the peripheral portions of the previously formed transmissive pixel electrodes 63a, 63b, and 63c. Further, the pixel electrodes 63a, 63b, and 63c are electrically connected to each other by being overlapped with the peripheral portions of the transmissive pixel electrodes 63a, 63b, and 63c.
[0127]
The reflective pixel electrode 73 also covers the portion of the TFT 9 and is directly connected to the source electrode 33 through the contact holes 43 and 53 on the source electrode 33 to be conductive. Further, the reflection pixel electrode 73 has an edge along the signal line 31 overlapped with both edges of the signal line 31 with the thick resin film 5 interposed therebetween.
[0128]
In this way, the large array substrate 10 ′ is completed.
[0129]
The production of the counter substrate 102 and the production of the display panel 100 ′ in combination therewith are the same as described in the first embodiment.
[0130]
<Comparative example 2>
Next, a manufacturing method of Comparative Example 2 will be described with reference to FIG.
[0131]
In the method of manufacturing the array substrate of Comparative Example 2, the interlayer insulating film 4 and the gate insulating film on the lower layer side were patterned using the pattern of the thick resin film 5 as a mask. In order to collectively etch the silicon nitride film and the silicon oxide film or the silicon oxynitride film, buffered hydrofluoric acid was used as in the above example.
[0132]
As a result, as shown in the upper part of FIG. 20, due to side etching, the lower edge of the upper contact hole 51 protrudes from the upper edge of the lower contact hole 41 to the inside of the contact hole, An overhang covering the edge was formed all around. Therefore, when the metal film 71 ′ covering the upper and lower contact holes 51, 41 is provided, a “step break” 71 a is generated in the metal film 71 ′.
[0133]
<Examples 3 to 4>
In the third to fourth embodiments, the contact hole 41 exposing the base portion of the pad wiring 14a is removed by a combination of dry etching and wet etching in the same method of manufacturing the array substrate as in the first or second embodiment. .
[0134]
Specifically, the second etching process (5PEP (2)) of the fifth patterning is performed by the following two-stage etching.
[0135]
(i) Removal of silicon nitride film by dry etching (upper part of FIG. 21)
First, the second gate insulating film 15b made of a silicon nitride film is removed by chemical dry etching (CDE). In the fourth embodiment corresponding to the second embodiment, the interlayer insulating film 4 is simultaneously removed (FIG. 22). While maintaining the inside of the etching chamber at a temperature of 60 ° C. and a vacuum of 45 Pa, 330 sccm of oxygen (O ₂ ) Gas and 670 sccm of carbon tetrafluoride (CF _Four ) Continued to introduce gas. Etching was performed at a power of 600 W for 45 seconds.
[0136]
(ii) Removal of silicon oxide film by wet etching (lower part of FIG. 21)
Next, the first gate insulating film 15a made of a silicon oxide film is removed by the same buffered hydrofluoric acid as in the above embodiment. At this time, for example, buffered hydrofluoric acid containing 6% hydrogen fluoride and 30% ammonium fluoride in a weight ratio is used and treated at 28 ° C. for 70 seconds by a spray method.
[0137]
The side etching during wet etching is generally larger than the side etching during dry etching. However, as shown in FIG. 21, the silicon nitride film (second gate insulating film 15b) is also subjected to side etching by wet etching. . As a result, the inner wall of the contact hole 41 is gently tapered.
[0138]
<Examples 5-6>
In the fifth to sixth embodiments, the gate insulating film 15 is a single-layer film made of only a silicon nitride film in the same method for manufacturing an array substrate as in the first or second embodiment. Then, all the steps of removing the gate insulating film 15 and forming the contact hole 41 are performed by dry etching (FIGS. 23 to 24).
[0139]
The side etching in the case of dry etching is smaller than that in the case of performing wet etching as in the above embodiment, but it has a certain size. Make sure to prevent it.
[0140]
Hereinafter, the details of the manufacturing method will be described only in points different from the first or second embodiment.
[0141]
In the second patterning step, a silicon nitride film (SiNx film) having a thickness of about 300 nm is deposited as a single-layer gate insulating film 15 ′. After the surface is treated with hydrofluoric acid, a 50 nm thick amorphous silicon (a-Si: H) layer for forming the semiconductor film 36 of the TFT 9, and a film for forming the channel protective film 21 of the TFT 9 and the like. A silicon nitride film (SiNx film) having a thickness of 200 nm is continuously formed without being exposed to the atmosphere.
[0142]
Then, the second etching in the fifth patterning is performed only by chemical dry etching (CDE).
[0143]
Specifically, while maintaining the inside of the etching chamber at a temperature of 60 ° C. and a vacuum of 45 Pa, 330 sccm of oxygen (O ₂ ) Gas and 670 sccm of carbon tetrafluoride (CF _Four ) Gas was introduced, and etching was performed at a power of 600 W for 60 seconds.
[0144]
<Examples 7 to 8>
In Examples 7 to 8, the thick resin film 5 is omitted at the position where the transparent pixel electrode 63 is arranged in the same method of manufacturing the array substrate as in Example 1 or 2. FIG. 25 is a stacked cross-sectional view of the pixel portion according to the seventh embodiment corresponding to the first embodiment. FIG. 26 is a cross-sectional view of the pixel portion in Example 8 corresponding to Example 2. The laminated structure of the peripheral part and the manufacturing process are exactly the same as in Example 1 or 2.
[0145]
By omitting the thick resin film 5 at the transparent pixel electrode 63 in this way, it is possible to avoid a loss when light passes through the resin film. That is, the utilization efficiency of the backlight light can be improved.
[0146]
<Examples 9 to 10>
In Examples 9 to 10, in the same method for manufacturing an array substrate as in Example 1 or 2, the concave portion 56 of the thick resin film 5 is omitted at the position where the reflective pixel electrode 73 is disposed. That is, the reflective pixel electrode does not have an uneven pattern but is a flat pattern.
[0147]
FIG. 27 is a cross-sectional view of the pixel portion in the ninth embodiment corresponding to the first embodiment. FIG. 28 is a cross-sectional view of the pixel portion in Example 10 corresponding to Example 2. The laminated structure of the peripheral part is exactly the same as in Example 1 or 2.
[0148]
The manufacturing process is exactly the same except that in the fourth patterning process, weak exposure for forming the recess 56 is not performed.
[0149]
<Examples 11 to 12>
In Examples 11 to 12, in the same method for manufacturing an array substrate as in Example 1 or 2, the thick resin film 5 is omitted at the position where the transparent pixel electrode 63 is disposed, and at the position where the reflective pixel electrode 73 is disposed, The concave portion 56 of the thick resin film 5 is omitted.
[0150]
FIG. 29 is a stacked cross-sectional view of the pixel portion for Example 11 corresponding to Example 1. FIG. FIG. 30 is a cross-sectional view of the pixel portion in Example 12 corresponding to Example 2. The laminated structure of the peripheral part is exactly the same as in Example 1 or 2.
[0151]
<Example 13>
Next, Example 13 will be described with reference to the cross-sectional views of FIGS. 31 to 32 and the plan view of FIG.
[0152]
The liquid crystal display device of the thirteenth embodiment is the same as the first to twelfth embodiments in that it is a normally white mode light transmission type. However, unlike the above embodiments, it is a polysilicon (p-Si) TFT type.
[0153]
FIG. 31 shows a layered structure of the pixel portion of the display panel 100 ″ according to the present embodiment. The TFT 9 for each pixel dot is composed of a polysilicon (p-Si) semiconductor layer 36 ′ and is a top gate type. That is, the gate electrode 11a is disposed above the semiconductor layer 36 ′ and the contact portions 32A and 33A surrounding the semiconductor layer 36 ′ via the gate insulating film 15.
[0154]
Further, the color filter layer is formed by the thick resin film (planarizing film) 5 on the array substrate 10 ″. Therefore, the black matrix is not provided on either the array substrate 10 ″ or the counter substrate 102. First, the color filter layer is an area that covers the entire pixel dot array portion, and is formed by dyeing using an inkjet method or the like.
[0155]
The reflective pixel electrode 73 is electrically connected to the source electrode 33 through a contact hole 43 ′ that penetrates the protective film 45 and a contact hole 53 that penetrates the thick resin film 5 as a color filter layer. Here, a donut-like ITO film 62 with a hole is formed on the source electrode 33 in exactly the same manner as in the second embodiment.
[0156]
Further, in the auxiliary capacitance line (Cs wiring) 12 formed simultaneously with the scanning line on the gate insulating film 15, an auxiliary medical pattern 35 ′ formed simultaneously with the TFT semiconductor layer 36 ′ is interposed through the gate insulating film 15. Are piled up. The auxiliary capacitance pattern 35 'is electrically connected to the source electrode 33 and the reflective pixel electrode 73 through a contact hole that penetrates the interlayer insulating film 4 and the gate insulating film.
[0157]
FIG. 32 shows a peripheral portion of the display panel 100 ″ according to the present embodiment. Just like the above embodiments, the upper layer wiring formed simultaneously with the signal line 31 and the lower layer formed simultaneously with the scanning line 11 are shown. The wiring is electrically connected by a conductive layer formed simultaneously with the pixel electrodes 73 and 63 through contact holes 51 and 52 that penetrate the thick resin film 5.
[0158]
The connection structure at the end of the signal line 31 in this embodiment is exactly the same as in the second embodiment. However, the interlayer insulating film 4 in the second embodiment is replaced with a protective film 45 in this embodiment.
[0159]
Further, the step of providing these contact holes 51 to 53, 53 ′ and 41 to 42, 43 ′, 43 ″ is the second etching (formation of a through hole; 5PEP (2)) in the above-described Examples 1-2. It is exactly the same as described.
[0160]
Other steps for producing such a p-Si TFT type array substrate 10 "can be performed, for example, according to the methods described in JP-A-2000-330484 and JP-A-2001-339070.
[0161]
As shown in FIG. 32, the structure of the connection pad 14 ″ in this embodiment is different from that in each of the above embodiments. Since the driving IC is built in the peripheral portion of the array substrate 10 ″, the connection pad 14 ″ is connected. The pad 14 ″ is a portion for connecting to the flexible wiring board from the external driving unit. Therefore, the thick resin film 5 is omitted around the connection pad 14 ″, and in the region within the connection pad 14 ″, A lower wiring layer formed simultaneously with the scanning line 11 and an upper wiring layer formed simultaneously with the signal line 31 are overlaid, and these are covered with an ITO film formed simultaneously with the transparent pixel electrode 63.
[0162]
The plan view of FIG. 33 shows each pixel dot portion on the array substrate 10 ″ of this embodiment. As shown in the figure, the reflective pixel electrode 73 made of aluminum (Al) forms a single window frame pattern. None, the transparent pixel electrode 63 made of ITO covers one opening formed by this pattern.
[0163]
<Example 14>
Finally, Example 14 will be described with reference to the cross-sectional view of FIG.
[0164]
FIG. 34 shows a laminated structure in a cross section that crosses the signal line 31 according to the example 14, with respect to the arrangement positions of the reflective pixel electrode 73 and the transparent pixel electrode 63. The thick resin film 5 is omitted at the position where the transparent pixel electrode 63 is disposed, thereby reducing light transmission loss. Further, a color filter layer is disposed on the counter substrate side, and a light shielding film 19 formed simultaneously with the scanning lines 11 is provided on the outer peripheral edge of the transmissive pixel electrode 63, that is, on the slope formed by the thick resin film 5. It has been. This is for preventing light leakage from the location and maintaining high display performance.
[0165]
Although the reflective pixel electrode 73 does not have an uneven pattern, the thick resin film 5 may be provided with irregularities so that the reflective electrode 73 has light scattering properties as in the above embodiment.
[0166]
The process of assembling the display panel 100 ″ from the array substrate 10 ″ is exactly the same as described in the first embodiment. Note that, in FIG. 31 according to the present embodiment, an alignment film 106 made of polyimide (PI), which is the uppermost layer on the liquid crystal side of the array substrate 10 ″ and the counter substrate 102, is depicted. 3 to 4 according to Example 1, FIGS. 13 to 14 according to Example 2, FIG. 25 according to Example 7, FIG. 26 according to Example 8, FIG. 27 according to Example 9, and FIG. 28, FIG. 29 related to Example 11, FIG. 30 related to Example 12, and FIG. 32 related to Example 13 are not shown.
[0167]
In this embodiment, the protective film 45 serving as the base of the thick resin film 5 is provided. However, the protective film 45 can be omitted. In this case, the structure and manufacturing process of the contact hole at the peripheral edge are exactly the same as those in the first embodiment.
[0168]
In each of the above embodiments, the holed conductive film (second conductive layer) is made of a transparent conductive material and the bridge-shaped conductive film (third conductive layer) is a metal film. It is. In this case, the first and third etchings in the fifth patterning are etchings for removing the metal film, and the conductive layer covering the bottom surface of the contact hole is made of a transparent conductive material.
[0169]
In the first to twelfth embodiments, the switching element for each pixel dot has been described as an etch stopper type TFT. However, the channel etch type is exactly the same. good.
[0170]
In the above embodiment, the first-layer wiring pattern (scanning line pattern, etc.) is described as being made of a refractory metal such as molybdenum-tungsten alloy (MoW), but aluminum (Al) and molybdenum (Mo). Or a laminated film. For example, a three-layer structure consisting of a 15 nm bottom Mo layer, an intermediate 270 nm Al layer, and a 50 nm top Mo layer, or a 270 nm Al layer and a 50 nm Mo layer covering this 2 layer. It can be a layered structure.
[0171]
In the above embodiment, the transflective liquid crystal display device has been described as an example of the display device. However, the present invention is not limited to this, and the pixel electrode is provided on the TFT or wiring pattern on the array substrate via a thick resin film. It can be applied to all display devices having a structure in which a plurality of pixel electrode films are provided on an array substrate.
[0172]
For example, the present invention can also be applied to a case where an anode and a cathode are formed on an array substrate like an organic EL display device. In this case, for example, a perforated conductive curtain can be formed with the anode, and a bridge-like conductive film can be configured with the cathode.
[0173]
【The invention's effect】
In a display device wiring board and a method for manufacturing the same, by reducing the number of patterning steps, it is possible to improve manufacturing efficiency and reduce manufacturing cost and process burden.
[Brief description of the drawings]
FIG. 1 is a schematic process diagram by partial lamination sectional views for explaining a main part of a manufacturing method of Example 1. FIG.
FIG. 2 is a schematic plan view of the array substrate of Example 1. FIG.
3 is a schematic cross-sectional view of a pixel portion of a display panel including an array substrate of Example 1. FIG.
4 is a schematic cross-sectional view of a peripheral portion of a display panel including an array substrate of Example 1. FIG.
5 is a substantial part plan view schematically showing the state after the first patterning in the method of manufacturing an array substrate in Example 1. FIG.
6 is a substantial part plan view schematically showing a state after the third patterning in the array substrate manufacturing method of Example 1. FIG.
7 is a plan view of a principal part schematically showing a state after the first etching of the fifth patterning in the method of manufacturing the array substrate of Example 1. FIG.
8 is a substantial part plan view schematically showing a state after completion of the fifth patterning in the array substrate manufacturing method of Example 1. FIG.
9 is a plan view of a principal part schematically showing a state after sixth patterning in the method for producing an array substrate of Example 1. FIG.
10 is a schematic process diagram corresponding to FIG. 1, for explaining a method of manufacturing the array substrate of Comparative Example 1. FIG.
FIG. 11 is a schematic process diagram with partial lamination cross-sectional views for explaining the main part of the manufacturing method of Example 2.
12 is a schematic plan view of an array substrate of Example 2. FIG.
13 is a schematic cross-sectional view of a pixel portion of a display panel including an array substrate of Example 2. FIG.
14 is a schematic cross-sectional view of a peripheral portion of a display panel including an array substrate of Example 2. FIG.
15 is a plan view of a principal part schematically showing a state after the first patterning in the method of manufacturing the array substrate of Example 2. FIG.
16 is a plan view of a principal part schematically showing the state after the third patterning in the method of manufacturing the array substrate of Example 2. FIG.
17 is a substantial part plan view schematically showing a state after the first etching of the fifth patterning in the array substrate manufacturing method of Example 2. FIG.
18 is a substantial part plan view schematically showing a state after completion of the fifth patterning in the method for manufacturing an array substrate in Example 2. FIG.
FIG. 19 is a plan view of the principal part schematically showing the state after the sixth patterning in the method of manufacturing the array substrate in Example 2;
20 is a schematic process diagram corresponding to FIG. 11 for describing the method for manufacturing the array substrate of Comparative Example 2. FIG.
FIG. 21 is a schematic process diagram for explaining the main part of the method for manufacturing the array substrate of Example 3;
22 is a schematic process diagram for explaining the main part of the method for manufacturing the array substrate of Example 4. FIG.
23 is a schematic process diagram for explaining the main part of the method for manufacturing the array substrate of Example 5. FIG.
24 is a schematic process diagram for explaining the main part of the method for manufacturing the array substrate of Example 6. FIG.
25 is a schematic cross-sectional view of a pixel portion corresponding to FIG. 3 for a display panel including an array substrate of Example 7. FIG.
26 is a schematic cross-sectional view of a pixel portion corresponding to FIG. 13 for a display panel including an array substrate of Example 8. FIG.
27 is a schematic cross-sectional view of a pixel portion corresponding to FIG. 3 for a display panel including an array substrate of Example 9. FIG.
28 is a schematic cross-sectional view of a pixel portion corresponding to FIG. 13 for a display panel including an array substrate of Example 10. FIG.
29 is a schematic cross-sectional view of a pixel portion corresponding to FIG. 3 for a display panel including an array substrate of Example 11. FIG.
30 is a schematic cross-sectional view of a pixel portion corresponding to FIG. 13 for a display panel including an array substrate of Example 12. FIG.
31 is a schematic cross-sectional view of a pixel portion of a display panel including an array substrate of Example 13. FIG.
32 is a schematic cross-sectional view of a peripheral portion of a display panel including an array substrate of Example 13. FIG.
33 is a plan view of a pixel dot portion on the array substrate of Example 13. FIG.
FIG. 34 is a cross-sectional view of the layers where transparent pixel electrodes and reflective pixel electrodes are arranged in the array substrate of Example 14;
[Explanation of symbols]
10 Display panel body
14 Connection pad
14a Pad wiring
15 Gate insulating film (oxide / silicon nitride film)
41 Lower layer contact hole penetrating the gate insulating film 15
5 Thick resin film made of photosensitive resin
51 Upper layer contact hole penetrating thick resin film 5
6a Eaves part of ITO film
61 Perforated ITO film patch
71 Bridge-like conductive film (Mo / Al)

Claims (16)

A pattern of a first conductive layer formed on the substrate;
A first insulating film disposed on the pattern of the first conductive layer and having an opening at a position corresponding to the pattern;
A second insulating film having a lower end diameter larger than the upper end diameter of the opening of the first insulating film and having a contact hole whose inner wall is covered with a second conductive layer;
A third conductive layer formed on the second conductive layer and connected to the first conductive layer through the contact hole;
The display device wiring board, wherein an upper end of the opening of the first insulating film and an opening of the second conductive layer have the same shape.   The display device wiring board according to claim 1, wherein the second insulating film is an insulating resin film having a thickness of 1 μm or more.   The display device according to claim 1, wherein the display device wiring substrate includes pixel electrodes made of the same conductive material as at least one of the second conductive layer and the third conductive layer in a matrix. Wiring board.   4. The display according to claim 3, wherein the pixel electrode includes the second conductive layer and the third conductive layer, one of which is a light-transmitting conductive film and the other is a light-reflecting conductive film. Device wiring board.   5. The display device wiring board according to claim 4, wherein the display device wiring board is used in a transflective liquid crystal display device.   The display device wiring board according to claim 4, wherein the second insulating film at a position corresponding to the pixel electrode made of the light-reflective conductive film has an uneven pattern.   5. The display device wiring board according to claim 4, wherein the second insulating film has an opening formed at a position corresponding to the pixel electrode made of the light transmissive conductive film.   The display device wiring board according to claim 1, wherein the display device wiring substrate is used in an organic EL display device.   9. The wiring board for a display device according to claim 8, wherein the second conductive layer is made of the same conductive material as the anode of the EL element and the third conductive layer is made of the cathode of the EL element. Forming a pattern of the first conductive layer on the insulating substrate;
Forming a first insulating film covering the same;
Forming a second insulating film formed on the first insulating film and having a contact hole at a position corresponding to the pattern of the first conductive layer;
Forming a second conductive layer on the second insulating film;
A first patterning step of patterning the second conductive layer using a resist pattern mask having an opening having a smaller diameter than the contact hole;
Etching the first insulating film through the opening of the second conductive layer using the resist pattern mask to form a contact hole having a diameter larger than the opening,
A second patterning step for exposing the first conductive layer;
A third patterning step of patterning the second conductive layer using the contact hole of the first insulating film as a mask;
The resist pattern mask is removed, producing the wiring board, characterized in that via the contact hole of the first and second insulating film and forming a third conductive layer connected to the first conductive layer Method. Further comprising a third insulating film between the first insulation film and said second insulating film, the third insulating film, according to claim 10, characterized in that it is etched in the first insulating film and the same process The manufacturing method of the wiring board as described. 12. The method for manufacturing a wiring board according to claim 11, wherein, in the second patterning step, the third insulating film has a higher side etching rate than the first insulating film. The first insulating film includes a lower insulating film and an upper insulating film disposed on the lower insulating film, and the upper insulating film has a higher side etching rate than the lower insulating film in the second patterning step. The method for manufacturing a wiring board according to claim 11. The method for manufacturing a wiring board according to claim 12, wherein the second patterning step is performed by wet etching. 15. The method for manufacturing a wiring board according to claim 14, wherein buffered hydrofluoric acid is used as an etchant during the wet etching. The method for manufacturing a wiring board according to claim 12, wherein the second etching is performed by dry etching.

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