JP4449258B2 - Electronic circuit device and manufacturing method thereof - Google Patents

Electronic circuit device and manufacturing method thereof Download PDF

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Publication number
JP4449258B2
JP4449258B2 JP2001182496A JP2001182496A JP4449258B2 JP 4449258 B2 JP4449258 B2 JP 4449258B2 JP 2001182496 A JP2001182496 A JP 2001182496A JP 2001182496 A JP2001182496 A JP 2001182496A JP 4449258 B2 JP4449258 B2 JP 4449258B2
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electronic
substrate
circuit device
electronic circuit
semiconductor chip
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JP2002373968A (en
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博幸 重田
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Sony Corp
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Sony Corp
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Description

【０００１】
【発明の属する技術分野】
本発明は、電子回路装置およびその製造方法に関し、特に複数の半導体チップが格納された電子回路装置およびその製造方法に関する。
【０００２】
【従来の技術】
デジタルビデオカメラ、デジタル携帯電話、あるいはノートパソコンなど、携帯用電子機器の小型化、薄型化、軽量化に対する要求は強くなる一方であり、これに応えるために近年のＶＬＳＩなどの半導体装置においては３年で７割の縮小化を実現してきた一方で、実装基板上の部品実装密度をいかに向上させるかが重要な課題として研究および開発がなされてきた。
【０００３】
そして、これに応えるため、近年、複数の半導体チップを１つのパッケージに実装したマルチチップパッケージが使用されてきている。
【０００４】
図６は、上記のマルチチップパッケージの断面図である。
図６に示すマルチチップパッケージでは、半導体チップ１１および半導体チップ１２が、ダイボンド材３により、インタポーザ５上に固定されている。
半導体チップ１１，１２は、それぞれ所定の配置でパッド８が形成されており、インタポーザ５に形成されたインナーリード６と、金線などからなるボンディングワイヤ４により、電気的に接続されている。
【０００５】
半導体チップ１１，１２が搭載されたインタポーザ５上には、半導体チップ１１，１２を保護するための封止樹脂９が形成されている。
インタポーザ５のチップ搭載面の裏面には、インナーリード６と電気的に接続された外部接続端子７が形成されている。
【０００６】
上記の半導体チップ１１，１２を格納するマルチチップパッケージは、不図示のマザーボードの端子とインタポーザ５の外部接続端子７とが電気的に接続されるように、マザーボード上に実装されて使用されることになる。
【０００７】
上記構成のマルチチップパッケージでは、２次元方向に横並びに半導体チップ１１，１２を搭載していることから、広い実装面積を必要とするため、さらなる素子の高集積化および高密度化の要求に対応することが困難となってきている。
【０００８】
従って、近年、上記のさらなる要求に対応すべく、半導体チップを積み上げて、３次元に搭載されたスタック構造のマルチチップパッケージが使用されるようになってきている。
【０００９】
図７は、スタック構造のマルチチップパッケージの断面図である。
図７に示すマルチチップパッケージでは、相対的に面積の大きい半導体チップ１１上に、相対的に面積の小さい半導体チップ１２が搭載されている構造となっている。
【００１０】
すなわち、相対的に面積の大きい半導体チップ１１がダイボンド材３により、インタポーザ５上に固定されており、半導体チップ１１のパッド８に干渉しないように、半導体チップ１２がダイボンド材３により半導体チップ１１上に固定されている。
【００１１】
半導体チップ１１，１２に形成された各パッド８と、インタポーザ５に形成されたインナーリード６とが、金線などからなるボンディングワイヤ４により、電気的に接続されている。
【００１２】
そして、インタポーザ５上に積み重ねられた半導体チップ１１，１２が封止樹脂９により封止されている。
インタポーザ５のチップ搭載面の裏面には、インナーリード６と電気的に接続された外部接続端子７が形成されている。
【００１３】
上記構成のスタック構造のマルチチップパッケージは、上述したように、マザーボード上に実装されて使用される際に、２次元のマルチチップパッケージに比して、平面方向の実装面積を縮小できることから、さらなる素子の高集積化および高密度化の要求に応えることができる。
【００１４】
【発明が解決しようとする課題】
しかしながら、例えば、スタック構造のマルチチップパッケージを採用する場合には、上述したように、半導体チップ１２は、半導体チップ１１のパッド８に干渉しないように搭載する必要があることから、半導体チップ１１に配置されたパッド８により制限を受ける。
【００１５】
図７に示すように、例えば、半導体チップ１１，１２のパッド８が、ともにチップの周囲に形成されており、半導体チップ１１に配置されたパッド８の内側に、半導体チップ１２が搭載することができる場合等、限られた条件下において上記の構造を採用することができる。
【００１６】
例えば、図８に示すように、主に、ＳＲＡＭ（Static Random Access Memory)などのメモリ系においては、パッド８がチップの中央に一方向に配置されたセンターパッド配置チップ１が使用されている。
このセンターパッド配置チップ１と、当該チップサイズ以下で、チップ周囲にパッド８が配置されたペリフェラルパッド配置チップ２とをマルチチップパッケージ化する場合には、センターパッド配置チップ１のパッド８とペリフェラルパッド配置チップ２とが干渉してしまうため、図７に示すスタック構造を採用することができず、図６に示す横並びにする構成しか採用することができないという問題がある。
【００１７】
本発明は上記の事情に鑑みてなされたものであり、その目的は、半導体チップ等の電子素子の端子配置にできるだけ制限されずに電子素子を積み重ねて、小型化を図ることができる電子回路装置およびその製造方法を提供することにある。
【００１８】
【課題を解決するための手段】
上記の目的を達成するため、本発明の電子回路装置は、所定の位置に端子が配置された複数の電子素子が基板上に積み重ねられた電子回路装置であって、前記基板上に搭載された第１の電子素子と、前記第１の電子素子の端子と重ならないように、少なくとも一部の部位が当該第１の電子素子上に搭載された第２の電子素子と、前記基板と前記第２の電子素子との間隙を埋めて、当該第２の電子素子を支持するスペーサとを有し、前記スペーサは、シリコン（Ｓｉ）または金属製である。
【００１９】
好適には、前記スペーサは、前記第１の電子素子の厚みと実質的に同等の厚みを有する。
【００２０】
例えば、前記第１および第２の電子素子は、前記端子が形成された面とは反対側の面を前記基板に向けて搭載されている。
この場合、前記基板は、前記第１および第２の電子素子の端子と電気的に接続するための基板端子を有し、前記第１および第２の電子素子の端子と前記基板端子とがワイヤにより結線されている。
【００２１】
好適には、前記第１の電子素子の少なくとも外縁部に、前記ワイヤの前記第１の電子素子への接触を防止するための絶縁性樹脂が形成されている。
【００２２】
例えば、前記第１の電子素子は、端子形成面の中央部において一方向に配列された端子を有する。
【００２３】
例えば、前記基板は、前記基板端子と電気的に接続された外部接続用端子を有する。
【００２４】
上記の本発明の電子回路装置では、基板上に第１の電子素子が搭載され、当該第１の電子素子の端子と重ならないように、第１の電子素子上において、第２の電子素子の一部の部位が搭載されている。
そして、基板と第２の電子素子との間隙を埋めて、当該第２の電子素子を支持するスペーサが形成されていることから、第２の電子素子は、第１の電子素子およびスペーサにより支持されて積み重ねられることとなる。
従って、第１の電子素子の端子配置により、第１の電子素子の端子を除く領域が、第２の電子素子を搭載するほどの領域を有さない場合であっても、スペーサが設けられていることで、第１の電子素子およびスペーサ上に第２の電子素子を搭載することができ、基板上に横並びに電子素子を搭載するのに比して、実装面積が削減される。
【００２５】
さらに、上記の目的を達成するため、本発明の電子回路装置の製造方法は、所定の位置に端子が配置された複数の電子素子が基板上に積み重ねられた電子回路装置の製造方法であって、前記基板上に第１の電子素子を搭載する工程と、前記基板上にシリコンまたは金属製のスペーサを搭載する工程と、前記第１の電子素子および前記スペーサ上に、前記第１の電子素子の前記端子と重ならないように、第２の電子素子を搭載する工程とを有する。
【００２６】
好適には、前記スペーサを搭載する工程において、前記第１の電子素子の厚みと実質的に同等な厚みを有するスペーサを搭載する。
【００２７】
例えば、前記第１および第２の電子素子を搭載する工程において、前記端子が形成された面とは反対側の面を前記基板に向けて前記第１および第２の電子素子を搭載する。
そして、前記基板は、前記第１および第２の電子素子の端子と電気的に接続するための基板端子を有し、前記第２の電子素子を搭載する工程の後に、前記第１および第２の電子素子の端子と前記基板端子とをワイヤにより結線する工程を有する。
【００２８】
好適には、前記ワイヤにより結線する工程の前に、前記第１の電子素子の少なくとも外縁部に、前記ワイヤの前記第１の電子素子への接触を防止するための絶縁性樹脂を形成する工程を有する。
【００２９】
上記の本発明の電子回路装置の製造方法によれば、基板上に第１の電子素子を搭載し、基板上にスペーサを搭載し、第１の電子素子およびスペーサ上に、第１の電子素子の端子に重ならないように、第２の電子素子を搭載することで、第１の電子素子の端子配置に影響されずに、電子素子を積み重ねることができる。
【００３０】
【発明の実施の形態】
以下に、本発明の実施の形態について、一例として、ＢＧＡ（Ball Grid Array)型のマルチチップパッケージからなる電子回路装置を例に図面を参照して説明する。
【００３１】
図１は、本実施形態に係る電子回路装置の断面図である。
図２は、図１に示す電子回路装置における半導体チップの積み重ねの様子を示す平面図である。
【００３２】
本実施形態に係る電子回路装置では、図２に示すように、チップの中央部に一方向に複数のパッド８が配置されたセンターパッド配置チップからなる第１の半導体チップ１上に、チップの周囲に沿って複数のパッド８が配置されたペリフェラルパッド配置チップからなる第２の半導体チップ２を積み重ねて、ＢＧＡ（Ball Grid Array)型のマルチチップパッケージからなる電子回路装置が構成されている。
上記の第１の半導体チップ１に示すパッド８の配置は、主に、ＳＲＡＭ（Static Random Access Memory)などのメモリ系に使用されている。
【００３３】
第１の半導体チップ１は、例えば、フィルムあるいはペースト状の接着材であるダイボンド材３により、例えば、０．４〜０．６ｍｍ程度の厚みのガラスエポキシ基板等からなるインタポーザ５上に固定されている。
ダイボンド材３は、例えば、ペースト状のものを使用する場合には、銀ペーストを使用することができ、２０μｍ程度の厚みを有する。
【００３４】
第１の半導体チップ１に隣接して、ダイボンド材３により、第１の半導体チップ１と同等の厚みを有するスペーサ１０が固定されている。
スペーサ１０は、例えば、半導体チップ１，２との熱膨張率の差が小さくなるように、例えば、半導体チップを構成する材料であるシリコン（Ｓｉ）により構成される。
あるいは、半導体チップ１，２から発せられる熱を効率的に放散させるために、熱伝導率の高い銅（Ｃｕ）等の金属を使用してもよい。
【００３５】
第１の半導体チップ１およびスペーサ１０上には、第１の半導体チップ１に配置されたパッド８に接触しないように、ダイボンド材３により、第２の半導体チップ２が固定されている。
上記の第１の半導体チップ１および第２の半導体チップ２は、例えば、１５０μｍ〜３００μｍの厚みを有している。
【００３６】
インタポーザ５のチップ搭載面には、銅（Ｃｕ）、ニッケル（Ｎｉ）、あるいは金（Ａｕ）等からなるインナーリード６が形成されており、半導体チップ１，２に配置された各パッド８とインタポーザ５のインナリード６とが、例えば、金線などからなるボンディングワイヤ４により接続されている。
ボンディングワイヤ４は、チップの周辺部に触れないように、チップ側で盛り上がったループ形状に形成されている。
また、ボンディングワイヤ４は、各ボンディングワイヤが重ならないように、図４の断面に直交する方向において、交互に形成されている。
【００３７】
ここで、下側の第１の半導体チップ１のエッジには、ボンディングワイヤ４と第１の半導体チップ１とが接触して短絡するのを防止するため、例えば、絶縁性の液状樹脂からなるエッジコート材１３が塗布されている。
これは、図１に示すように、半導体チップ１，２のパッド８とインナーリード等の距離が長い場合や、チップの中央部にパッド８が配置されている場合等には、後に説明する封止樹脂を封入する際に、ボンディングワイヤ４が樹脂の重みでチップのエッジに接触する恐れがあるため、これを防止するためである。
【００３８】
インタポーザ５上には、第１の半導体チップ１および第２の半導体チップ２を被覆して、当該半導体チップ１，２を保護するための封止樹脂９が形成されている。
インタポーザ５のチップ搭載面の裏面には、インナーリード６と電気的に接続された例えば半田等からなる球状の外部接続端子７が形成されている。
【００３９】
上記の第１の半導体チップ１と第２の半導体チップ２を格納する電子回路装置は、不図示のマザーボードの端子とインタポーザ５の外部接続端子とが電気的に接続されるように、マザーボード上に実装されて使用されることになる。
【００４０】
上記の本実施形態に係る電子回路装置では、第１の半導体チップ１上に、当該第１の半導体チップ１のパッド８に干渉しないように、第２の半導体チップ２が積み重ねられており、第１の半導体チップ１に支持されていない第２の半導体チップ２の下側には、第２の半導体チップ２を支持するスペーサ１０が配置されて、安定した３次元実装を可能にしている。
従って、第１の半導体チップ１のパッド８とインタポーザ５のインナーリード６との、ボンディングワイヤ４による接続を妨げることなく、チップを積み重ねることができ、電子回路装置の小型化を実現することができる。
さらに、スペーサ１０が第１の半導体チップ１の厚みと同等の厚みを有することにより、第２の半導体チップ２を平行に搭載することができ、安定した搭載を実現することができる。
【００４１】
次に、上記の本実施形態の電子回路装置の製造方法について、図３〜図５を用いて説明する。
【００４２】
まず、図３（ａ）に示すように、インナーリード６が形成されたインタポーザ５上において、第１の半導体チップ１およびスペーサ１０を搭載する箇所に、ダイボンド材３を塗布する。
続いて、マウンタにより、第１の半導体チップ１をダイボンド材３を介して、インタポーザ５上に搭載する。
【００４３】
次に、図３（ｂ）に示すように、第１の半導体チップ１と同等の厚みを有するスペーサ１０を用意して、マウンタにより当該スペーサ１０をダイボンド材３を介してインタポーザ５上に搭載する。
【００４４】
次に、図３（ｃ）に示すように、第１の半導体チップ１に配置されたパッド８に干渉しないように、第１の半導体チップ１およびスペーサ１０上に、ダイボンド材３を塗布する。
続いて、マウンタにより、第２の半導体チップ２をダイボンド材３を介して、第１の半導体チップ１およびスペーサ１０上に搭載する。
【００４５】
次に、図４（ｄ）に示すように、第１の半導体チップ１のエッジに、例えば、絶縁性の液状樹脂からなるエッジコート材１３を塗布する。このエッジコート材１３は、半導体チップ１のエッジの全てに塗布する必要はなく、比較的長いボンディングワイヤが半導体チップ１のエッジをまたぐこととなる部位に塗布すればよい。
【００４６】
次に、図４（ｅ）に示すように、第１の半導体チップ１および第２の半導体チップ２のパッド８と、インタポーザ５のインナ−リード６とを、例えば、金線などからなるボンディングワイヤ４により接続する。
【００４７】
次に、図５（ｆ）に示すように、上記の第１および第２の半導体チップ１，２が搭載されたインタポーザ５を金型成形機にセットして、樹脂を流しこんで成形硬化させて、第１および第２の半導体チップ１，２を保護する封止樹脂９を形成する。
【００４８】
最後に、図５（ｇ）に示すように、インタポーザ５のチップ搭載面の裏面において、インナーリード６に接続するように配置された不図示のランド上に、球状の半田等からなる外部接続端子７を形成することにより、本実施形態に係る電子回路装置が製造される。
【００４９】
上記のようにして形成された電子回路装置は、不図示のマザーボードに形成された電極と、外部接続端子７とをリフローはんだ付けなどにより、接続させることにより、マザーボード上に実装されることとなる。
【００５０】
上記の本実施形態に係る電子回路装置の製造方法によれば、スペーサ１０を形成する工程を追加するのみで、第１の半導体チップ１のパッド配置に影響されることなく、第２の半導体チップ２を搭載することができ、小型化されたスタック型の電子回路装置を製造することができる。
【００５１】
本発明は、上記の実施形態の説明に限定されない。
例えば、本実施形態では、第１の半導体チップとして、チップの中央部に一方向に複数配置されたパッドを有するセンターパッド配置チップを一例に説明したが、これに限られるものでなく、特に、パッドの配置には限定はない。
同様に、第２の半導体チップとして、チップの周辺部に沿ってパッドが複数配置されたペリフェラルパッド配置チップを例に説明したが、特に限定されるものでなく、センターパッド配置チップの他、様々なパッド配置を有するチップを使用することができる。
【００５２】
また、スペーサ１０は、第１の半導体チップ１と同じ厚さで、その上に搭載される第２の半導体チップ２を平行に保つことができ、かつ、半導体チップ１，２のパッド８とインナーリード６とのボンディングワイヤ４による接続に問題がなければ、どのような形状でもよく、またどのような材質であってもよい。
例えば、スペーサ１０は、第２の半導体チップ２とインタポーザ５との間隙を全て埋める必要はなく、第２の半導体チップ２を平行に搭載できる限りにおいて、間隙の一部を埋めるように形成してもよい。
【００５３】
また、ダイボンド材３は、信頼性の向上等のため、第１の半導体チップ１の搭載用と、第２の半導体チップ２の搭載用とで材料を変えてもよい。
例えば、第２の半導体チップ２の搭載用に、フィルム状のダイボンド材を使用することで、ダイボンド材が流れて第１の半導体チップ１のパッド８を覆ってしまうのを防止することができる。
また、例えば、第１の半導体チップ１の搭載用に、フィルム状のダイボンド材を使用することで、搭載後の第１の半導体チップ１が傾くのを防止でき、その後にマウンタにより、第２の半導体チップ２を第１の半導体チップ１上に搭載する際に、位置決めを容易にすることができる。
【００５４】
また、本実施形態では、ＢＧＡ型のパッケージからなる電子回路装置について説明したが、これに限られるものでなく、例えば、半田等からなる球状の外部接続端子７は存在せず、チップ搭載面の裏面にはパッドしか形成されていないＬＧＡ（Land Grid array)型に適用することも可能である。
また、本実施形態における電子回路装置の外形サイズを限りなく半導体チップのサイズに近づけたＣＳＰ（Chip Size Package)形態の電子回路装置に適用することもできる。
その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。
【００５５】
【発明の効果】
本発明によれば、半導体チップ等の電子素子の端子配置にできるだけ制限されずに電子素子を積み重ねて、小型化された電子回路装置を実現することができる。
【図面の簡単な説明】
【図１】本実施形態に係る電子回路装置の断面図である。
【図２】図１に示す電子回路装置における半導体チップの積み重ねの様子を示す平面図である。
【図３】本実施形態に係る電子回路装置の製造工程において、（ａ）は第１の半導体チップの搭載工程までを示す断面図、（ｂ）はスペーサの搭載工程までを示す断面図、（ｃ）は第２の半導体チップの搭載工程までを示す断面図である。
【図４】本実施形態に係る電子回路装置の製造工程において、（ｄ）はエッジコート材の塗布工程までを示す断面図、（ｅ）はボンディングワイヤによる接続工程までを示す断面図である。
【図５】本実施形態に係る電子回路装置の製造工程において、（ｆ）は封止樹脂の形成工程までを示す断面図、（ｇ）は外部接続端子の形成工程までを示す断面図である。
【図６】図６は、従来例に係る２次元マルチチップパッケージの断面図である。
【図７】図７は、従来例に係る３次元マルチチップパッケージの断面図である。
【図８】図８は、従来例に係るマルチチップパッケージの問題点を説明するための図である。
【符号の説明】
１…第１の半導体チップ、２…第１の半導体チップ、３…ダイボンド材、４…ボンディングワイヤ、５…インターポーザ、６…インナーリード、７…外部接続端子、８…パッド、９…封止樹脂、１０…スペーサ、１１…半導体チップ、１２…半導体チップ、１３…エッジコート材。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic circuit device and a manufacturing method thereof, and more particularly to an electronic circuit device storing a plurality of semiconductor chips and a manufacturing method thereof.
[0002]
[Prior art]
The demand for downsizing, thinning, and weight reduction of portable electronic devices such as digital video cameras, digital mobile phones, and notebook personal computers is increasing. While 70% reduction has been achieved year by year, research and development have been conducted as an important issue on how to improve the component mounting density on the mounting board.
[0003]
In response to this, in recent years, a multi-chip package in which a plurality of semiconductor chips are mounted in one package has been used.
[0004]
FIG. 6 is a cross-sectional view of the multichip package.
In the multichip package shown in FIG. 6, the semiconductor chip 11 and the semiconductor chip 12 are fixed on the interposer 5 by the die bond material 3.
The semiconductor chips 11 and 12 each have a pad 8 formed in a predetermined arrangement, and are electrically connected by an inner lead 6 formed on the interposer 5 and a bonding wire 4 made of a gold wire or the like.
[0005]
A sealing resin 9 for protecting the semiconductor chips 11 and 12 is formed on the interposer 5 on which the semiconductor chips 11 and 12 are mounted.
On the back surface of the chip mounting surface of the interposer 5, external connection terminals 7 electrically connected to the inner leads 6 are formed.
[0006]
The multi-chip package for storing the semiconductor chips 11 and 12 is used by being mounted on the motherboard so that the terminal of the motherboard (not shown) and the external connection terminal 7 of the interposer 5 are electrically connected. become.
[0007]
In the multichip package having the above configuration, since the semiconductor chips 11 and 12 are mounted side by side in the two-dimensional direction, a large mounting area is required. It has become difficult to do.
[0008]
Therefore, in recent years, in order to meet the above-described further demand, a multi-chip package having a stack structure in which semiconductor chips are stacked and mounted three-dimensionally has been used.
[0009]
FIG. 7 is a cross-sectional view of a multi-chip package having a stack structure.
The multichip package shown in FIG. 7 has a structure in which a semiconductor chip 12 having a relatively small area is mounted on a semiconductor chip 11 having a relatively large area.
[0010]
That is, the semiconductor chip 11 having a relatively large area is fixed on the interposer 5 by the die bonding material 3, and the semiconductor chip 12 is formed on the semiconductor chip 11 by the die bonding material 3 so as not to interfere with the pads 8 of the semiconductor chip 11. It is fixed to.
[0011]
Each pad 8 formed on the semiconductor chips 11 and 12 and the inner lead 6 formed on the interposer 5 are electrically connected by a bonding wire 4 made of a gold wire or the like.
[0012]
The semiconductor chips 11 and 12 stacked on the interposer 5 are sealed with a sealing resin 9.
On the back surface of the chip mounting surface of the interposer 5, external connection terminals 7 electrically connected to the inner leads 6 are formed.
[0013]
As described above, when the multi-chip package having the stack structure is mounted on a mother board and used, the mounting area in the planar direction can be reduced as compared with a two-dimensional multi-chip package. It is possible to meet the demand for higher integration and higher density of elements.
[0014]
[Problems to be solved by the invention]
However, for example, when a multi-chip package having a stack structure is adopted, the semiconductor chip 12 needs to be mounted so as not to interfere with the pads 8 of the semiconductor chip 11 as described above. Limited by the placed pad 8.
[0015]
As shown in FIG. 7, for example, the pads 8 of the semiconductor chips 11 and 12 are both formed around the chip, and the semiconductor chip 12 is mounted inside the pads 8 arranged on the semiconductor chip 11. The above structure can be employed under limited conditions, such as when possible.
[0016]
For example, as shown in FIG. 8, in a memory system such as an SRAM (Static Random Access Memory), a center pad arrangement chip 1 in which a pad 8 is arranged in one direction at the center of the chip is used.
When the center pad placement chip 1 and the peripheral pad placement chip 2 having the chip size or less and the pads 8 placed around the chip are packaged in a multichip package, the pads 8 and the peripheral pads of the center pad placement chip 1 are used. Since the arrangement chip 2 interferes, the stack structure shown in FIG. 7 cannot be adopted, and there is a problem that only the side-by-side configuration shown in FIG. 6 can be adopted.
[0017]
The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the size by stacking electronic elements without being limited to the terminal arrangement of electronic elements such as semiconductor chips as much as possible. And providing a manufacturing method thereof.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, an electronic circuit device of the present invention is an electronic circuit device in which a plurality of electronic elements having terminals arranged at predetermined positions are stacked on a substrate, and mounted on the substrate. A second electronic element mounted on the first electronic element so that the first electronic element does not overlap with a terminal of the first electronic element; the substrate; to fill the gap between the second electronic device, to have a spacer that supports the second electronic element, wherein the spacer is a silicon (Si) or metal.
[0019]
Preferably, the spacer has a thickness substantially equal to the thickness of the first electronic element.
[0020]
For example, the first and second electronic elements are mounted with the surface opposite to the surface on which the terminals are formed facing the substrate.
In this case, the substrate has substrate terminals for electrical connection with the terminals of the first and second electronic elements, and the terminals of the first and second electronic elements and the substrate terminals are wired. It is connected by.
[0021]
Preferably, an insulating resin for preventing the wire from coming into contact with the first electronic element is formed on at least an outer edge portion of the first electronic element.
[0022]
For example, the first electronic element has terminals arranged in one direction at the center of the terminal formation surface.
[0023]
For example, the substrate has an external connection terminal electrically connected to the substrate terminal.
[0024]
In the above electronic circuit device of the present invention, the first electronic element is mounted on the substrate, and the second electronic element is placed on the first electronic element so as not to overlap the terminal of the first electronic element. Some parts are mounted.
And since the spacer which fills the gap between the substrate and the second electronic element and supports the second electronic element is formed, the second electronic element is supported by the first electronic element and the spacer. Will be stacked.
Therefore, even if the region excluding the terminal of the first electronic element does not have a region for mounting the second electronic element due to the terminal arrangement of the first electronic element, the spacer is provided. Therefore, the second electronic element can be mounted on the first electronic element and the spacer, and the mounting area is reduced as compared with mounting the electronic element side by side on the substrate.
[0025]
Furthermore, in order to achieve the above object, a method for manufacturing an electronic circuit device according to the present invention is a method for manufacturing an electronic circuit device in which a plurality of electronic elements having terminals arranged at predetermined positions are stacked on a substrate. Mounting the first electronic element on the substrate; mounting a silicon or metal spacer on the substrate; and the first electronic element on the first electronic element and the spacer. Mounting a second electronic element so as not to overlap the terminal.
[0026]
Preferably, in the step of mounting the spacer, a spacer having a thickness substantially equal to the thickness of the first electronic element is mounted.
[0027]
For example, in the step of mounting the first and second electronic elements, the first and second electronic elements are mounted with the surface opposite to the surface on which the terminals are formed facing the substrate.
The substrate has substrate terminals for electrical connection with the terminals of the first and second electronic elements, and after the step of mounting the second electronic elements, the first and second A step of connecting the terminal of the electronic device and the substrate terminal with a wire.
[0028]
Preferably, before the step of connecting with the wire, an insulating resin for preventing the wire from contacting the first electronic device is formed at least on the outer edge portion of the first electronic device. Have
[0029]
According to the manufacturing method of the electronic circuit device of the present invention, the first electronic element is mounted on the substrate, the spacer is mounted on the substrate, and the first electronic element and the spacer are mounted on the first electronic element. By mounting the second electronic element so as not to overlap the terminal, the electronic elements can be stacked without being affected by the terminal arrangement of the first electronic element.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
In the following, an embodiment of the present invention will be described with reference to the drawings, taking as an example an electronic circuit device composed of a BGA (Ball Grid Array) type multi-chip package.
[0031]
FIG. 1 is a cross-sectional view of the electronic circuit device according to the present embodiment.
FIG. 2 is a plan view showing how the semiconductor chips are stacked in the electronic circuit device shown in FIG.
[0032]
In the electronic circuit device according to the present embodiment, as shown in FIG. 2, the chip is formed on the first semiconductor chip 1 including a center pad arrangement chip in which a plurality of pads 8 are arranged in one direction at the center of the chip. An electronic circuit device composed of a BGA (Ball Grid Array) type multi-chip package is configured by stacking the second semiconductor chips 2 composed of peripheral pad-arranged chips in which a plurality of pads 8 are disposed along the periphery.
The arrangement of the pads 8 shown in the first semiconductor chip 1 is mainly used for a memory system such as an SRAM (Static Random Access Memory).
[0033]
The first semiconductor chip 1 is fixed on an interposer 5 made of, for example, a glass epoxy substrate having a thickness of about 0.4 to 0.6 mm, for example, by a die bond material 3 which is a film or paste-like adhesive. Yes.
For example, when a paste-like material is used as the die bond material 3, a silver paste can be used and has a thickness of about 20 μm.
[0034]
A spacer 10 having a thickness equivalent to that of the first semiconductor chip 1 is fixed by a die bonding material 3 adjacent to the first semiconductor chip 1.
The spacer 10 is made of, for example, silicon (Si), which is a material constituting the semiconductor chip, so that the difference in coefficient of thermal expansion from the semiconductor chips 1 and 2 becomes small.
Alternatively, a metal such as copper (Cu) having a high thermal conductivity may be used in order to efficiently dissipate heat generated from the semiconductor chips 1 and 2.
[0035]
On the first semiconductor chip 1 and the spacer 10, the second semiconductor chip 2 is fixed by a die bond material 3 so as not to contact the pads 8 arranged on the first semiconductor chip 1.
The first semiconductor chip 1 and the second semiconductor chip 2 have a thickness of 150 μm to 300 μm, for example.
[0036]
Inner leads 6 made of copper (Cu), nickel (Ni), gold (Au), or the like are formed on the chip mounting surface of the interposer 5, and each pad 8 arranged on the semiconductor chips 1 and 2 and the interposer. The inner lead 6 of 5 is connected by the bonding wire 4 which consists of gold wires etc., for example.
The bonding wire 4 is formed in a loop shape raised on the chip side so as not to touch the peripheral portion of the chip.
Further, the bonding wires 4 are alternately formed in a direction orthogonal to the cross section of FIG. 4 so that the bonding wires do not overlap each other.
[0037]
Here, in order to prevent the bonding wire 4 and the first semiconductor chip 1 from coming into contact with the edge of the lower first semiconductor chip 1, for example, an edge made of an insulating liquid resin A coating material 13 is applied.
As shown in FIG. 1, this is the case when the distance between the pads 8 of the semiconductor chips 1 and 2 and the inner leads is long, or when the pads 8 are arranged at the center of the chip. This is to prevent the bonding wire 4 from coming into contact with the edge of the chip with the weight of the resin when sealing resin is sealed.
[0038]
On the interposer 5, a sealing resin 9 for covering the first semiconductor chip 1 and the second semiconductor chip 2 and protecting the semiconductor chips 1 and 2 is formed.
On the back surface of the chip mounting surface of the interposer 5, spherical external connection terminals 7 made of, for example, solder or the like electrically connected to the inner leads 6 are formed.
[0039]
The electronic circuit device storing the first semiconductor chip 1 and the second semiconductor chip 2 is arranged on the mother board so that the mother board terminal (not shown) and the external connection terminal of the interposer 5 are electrically connected. Will be implemented and used.
[0040]
In the electronic circuit device according to the present embodiment, the second semiconductor chip 2 is stacked on the first semiconductor chip 1 so as not to interfere with the pads 8 of the first semiconductor chip 1. A spacer 10 that supports the second semiconductor chip 2 is disposed below the second semiconductor chip 2 that is not supported by one semiconductor chip 1 to enable stable three-dimensional mounting.
Therefore, the chips can be stacked without hindering the connection by the bonding wires 4 between the pads 8 of the first semiconductor chip 1 and the inner leads 6 of the interposer 5, and the electronic circuit device can be miniaturized. .
Furthermore, since the spacer 10 has a thickness equivalent to the thickness of the first semiconductor chip 1, the second semiconductor chip 2 can be mounted in parallel, and stable mounting can be realized.
[0041]
Next, a method for manufacturing the electronic circuit device according to the present embodiment will be described with reference to FIGS.
[0042]
First, as shown in FIG. 3A, a die bond material 3 is applied to a place where the first semiconductor chip 1 and the spacer 10 are mounted on the interposer 5 on which the inner leads 6 are formed.
Subsequently, the first semiconductor chip 1 is mounted on the interposer 5 through the die bond material 3 by a mounter.
[0043]
Next, as shown in FIG. 3B, a spacer 10 having a thickness equivalent to that of the first semiconductor chip 1 is prepared, and the spacer 10 is mounted on the interposer 5 via the die bond material 3 by a mounter. .
[0044]
Next, as shown in FIG. 3C, a die bond material 3 is applied on the first semiconductor chip 1 and the spacer 10 so as not to interfere with the pads 8 arranged on the first semiconductor chip 1.
Subsequently, the second semiconductor chip 2 is mounted on the first semiconductor chip 1 and the spacer 10 via the die bond material 3 by a mounter.
[0045]
Next, as shown in FIG. 4D, an edge coat material 13 made of, for example, an insulating liquid resin is applied to the edge of the first semiconductor chip 1. The edge coating material 13 does not need to be applied to all the edges of the semiconductor chip 1, and may be applied to a portion where a relatively long bonding wire crosses the edge of the semiconductor chip 1.
[0046]
Next, as shown in FIG. 4E, the pads 8 of the first semiconductor chip 1 and the second semiconductor chip 2 and the inner leads 6 of the interposer 5 are bonded to, for example, a gold wire or the like. 4 to connect.
[0047]
Next, as shown in FIG. 5 (f), the interposer 5 on which the first and second semiconductor chips 1 and 2 are mounted is set in a mold molding machine, and the resin is poured into the mold and cured. Thus, a sealing resin 9 that protects the first and second semiconductor chips 1 and 2 is formed.
[0048]
Finally, as shown in FIG. 5G, on the back surface of the chip mounting surface of the interposer 5, an external connection terminal made of spherical solder or the like on a land (not shown) arranged to be connected to the inner lead 6. By forming 7, the electronic circuit device according to this embodiment is manufactured.
[0049]
The electronic circuit device formed as described above is mounted on the mother board by connecting electrodes formed on the mother board (not shown) and the external connection terminals 7 by reflow soldering or the like. .
[0050]
According to the manufacturing method of the electronic circuit device according to the above-described embodiment, the second semiconductor chip is not affected by the pad arrangement of the first semiconductor chip 1 only by adding the step of forming the spacer 10. 2 can be mounted, and a miniaturized stack type electronic circuit device can be manufactured.
[0051]
The present invention is not limited to the description of the above embodiment.
For example, in the present embodiment, as the first semiconductor chip, the center pad arrangement chip having a plurality of pads arranged in one direction at the center of the chip has been described as an example, but the present invention is not limited to this, and in particular, There is no limitation on the arrangement of the pads.
Similarly, as the second semiconductor chip, the peripheral pad arrangement chip in which a plurality of pads are arranged along the peripheral portion of the chip has been described as an example. However, the second semiconductor chip is not particularly limited. A chip having a suitable pad arrangement can be used.
[0052]
The spacer 10 has the same thickness as that of the first semiconductor chip 1 and can keep the second semiconductor chip 2 mounted thereon parallel to each other. As long as there is no problem in connection with the lead 6 by the bonding wire 4, any shape and any material may be used.
For example, the spacer 10 does not need to fill all the gaps between the second semiconductor chip 2 and the interposer 5, and is formed so as to fill a part of the gaps as long as the second semiconductor chips 2 can be mounted in parallel. Also good.
[0053]
Further, the material of the die bond material 3 may be changed for mounting the first semiconductor chip 1 and for mounting the second semiconductor chip 2 in order to improve reliability.
For example, by using a film-like die bond material for mounting the second semiconductor chip 2, it is possible to prevent the die bond material from flowing and covering the pads 8 of the first semiconductor chip 1.
Further, for example, by using a film-like die bond material for mounting the first semiconductor chip 1, it is possible to prevent the first semiconductor chip 1 after mounting from being tilted, and thereafter, the second semiconductor chip 1 is mounted by the mounter. When mounting the semiconductor chip 2 on the first semiconductor chip 1, positioning can be facilitated.
[0054]
In the present embodiment, the electronic circuit device including the BGA type package has been described. However, the present invention is not limited to this. For example, the spherical external connection terminal 7 made of solder or the like does not exist, and the chip mounting surface is not provided. The present invention can also be applied to an LGA (Land Grid array) type in which only a pad is formed on the back surface.
Also, the present invention can be applied to an electronic circuit device in a CSP (Chip Size Package) form in which the outer size of the electronic circuit device in this embodiment is as close as possible to the size of the semiconductor chip.
In addition, various modifications can be made without departing from the scope of the present invention.
[0055]
【The invention's effect】
According to the present invention, it is possible to realize a miniaturized electronic circuit device by stacking electronic elements without being limited to the terminal arrangement of the electronic elements such as a semiconductor chip as much as possible.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of an electronic circuit device according to an embodiment.
2 is a plan view showing a state in which semiconductor chips are stacked in the electronic circuit device shown in FIG. 1; FIG.
3A is a cross-sectional view illustrating a process up to a first semiconductor chip mounting process, and FIG. 3B is a cross-sectional view illustrating a process up to a spacer mounting process in the manufacturing process of the electronic circuit device according to the embodiment; (c) is sectional drawing which shows to the mounting process of the 2nd semiconductor chip.
FIG. 4D is a cross-sectional view showing the process up to the edge coating material application process and FIG. 4E is a cross-sectional view showing the connection process using a bonding wire in the manufacturing process of the electronic circuit device according to the present embodiment;
FIGS. 5A and 5B are cross-sectional views up to a sealing resin forming step, and FIG. 5G is a cross-sectional view up to an external connection terminal forming step in the manufacturing process of the electronic circuit device according to the present embodiment. .
FIG. 6 is a cross-sectional view of a conventional two-dimensional multichip package.
FIG. 7 is a cross-sectional view of a conventional three-dimensional multichip package.
FIG. 8 is a diagram for explaining a problem of a multichip package according to a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... 1st semiconductor chip, 2 ... 1st semiconductor chip, 3 ... Die bond material, 4 ... Bonding wire, 5 ... Interposer, 6 ... Inner lead, 7 ... External connection terminal, 8 ... Pad, 9 ... Sealing resin DESCRIPTION OF SYMBOLS 10 ... Spacer, 11 ... Semiconductor chip, 12 ... Semiconductor chip, 13 ... Edge coat material.

Claims (12)

所定の位置に端子が配置された複数の電子素子が基板上に積み重ねられた電子回路装置であって、
前記基板上に搭載された第１の電子素子と、
前記第１の電子素子の端子と重ならないように、少なくとも一部の部位が当該第１の電子素子上に搭載された第２の電子素子と、
前記基板と前記第２の電子素子との間隙を埋めて、当該第２の電子素子を支持するスペーサとを有し、
前記スペーサは、シリコン（Ｓｉ）または金属製である
電子回路装置。An electronic circuit device in which a plurality of electronic elements having terminals arranged at predetermined positions are stacked on a substrate,
A first electronic element mounted on the substrate;
A second electronic element having at least a portion thereof mounted on the first electronic element so as not to overlap with a terminal of the first electronic element;
A spacer that fills a gap between the substrate and the second electronic element and supports the second electronic element ;
The spacer is an electronic circuit device made of silicon (Si) or metal . 前記スペーサは、金属製である
請求項１記載の電子回路装置。The electronic circuit device according to claim 1, wherein the spacer is made of metal . 前記第１および第２の電子素子は、前記端子が形成された面とは反対側の面を前記基板に向けて搭載されている
請求項１または２記載の電子回路装置。It said first and second electronic devices, the electronic circuit device according to claim 1 or 2, wherein is mounted toward the surface opposite to the substrate and the terminals are formed face. 前記基板は、前記第１および第２の電子素子の端子と電気的に接続するための基板端子を有し、
前記第１および第２の電子素子の端子と前記基板端子とがワイヤにより結線されている
請求項３記載の電子回路装置。The substrate has substrate terminals for electrically connecting to the terminals of the first and second electronic elements,
The electronic circuit device according to claim 3, wherein a terminal of the first and second electronic elements and the substrate terminal are connected by a wire. 前記第１の電子素子の少なくとも外縁部に、前記ワイヤの前記第１の電子素子への接触を防止するための絶縁性樹脂が形成されている
請求項４記載の電子回路装置。The electronic circuit device according to claim 4, wherein an insulating resin for preventing the wire from contacting the first electronic element is formed on at least an outer edge portion of the first electronic element. 前記第１の電子素子は、端子形成面の中央部において一方向に配列された端子を有する
請求項１または２記載の電子回路装置。Wherein the first electronic device, the electronic circuit device according to claim 1 or 2, wherein having terminals arranged in one direction at the center of the terminal formation surface. 前記基板は、前記基板端子と電気的に接続された外部接続用端子を有する
請求項１または２記載の電子回路装置。The substrate is an electronic circuit device according to claim 1 or 2, wherein with said substrate terminal electrically connected to an external connection terminal. 所定の位置に端子が配置された複数の電子素子が基板上に積み重ねられた電子回路装置の製造方法であって、
前記基板上に第１の電子素子を搭載する工程と、
前記基板上にシリコンまたは金属製のスペーサを搭載する工程と、
前記第１の電子素子および前記スペーサ上に、前記第１の電子素子の前記端子と重ならないように、第２の電子素子を搭載する工程と
を有する電子回路装置の製造方法。A method of manufacturing an electronic circuit device in which a plurality of electronic elements having terminals arranged at predetermined positions are stacked on a substrate,
Mounting a first electronic element on the substrate;
Mounting a silicon or metal spacer on the substrate;
Mounting the second electronic element on the first electronic element and the spacer so as not to overlap the terminal of the first electronic element. 前記スペーサを搭載する工程は、金属製のスペーサを搭載する工程である
請求項８記載の電子回路装置の製造方法。9. The method of manufacturing an electronic circuit device according to claim 8 , wherein the step of mounting the spacer is a step of mounting a metal spacer . 前記第１および第２の電子素子を搭載する工程において、前記端子が形成された面とは反対側の面を前記基板に向けて前記第１および第２の電子素子を搭載する
請求項８または９記載の電子回路装置の製造方法。In the step of mounting the first and second electronic devices, said terminal are formed face for mounting the first and second electronic devices toward the surface opposite to the substrate according to claim 8 or A method for manufacturing an electronic circuit device according to claim 9 . 前記基板は、前記第１および第２の電子素子の端子と電気的に接続するための基板端子を有し、
前記第２の電子素子を搭載する工程の後に、前記第１および第２の電子素子の端子と前記基板端子とをワイヤにより結線する工程を有する
請求項１０記載の電子回路装置の製造方法。The substrate has substrate terminals for electrically connecting to the terminals of the first and second electronic elements,
The method for manufacturing an electronic circuit device according to claim 10, further comprising a step of connecting the terminals of the first and second electronic elements and the substrate terminal with a wire after the step of mounting the second electronic element. 前記ワイヤにより結線する工程の前に、前記第１の電子素子の少なくとも外縁部に、前記ワイヤの前記第１の電子素子への接触を防止するための絶縁性樹脂を形成する工程を有する
請求項１１記載の電子回路装置の製造方法。The step of forming an insulating resin for preventing contact of the wire with the first electronic element at least on an outer edge portion of the first electronic element before the step of connecting with the wire. 11. A method for manufacturing an electronic circuit device according to 11.
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KR101413220B1 (en) 2007-10-02 2014-06-30 삼성전자주식회사 Semiconductor package having interposer and method for manufacturing semiconductor package
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