JP4425115B2 - Clock synchronization apparatus and program - Google Patents

Description

  The present invention relates to a clock synchronizer and a program, and more particularly to a system for transmitting data continuously generated at a constant rate, such as video data, in a data clock between transmission and reception in a system for packetizing and transmitting continuous data. The present invention relates to a synchronization device.

When data generated continuously at a constant rate such as video data is transmitted using a packet communication line such as ATM or IP (Internet Protocol), the clock frequency of data input to the transmission side and packet reception When there is a difference in the clock frequency for reproducing and outputting continuous data on the side, there are problems of data interruption due to underflow of continuous data reproduced on the packet receiving side and data loss due to overflow of the receiving side buffer.
Therefore, in a packet transmission method such as MPEG-TS, time information based on a clock signal of input data is added to each packet on the transmission side, and time information in the packet received on the reception side and data on the reception side are added. By comparing the time information based on the reproduction clock and controlling the frequency of the data reproduction clock on the receiving side based on the comparison result, the data clock frequencies between the transmission and reception are matched.

As prior art documents related to the invention of the present application, there are the following.
Wataru Kameyama, Takeshi Hanamura, “Digital Broadcasting Textbook (above)”, Impress Net Business Company, Chapter 4, ISBN4-87280-477-5

A conventional MPEG-TS video clock synchronizer is generally realized by the configuration shown in FIG.
In the apparatus shown in FIG. 11, the video signal from the video device 12 synchronized with the master clock 11 is transmitted from the transmission unit 13 to the reception unit 15 via the transmission path 14.
In the transmission unit 13, the video input unit 16 is divided into two systems, and one video signal is temporarily buffered in the transmission buffer unit 17. The frequency component of the other video signal is extracted from the video signal by the clock reproduction unit 19 and the transmission side time is generated based on the extracted frequency component.
The packet transmission unit 18 packetizes the video signal, embeds transmission time information (PCR) output from the clock recovery unit 19, and outputs it to the transmission path 14.
In the reception unit 15, the packet reception unit 20 receives the packet, the reception buffer unit 21 performs assembly, and the PCR extraction 23 extracts the transmission time information (PCR) stored in the packet.
On the other hand, the reception unit 15 uses the clock information generated by the VCXO unit 26, the reception time information (STC) is generated by the STC generation unit 27, the comparator 24 compares the PCR and the STC, and the comparison value is obtained. After the noise component is removed by the LPF unit 25, the frequency of the VCXO unit 26 is controlled to reproduce the transmission-side clock, and the video output unit 22 outputs a video signal according to the reproduced clock.

However, the conventional techniques have the following problems.
(1) When the transmission line 14 has a lot of jitter such as an IP network, a large time fluctuation occurs in the comparison value between the transmission time information (PCR) and the reception time information (STC), and the video clock signal stabilized by the reception unit 15 Cannot be obtained.
(2) Since the video clock of the transmission unit 13 is reproduced by the reception unit 15, the application is limited. For example, in a live broadcast or the like, after a video transmitted from the transmission unit 13 in the relay destination according to the master clock 11 of the relay destination is received by the reception unit 15 in the broadcast station, the video clock used in the broadcast station is replaced. Is required. At that time, the frame difference and the extra frame problem occur due to the frequency difference of the video clock.
(3) The clock delay (phase difference) between transmission and reception cannot be controlled.

The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a video clock between transmission and reception even in video transmission using a jittery transmission line such as an IP network. It is an object of the present invention to provide a clock synchronization device that can be synchronized and realizes video transmission without dropping frames.
Another object of the present invention is to supply a video clock signal synchronized with the video master clock installed on the receiving side to the transmitting side video equipment, so that it is not necessary to replace the video clock in the broadcasting station even during live broadcasting. Therefore, an object of the present invention is to provide a clock synchronizer capable of broadcasting without dropping frames.
Another object of the present invention is to provide a clock synchronizer that can synchronize a plurality of video devices installed via a transmission line by controlling a delay between transmission and reception.
Another object of the present invention is to provide a program for causing a computer to execute a part of the processing of the clock synchronizer.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
In order to achieve the above-mentioned object, the present invention comprises a packet transmission device and a packet reception device connected to each other via a communication line , and transmits continuous data sent from an external continuous data output device to the packet transmission device. wherein the continuous data clock a clock synchronization system for synchronizing between the transmitter, the packet reception device, the communication times line or al the continuous data when transmitting to the packet receiving apparatus via the communication line from a packet receiving unit that receives a packet, a receiving buffer unit for storing information in the received packet as data, in synchronization with an external clock supplied from an external clock source in the packet receiving apparatus side when viewed from the communication line a data output unit which outputs the continuous data Te, reception buffer to observe the buffer usage of the receiving buffer unit A measuring unit, from the reception buffer usage, the external clock and the seeking the difference between successive data clock determines the clock adjustment amount, the communication by calculating a clock control amount of the continuous data from the clock adjustment amount and a clock control unit for transmitting the clock control amount in time line, the packet transmission apparatus includes a controller that generates a VCXO control signal the communication times line or al the clock control amount as an input, the VCXO control a D / a converter for converting a signal to the input control voltage, the VCXO unit for generating a reference clock of the frequency determined by the input control voltage, based on the basic clock generated by the VCXO unit, the continuous data output and a clock generator for generating a clock supplied device, the communication clock of the continuous data synchronized with said external clock source It characterized the Turkey be supplied to the data output device.

The present invention also includes a packet transmission device and a packet reception device connected to each other via a communication line , and continuous data sent from an external continuous data output device is transmitted from the packet transmission device via the communication line. a said clock synchronization device for synchronizing the generated pseudo consecutive data clock and the said consecutive data clock from the continuous data when transmitting to the packet receiving device, the packet reception device, the communication times line or al and a pseudo packet receiving unit that receives the pseudo-continuous data as packets, external with the information in the received by the pseudo packet receiving unit packet and the receiving buffer unit for storing as data, in the packet receiving apparatus side when viewed from the communication line and a pseudo data output unit external clock from the clock source is input, the buffer of the receiving buffer unit A receive buffer observation unit for observing the dose, from the amount for the reception buffer used to seek a difference between the external clock and the pseudo-continuous data clock determines the clock adjustment amount, the pseudo-continuous data from said clock adjustment amount It has of a clock control unit for the clock control amount is calculated to transmit the clock control amount to said communication round wire, wherein the packet transmitting apparatus generates the pseudo-continuous data from the continuous data, pseudo continuous data A pseudo-packet transmission unit that transmits the packet as a packet to the communication line, a control unit that inputs the clock control amount from the communication line and generates a VCXO control signal , and converts the VCXO control signal into an input control voltage Generated by a D / A converter, a VCXO unit that generates a basic clock having a frequency determined by the input control voltage, and the VCXO unit Based on the basic clocks, wherein and a clock generator for generating a clock to be supplied to the continuous data output device, to supply the said continuous data synchronized to an external clock source clock to the continuous data output device Turkey And features.

In addition, when a transmission path with a large jitter such as an IP network is used as a transmission path, a large jitter component is also included in the usage amount of the reception buffer unit. Therefore, in the present invention, the jitter component of the reception buffer usage amount is reduced. The reception buffer observation unit further accumulates the buffer usage sampled at a constant time interval for a predetermined time, and the average value is used as the usage amount of the reception buffer unit.
Further, the present invention is a program for causing a computer to execute a part of the processing of the clock synchronization device described above.
The present invention is also a computer-readable recording medium that records the above-described program.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, even in video transmission using a jittery transmission line such as an IP network, it is possible to synchronize the video clock between transmission and reception, and to realize video transmission without dropping frames. It becomes possible.
(2) According to the present invention, the video clock signal synchronized with the master clock of the video installed on the receiving side is supplied to the transmitting side video equipment, so that it is not necessary to replace the video clock in the broadcasting station even in live broadcasting. Yes, broadcasts without frame dropping are possible.
(3) According to the present invention, by controlling delays between a plurality of receiving sides to which the same master clock is supplied and a plurality of transmitting sides with respect to each of the plurality of receiving sides, Video equipment can be synchronized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Example 1]
1, Ri block diagram showing a schematic configuration of a video clock synchronization device of Example 1 of the present invention, the packet transmission unit (hereinafter, simply, a transmission unit hereinafter) and the synchronous clock generator 36 in 13, a packet A clock synchronization control unit 37 in the receiving unit (hereinafter simply referred to as a receiving unit) 15 is a part of the present invention.
In the figure, 16 is a video input unit for writing video data input from an external device to a transmission buffer, 17 is a transmission buffer unit for buffering between the video input unit and the packet transmission unit, and 28 is a packet for video data. A packet transmission unit for sending the data to the transmission line, 20 a packet reception unit for writing the video data input from the transmission line to the reception buffer unit 21, and 21 a reception buffer for buffering between the packet reception unit and the video output unit , 22 is a video output unit that reads video data from the reception buffer unit 21 and outputs a video signal according to the timing of the video clock signal input from the outside, and 34 is a reception buffer observation unit that observes the usage of the reception buffer unit 21 , 35 determine the control amount of the transmission side clock frequency, and send the control amount information to the VCXO control unit 29 on the transmission line 14. A clock control unit 29 that transmits the control amount information from the clock control unit 35 and outputs a VCXO control signal, and a D / A conversion unit 30 that performs a D / A conversion and generates a VCXO control voltage , 31 is an LPF unit that suppresses the high frequency component of the control voltage of the VCXO, 32 is a VCXO unit that generates a fundamental frequency for the transmission side video clock, and 33 is a video clock supplied to an external video device using the output of the VCXO It is a video clock generator that generates (a ternary synchronization signal, a black burst signal, etc.).

In the video clock synchronization apparatus shown in FIG. 1, the video signal input from the external video device 12 is output to the transmission line 14 via the packet transmission unit 28 that packetizes the video signal in the transmission unit 13. Reception processing is performed in the receiving unit 15 and reproduced and output as a video signal.
At this time, the output video from the receiving unit 15 is output in synchronization with the master clock 11 placed on the receiving side.
On the other hand, the video signal of the video equipment 12 input to the transmission unit 13 is transmitted from the clock synchronization control unit 37 in the reception unit 15 to the synchronous clock generation unit 36 in the transmission unit 13 via the transmission path 14. The case where it synchronizes with the produced | generated video clock output by sending is shown.
Here, the reception buffer observation unit 34 and the clock control unit 35 of the clock synchronization control unit 37 are a program that operates on a general-purpose personal computer or workstation, or a hardware such as a controller based on a microprogram that operates in cooperation with the program on the board. It can be configured with hardware.
Further, the VCXO control unit 29 of the synchronous clock generation unit 36 operates on a general-purpose personal computer or workstation, and hardware such as a controller configured by a program for setting registers such as a board or a microprogram operating in cooperation with the program on the board. Can be configured.
Further, the D / A conversion unit 30, the LPF unit 31, the VCXO unit 32, and the video clock generation unit 33 can be configured by commercially available D / A conversion ICs, RC filter circuits, VCXO components, video signal ICs, and the like.

Hereinafter, the operation of the clock synchronization control unit 37 of the reception unit 15 will be described.
The reception buffer observation unit 34 observes the buffer usage of the reception buffer unit 21. If the frequency of the master clock 11 is higher than the clock input to the video equipment 12, a decrease in the buffer amount is observed, and if the frequency of the master clock 11 is lower than the clock input to the video equipment 12. Observed as an increase in buffer volume.
When the transmission path 14 is a transmission path with a large jitter such as an IP network, a large jitter component is also observed in the increase and decrease of the usage amount of the reception buffer unit.
Therefore, in order to reduce the jitter component of the reception buffer usage, the buffer usage sampled at regular time intervals is further accumulated for a certain time (Ts seconds), and the average value is used as the usage of the reception buffer unit.
Next, as an example of the operation, in the case of HDTV 1080 / 30i (1080 interlace HDTV system at 30 frames per second), the operation is as follows.
(1) The usage amount of the reception buffer unit 21 is observed every frame (1/30 second).
(2) Accumulate sample data for 30 seconds (30 × 30 = 900 samples) and calculate an average value.
(3) The calculated average value is sent to the clock control unit 35 as a reception buffer usage amount.
The clock control unit 35 estimates the clock difference between transmission and reception based on the reception buffer usage received from the reception buffer observation unit 34, and further buffers the buffering amount so that the delay amount between transmission and reception becomes a preset value. The amount of adjustment of the clock on the transmission side is calculated to adjust
Based on the clock difference and the adjustment amount, the control amount of the transmission side clock frequency is determined, and the control amount information is sent to the VCXO control unit 29 via the transmission line 14.

Next, the operation of the clock control unit 35 will be described in detail.
First, a function for determining a target reception buffer usage (Bt), a reception buffer fluctuation threshold (Bth), and a transmission clock adjustment amount (fa) necessary for the operation of the clock control unit 35 is defined as follows.
The target reception buffer usage (Bt) is obtained by subtracting the transmission side delay amount, the transmission path delay amount, and the delay amount of the reception unit excluding the reception buffer unit 21 from the target transmission / reception delay. The delay time of the buffer unit 21 is calculated, and then the target reception buffer usage (Bt) is calculated. When setting of a delay value between transmission and reception is unnecessary, the reception buffer usage amount observed first is Bt.
Here, since the amount of use of the transmission buffer unit 17 is usually smaller than the amount of use of the reception buffer unit 21, both the amount and variation are small, so the variation in the transmission side delay amount is small and can be prepared in advance as a constant. .
Further, the delay amount of the transmission path can be prepared in advance by a method of calculating from the transmission distance or by measuring a round trip time using ICMP of the IP network.
Further, the delay amount of the receiving unit 15 excluding the receiving buffer unit 21 can be determined by a circuit configuration or the like and prepared in advance.

The reception buffer fluctuation threshold (Bth) is a value set in advance with reference to the observation accuracy of the reception buffer usage observed by the reception buffer observation unit 34.
In one example, if the reception buffer usage is observable with an accuracy within ± 10 lines, Bth is set to 20 lines, which is about twice the reception buffer usage observation accuracy.
The transmission clock adjustment amount (fa) determination function is defined as a function for obtaining the transmission clock adjustment amount (fa) based on the difference (ΔB) between the reception buffer usage amount (B) and the target reception buffer usage amount (Bt). An example is shown in FIG.
In the example shown in FIG. 2, a case is considered in which the maximum clock adjustment amount (fa_max) is set to 10 ppm in accordance with the characteristics of the connected device, and the shift of 100 lines is controlled within about 5 minutes.
In the case of a frequency difference of 1 ppm, the difference is about 1 line per 30 seconds in the HDTV 1080 / 30i system. In this case, when ΔB = 100 lines, fa = fa_max is set.

The clock control unit 35 operates according to the transition state shown in FIG. 3 every time the reception buffer usage (B) is sent from the reception buffer observation unit 34. 3, 51 indicates an initial state, 52 indicates an adjustment state, and 53 indicates a steady state. At the time of start-up, it starts from the initial state 51.
The operation in the initial state 51 is shown in the flowchart of FIG. 4, the operation in the adjustment state 52 is shown in the flowchart of FIG. 5, and the operation in the steady state 53 is shown in the flowchart of FIG.
In the following, the time counter value in the clock control unit 35 is t seconds, the reception buffer usage amount before t time is B0, the predicted value of the reception buffer usage amount is Be, the difference between Be and Bt is ΔBe, and the clock difference between transmission and reception is Let the estimated value be Δf.
The operation in the initial state 51 will be described using the flowchart of FIG.
When setting of a delay value between transmission and reception is unnecessary, the buffer usage amount first output from the reception buffer observation unit 34 is set to Bt (step 102), ΔB and t are calculated (step 103), and Δf is initialized ( Step 104), initial value of fa is set (Step 105).
When ΔB> Bth or ΔB <−Bth (step 106), fa is recalculated (step 107), the convergence prediction time (T) is calculated (step 108), the control amount fc is calculated, and the VCXO control unit 29 Send (step 109), reset at time t and update B0 (step 110), and transition to the adjustment state 52 (step 111).
When −Bth ≦ ΔB ≦ Bth (step 106), reset at time t and update B0 (step 112), and transition to the steady state 53 (step 113).

The operation in the adjustment state 52 will be described using the flowchart of FIG.
The reception buffer usage amount sent from the reception buffer observation unit 34 is set to B (step 115), the reception buffer expected amount (Be) is calculated (step 116), and ΔBe, ΔB, t are calculated (step 117). .
If ΔBe> Bth or ΔBe <−Bth (step 118), Δf is calculated (step 119), fa is calculated (step 119), T is calculated (step 121), fc is calculated and sent to the VCXO controller 29. (Step 122), t and B0 are updated (Step 123), and a transition is made to the adjustment state 52 (Step 124).
When −Bth ≦ ΔBe ≦ Bth (step 118), if t <T (step 125), transition to the adjustment state 52 (step 129), and if t ≧ T (step 125), the calculation of fc and the VCXO control unit 29 (Step 126), t and B0 are updated (step 127), and a transition is made to the steady state 53 (step 128).
The operation in the steady state 53 will be described using the flowchart of FIG.
The reception buffer usage amount sent from the reception buffer observation unit 34 is set to B (step 131), and ΔB and t are calculated (step 132).
When ΔB> Bth or ΔB <−Bth (step 133), Δf is calculated (step 134), fa is calculated (step 135), T is calculated (step 136), fc is calculated and sent to the VCXO controller 29. (Step 137), t and B0 are updated (Step 138), and a transition is made to the adjustment state 52 (Step 139).
When −Bth ≦ ΔB ≦ Bth (step 133), the state transitions to the steady state 53 (step 140).

Hereinafter, the operation of the synchronous clock generation unit 36 of the transmission unit 13 will be described.
Control amount information fc is received by the video clock generation unit 36 from the clock control unit 35 in the clock synchronization control unit 37 via the transmission line 14, and the VCXO control unit 29 outputs the VCXO control signal Vc as shown in FIG. To do this, the following operation is performed. Vc is an input value of the D / A converter 30 and is an integer value.
(1) At startup, an initial value is set for the VCXO control signal Vc.
(2) When the control information fc is received from the clock control unit 35, the control amount ΔVc is calculated as ΔVc = fc / k.
However, k is a value determined in advance by the characteristics of the D / A conversion unit 30, the LPF unit 31, and the VCXO unit 32 in the subsequent stage. The unit is (ppm / div), which is the amount of change in the output frequency of the VCXO unit 32 when the input value of the D / A conversion unit 30 is increased by one.
(3) Vc is gradually changed by ΔVc in accordance with a predetermined control speed v (div / s).
Here, v is an output change amount of Vc per unit time, and Vc is incremented (decreased) by 1 / v (second). This is a value for suppressing an abrupt video clock frequency change.
For example, when a 10-bit control, 5V output D / A converter and a 50 (ppm / V) VCXO component are used, the output of the D / A converter 30 is about 5 (mV) assuming that the LPF gain can be ignored. / Div), k = 50 * (5/1000) = 0.25 (ppm / div).
Further, when the maximum frequency change amount per second is set to 1 ppm, v = 1 / 0.25 = 4 (div / s).
By setting the Vc generated by the VCXO control unit 29 in a register on the board, the D / A conversion unit 30 converts it into a voltage, and the high frequency component is converted into a VCXO via the LPF unit 31 composed of an RC filter or the like. Input to the unit 32, the VCXO unit 32 generates a basic clock having a frequency determined by the input voltage, and the video clock generation unit 33 supplies the video clock to the external video equipment 12 (a ternary synchronization signal, a black burst signal, etc.) ) Is generated.

[ Reference example ]
Figure 8 is a reference example of a block diagram showing a schematic configuration of a video clock synchronizer is, synchronization in the receiver unit 15 clock generating unit 36 and the clock synchronization control unit 37 of the present invention is installed together.
In the operation of the figure, the video signal input from the video equipment 12 synchronized with the master clock 11 on the transmission side is output from the transmission unit 13 to the transmission path 14, and the reception unit 15 performs reception processing to reproduce the video signal. Is output.
At this time, the clock synchronization control unit 37 observes the reception buffer unit 21 in the reception unit 15 and sends an adjustment signal to the synchronization clock generation unit 36, so that the basic clock having a frequency synchronized with the master clock 11 on the transmission unit side. Is generated and synchronized with the video output unit 22 based on this basic clock to output video.
However, the control amount fc output from the clock control unit 35 of the reference example is obtained by inverting the sign of the control amount fc in the first embodiment.

[ Example 2 ]
9, Ri block diagram showing a schematic configuration of a video clock synchronization device according to a second embodiment of the present invention, by sending the actual pseudo video data instead of the video data, can be synchronized video clocks between transmitting and receiving This is an example.
In the figure, 38 is a pseudo packet transmitter for transmitting dummy packet data instead of a video signal, 39 is a pseudo receiver for receiving and processing pseudo data, and 40 is receiving the pseudo data to the length of the original video data. A decompressed pseudo packet receiving unit 41 is a pseudo video output unit that performs a pseudo video output operation.
The operation shown in FIG. 5 is that the video signal input from the video equipment 12 is output to the transmission path 14 via the packet transmission unit 28 that packetizes the video signal in the transmission unit 13, and at the same time from the pseudo packet transmission unit 38. Short pseudo video data is output to the transmission path 14.
The receiving unit 15 receives only the actual video signal and outputs the video signal in synchronization with the master clock 11.
On the other hand, the pseudo receiver 39 receives the pseudo video data by the pseudo packet receiver 40 and expands it to the actual video data length and passes it to the reception buffer unit 21. While synchronizing, video is output in a pseudo manner.
As a result, the clock synchronization control unit 37 can operate without using the actual video data, and the adjustment instruction is sent to the synchronous clock generation unit 36 in the transmission unit 13 via the transmission path 14, so On the other hand, a clock synchronized with the master clock on the receiving side can be given.

As described above, according to each of the above-described embodiments, it is possible to synchronize the video clock between transmission and reception even in video transmission using a jittery transmission line such as an IP network, and the video without dropping frames. Transmission can be realized.
In addition, by supplying a video clock signal synchronized with the master clock of the video installed on the receiving side to the transmitting side video equipment, it is not necessary to replace the video clock in the broadcasting station even during live broadcasting, and broadcast without frame dropping Is possible.
Furthermore, as shown in FIG. 10, by controlling the delays between a plurality of receiving sides to which the same master clock is supplied and a plurality of transmitting sides for each, a plurality of images installed via a transmission path Device synchronization is possible.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

It is a block diagram which shows schematic structure of the video clock synchronizer of Example 1 of this invention. It is a figure for demonstrating operation | movement of the determination function of the transmission clock adjustment amount of the clock control part shown in FIG. It is a state transition diagram for demonstrating the operation | movement of the state of the clock control part shown in FIG. 2 is a flowchart for explaining an operation in an initial state of a clock control unit shown in FIG. 1. 2 is a flowchart for explaining an operation in an adjustment state of the clock control unit shown in FIG. 1. 2 is a flowchart for explaining the steady state operation of the clock controller shown in FIG. It is a figure for demonstrating operation | movement of the VCXO control part shown in FIG. It is a block diagram which shows schematic structure of the video clock synchronizer of the reference example of this invention. It is a block diagram which shows schematic structure of the video clock synchronizer of Example 2 of this invention. It is a figure for demonstrating the effect produced by this invention. It is a figure for demonstrating operation | movement of the conventional video clock synchronizer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Master clock 12 Video equipment 13 Packet transmission part 14 Transmission path 15 Packet reception part 16 Video input part 17 Transmission buffer part 18 Packet transmission part (PCR insertion)
19 clock recovery unit 20 packet reception unit 21 reception buffer unit 22 video output unit 23 PCR extraction 24 comparator 25, 31 LPF unit 26, 32 VCXO unit 27 STC generation unit 28 packet transmission unit 29 VCXO control unit 30 D / A conversion unit 33 Video Clock Generation Unit 34 Reception Buffer Observation Unit 35 Clock Control Unit 36 Synchronization Clock Generation Unit 37 Clock Synchronization Control Unit 38 Pseudo Packet Transmission Unit 39 Pseudo Reception Unit 40 Pseudo Packet Reception Unit 41 Pseudo Video Output Unit

Claims (6)

A packet transmitter and a packet receiver connected to each other via a communication line are provided , and continuous data transmitted from an external continuous data output device is transmitted from the packet transmitter to the packet receiver via the communication line. A clock synchronization device for synchronizing the clock of the continuous data between transmission and reception when
The packet receiving apparatus, a packet receiving unit that receives the communication times line or al the continuous data as packets,
A reception buffer unit that stores information in the received packet as data;
A data output unit for outputting the continuous data in synchronization with an external clock input from an external clock source on the packet receiving device side as seen from the communication line ;
A reception buffer observation unit for observing the buffer usage of the reception buffer unit;
From the receiving buffer usage, the external clock and the seeking the difference between successive data clock determines the clock adjustment amount, the clock to the communication line to calculate the clock control amount of the continuous data from the clock adjustment amount A clock control unit for transmitting a control amount ;
The packet transmission device includes a control unit for generating a VCXO control signal the communication times line or al the clock control amount as an input,
A D / A converter for converting the VCXO control signal into an input control voltage;
A VCXO unit for generating a basic clock having a frequency determined by the input control voltage;
Based on the basic clock generated by the VCXO unit, and a clock generator for generating a clock to be supplied to the continuous data output device,
Clock synchronization device comprising a Turkey to supply the said continuous data clock synchronized to an external clock source to the continuous data output device. A packet transmitter and a packet receiver connected to each other via a communication line are provided , and continuous data transmitted from an external continuous data output device is transmitted from the packet transmitter to the packet receiver via the communication line. A clock synchronization device that synchronizes a clock of pseudo continuous data generated from the continuous data and a clock of the continuous data when
The packet receiving apparatus, and a pseudo packet receiving unit that receives the communication times line or al the pseudo-continuous data as packets,
A reception buffer for storing information in the packet received by the pseudo packet receiver as data;
A pseudo data output unit to which an external clock from an external clock source on the packet receiving device side as viewed from the communication line is input;
A reception buffer observation unit for observing the buffer usage of the reception buffer unit;
From the amount for the reception buffer used, the external clock and by obtaining a difference between the pseudo-continuous data clock determines the clock adjustment amount, the communication from the clock adjustment amount by calculating the clock control of the pseudo-continuous data A clock control unit for transmitting the clock control amount to the line,
The packet transmission device generates the pseudo continuous data from the continuous data, and transmits the pseudo continuous data as a packet to the communication line;
A control unit that inputs the clock control amount from the communication line and generates a VCXO control signal ;
A D / A converter for converting the VCXO control signal into an input control voltage;
A VCXO unit for generating a basic clock having a frequency determined by the input control voltage;
Based on the basic clock generated by the VCXO unit, and a clock generator for generating a clock to be supplied to the continuous data output device,
Clock synchronization device comprising a Turkey to supply the said continuous data clock synchronized to an external clock source to the continuous data output device. 3. The reception buffer observation unit according to claim 1 or 2 , wherein the reception buffer observation unit accumulates the buffer usage sampled at a constant time interval for a predetermined time, and uses the average value as the usage amount of the reception buffer unit. The clock synchronizer of description. In the clock synchronization device according to claim 1 or claim 2, wherein the receiving buffer monitoring section of the packet reception device, or, the clock control unit, or the processing of the control portion of the front Kipa packet transmission device to the computer A program to be executed. The program for making a computer perform the process of the said receiving buffer observation part of the said packet receiver in the clock synchronizer of Claim 3 . A computer-readable recording medium on which the program according to claim 4 or 5 is recorded.

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