JP4423728B2 - Data transmission apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transmission apparatus and method for transmitting packet data between a software processing apparatus that performs predetermined software processing and a hardware processing apparatus that performs predetermined hardware processing.
[0002]
[Prior art]
In companies and the like, terminals such as a plurality of personal computers are connected by a LAN (Local Area Network) such as Ethernet, and information is exchanged between the terminals. In a LAN, information is generally exchanged in units called packets. This packet includes types such as an IP (Internet Protocol) packet, an ARP (Address Resolution Protocol) packet, and an NHRP (Next Hop Resolution Protocol) packet. The packet has a format (packet format) defined for each packet type. Based on this packet format, the attributes of the packet can be recognized.
[0003]
By the way, various data processing apparatuses that process the above-described packets generally realize a function for performing high-speed processing with a hardware processing apparatus (H / W), and a function for performing complicated processing with a software processing apparatus (S / W). Therefore, it is necessary to exchange packets between H / W and S / W. The data transmission apparatus exchanges packets between H / W and S / W in such a data processing apparatus.
[0004]
FIG. 4 is a block diagram showing a configuration of a conventional data transmission apparatus. The data transmission apparatus 400 shown in the figure includes a data bus 401, a CPU 410, an address bus 411, an input / output signal bus 412, an integrated circuit (LSI) 420, an address decoder 430, a chip select signal bus 431, and a FIFO (First In First Out). A memory 440 is included. The data transmission apparatus 400 uses a CPU 410 as an S / W and an LSI 420 as an H / W, and transmits packet data from the LSI 420 to the CPU 410 via a data bus 401. The data bus 401 is a 16-bit width transmission path capable of transmitting 16-bit data in parallel.
[0005]
Hereinafter, the operation when packet data is transmitted from the LSI 420 to the CPU 410 will be described with reference to a time chart during packet data transmission shown in FIG. The CPU 410 transmits the read signal to the input / output signal bus 412. Each time the read signal is transmitted, the LSI 420 transmits the packet data in units of 8 bits (one word) in parallel to the data bus 401, and in synchronization with the transmission of the packet data in units of 8 bits. Two-bit data (packet status signal) for identifying the head is transmitted to the data bus 401. As shown in FIG. 4, the packet status signal indicates “1” when the first word (D1) of the packet data is transmitted, and indicates “0” when the second and subsequent words are transmitted. Accordingly, one word of packet data and a 1-bit packet status signal are transmitted in parallel to the data bus 401. The packet data and the packet status signal transmitted to the data bus 401 are stored in the FIFO memory 440.
[0006]
On the other hand, the CPU 410 recognizes that the packet data and the packet status signal are stored in the FIFO memory 440 by receiving a predetermined interrupt signal or the like, reads the packet data from the FIFO memory 430 word by word, A packet status signal corresponding to packet data for a word is read. As described above, the CPU 410 can recognize the head of the packet data by reading the packet status signal together with the packet data.
[0007]
[Problems to be solved by the invention]
By the way, the contents of packet data are generally divided in units of 8 bits (1 word). For this reason, when packet data is processed, it is possible to reduce the complexity of the circuit and the program by processing in units of bits that are an integral multiple of 8 rather than in units of arbitrary bits. For the above reason, the above-described data transmission apparatus 400 transmits packet data in units of 8 bits.
[0008]
On the other hand, the data bus generally has a number of signal lines that is an integer multiple of eight. For this reason, if the data bus can be used only for transmission of packet data, all signal lines are used. However, as described above, since the packet status signal is transmitted along with the packet data to the data bus, some signal lines are not used, and the transmission efficiency of the packet data is reduced.
[0009]
For example, in the data transmission apparatus 400, the data bus 401 has 16 signal lines. Therefore, if the data bus 401 can be used only for packet data transmission, packet data is transmitted in units of two words. can do. However, since a 2-bit packet status signal is transmitted along with the packet data to the data bus 401, some signal lines are not used and the packet data can be transmitted only in units of one word. For this reason, it has been required to improve the transmission efficiency of packet data.
[0010]
An object of the present invention is to provide a data transmission apparatus that solves the above-described conventional problems and improves the transmission efficiency of packet data.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a data transmission device of the present invention transmits the packet data between a first processing device that processes packet data and a second processing device that processes packet data. N + m bit width storage means for temporarily storing a bit string of n-bit packet data transmitted from the first processing device to the second processing device; the first processing device; and the storage means. A first bus having an n-bit width that enables transmission of the bit string of the n-bit packet data between the storage unit and the second processing device, and a bit string of the n-bit packet data between the storage unit and the second processing device. a second bus width of n bits of the n-bit width to be transmitted, provided in the first processing unit, whether the bit string of the packet data of the n bits is the head of the packet data The information bit generating means for generating information bits of m bits used to identify whether, in the storage unit from the information bit generating means, for each bit string of the packet data of n bits, inputs the information bits in correspondence the information bit input means for a predetermined bits included in the bit string of n bits packet data of the head that is transmitted from said storage means to the second bus, while replacing the information bits indicating the beginning, otherwise For the bit string, a bit replacement means that does not replace the bit, and the information bit is extracted from the bit string of the n-bit packet data transmitted to the second processing device via the second bus, and the information and a packet position detection means for detecting the head position of the bit string of the packet data of the n bits from the bit It is made.
[0012]
In particular, it is preferable that the bit string of the n-bit packet data corresponding to the head of the packet data includes a packet length of the packet data.
[0013]
The data transmission method of the present invention includes a first procedure for temporarily storing a bit string of the n-bit packet data transmitted from the first processing device to the second processing device in the storage means. A second procedure that is provided in the first processing device and generates m-bit information bits used to identify whether a bit string of the n-bit packet data is the head of the packet data ; A third procedure for inputting the information bits in correspondence with each bit string of n-bit packet data from the information bit generation means to the storage means, and a head transmitted from the storage means to the second bus wherein the predetermined bits included in the bit string of n bits packet data, while replacing the information bits indicating the head, replacement of the bit in the case of other bit string of A fourth step which does not, the second by extracting the information bits from the bit string of the packet data of the n bits transmitted to the second processing unit via a bus, of the n bits from the information bits And a fifth procedure for detecting the leading position of the bit string of the packet data.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on the illustrated embodiment. FIG. 1 is a block diagram showing a configuration of a data transmission apparatus according to the present invention. The data transmission apparatus 100 shown in the figure includes a data bus 101a, 101b, 101c, 101d, a CPU 110, an address bus 111, an input / output signal bus 112, an address decoder 120, a chip select signal bus 121, an LSI 130, a control information generation circuit 131, A packet status signal bus 132, a selector 133, and a selector control signal bus 134 are included. The data transmission apparatus 100 uses a CPU 110 as S / W and an LSI 1130 as H / W, and transmits packet data from the LSI 130 to the CPU 110 via data buses 101a, 101b, and 101c. In the following, it is assumed that the most significant bit of the packet data has no content, and the second to eighth bits indicate the length of the packet data (packet length).
[0015]
The data bus 101a enables transmission of packet data from the LSI 130 to the FIFO memory 140, and is a 16-bit width transmission path capable of transmitting 16-bit data in parallel. On the other hand, the data bus 101b and the data bus 101c enable transmission of packet data from the FIFO memory 140 to the CPU 110. The data bus 101b is a 15-bit transmission path capable of transmitting 15-bit data in parallel. The data bus 101c is a 1-bit width transmission path. In addition, the data bus 101d enables data transmission from the CPU 110 to the LSI 130.
[0016]
The CPU 110 performs predetermined software processing on the packet data transmitted from the LSI 130. Further, the CPU 110 controls the entire data transmission apparatus 100 in transmission of packet data. Specifically, when starting transmission of packet data from the LSI 130 to the CPU 110, the CPU 110 transmits a write signal to the input / output signal bus 112 and is assigned to the control information generation circuit 131 prior to the transmission. The address “B” is transmitted to the address bus 111, and data “X” to start transmission of packet data is transmitted to the data bus 101d. When transmitting packet data from the LSI 130 to the CPU 110, the CPU 110 transmits a read signal to the input / output signal bus 112 and transmits an address “A” assigned to the FIFO memory 140 to the address bus 111. The address “A” and the address “B” are taken into the address decoder 120. Further, data “X” indicating that transmission of packet data is started is taken into the control information generation circuit 131.
[0017]
The address decoder 120 generates a chip select signal for controlling input / output of data by the control information generation circuit 131 and the FIFO memory 140 based on the address transmitted from the CPU 110. Here, the control information generation circuit 131 can take in data when the chip select signal is at a low level, and the FIFO memory 140 can input / output data when the chip select signal is at a low level. It has become. When the address “A” assigned to the FIFO memory 140 is transmitted, the address decoder 120 sends a low-level chip select signal to the chip select signal bus 121 so that the FIFO memory 140 can input and output data. To the FIFO memory 140. In addition, when the address “B” assigned to the control information generation circuit 131 is transmitted, the address decoder 120 outputs a low-level chip select signal so that the control information generation circuit 131 can capture data. The data is transmitted to the control information generation circuit 131 via the chip select signal bus 121.
[0018]
The LSI 130 performs predetermined hardware processing on the packet data. The LSI 130 is provided with a control information generation circuit 131. The control information generation circuit 131 recognizes that transmission of packet data is instructed by the CPU 110 by taking in data “X” to start transmission of packet data transmitted from the CPU 110 via the data bus 101c. Thereafter, each time a read signal is transmitted from the CPU 110, the processed packet data is transmitted in parallel to the data bus 101a in units of 16 bits (2 words). Hereinafter, a bit string of packet data for two words, which is a unit of transmission, is referred to as a “packet block”. The transmitted packet block is stored in the FIFO memory 140.
[0019]
In addition, every time a packet block is transmitted, the control information generation circuit 131 generates a 1-bit packet status signal corresponding to the packet block. The packet status signal indicates to which position of the packet data the packet block corresponds, and is “1” when the packet block corresponds to the head of the packet data, and “0” otherwise. ". The control information generation circuit 131 transmits the packet information signal thus generated to the packet status signal bus 132 having a 1-bit width so that the packet information signal is stored in the FIFO memory 140 simultaneously with the packet block corresponding to the packet information signal. To do.
[0020]
The FIFO memory 140 stores and outputs data in units of 17 bits, and simultaneously stores a packet block and a packet status signal corresponding to the packet block, and outputs them in this storage order. Among the output packet blocks, the most significant bit is transmitted to the selector 133 via the data bus 101c, and the second and subsequent bits are transmitted to the CPU 110 via the data bus 101b. The output packet status signal is transmitted to the selector 133 via the packet status signal bus 132.
[0021]
Further, the control information generation circuit 131 controls the selector 133 by sending a selector control signal. Specifically, the control information generation circuit 131, when the most significant bit of the packet block corresponding to the head of the packet data and the packet status signal “1” corresponding to the packet block are input to the selector 133, The packet status signal is output, and in other cases, the selector 133 is controlled to output the most significant bit of the packet block. The selector 133 performs a switching operation in accordance with the control of the control information generation circuit 131 and replaces the most significant bit of the packet block corresponding to the head of the packet data with the packet status signal “1” corresponding to the packet block. The 1-bit data output from the selector 133 is transmitted to the CPU 110 via the data bus 101c.
[0022]
The CPU 110 receives 1-bit data output from the selector 133 and 15-bit data after the second bit of the packet block output from the FIFO memory 140, and restores the packet block from these data. As described above, the selector 133 replaces the most significant bit of the packet block corresponding to the head of the packet data with the packet status signal “1” corresponding to the packet block. Therefore, the CPU 110 can recognize the head of the packet data by analyzing the most significant bit of the restored data block and detecting the packet status signal. Further, since the second to eighth bits of the packet block corresponding to the head of the packet data indicate the packet length, the CPU 110 can also recognize the length of the packet data.
[0023]
The data transmission apparatus 100 according to the present invention has the configuration described above, and the operation thereof will be described next. FIG. 2 is a time chart when the data transmission apparatus 100 transmits packet data. In the following, a case where packet data is divided into 80 packet blocks “D1” to “D80” and transmitted is described.
[0024]
In the first CPU cycle (CPU cycle 1), the CPU 110 transmits a write signal to the input / output signal bus 112 and transmits the address “B” assigned to the control information generation circuit 131 to the address bus prior to transmission of the packet data. The data “X” to start transmission of packet data is transmitted to the data bus 101 d. When the address “B” is transmitted, the address decoder 120 outputs a low-level chip select signal so that the control information generation circuit 131 can capture data and the FIFO memory 140 cannot input / output data. The high-level chip select signal is transmitted to the FIFO memory 140. The control information generation circuit 131 can capture data, captures data “X” to start transmission of packet data, and recognizes that transmission of packet data has been instructed.
[0025]
In the next CPU cycle (CPU cycle 2), the CPU 110 transmits the read signal to the input / output signal bus 112 and transmits the address “A” assigned to the FIFO memory 140 to the address bus 111. When the address “A” is transmitted, the address decoder 120 outputs a low-level chip select signal so that the FIFO memory 140 can input / output data and the control information generation circuit 131 cannot capture data. The data is transmitted to the FIFO memory 140, and a high-level chip select signal is transmitted to the control information generation circuit 131. The LSI 130 transmits the packet block “D1” to the FIFO memory 140 when the read signal is transmitted. Further, the control information generation circuit 131 generates a packet status signal “1” corresponding to the data block “D1” and transmits the packet status signal “1” to the FIFO memory 140. Accordingly, the packet block “D1” and the packet status signal “1” corresponding to the packet block “D1” are simultaneously stored and output in the FIFO memory 140. The control information generation circuit 131 sends a selector control signal to control the selector 133 to output a packet status signal based on an instruction to start transmission of packet data in the CPU cycle 1. Therefore, the packet block received by the CPU 110 is the one in which the most significant bit is replaced with the packet status signal.
[0026]
In CPU cycle 3, CPU 110 transmits a read signal and continues transmission of address “A”. Since the transmission of the address “A” is continued, the address decoder 120 maintains the chip select signal to be transmitted to the FIFO memory 140 at a low level, and enables the FIFO memory 140 to input / output data. When the read signal is transmitted, the LSI 130 transmits the packet block “D2” to the FIFO memory 140. Further, the control information generation circuit 131 generates a packet status signal “0” corresponding to the data block “D2” and transmits the packet status signal “0” to the FIFO memory 140. Accordingly, the packet block “D2” and the packet status signal “0” corresponding to the packet block “D2” are simultaneously stored and output in the FIFO memory 140. Further, the control information generation circuit 131 sends a selector control signal to control the selector 133 to output the most significant bit of the packet block based on the generation of the packet control signal “1” in the CPU cycle 2. To do. Therefore, the packet block received by the CPU 110 is such that the most significant bit is not replaced with the packet status signal. Thereafter, the same operation is repeated until the packet block “D80” is transmitted in the CPU cycle 81.
[0027]
As described above, in the data transmission apparatus 100, the most significant bit of the packet block corresponding to the head of the packet data is replaced with the packet status signal “1” corresponding to the packet block. For this reason, it is not necessary to separately transmit a packet status signal as in the conventional case. Therefore, only the packet data can be transmitted to the data buses 101a and 101b, and the transmission efficiency of the packet data can be improved.
[0028]
The embodiment of the present invention has been described with reference to the drawings. However, the present invention is not limited to the matters shown in the above-described embodiments, and it is obvious that changes, improvements, etc. can be made based on the description of the scope of claims. For example, in the above-described embodiment, the data bus 101a is 16 bits wide, but the bit width may be a multiple of 8. As for the bit width of the data bus 101b, a result obtained by subtracting the number of bits of the packet status signal from the bit width of the data bus 101a may be set.
[0029]
【The invention's effect】
As described above, according to the present invention, since a part of packet data is transmitted by being replaced with information bits used for identifying packet positions, the transmission efficiency of packet data can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a data transmission apparatus according to the present invention.
2 is a time chart at the time of packet data transmission of the data transmission device data shown in FIG. 1; FIG.
FIG. 3 is a block diagram showing a configuration of a conventional data transmission apparatus.
4 is a time chart at the time of packet data transmission of the data transmission device data shown in FIG. 3; FIG.
[Explanation of symbols]
100 Data transmission devices 101a, 101b, 101c, 101d Data bus 110 CPU
111 Address bus 112 Input / output signal bus 120 Address decoder 121 Chip select signal bus 130 LSI
131 Control Information Generation Circuit 132 Packet Status Signal Bus 133 Selector 134 Selector Control Signal Bus 140 FIFO Memory

Claims (3)

In a data transmission device for transmitting the packet data between a first processing device for processing packet data and a second processing device for processing packet data,
N + m bit width storage means for temporarily storing a bit string of n-bit packet data transmitted from the first processing device to the second processing device;
An n-bit width first bus enabling transmission of a bit string of the n-bit packet data between the first processing device and the storage means;
An n-bit wide n-bit second bus enabling transmission of a bit string of the n-bit packet data between the storage means and the second processing device;
An information bit generating means provided in the first processing device for generating m bits of information bits used to identify whether a bit string of the n-bit packet data is the head of the packet data ;
Information bit input means for inputting the information bits in correspondence with each bit string of n-bit packet data from the information bit generation means to the storage means;
The predetermined bits included in the bit string of n bits packet data of the head that is transmitted from said storage means to the second bus, while replacing the information bits indicating the beginning, the replacement of the bit in the case of other bit strings Not bit replacement means,
Extracting the information bits from the bit string of the n-bit packet data transmitted to the second processing device via the second bus, and starting position of the bit string of the n-bit packet data from the information bits A data transmission apparatus comprising: a packet position detecting means for detecting The data transmission apparatus according to claim 1, wherein a bit string of the n-bit packet data corresponding to a head of the packet data includes a packet length of the packet data. In the data transmission method in the data transmission device according to claim 1 or 2,
A first procedure for temporarily storing a bit string of the n-bit packet data transmitted from the first processing device to the second processing device in the storage means;
A second procedure that is provided in the first processing device and generates m-bit information bits used to identify whether a bit string of the n-bit packet data is the head of the packet data ;
A third procedure for inputting the information bits in association with each bit string of n-bit packet data from the information bit generation means to the storage means;
The predetermined bits included in the bit string of n bits packet data of the head that is transmitted from said storage means to the second bus, while replacing the information bits indicating the beginning, the replacement of the bit in the case of other bit strings Don't do the fourth step,
Extracting the information bits from the bit string of the n-bit packet data transmitted to the second processing device via the second bus, and starting position of the bit string of the n-bit packet data from the information bits A data transmission method comprising: a fifth procedure for detecting the data.

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