JP4416775B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus that captures a plurality of subject images using a plurality of solid-state imaging elements and synthesizes a plurality of series of image signals obtained thereby.

  In an imaging apparatus such as a digital still camera, it is considered that a plurality of solid-state imaging elements are mounted and different subjects are simultaneously imaged. Such an imaging device is configured to combine a plurality of series of image signals obtained from a plurality of solid-state imaging devices and display, for example, a plurality of reproduced images on one display screen. FIG. 10 is a block diagram illustrating an example of an imaging apparatus equipped with a plurality of solid-state imaging elements.

  The image pickup apparatus shown in FIG. 10 has two image pickup apparatuses 20a and 20b corresponding to the respective subjects in order to pick up two subject images, and the respective outputs are controlled by the memory controller 9. .

  The first imaging device 20a includes a first CCD solid-state imaging device 1a, a first booster circuit 2a, a first CCD driver circuit 3a, a first timing control circuit 4a, a first analog signal processing circuit 5a, a first 1 A / D conversion circuit 6a, first digital signal processing circuit 7a, and first memory 8a, and constitutes a first imaging system. In the first CCD solid-state imaging device 1a, a plurality of light receiving pixels are arranged in a matrix, and information charges generated in response to the incident first subject image are accumulated in each light receiving pixel. Further, the first CCD solid-state imaging device 1a has a so-called vertical overflow drain structure that absorbs excessive information charges generated in each light receiving pixel to the substrate side, and information charges accumulated in each light receiving pixel. Can be discharged to the substrate side.

  The first booster circuit 2a boosts an input power supply voltage VD (not shown) to generate a boosted voltage, which is supplied to the first CCD driver circuit 3a. The first CCD driver circuit 3a generates a plurality of clock pulses using the boosted voltage generated by the first booster circuit 2a, and supplies the clock pulses to the first CCD solid-state imaging device 1a. The plurality of clock pulses are generated based on various timing signals supplied from the first timing control circuit 4a. As a result, an image signal Y (t) corresponding to the amount of information charges accumulated in each light receiving pixel of the first CCD solid-state imaging device 1a is taken out from the first CCD solid-state imaging device 1a in units of one pixel. .

  The first timing control circuit 4a includes a plurality of counters that count a reference clock CK having a fixed period, and generates a vertical synchronization signal VD and a horizontal synchronization signal HD by dividing the reference clock CK. Various timing signals to be supplied to the first CCD driver circuit 1b are generated at a timing synchronized with the vertical synchronization signal VD and the horizontal synchronization signal HD. As a result, the first CCD solid-state imaging device 1a outputs the image signal Y (t) for each line at the timing synchronized with the horizontal synchronization signal HD, and for each screen at the timing synchronized with the vertical synchronization signal VD. An image signal Y (t) is output.

The first analog signal processing circuit 5a performs CDS (Correlated Double Sampling) and AGC (Automatic Gain Control) on the image signal Ya (t) output from the first CCD solid-state imaging device 1a. Analog signal processing such as automatic gain control. In the CDS, for the image signal that repeats the reset level and the signal level, the signal level is extracted after the reset level is clamped to generate an image signal having a continuous signal level. In AGC, the image signal extracted by CDS is integrated in one screen or in units of one vertical scanning period, and gain adjustment is performed so that the integration data falls within a predetermined range. 1st A
The / D converter 6a normalizes the first image signal Ya (t) output from the first analog signal processing circuit 5a in synchronization with the output timing of the first CCD solid-state imaging device 1a, and converts the digital signal The first image data Ya (n) is output.

  The first digital signal processing circuit 7a performs processing such as color separation and matrix calculation on the first image data Ya (n) to generate image data Y ′ (n) including luminance data and color difference data. To do. Further, the first digital signal processing circuit 7a includes an exposure control circuit and a white balance control circuit, exposure control for controlling the exposure state of the first CCD solid-state imaging device 1a, and white balance of the image signal Y (t). Apply white balance correction processing. The first memory 8a is a frame memory, and stores luminance data and color difference data output from the first digital signal processing circuit 7a in response to a write instruction from the memory controller 9 in units of one screen.

  The second imaging device 20b includes a second CCD solid-state imaging device 1b, a second booster circuit 2b, a second CCD driver circuit 3b, a second timing control circuit 4b, a second analog signal processing circuit 5b, 2 A / D conversion circuit 6b, second digital signal processing circuit 7b, and second memory 8b, and forms a second imaging system. Each circuit constituting the second imaging device 20b has the same circuit configuration as each circuit constituting the first imaging device 20a, and the second image signal output from the second CCD solid-state imaging device 1b. The same processing is performed for.

  The memory controller 9 controls the readout timing of the first and second image data from the first and second memories 8a and 8b, and the captured image captured by the first imaging device 20a and the second imaging device. Control is performed so that the captured image captured in 20b is reproduced on a single display screen. For example, as illustrated in FIG. 11A, the first captured image A and the second captured image captured by the first imaging device 20a in two regions divided in the vertical direction on a single display screen. When displaying the second captured image B captured by the device 20b, the first image data Ya (n) and the first image data corresponding to the first captured image A from the first and second memories 8a and 8b. The second image data Yb (n) corresponding to the second captured image B is extracted. Thereafter, the two image data are combined so as to match the display form on the display screen. Further, as shown in FIG. 11B, when the first captured image A is mainly displayed on the display screen and the second captured image B is reduced and displayed in the lower left quarter region of the display screen, First image data Ya (n) corresponding to the upper half of the display screen is read from the first memory 8a, and then the first image data Ya (n) corresponding to the lower half of the display screen is read from the first and second memories 8a and 8b. The first image data Ya (n) and the second image data Yb (n) are read out. At this time, the image data for one screen read from the second memory 8 is compressed to ¼ data in order to display one screen for the area where the second captured image B is allocated on the display screen. To do. Then, the first image data Ya (n) and the compressed second image data Yb (n) are combined, and the first captured image A and the second captured image B reduced to ¼. Are simultaneously displayed on one display screen.

  An imaging apparatus that captures a plurality of subject images as described above using a plurality of solid-state imaging devices and synthesizes and displays a plurality of captured images on a single display screen includes a solid-state imaging device, a drive circuit, and timing control. Since a plurality of sets of circuits and signal processing circuits are mounted, there is an inconvenience that the circuit scale increases and the power consumption increases. For this reason, it is conceivable to reduce the circuit scale of the image pickup apparatus by sharing a circuit other than the solid-state image pickup device, but there are a number of choices as to which of the circuits included in the image pickup apparatus is common. If a simple circuit to be shared is selected from among the options, it will cause adverse effects such as functional degradation. For example, when the drive system is shared, a plurality of solid-state image sensors cannot be driven simultaneously, and the frame rate of each solid-state image sensor decreases.

  Therefore, the present invention finds an optimal combination of an individually provided circuit and a common circuit in an imaging apparatus using a plurality of solid-state imaging elements, and realizes reduction in circuit scale and efficient operation. An object of the present invention is to provide an imaging apparatus.

  The present invention has been made in order to solve the above-described problems. The feature of the present invention is that a plurality of light receiving pixels are arranged in a matrix and each information light generated in response to the first subject image is received. A first solid-state imaging device that accumulates in pixels, a plurality of light-receiving pixels arranged in a matrix, and a second solid-state imaging device that accumulates information charges generated in response to a second subject image in each light-receiving pixel; A first drive circuit that transfers and outputs information charges accumulated in each light receiving pixel of the first solid-state image sensor to obtain a first image signal, and is accumulated in each light-receiving pixel of the second solid-state image sensor. A second driving circuit for transferring and outputting information charges to obtain a second image signal; and a first driving circuit for determining a vertical scanning timing and a horizontal scanning timing of the first solid-state imaging device based on a reference clock having a fixed period. Timing control circuit and the reference clock And a second timing control circuit for determining the timing of the vertical scanning and the horizontal scanning of the second solid-state imaging device, and the first and second solid-state imaging devices in synchronization with the operation timing of the first and second solid-state imaging devices. A selection circuit that selectively outputs one of the two image signals, and a signal processing circuit that receives the output from the selection circuit and generates a predetermined image signal, the selection circuit having a predetermined time The first and second image signals are alternately selected every time.

  According to the present invention, the first and second image signals are taken into the selection circuit from the first and second solid-state imaging devices, and the first and second image signals are alternately changed at predetermined intervals by the selection circuit. Is selected and output. As a result, the first and second image signals are substantially synthesized on the output side of the selection circuit. For this reason, the signal processing circuit after the selection circuit can be shared by the first and second solid-state imaging devices. In addition, since the timing control circuit is provided in association with each solid-state imaging device, a plurality of solid-state imaging devices having different driving conditions can be incorporated into one imaging device.

  FIG. 1 is a block diagram showing the configuration of the first embodiment of the imaging apparatus of the present invention. This imaging device includes two solid-state imaging devices, and first and second CCD solid-state imaging devices 31a and 31b, first and second boosting circuits 32a and 33b, and first and second CCDs. The driver circuits 33a and 33b, the timing control circuit 34, the first and second clamp circuits 35a and 35b, the selection circuit 36, the analog signal processing circuit 37, the A / D conversion circuit 38, and the digital signal processing circuit 39 are included.

The first CCD solid-state imaging device 31a is, for example, a frame transfer type solid-state imaging device as shown in FIG. 2, and includes a plurality of vertical shift registers 1v continuous from the imaging unit to the storage unit, and the plurality of vertical shift registers 1v. The horizontal shift register 1h disposed on the output side of the horizontal shift register 1h and the output unit 1d disposed on the output side of the horizontal shift register 1h. In the imaging unit, the vertical shift register 1v is electrically separated to form a plurality of light receiving pixels.
Information charges generated by receiving the subject image are accumulated in each light receiving pixel. Further, in the imaging unit, some columns of the plurality of vertical shift registers are shielded from light and set in a so-called OPB (Optical Black) region. Information charges accumulated in each light receiving pixel of the imaging unit are transferred to the accumulation unit at a high speed by a frame transfer clock φa (f) and a vertical transfer clock φa (v). The information charges output to the storage unit are temporarily stored in the storage unit, transferred to the horizontal shift register 1h by the vertical transfer clock φa (v) in units of one line, and output from the horizontal shift register 1h by the horizontal transfer clock φh. The data is transferred to the unit 1d side in units of one pixel. The information charge output to the output unit 1d is stored in a capacitor for each pixel, thereby being converted into a voltage value corresponding to the amount of charge and output as an image signal Ya (t). At this time, in the output unit 1d, the information charge accumulated in the capacitor is discharged to the drain in response to the reset clock φr synchronized with the horizontal transfer clock φh. Further, the first CCD solid-state imaging device 1a has a so-called vertical overflow drain structure that absorbs excessive charges generated in the imaging unit to the substrate side, and information charges accumulated in the imaging unit are transferred to the substrate clock φa. It is possible to discharge to the substrate side by (b). Similar to the first CCD solid-state image sensor 31a, the second CCD solid-state image sensor 31b has a plurality of light-receiving pixels arranged in a matrix and accumulates information charges generated in response to the second subject image in each light-receiving pixel. Then, the second image signal Yb (t) corresponding to the stored information charge is output. This second CCD solid-state imaging device 1b also has a vertical overflow drain structure, and information charges can be discharged to the substrate side.

  The first booster circuit 32a is disposed corresponding to the first CCD solid-state imaging device 31a, boosts and boosts the input power supply voltage VD (not shown), and supplies the boosted voltage to the first CCD driver circuit 33a. To do. The second booster circuit 33b is arranged corresponding to the second CCD solid-state imaging device 31b, and, like the first booster circuit 32a, the booster voltage obtained by boosting the power supply voltage VD is supplied to the second CCD driver. Supply to the circuit 33b.

  Based on the timing signal supplied from the timing control circuit 34, the first CCD driver circuit 33a has a first frame transfer clock φa (f), a first vertical transfer clock φa (v), and a first horizontal transfer clock. φa (h), a first reset clock φa (r), and a first substrate clock φa (b) are generated and supplied to the first CCD solid-state imaging device 31a. Based on the timing signal supplied from the timing control circuit 34, the second CCD driver circuit 33b generates a second frame transfer clock φb (f), a second vertical transfer clock φb (v), and a second horizontal transfer clock. φb (h), a second reset clock φb (r) and a second substrate clock φb (b) are generated and supplied to the second CCD solid-state image sensor 33b. The first and second CCD driver circuits 33a and 33b are arranged corresponding to the first and second CCD solid-state imaging devices 31a and 31b, respectively. For this reason, the first and second solid-state imaging are performed. The elements 31a and 31b can be driven simultaneously.

  The timing control circuit 34 includes a plurality of counters 34a that count a reference clock CK having a fixed period and a decoder 34b that decodes the output of the counter, and generates a plurality of various timing signals by changing the set values of the decoder 34b. can do. The timing control circuit 34 is arranged in common with respect to the first and second CCD driver circuits 33a and 33b.

  Further, the timing control circuit 34 receives, for example, one of a plurality of setting data corresponding to each of a plurality of display modes set as shown in FIG. 3 from a register 40 which will be described later, and according to this, the decoder 34b. The set value of is changed. Thereby, the supply start timing and rise timing of each clock pulse are changed. For example, in the case of FIG. 3B, setting data corresponding to this is supplied to the decoder 34b, and the phase of the clock pulse supplied to the first CCD driver circuit 33a and the clock pulse supplied to the second CCD driver circuit 33b. Each clock pulse is generated so as to be out of phase. These clock pulses are supplied to the first and second CCD solid-state imaging devices 31a and 31b, and the first image signal Ya (t) and the second image signal Yb (t) are output in a time division manner. It is controlled so that

The register 40 stores a plurality of setting data associated with each of a plurality of display modes, receives a display mode switching signal MODE given from the outside, and sets data corresponding to the display mode specified thereby Is output to the timing control circuit 34. Thereby, the supply start timing or the rising timing of each clock pulse is changed in accordance with the designated display mode.

  The first clamp circuit 35a is arranged corresponding to the first CCD solid-state imaging device 31a, clamps the first image signal Ya (t) and supplies it to the selection circuit 36, and the second clamp circuit 35b The second image signal Yb (t) is clamped and supplied to the selection circuit 36, corresponding to the second CCD solid-state imaging device 31b. The first and second clamp circuits 35a and 35b have the same clamp level, and the black levels of the first and second image signals Ya (t) and Yb (t) are set to the same voltage. Output is made after fixing the level.

  The selection circuit 36 includes two input terminals 36a and 36b and one output terminal 36c, and the first and second image signals Ya () output from the first and second clamp circuits 35a and 35b. t) and Yb (t) are taken in, one of these signals is selected and output as an image signal Y (t). The selection circuit 36 operates in accordance with the timing signal supplied from the timing control circuit 34, and the input terminal 36a and the output terminal in a period during which the first image signal Ya (t) is output from the first CCD solid-state imaging device 31a. 36c is connected, and the input terminal 36b and the output terminal 36c are connected during a period in which the second image signal Yb (t) is output from the second CCD solid-state imaging device 31b. That is, the selection circuit 36 selectively captures and outputs two series of image signals output in a time-sharing manner from the first and second CCD solid-state imaging devices 31a and 31b according to their output timings. On the output side, it is synthesized into one series of image signals.

  The analog signal processing circuit 37 takes in the image signal Y (t) output from the selection circuit 36, performs signal processing such as CDS and AGC, and outputs the image signal Y ′ (t). The A / D conversion circuit 38 converts the image signal Y ′ (t) subjected to the analog signal processing into a digital signal and outputs it as image data Y (n). The digital signal processing circuit 39 performs processing such as color separation and matrix calculation on the image data Y (n) to generate image data including luminance data and color difference data. Further, the digital signal processing circuit 39 includes an exposure control circuit, a white balance control circuit, and an integration circuit. The digital signal processing circuit 39 integrates image data in units of a predetermined period, and performs exposure control and white balance correction based on the integration value. I do. In the analog signal processing circuit 37, the A / D conversion circuit 38, and the digital signal processing circuit 39, the first and second image signals Ya (t) and Yb (t) are controlled by the timing control circuit 34, respectively. Signal processing is performed separately in time division.

  As described above, the first and second CCD driver circuits 33a and 33b and the first and second clamp circuits 35a and 35b are individually provided for the first and second CCD solid-state imaging devices 31a and 31b. By sharing the analog signal processing circuit 37, the A / D conversion circuit 38, and the digital signal processing circuit 39, it is possible to reduce the circuit scale as an imaging apparatus while preventing functional degradation. That is, the output timings of the first and second image signals are set in time division while simultaneously driving the two CCD solid-state imaging devices 31a and 31b, and the selection circuit 36 is operated in accordance with the output timing to The switching operation of two image signals is performed efficiently. By sharing the analog signal processing circuit 37, the A / D conversion circuit 38, and the digital signal processing circuit 39 after the selection circuit 36, it is possible to effectively reduce the circuit scale as the imaging apparatus. Further, the timing control circuit 34 is provided in common for the first and second CCD solid-state image pickup devices 31a and 31b, thereby further reducing the circuit scale.

In the image pickup apparatus of the present invention, two clamp circuits 35a and 35b are individually provided for the two CCD solid-state image pickup devices 31a and 31b. For this reason, even if a level difference occurs between the black levels of the first and second image signals Ya (t) and Yb (t) due to manufacturing variations of the two CCD solid-state imaging devices 31a and 31b, the level difference is reduced. After correction, it can be supplied to the selection circuit 36. Thereby, it is possible to suppress variations in contrast between the two captured images obtained from the two CCD solid-state imaging devices 31a and 31b, and to prevent the two captured images from being different in image quality.

  FIG. 4 is a timing chart for explaining the operation of FIG. Here, among the plurality of display modes shown in FIG. 3, the first captured image A is mainly displayed, and the second captured image B is displayed in the lower left quarter region (FIG. 3A). ) As an example. In the following description, it is assumed that the imaging units of the first and second CCD solid-state imaging devices 31a and 31b are configured with 12 lines.

  At timings t0 to t1, the first frame transfer clock φa (f) and the first vertical transfer clock φa (v) are clocked within the blanking period of the vertical synchronization signal VD, so that the first CCD solid-state imaging device is used. Information charges for one screen accumulated in the imaging unit 31a are transferred and output to the accumulation unit. At subsequent timings t1 to t2, the second frame transfer clock φb (f) and the second vertical transfer clock φb (v) are clocked and stored in the imaging unit of the second CCD solid-state imaging device 31b. Information charges for the screen are transferred and output to the storage unit. Here, the reason why the frame shift timing is shifted between the first CCD solid-state image sensor 31a and the second CCD solid-state image sensor 31b is to reduce the peak value of the inrush current at the start of the frame shift. That is, in the frame shift, the information charges accumulated in the imaging unit are transferred and output to the accumulation unit at a high speed, and therefore an excessive inrush current flows at the start of the frame shift. Therefore, the peak value of the inrush current is kept low by not starting the frame shift simultaneously with the two CCD solid-state imaging devices.

  Subsequently, at the timing t3, the first vertical transfer clock φa (v) starts to be clocked at a timing synchronized with the horizontal synchronization signal HD, and is output for one screen output to the storage unit of the first CCD solid-state imaging device 31a. Are sequentially transferred to the horizontal transfer unit in units of one line, and the information charges output to the horizontal transfer unit are sequentially output as the image signal Ya (t). This continues until timing t5, and image signals for 6 lines corresponding to the upper half area for one screen are output. During this period, power supply to the second CCD driver circuit 33b is stopped, and the second vertical transfer clock φb (v) is fixed at a low level. As a result, the second image signal Yb (t) is not output from the second CCD solid-state imaging device 31b.

  At timing t4, the first substrate clock φa (b) is raised, and the information charges accumulated in the imaging unit of the first CCD solid-state imaging device 31a are discharged to the substrate side. Information charges are accumulated in the imaging unit during a period La until the next frame shift timing. Further, at timing t6, the second substrate clock φb (b) is raised, and information charges are accumulated in the imaging unit of the second CCD solid-state imaging device 31b in the period Lb until the next frame shift timing.

When the output of the image signals for six lines from the first CCD solid-state imaging device 31a is completed at the timing t5, the cycle of the first vertical transfer clock φa (v) is changed to twice, and the first cycle is the same cycle. Clocking of two vertical transfer clocks φb (v) is started. The first and second vertical transfer clocks φa (v) and φb (v) are clocked over timings t5 to t7, and the second image signal Yb (b) is output from the first CCD solid-state imaging device 31a. The In this period, as shown in FIG. 4, the first and second vertical transfer clocks φa (v) and φb (v) are set to rise alternately. As a result, the first and second CCD solid-state imaging The first and second image signals Ya (t) and Yb (t) are alternately output from the elements 31a and 31b in units of one line. At this time, since the display area of the second image signal Yb (t) is set to a half area in the vertical direction, one screen composed of 12 lines is thinned out every other line. Output in 6 lines. In addition, at timings t5 to t7, in response to the output timings of the first and second image signals Ya (t) and Yb (t), the selection circuit 36 selectively extracts each image signal, and the image Output as signal Y (t). In this way, the output timing of the first and second image signals Y (t) is controlled, and the selection circuit 36 is operated in accordance with the output timing, so that the image signals are in the order according to the designated display mode. Can be taken out.

  FIG. 5 shows the first and second image signals Ya (t) and Yb (t) output from the first and second CCD solid-state imaging devices 31a and 31b at the timing shown in FIG. FIG. 4 is a timing chart showing a state of an output image signal Y (t) and image data D (n) output from a digital signal processing circuit 39.

  As described with reference to FIG. 4, the first image signal Ya (t) is sequentially output in units of one line up to the sixth line. Thereafter, from the seventh line, the second image signal Yb (t) is alternately output at different timing. Output of the second image signal Yb (t) is started after the output of the first image signal Ya (t) for six lines is completed.

  In the image signal Y (t) output from the selection circuit 36, the first line is the 6th line of the first image signal Ya (t) up to the 6th line, and the 7th and subsequent lines are the first image signal Ya (t) and the 1st line. Two image signals Yb (t) are alternately assigned in units of one line. That is, in the period until the first image signal Ya (t) is output up to the sixth line, the selection circuit 36 selects the first CCD solid-state imaging device 31a side, and the first image signal Ya (t ) Up to the sixth line are selected as they are and output as an image signal Y (t). In the subsequent period, the selection circuit 36 alternately selects the first CCD solid-state image sensor 31a side and the second CCD solid-state image sensor 31b side, and the first line of the second image signal Yb (t) is selected. The first and second image signals include the signal of the seventh line of the first image signal Ya (t) following the signal, the signal of the third line of the second image signal Yb (t), and so on. Ya (t) and Yb (t) are alternately assigned and output as an image signal Y (t). As a result, after the seventh line of the image signal Y (t), the first image signal Ya (t) and the second image signal Yb (t) are substantially combined.

  The image data D (n) output from the digital signal processing circuit 39 is sequentially subjected to signal processing up to the sixth line of the image signal Y (t) corresponding to the sixth line of the first image signal Ya (t). Applied and output. From the seventh line onward, image data corresponding to one line of the second image signal Yb (t) is compressed into half the data of one line by the compression circuit built in the digital signal processing circuit 39. In addition to this, for the seventh and subsequent lines, the first half of one line that does not fall within the display area is removed from the image data corresponding to one line of the first image signal Ya (t). Then, the compressed image data and the data obtained by taking out only the second half of one line are combined into image data D (n) for one line. For example, the data of the seventh line of the image data D (n) includes the first image and data obtained by compressing the image data generated from the first line of the second image signal Yb (t) to half of one line. The second half of one line of the image data generated from the seventh line of the signal Ya (t) is synthesized and generated. As a result, on the display screen, the second captured image captured by the second CCD solid-state image sensor 31b in the lower left quarter region of the first captured image A captured by the first CCD solid-state image sensor 31a. B is reduced and two captured images are displayed simultaneously.

In this way, by switching the output of the first image signal Ya (t) and the second image signal Yb (t) and performing compression processing and synthesis processing according to the output, the reproduced image on the display screen is displayed. The display form can be switched. In other words, by controlling the output of the first and second image signals Ya (t) and Yb (t) in accordance with the respective display areas, the designated display mode can be used without using a frame memory. It is possible to generate image data according to the above. For example, as shown in FIG. 3B, in order to display the first and second captured images A and B in each of the regions divided in half in the vertical direction of the display screen, the first and second The first and second CCDs 31a and 31b may be driven so as to alternately output the image signals Ya (t) and Yb (t). Further, when only one of the first photographed image A or the second photographed image B is displayed as shown in FIGS. 3C and 3D, the display is adjusted to the desired image. Any one of the first CCD solid-state image pickup device 31a or the second CCD solid-state image pickup device 31b may be driven.

  FIG. 6 is a block diagram showing the configuration of the digital signal processing circuit 39. The digital signal processing circuit 39 includes a line memory 41, first and second integrating circuits 42 and 43, an exposure control circuit 44, an RGB process circuit 45, third and fourth integrating circuits 46 and 47, and a white balance control circuit 48. Consists of.

  The line memory 41 stores an appropriate number of lines of image data Y (n) output from the A / D conversion circuit 38 in units of one line, and holds the image data Y (n) in one horizontal scanning period, and then the first and second integration circuits 42. , 43. The first and second integration circuits 42 take in the image data Y (n) output from the line memory 41 and integrate, for example, in a period corresponding to the central area of one screen. The first and second integration circuits 42 and 43 operate in response to the first and second integration control signals W1 and W2 supplied from the timing control circuit 34, and these first and second integration control signals. The integration period is controlled by W1 and W2. The first and second integration control signals W1 and W2 are generated according to the output timing or the output order of the first and second image signals Ya (t) and Yb (t). For example, the line memory 41 When the data output from the first image signal Ya (t) is generated, as shown in FIG. 7, the first integration control signal W1 corresponds to the period during which the data is output. Launched to a high level. As a result, in the first integration circuit 42 that receives the first integration control signal W1, the integration processing of the image data generated from the first image signal Ya (t) is performed. Conversely, when the data output from the line memory 41 is data generated from the second image signal Yb (t), the second integration control signal W2 is high corresponding to the period during which the data is output. The second integration circuit 43 integrates the image data generated from the second image signal Yb (t). That is, the first and second integration circuits 42 and 43 correspond to the first and second image signals Ya (t) and Yb (t), respectively, and the first image signal Ya (t) The integration of the corresponding image data and the integration of the image data corresponding to the second image signal Yb (t) can be performed independently.

The exposure control circuit 44 is disposed in common with respect to the first and second integration circuits 42 and 43, and the first and second CCD solid-state imaging devices 31a are based on outputs from the two integration circuits 42 and 43. , 31b are controlled in a time-sharing manner independently of each other. That is, the storage time of the first CCD 31a is controlled to expand / contract based on the integration data output from the first integration circuit 42, and the second CCD solid-state image pickup is performed based on the integration data output from the second integration circuit 43. The accumulation time of the element 31b is controlled to expand and contract. For example, when controlling the exposure state of the first CCD solid-state image sensor 31a, if the integral value of the image data generated from the first image signal Ya (t) becomes larger than the appropriate range, the first CCD solid-state image sensor 31a. An instruction is given to the timing control circuit 33 so as to shorten the accumulation time of 31a. On the contrary, when the integrated value becomes smaller than the appropriate range, an instruction is given to extend the accumulation time, and feedback control is performed so that the exposure state of the first CCD solid-state imaging device 31a is always appropriate.

The RGB process circuit 45 performs processing such as color separation and matrix calculation on the image data Y (n) to generate image data D (n) including luminance data and color difference data. For example, in the color separation process, the image data Y (n) is distributed according to the color arrangement of the color filters attached to the imaging units of the first and second CCDs 31a, 31b, and a plurality of color component data R (n), G (n) and B (n) are generated. Further, in the matrix calculation process, luminance data is generated by combining the distributed color component data, and color difference data is generated by subtracting the luminance data from the color component data. In addition, the RGB process circuit 45 includes a compression circuit and a synthesis circuit, and performs compression processing on specific image data as necessary, as well as image data obtained from the first CCD solid-state imaging device 31a and the second image data. The image data obtained from the CCD solid-state imaging device 31b is synthesized.

  The third and fourth integration circuits 46 and 47 take in the color component data R (n), G (n), and B (n) output from the RGB process circuit 45, for example, from one screen unit to several screen units. To integrate for each color component data. The third and fourth integration circuits 46 and 47 generate the third and the second image signals corresponding to the output timing or the output order of the first and second image signals Ya (t) and Yb (t). 4 integration control signals W3 and W4, and the integration of the color component data R (n), G (n) and B (n) generated from the first image signal Ya (t) and the second Integration of the color component data R (n), G (n), and B (n) generated from the image signal Yb (t) is performed independently.

  The white balance control circuit 48 is arranged in common with respect to the third and fourth integration circuits 46 and 47, and the first and second images are based on the integration data output from the two integration circuits 46 and 47. The white balance correction of the image data generated from the signals Ya (t) and Yb (t) is performed independently by time division. In this white balance correction, for example, when correcting the white balance of the image data generated from the first image signal Ya (t), the color component data R (n) output from the third integrating circuit 46 is used. , G (n), and B (n) are compared, and the color component signals R (n) and B (n) are multiplied by specific coefficients so that these integrated values match.

  Thus, a plurality of integration circuits are provided corresponding to the first and second image signals Ya (t) and Yb (t), respectively, and the first and second image signals Ya (t) and Yb (t ), The integration processing of the image data generated from the first and second image signals Ya (t) and Yb (t) is performed independently. Can do. Furthermore, since the exposure control circuit 44 or the white balance control circuit 48 is provided in common for these integration circuits, the increase in the circuit scale of the digital signal processing circuit 39 is minimized. .

  In the first embodiment, since the timing control circuit 34 is common to the first and second CCD solid-state image sensors, the driving conditions of the two CCD solid-state image sensors are set equal. These two CCD solid-state imaging devices do not have to have exactly the same configuration. For example, if the drive conditions are the same, a CCD solid-state image sensor for color imaging or monochrome imaging may be used in combination, or a CCD solid-state image sensor having a different device structure may be used. However, when a CCD solid-state imaging device for color imaging and monochrome imaging is used in combination, a signal processing circuit that can handle both color imaging and monochrome imaging is applied.

  Subsequently, a second embodiment of the present invention will be described. FIG. 8 is a block diagram showing a second embodiment of the present invention. The second embodiment is different from the first embodiment in that a timing control circuit is provided for each of the first and second CCD solid-state imaging devices 31a and 31b.

The first and second timing control circuits 50a and 50b are provided separately for the first and second CCD solid-state imaging devices 31a and 31b, and operate independently. The first and second timing control circuits 50a and 50b are circuits having the same configuration, and are configured to include a counter that counts a reference clock CK having a fixed period and a decoder that decodes the output of the counter. First and second timing control circuits 50a,
In 50b, a plurality of various timing signals can be generated by changing the setting value of the decoder.

In such a configuration, for example, when driving the first CCD solid-state imaging device 31a, the timing signal generated by the first timing control circuit 50a is supplied to the first CCD driver circuit 31a, and this timing signal The first frame transfer clock φa (f), the first vertical transfer clock φa (v), the first horizontal transfer clock φa (h), and the first reset clock φa (r) are generated based on the above. Then, the first CCD solid-state imaging device 31a is driven, and the first image signal Y (t) is taken into the first clamp circuit 5a. At this time, the second timing control circuit 50b stops outputting the timing signal, thereby stopping the driving of the second CCD driver circuit 32b and the second CCD solid-state imaging device 31b.

  In this way, by separately providing a timing control circuit in association with each of the first and second CCD solid-state imaging devices 31a and 31b, separate clock pulses are generated in accordance with the specifications of each CCD solid-state imaging device. It becomes possible. Therefore, even if the first and second CCD solid-state imaging devices 31a and 31b are solid-state imaging devices that operate with clock pulses having different frequencies, the same operation as in the first embodiment can be performed. In the second embodiment, the first and second booster circuits 33a and 33b are provided corresponding to the first and second CCD solid-state imaging devices 31a and 31b, respectively. Even if the operating voltages of the solid-state imaging devices are different, there is no problem and the two CCD solid-state imaging devices can be efficiently operated. The operation control of the analog signal processing circuit 37, the digital signal processing circuit 39, and the like is performed by a timing signal from the timing control circuit in operation.

  Subsequently, a third embodiment of the present invention will be described. FIG. 9 is a block diagram showing the configuration of the third embodiment of the present invention. The third embodiment is different from the first embodiment in that first and second timing control circuits 50a and 50b similar to those of the second embodiment are provided, and then the first CCD solid-state imaging. The booster circuit 61 is shared by the element 31a and the second CCD solid-state image pickup element 31b, and the selection circuit 62 is arranged in front of the clamp circuit 35 to unify the signal processing series after the clamp circuit 35. There is.

  The booster circuit 61 includes a booster 61a and an output selector 61b. The booster 61a boosts an input power supply voltage to generate a boosted voltage, and the output selector 61b supplies an output to the booster 61b. Are switched in accordance with the operation timing of the first CCD solid-state imaging device 31a and the second CCD solid-state imaging device 33a. When driving the first CCD solid-state image sensor 31a, the booster circuit 61 outputs the boosted voltage generated by the booster 61a to the first CCD solid-state image sensor 31a and the first CCD driver circuit 32a. When driving the second CCD solid-state imaging device 31b, the boosted voltage is output to the second CCD solid-state imaging device 33a and the second CCD driver circuit 32b. The switching operation by the output selection unit 61b is performed in synchronization with the switching operation of the first and second CCD solid-state imaging devices 31a and 31b.

  The selection circuit 62 includes first and second transistors 62a and 62b and a resistance element 62c. The first and second transistors 62a and 62b are provided corresponding to the first CCD solid-state imaging device 31a and the second CCD solid-state imaging device 31b, respectively, and a resistance element 62c is provided between the power supply voltage VD and the ground point. Connected in series. The first and second transistors 62a and 62b are composed of, for example, bipolar transistors, and receive the outputs of the first and second CCD solid-state imaging devices 31a and 31b at the base terminals, respectively. Therefore, the selection circuit 62 impedance-converts the image signal from the active CCD solid-state image sensor among the first and second CCD solid-state image sensors 31a and 31b, and supplies the image signal Y ( Output as t).

  In such a configuration, for example, when driving the first CCD solid-state imaging device 31a, the timing signal generated by the first timing control circuit 60a is supplied to the first CCD driver circuit 32a and output. The selector 61b selects the first CCD driver circuit 32a side, and the boosted voltage is supplied to the first CCD driver circuit 32a. As a result, the first CCD solid-state imaging device 31 a is driven, and the first image signal Ya (t) is taken into the first transistor 62 a in the selection circuit 62. Then, the first transistor 62a is activated, and the first image signal Ya (t) is output as the image signal Y (t).

  According to the third embodiment, since the booster circuit 51 is common, there is a restriction that the two CCD solid-state imaging devices cannot be driven simultaneously. The circuit configuration can be simplified as compared with the embodiment, and the system scale can be greatly reduced compared to the conventional configuration. In the third embodiment, since only one booster circuit is operated for driving two CCD solid-state imaging devices, it is possible to reduce power consumption and to perform imaging driven by a battery. This is particularly effective for the device.

  The present invention has been described above by exemplifying the first to third embodiments. According to the imaging apparatus of the present invention, it is possible to reduce the system scale while enabling efficient operation. Further, as in the second and third embodiments, by providing a timing control circuit corresponding to each CCD solid-state image sensor, even a CCD solid-state image sensor having different driving conditions can be operated efficiently. And a reduction in system scale can be achieved. Such an imaging apparatus is highly versatile, and can be applied to various applications by selectively adopting each embodiment. Below, an example of the application form is demonstrated.

  In general, a CCD solid-state imaging device used in a surveillance camera system is desired to have both a very wide dynamic range and high light receiving sensitivity. In order to realize this with a single CCD solid-state imaging device, a dark place such as a nighttime is required. In addition to adopting a CCD solid-state imaging device and infrared illumination with high light receiving sensitivity in accordance with imaging at, the infrared cut filter is set on the light receiving surface side of the CCD in accordance with imaging in bright places such as daytime. Conceivable. In addition to these configurations, a mechanism for controlling infrared illumination, opening / closing control of an infrared cut filter, and the like is required, and the mechanism as a whole system becomes complicated. For this reason, although the number of the CCD solid-state imaging device is one, as a result, the scale of the camera system increases and the cost increases.

  Therefore, among the first and second CCD solid-state imaging devices, the second CCD solid-state imaging device is set as a solid-state imaging device having high infrared sensitivity, and the first CCD solid-state imaging device has infrared sensitivity higher than that. Set to a low, general solid-state image sensor. In imaging in a bright place such as daytime, only the first CCD solid-state imaging device is driven. Conversely, in imaging in a dark place such as nighttime, only the second CCD solid-state imaging device is driven. At this time, it is desirable that the switching of the driving of the first and second CCD solid-state imaging devices is automatically performed according to the illuminance of the subject. That is, the exposure can be performed using the illuminance measured by the photometric sensor or the integral value of the image signal calculated by the signal processing circuit.

  If the present invention is applied as described above, two CCD solid-state image pickup devices and CCD driver circuits are arranged as compared with the case of one CCD solid-state image pickup device. A mechanism for controlling these becomes unnecessary. For this reason, the system scale can be substantially reduced, and the cost can be reduced accordingly. In addition, since two CCD solid-state imaging devices are arranged, it is possible to separately set lenses suitable for the respective imaging conditions for each solid-state imaging device.

  Next, another application form will be described. 2. Description of the Related Art Conventionally, some mobile devices such as mobile phones have a built-in camera function and can be used as a simple digital camera at the destination. Such mobile phones often include a function capable of transmitting an image captured at a destination through an Internet line. To use this function, a user can use an operation key of the mobile phone. It is necessary to enter an address that specifies the destination of the image. In recent years, it has been considered to incorporate a function of displaying an address as a barcode and reading the barcode with a sensor to complete the address input collectively in order to eliminate the troublesomeness of inputting an address.

  Therefore, a CCD solid-state image sensor having a larger number of light receiving pixels than the first CCD solid-state image sensor is applied to the second CCD solid-state image sensor. In the case of image recognition such as barcode reading, which generally requires a high resolution, the second CCD solid-state imaging device having a high resolution is driven. On the other hand, when performing normal imaging, the first CCD A solid-state image sensor is driven. Such a configuration can be applied not only to the barcode reading function but also to the case where, for example, a fingerprint sensor for security and normal imaging are compatible.

  Here, the monitoring camera system, the barcode reading system, and the fingerprint sensor system described above are a part of application forms of the present invention. That is, the present invention is sufficiently applicable when a plurality of images having different imaging conditions are compatible with one system.

  In the above embodiment, the case where the first and second CCD solid-state imaging devices are frame transfer types has been described as an example. However, the present invention is not limited to this, and information for one screen is used. It is also suitable for an image pickup apparatus using a frame interline type solid-state image pickup device including a storage unit capable of temporarily holding electric charges.

  Further, in the exposure control and white balance control of digital signal processing, a configuration in which a plurality of integration circuits are provided in association with two CCD solid-state imaging devices is illustrated, but the present invention is not limited to this. For example, in the case of frequently switching the operation of two CCD solid-state image pickup devices, such as alternately driving the first and second CCD solid-state image pickup devices in units of one line or one screen, an integration circuit is provided for each CCD solid-state image pickup. It is desirable to provide them separately in association with the elements. However, when switching the operation of two CCD solid-state image sensors in units of a plurality of screens, the integration circuit may be shared by the two CCD solid-state image sensors.

  According to the present invention, the output timing of the image signals from the two CCD solid-state imaging devices is set in time division, and the selection circuit is operated in accordance with the output timing. As a result, the switching operation of the two image signals can be performed efficiently, and the adverse effect of functional degradation can be prevented. Furthermore, by arranging the selection circuit in the preceding stage of the signal processing circuit and sharing the subsequent circuits, it is possible to reduce the circuit scale as the imaging device to the maximum.

1 is a block diagram illustrating a configuration of a first embodiment of an imaging apparatus according to the present invention. It is a top view which shows the structure of a solid-state image sensor. It is a schematic diagram which shows an example of a display mode. FIG. 2 is a timing chart for explaining the operation of FIG. 1. FIG. 6 is a timing chart showing states of first and second image signals Ya (t), Yb (t), image signal Y (t), and image data D (n). It is a block diagram which shows the structure of a digital signal processing circuit. It is a timing diagram explaining the 1st and 2nd integral control signal. It is a block diagram which shows the structure of 2nd Embodiment of this invention. It is a block diagram which shows the structure of 3rd Embodiment of this invention. It is a block diagram which shows the structure of the conventional imaging device. It is a schematic diagram which shows an example of a display mode.

Explanation of symbols

1a, 31a: first CCD solid-state imaging device 1b, 31b: second CCD solid-state imaging device 2a, 32a: first boosting circuit 2b, 33b: second boosting circuit 3a, 33a: first CCD driver circuit 3b, 33b: second CCD driver circuit 4a: first timing control circuit 4b: second timing control circuit 5a: first analog signal processing circuit 5b: second analog signal processing circuit 6a: first A / D converter 6b: second A / D converter 7a: first digital signal processing circuit 7b: second digital signal processing circuit 8a: first memory 8b: second memory 9: memory controller 34: Timing control circuit 35a: first clamp circuit 35b: second clamp circuit 36: selection circuit 37: analog signal processing circuit 38: A / D conversion circuit 39: digital signal processing circuit 4 : Line memory 42: first integration circuit 43: second integration circuit 44: exposure control circuit 45: RGB process circuit 46: third integration circuit 47: fourth integration circuit 48: white balance control circuit 50a: first 1 timing control circuit 50b: second timing control circuit 61: boosting circuit 61a: boosting unit 61b: output selecting unit

Claims (7)

A plurality of light receiving pixels arranged in a matrix, and a first solid-state imaging device that accumulates information charges generated in response to the first subject image in each light receiving pixel;
A plurality of light receiving pixels arranged in a matrix, and a second solid-state imaging device that accumulates information charges generated in response to the second subject image in each light receiving pixel;
A first drive circuit that transfers and outputs information charges accumulated in each light receiving pixel of the first solid-state imaging device to obtain a first image signal;
A second drive circuit for transferring and outputting information charges accumulated in each light receiving pixel of the second solid-state imaging device to obtain a second image signal;
A first timing control circuit for determining a timing of vertical scanning and horizontal scanning of the first solid-state imaging device based on a reference clock having a fixed period;
A second timing control circuit for determining a timing of vertical scanning and horizontal scanning of the second solid-state imaging device based on the reference clock;
When the first timing control circuit drives the first solid-state imaging device by taking in the first image signal and the second image signal, the first image signal is selectively output; A selection circuit that selectively outputs the second image signal when the second timing control circuit drives the second solid-state imaging device;
A clamp circuit for clamping and outputting the output of the selection circuit;
A signal processing circuit that receives the output from the clamp circuit and generates a predetermined image signal;
An imaging apparatus comprising: The imaging device according to claim 1,
A boost circuit that boosts an input voltage to generate a boost voltage;
The booster circuit includes a booster that generates the boosted voltage, and the boosted voltage is applied to one of the first and second drive circuits in synchronization with the operation timing of the first and second solid-state imaging devices. An image pickup apparatus comprising: an output selection unit that selectively outputs. The imaging device according to claim 1,
The signal processing circuit takes in the first and second image signals, respectively, and integrates them in units of a predetermined period; and
An image pickup apparatus comprising: an exposure control circuit that independently controls exposure states of the first and second solid-state image pickup devices based on outputs of the first and second integration circuits, respectively. . The imaging device according to claim 3 .
The signal processing circuit captures the first and second image signals, respectively, and integrates them in a predetermined period unit;
And a white balance control circuit that independently corrects the white balance of the first and second image signals based on the outputs of the third and fourth integration circuits, respectively. apparatus. The imaging device according to claim 1,
The first and second solid-state imaging devices have different driving conditions from each other. The imaging apparatus according to claim 5 ,
The second solid-state imaging device is set to have an infrared sensitivity higher than that of the first solid-state imaging device. The imaging apparatus according to claim 5 ,
The imaging device, wherein the first and second solid-state imaging devices have different numbers of light receiving pixels.

Images