JP4410095B2 - Semiconductor memory - Google Patents

Description

  The present invention relates to a semiconductor memory having a cell unit composed of a storage element and a selection element, and in particular, a magnetic random access memory (MRAM), a phase change memory (OUM), a ferroelectric memory. Used for non-volatile memory based on new principles such as (FeRAM: ferroelectric random access memory).

  In recent years, non-volatile memories based on new principles such as a magnetic random access memory that uses the magnetoresistive effect, a PRAM that uses a resistance change due to phase transition (also known as OUM), and a ferroelectric memory that uses the spontaneous polarization of a ferroelectric have been developed. Many have been proposed.

  For example, in a magnetic random access memory, a magneto-resistive (MR) element composed of two ferromagnetic layers and an insulating layer (tunnel barrier) between them is used as a memory element, and two ferromagnetic layers are formed. Data is stored according to the direction of magnetization. The case where the magnetization directions of the two ferromagnetic layers are the same is defined as a parallel state (low resistance state), which corresponds to “0”, while the opposite case is defined as an antiparallel state (high resistance state). This is made to correspond to “1”.

  In the phase change memory, for example, a chalcogenide semiconductor is used as a storage element. Since the chalcogenide semiconductor is capable of phase transition between two states, crystalline and amorphous, data “0” and “1” can be stored using the fact that the resistance values of both states are different. It becomes possible.

  All of these memories have common development issues such as large capacity (small area), high speed, high S / N ratio, and low power consumption.

  First, as an approach from the problem of increasing capacity (reducing area), a cross-point cell array structure has been studied. According to this structure, it is possible to realize a large capacity by miniaturizing the memory element by arranging the memory element at the intersection of the word line and the bit line without using the selection element.

  However, in this case, even if the storage capacity can be increased by miniaturizing the storage element, an extra current path called a sneak path is generated in addition to the original current path during reading. It becomes noise and causes a new problem of a decrease in sense performance.

  By the way, as a technique for reducing noise due to a sneak path, a proposal has been made to apply a bias voltage Vg to each of an unselected word line and an unselected bit line during a read operation. However, the sneak path is still completely eliminated. However, the read time is about two orders of magnitude longer than that of a cell array structure having a selection element (see, for example, Patent Documents 1 and 2).

  As described above, the cross-point type cell array structure that is most advantageous for increasing the capacity cannot solve the problems of high speed and high S / N ratio.

  Therefore, a cell array structure in which one selection element (for example, a MOS transistor) is connected to one storage element is adopted as an approach from the problem of speeding up and high S / N ratio. According to this structure, since read selectivity can be improved, high speed and high S / N ratio can be realized.

  However, in the current technology, the size of the selection element is several times larger than the size of the storage element, and when one selection element is associated with one storage element, it is inevitably required per cell. The area becomes large, and a large capacity (small area) cannot be realized.

As described above, in the cell array structure in which one selection element is connected to one storage element that is most advantageous for high speed and high S / N ratio, the problem of large capacity (small area) cannot be solved.
JP 2003-288777 A JP 2001-325791 A JP 2003-100071 A JP 2003-249629 A Japanese Patent No. 2616134

  The present invention proposes a cell layout for realizing high integration of memory elements in a semiconductor memory in which read selectivity is improved by a cell array structure having selection elements.

The semiconductor memory according to the example of the present invention, the pitch Px in the row direction, at a pitch Py in the column direction, a plurality of storage elements arranged in rows and columns, is placed immediately below the plurality of storage elements, the row direction A plurality of selection elements having a size Lx of n × Px and a column direction size Ly of m × Py, and a plurality of first conductive layers that connect one end of the X storage elements arranged in the row direction to each other; The plurality of selection elements are arranged in m or more different layers, and the number of X storage elements is n + 1 or more.

The semiconductor memory according to the example of the present invention, the pitch Px in the row direction, at a pitch Py in the column direction, a plurality of storage elements arranged in rows and columns, is placed immediately below the plurality of storage elements, the row direction A plurality of selection elements having a size Lx of n × Px and a column direction size Ly of m × Py, and a plurality of first conductive layers that connect one end of the X storage elements arranged in the row direction to each other; The plurality of selection elements are arranged in different layers of m + 1 stages or more, and the X memory elements are n (however, only when n ≧ m).

The semiconductor memory according to the example of the present invention, the pitch Px in the row direction, at a pitch Py in the column direction, a plurality of storage elements arranged in rows and columns, is placed immediately below the plurality of storage elements, the row direction A plurality of selection elements having a size Lx of n × Px and a column direction size Ly of m × Py, and a plurality of first conductive layers that connect one end of the X storage elements arranged in the row direction to each other; The plurality of selection elements are arranged in m or more different layers, and the X storage elements are n + m−1 or more.

  The pitch Px and the pitch Py have values when the plurality of storage elements are arranged closest in the same layer. The pitch Px and the pitch Py are determined by a minimum processing dimension determined by a lithography technique.

  Each of the plurality of first conductive layers is connected to one of the plurality of selection elements via a second conductive layer. The second conductive layer extends in the column direction.

  One of the pitch Px and the pitch Py may have a value larger than a value when the plurality of memory elements are arranged closest in the same layer.

  A semiconductor memory according to an example of the present invention includes a plurality of storage elements arranged in a matrix, a plurality of selection elements arranged in a plurality of stages immediately below the plurality of storage elements, and arranged in the row direction. And a plurality of conductive layers that connect one ends of the plurality of storage elements to each other, and each of the plurality of conductive layers is connected to one of the plurality of selection elements disposed immediately below the plurality of conductive layers.

  The plurality of storage elements are arranged in the same layer at a pitch that is looser than the closest density determined by the lithography technique.

  Of the plurality of selection elements, the size of the contact plug connected to the selection element at the uppermost stage is smaller than the size of the contact plug connected to the selection element at a stage other than the uppermost stage.

  The plurality of storage elements are magnetoresistive elements. The magnetoresistive effect element has, for example, a rectangular shape, and the short side has a length of 0.15 μm or less. The memory element may be a phase change element using a phase transition between crystalline and amorphous, or a ferroelectric element.

  According to the example of the present invention, high integration of memory elements can be realized with a novel cell layout in a semiconductor memory in which read selectivity is improved by a cell array structure having selection elements.

  The best mode for carrying out an example of the present invention will be described below in detail with reference to the drawings.

1. Overview
(1) Target
An example of the present invention is directed to a semiconductor memory in which a memory cell array is configured by a cell unit including a storage element (for example, a magnetoresistive effect element) and a selection element (for example, a MOS transistor).

  In a semiconductor memory having such a cell array structure, a selection element must be arranged in the memory cell array. Therefore, in principle, it is difficult to realize a large capacity equivalent to that of a cross-point cell array structure. .

  Therefore, in the example of the present invention, a novel cell layout is proposed that can realize a large capacity (dense packing) comparable to that of a cross-point cell array structure even in a cell array structure having such a selection element. .

  First, a memory element is considered.

  In the case of a dynamic random access memory (DRAM) using a capacitor capacity, if the size of the storage element (capacitor) is reduced, the capacitor capacity is reduced, and the signal intensity required for reading cannot be obtained sufficiently. There is.

  On the other hand, in the case of new memories that have been attracting attention in recent years, for example, non-volatile memories such as magnetic random access memories and phase change memories, it is necessary to reduce the size of the storage element to reduce the signal strength required for reading. It does not have a big influence on.

  In particular, a magnetoresistive effect (MR) element, which is a storage element of a magnetic random access memory, conventionally has a problem that data cannot be retained due to the influence of a demagnetizing field when the size is reduced. It was solved by adopting the writing method by technology.

  On the contrary, according to this technology, if the size of the memory element is not small, the writing / reading effect by the electron spin cannot be exhibited. Therefore, in the magnetic random access memory, the memory element can be miniaturized at once.

  Next, the selection element will be considered.

  As described above, the size of the selection element is several times larger than the size of the storage element. For this reason, in a cell array structure in which one selection element is connected to one memory element, the size of the selection element becomes a bottleneck even if the memory element is miniaturized, and it is difficult to realize a large capacity.

  Here, in the dynamic random access memory, the size of the storage element (capacitor capacity) affects the signal intensity required for reading. For this reason, in order to miniaturize the memory cell, it is necessary to consider the size of the storage element in consideration of the signal intensity required for reading in addition to the size of the selection element.

  On the other hand, for example, in the case of a new memory such as a magnetic random access memory or a phase change memory, the size of the storage element does not affect the signal intensity required for reading. For this reason, when miniaturizing a memory cell, the size (layout) of the selection element should be mainly examined.

  Therefore, in such a new memory, examination of the layout of a selection element that can reduce the area per cell is an important issue.

(2) Examples and problems of cell array structure
FIG. 1 shows an example of such a cell array structure. FIG. 2 is a layout of storage elements and selection elements in one block of the cell array structure of FIG. FIG. 3 is a cross-sectional structure of the memory element and the selection element in FIG.

  The cell array structure is characterized in that one end of a plurality of memory elements 12 is connected in common and the connection point is connected to one selection element RSW.

  Specifically, one end of the four memory elements 12 arranged in the row direction is connected to each other by the conductive layer (metal plate) 17. Further, the contact plug 24 connects the conductive layer 17 to the drain 22D of the MOS transistor as the selection element RSW. Further, the four storage elements 12 are independently connected to the bit lines BL1, BL2, BL3, BL4.

  According to such a cell array structure, one end of the plurality of storage elements 12 is collectively connected to one selection element RSW arranged immediately below the large number of memory cell arrays while ensuring read selectivity. Capacity can be increased.

  However, as shown in FIGS. 4 and 5, there is a limit due to the size of the selection element RSW in increasing the capacity.

  That is, with respect to the row direction in which the word line WL1 extends, the memory elements 12 can be densely arranged within the range allowed by the minimum processing dimension (design rule) by the lithography technique, but the column direction in which the bit lines BL1, BL2, BL3, BL4 extend. As for the memory element 12, the memory elements 12 cannot be arranged densely.

  This is because, in this cell array structure, the plurality of storage elements 12 connected to one selection element RSW must be connected to the bit lines BL1, BL2, BL3, BL4, respectively.

  Therefore, if only the size of the storage element 12 is considered, as shown by the broken line, the storage elements 12 should be densely arranged in the column direction. However, in reality, most of the region immediately above the selection element RSW is useless space. Thus, the memory element 12 is not sufficiently integrated.

  In the example of the present invention, by proposing a new layout of the selection element RSW under such circumstances, the storage element 12 can be arranged in the wasted space on the selection element RSW. As a result, the capacity can be increased to the same level as the cross-point cell array structure.

(3) Concept of the example of the present invention
6 and 7 illustrate the concept of an example of the present invention.
In the example of the present invention, first, in order to realize the same cell density (dense packing) as the cross-point cell array structure, the memory elements 12 are regularly arranged with a pitch Px in the row direction and a pitch Py in the column direction. Assume an array of storage elements 12 arranged in a matrix.

  Then, a layout of the selection element RSW in the case where the selection element RSW in which the size Lx in the row direction is n × Px and the size Ly in the column direction is m × Py is arranged in the array of the storage elements 12 is proposed. .

  Here, as described above, the example of the present invention is a semiconductor memory in which a memory cell array is configured by cell units each including the storage element 12 and the selection element RSW. Therefore, here, it is assumed that X memory elements 12 are connected to one selection element RSW.

  Note that n, m, and X are all natural numbers (1, 2, 3,...).

  In the first example of the present invention, the number X of storage elements 12 connected to one selection element RSW is set to n + 1 or more. In this case, in order to properly contact the selection element RSW and the storage element 12, one end of the X storage elements 12 arranged in the row direction is connected to each other, and the selection element RSW is in different layers of m stages or more. Stack and form.

  In the second example of the present invention, the number X of storage elements 12 connected to one selection element RSW is n or more. In this case, in order to properly contact the selection element RSW and the storage element 12, one end of the X storage elements 12 arranged in the row direction is connected to each other, and the selection element RSW is in different layers of m + 1 stages or more. Stack and form. However, it is set as n> = m.

  Furthermore, in the third example of the present invention, the number X of storage elements 12 connected to one selection element RSW is set to n + m−1 or more. In this case, in order to properly contact the selection element RSW and the storage element 12, one end of the X storage elements 12 arranged in the row direction is connected to each other, and the selection element RSW is in different layers of m stages or more. Stack and form.

  The point to be noted here is that the example of the present invention is not merely a high integration by stacking a plurality of selection elements RSW larger than the storage element 12 on the semiconductor substrate 21 in a plurality of stages. . That is, it is clear that a problem arises in how to contact the memory element 12 and the selection element RSW by simply stacking the selection elements.

  In the example of the present invention, in order to maximize the effect of high integration, it is premised that the memory elements 12 are arranged at a cell density (closest density) similar to that of the cross-point cell array structure. .

  However, for example, when considering a reduction in wiring resistance, the example of the present invention can be applied to the case where the memory elements 12 are not closely arranged.

  Thus, the example of the present invention proposes a cell layout in consideration of how to contact the storage element 12 and the selection element RSW when the array of the storage elements 12 and the size of the selection element RSW are provided. .

  According to the example of the present invention, in a semiconductor memory in which read selectivity is improved by a cell array structure having a selection element, a storage element can be highly integrated to the same extent as a cross-point cell array structure.

  The direction in which the word line connected to the selection element RSW and the bit line connected to the storage element 12 extend is not particularly limited. For example, the conductive lines are arranged so that the word lines extend in the row direction and the bit lines extend in the column direction.

2 embodiment
Next, some preferred embodiments will be described.

  As described above, the example of the present invention can be applied to a semiconductor memory having a cell unit composed of a storage element and a selection transistor. Hereinafter, a magnetic random access memory will be described as a representative example.

  Further, in the following example, a magnetic random access memory adopting a writing method based on the most promising spin injection technology will be described, but the example of the present invention is a magnetic random access memory that performs magnetization reversal by a magnetic field by a write current. Of course it can also be applied.

(1) Cell array structure
First, the cell array structure of the magnetic random access memory by the spin injection writing method will be described.

  FIG. 8 shows a cell array structure of a magnetic random access memory based on the spin injection writing method.

  The memory cell array 11 includes a plurality of cell units (blocks) BK11-1,... BK11-k,... BKjn-1,. , 2,..., K = 1, 2,.

  Each of the cell units BK11-1, ... BK11-k, ... BKjn-1, ... BKjn-k has X storage elements (in this example, magnetoresistive effect elements) 12, and these X It is composed of one selection element (in this example, a MOS transistor) RSW connected to one end of each memory element 12. In this example, the number X of storage elements 12 in the cell units BK11-1,... BK11-k,... BKjn-1,.

  In this example, one group (unit block) is constituted by k cell units. In the region S occupied by the group of k cell units, k or more selection elements RSW are arranged stacked in Z (= k) stages or more.

  Word lines WL1,... WLj are connected to the gates of the MOS transistors as the selection elements RSW. Word lines WL1,... WLj extend in the row direction, and one end thereof is connected to the row decoder & word line driver 13A.

  The row decoder & word line driver 13A drives one word line selected based on the row address signal at the time of reading / writing.

  Source lines SL1,... SLn are connected to the source of the MOS transistor as the selection element RSW. The source lines SL1,... SLn extend in the column direction, and one end thereof is connected to the write driver / sinker 15A via a column selection switch (MOS transistor) CSW1.

  The write driver / sinker 15A serves as a supply source or an absorption source of a write current for executing writing by electron spin injection at the time of writing. At the time of reading, the write driver / sinker 15A sets the source lines SL1,... SLn to the ground potential VSS.

  The gate of the MOS transistor as the column selection switch CSW1 is connected to the column decoder & column selection line driver 14.

  The column decoder & column selection line driver 14 selects one source line through which a write current flows based on a column address signal at the time of writing. At the time of reading, the column decoder & column selection line driver 14 selects one source line based on the column address signal. The selected source line is set to the ground potential VSS by the write driver / sinker 15A.

  The memory elements 12 in the cell units BK11-1,... BK11-k,... BKjn-1,... BKjn-k are independently bit lines BL4 (n−1) +1, BL4 ( n-1) +2, BL4 (n-1) +3, BL4 (n-1) +4.

  The bit lines BL4 (n-1) +1, BL4 (n-1) +2, BL4 (n-1) +3, BL4 (n-1) +4 extend in the column direction, and one end thereof is a column selection switch (MOS transistor). ) It is connected to the write driver / sinker 15B and the read circuit (including the sense amplifier) 16 via the CSW2.

  The write driver / sinker 15B serves as a supply source or an absorption source of a write current for executing writing by electron spin injection at the time of writing. At the time of reading, the write driver / sinker 15B is in a non-operating state. Instead, the reading circuit 16 is in an operating state.

  The gate of the MOS transistor as the column selection switch CSW2 is connected to the column decoder 13B.

  The column decoder 13B selects one bit line through which a write current flows based on a column address signal at the time of writing. In reading, the column decoder 13B selects one bit line based on the column address signal. The selected bit line is electrically connected to the read circuit 16.

(2) First embodiment
A. Cell layout
FIG. 9 shows a cell layout of the magnetic random access memory according to the first embodiment. 10 is a cross-sectional view taken along line XX in FIG. 9, FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 9, and FIG. 12 is a cross-sectional view taken along line XII-XII in FIG.

  The memory elements are arranged in a matrix with a pitch Px in the row direction and a pitch Py in the column direction. For example, the pitch Px and the pitch Py have values when these storage elements are arranged in the same layer in the closest density, that is, at a cell density similar to that of the cross-point cell array structure. The pitch Px and the pitch Py are determined by a minimum processing dimension (design rule) determined by the lithography technique.

  The unit block is composed of 3 × 3 storage elements.

  One ends of the three storage elements m11, m12, and m13 in the row direction are connected to each other by a strip-shaped conductive layer (for example, a metal plate) ST1. The strip-shaped conductive layer ST1 is connected via a contact plug CP1 to a selection element (MOS transistor) Tr1 disposed immediately below.

  Further, one ends of the three storage elements m21, m22, and m23 in the row direction are connected to each other by a strip-shaped conductive layer (for example, a metal plate) ST2. The strip-shaped conductive layer ST2 is connected to a selection element (MOS transistor) Tr2 disposed immediately below the conductive layer (auxiliary strip) SST2 and the contact plug CP2.

  Furthermore, one ends of the three storage elements m31, m32, and m33 in the row direction are connected to each other by a strip-shaped conductive layer (for example, a metal plate) ST3. The strip-shaped conductive layer ST3 is connected to a selection element (MOS transistor) Tr3 disposed immediately below the conductive layer (auxiliary strip) SST3 and the contact plug CP3.

  The selection elements Tr1, Tr2, Tr3 are stacked in three stages corresponding to the number of strip-like conductive layers ST1, ST2, ST3 in the unit block.

  The sizes of the selection elements Tr1, Tr2, Tr3 are set to Px (row direction) × 3Py (column direction). As shown in FIG. 13, the selection elements Tr1, Tr2, and Tr3 are arranged with their positions shifted so as not to overlap each other.

  The gates of the MOS transistors as the selection elements Tr1, Tr2, Tr3 are word lines WL1, WL2, WL3.

  The conductive layers (auxiliary strips) SST2, SST3 extend in the column direction in order to make contact between the strip-shaped conductive layers ST2, ST3 and the selection elements Tr2, Tr3.

  According to such a cell layout, three memory elements can be connected to one selection element at a time with respect to all the memory elements even if the memory elements are arranged in the closest range within the range allowed by the lithography technique.

  Therefore, improvement in read selectivity and high integration equivalent to that of the cross-point type cell array structure can be realized.

B. Operation
Next, the operation of the magnetic random access memory shown in FIGS. 9 to 12 will be briefly described.

  Read operation: Consider the case of reading data from the storage element m22.

  First, the word line WL2 is driven to turn on the selection element Tr2. Further, the bit line BL2 is selected, and the bit line BL2 is connected to the reading circuit.

  At the time of reading, since the source lines SL1, SL2, and SL3 are set to the ground potential VSS, the reading current supplied from the reading circuit flows to the source line SL2 via the storage element m22.

  At this time, since the potential of the bit line BL2 changes according to the data (resistance value) of the memory element m22, if the potential change of the bit line BL2 is detected by a read circuit (sense amplifier), the data of the memory element m22 is read. be able to.

  Here, the selection elements Tr1 and Tr3 connected to the non-selected word lines WL1 and WL3 are in the off state.

  Accordingly, of the nine storage elements m11, m12, m13, m21, m22, m23, m31, m32, and m33 in the unit block, the memory element through which the read current flows is only m22, which is a problem in the cross-point cell array structure. Therefore, a high S / N ratio and high speed can be realized.

  As for reading, the data in the memory element may be read as a voltage value or a current value.

  The cell layout according to the example of the present invention is not affected by the reading method. As a reading method, for example, any method may be used as long as the resistance value of the memory element can be detected.

  Write Operation: The magnetic random access memory shown in FIGS. 9 to 12 is an example in the case of adopting a spin injection write method, and does not have a write line used only for writing.

  First, a memory element to be written is selected.

  When writing data to the storage element m22, the word line WL2 is driven to turn on the selection element Tr2. Then, the strip-like conductive layer ST2 on which the memory element m22 is mounted is connected to the first write driver / sinker. Further, the bit line BL2 is selected, and the bit line BL2 is connected to the second write driver / sinker.

  Here, it is assumed that the memory element m22 includes a pinned layer (filter layer), a tunnel barrier layer, and a free layer in this order from the strip-shaped conductive layer ST2 toward the bit line.

  In this case, when “0” is written to the memory element m22 (when the magnetization state is made parallel), a write current from the strip-shaped conductive layer ST2 to the bit line BL2 is supplied to the memory element m22. At this time, electrons having spins opposite to the magnetization direction of the pinned layer are reflected by the pinned layer, and only electrons having spins in the same direction pass through the free layer. As a result, the magnetization direction of the free layer is the same as the magnetization direction of the pinned layer.

  Further, when “1” is written to the memory element m22 (when the magnetization state is made antiparallel), a write current from the bit line BL2 toward the strip-shaped conductive layer ST2 is supplied to the memory element m22. At this time, among the electrons that have passed through the free layer, those having spins in the same direction as the magnetization direction of the pinned layer pass through the pinned layer as they are, and only electrons having the same direction of spin are reflected by the pinned layer. . As a result, the magnetization direction of the free layer is opposite to the magnetization direction of the pinned layer.

c. Summary
As can be seen from the above description of the operation, when the selected memory elements are the same, the read operation and the write operation are executed using the same word line and bit line. That is, the read current and the write current differ only in magnitude, and their current paths are the same.

  Therefore, in the case of a spin random write memory magnetic random access memory, a write line used only for the write operation is not required, so that the effect of the example of the present invention, that is, the high integration of the memory element becomes more remarkable.

d. Other
In the magnetic random access memory shown in FIGS. 9 to 12, when the memory element is a phase change type element (for example, a chalcogenide semiconductor), it can be used as a phase change memory.

  For example, when a long electric pulse is applied to the memory element using a word line and a bit line, the memory element is in a crystalline state, and when a short electric pulse is applied, the memory element is in an amorphous state. Thus, the value of the write data can be controlled only by adjusting the length of the electric pulse.

  Note that the direction of the write pulse is only one direction, unlike the magnetic random access memory of the spin injection write method.

  Further, in the magnetic random access memory of FIGS. 9 to 12, if a write line used only for the write operation is added, a normal magnetic field write type magnetic random access memory can be obtained.

(3) Second embodiment
The second embodiment is a modification of the first embodiment.

  In the first embodiment, for example, as shown in FIG. 14, the contact between the memory element and the selection element is ensured by using the strip-like conductor layers ST1, ST2, ST3 and the conductor layers (auxiliary strips) SST2, SST3. .

  However, the strip-shaped conductor layer ST1 is directly connected to the selection element Tr1 by the contact plug CP1, whereas the strip-shaped conductor layer ST2 is selected via the conductor layer (auxiliary strip) SST2 and the contact plug CP2. The strip-shaped conductor layer ST3 connected to the element Tr2 is connected to the selection element Tr2 via the conductor layer (auxiliary strip) SST3 and the contact plug CP3.

  Thus, there is a considerable difference in the length of the path connecting the storage element and the selection element for each storage element, and this difference also affects the wiring resistance.

  Therefore, in the second embodiment, a cell layout is proposed in which the wiring resistance from the storage element to the selection element is substantially equal for all the storage elements.

A. Cell layout
FIG. 15 shows a cell layout of the magnetic random access memory according to the second embodiment. 16 is a sectional view taken along line XVI-XVI in FIG. 15, FIG. 17 is a sectional view taken along line XVII-XVII in FIG. 15, and FIG. 18 is a sectional view taken along line XVIII-XVIII in FIG.

  The memory elements are arranged in a matrix with a pitch Px in the row direction and a pitch Py in the column direction. For example, the pitch Px and the pitch Py have values when these storage elements are arranged in the same layer in the closest density, that is, at a cell density similar to that of the cross-point cell array structure. The pitch Px and the pitch Py are determined by a minimum processing dimension (design rule) determined by the lithography technique.

  The unit block is composed of 3 × 3 storage elements.

  One ends of the three storage elements m11, m12, and m13 in the row direction are connected to each other by a strip-shaped conductive layer (for example, a metal plate) ST1. The strip-shaped conductive layer ST1 is connected to a selection element (MOS transistor) Tr1 disposed immediately below the conductive layer (auxiliary strip) SST1 and the contact plug CP1.

  Further, one ends of the three storage elements m21, m22, and m23 in the row direction are connected to each other by a strip-shaped conductive layer (for example, a metal plate) ST2. The strip-shaped conductive layer ST2 is connected via a contact plug CP2 to a selection element (MOS transistor) Tr2 arranged immediately below.

  Furthermore, one ends of the three storage elements m31, m32, and m33 in the row direction are connected to each other by a strip-shaped conductive layer (for example, a metal plate) ST3. The strip-shaped conductive layer ST3 is connected to a selection element (MOS transistor) Tr3 disposed immediately below the conductive layer (auxiliary strip) SST3 and the contact plug CP3.

  The selection elements Tr1, Tr2, Tr3 are stacked in three stages corresponding to the number of strip-like conductive layers ST1, ST2, ST3 in the unit block.

  The sizes of the selection elements Tr1, Tr2, Tr3 are set to Px (row direction) × 3Py (column direction). As shown in FIG. 19, the selection elements Tr1, Tr2, and Tr3 are arranged with their positions shifted so as not to overlap each other.

  In addition, the positions of the contact plugs CP1, CP2, and CP3 are devised in order to make the lengths of the paths connecting the storage element and the selection element substantially equal. Accordingly, the region where the selection elements Tr1, Tr2, Tr3 are arranged does not completely overlap with the unit block, and is shifted in the column direction by the pitch Py.

  The gates of the MOS transistors as the selection elements Tr1, Tr2, Tr3 are word lines WL1, WL2, WL3.

  The conductive layers (auxiliary strips) SST1, SST3 extend in the column direction in order to make contact between the strip-shaped conductive layers ST1, ST3 and the selection elements Tr1, Tr3.

  According to such a cell layout, three memory elements can be connected to one selection element at a time with respect to all the memory elements, even if the memory elements are arranged in the closest range within the range allowed by the lithography technique.

  Further, since the conductive layers (auxiliary strips) SST1 and SST3 have the same length, the wiring resistance from the storage element to the selection element is almost equal for all the storage elements.

  Accordingly, improvement in read selectivity and high integration can be realized, and variations in wiring resistance between cell units can be eliminated, and a high-performance magnetic random access memory can be obtained.

B. Operation Since the read operation and the write operation are the same as those in the first embodiment, the description thereof is omitted here.

c. Summary
According to the magnetic random access memory shown in FIGS. 15 to 18, it is possible to propose a cell layout in which the wiring resistance from the storage element to the selection element is substantially equal for all the storage elements. Therefore, improvement in read selectivity and high integration can be realized, and further high performance can be realized.

d. Other
In the second embodiment, in addition to controlling the lengths of the conductor layers (auxiliary strips) SST1, SST2, and SST3, the wiring resistance is controlled, for example, by controlling the depths of the contact plugs CP1, CP2, and CP3, that is, a strip shape. Control is also possible by the position (which stage is arranged) of the selection elements Tr1, Tr2, Tr3 connected to the conductor layers ST1, ST2, ST3.

(4) Third embodiment
The third embodiment is an example in which only a contact plug is used as a member for connecting a memory element and a selection element without using a conductor layer (auxiliary strip). The third embodiment is a technique effective when it is desired to reduce the wiring resistance between the storage element and the selection element as much as possible.

  When this technique is used, in principle, it is difficult to arrange the memory elements at the pitches Px and Py so that the memory elements are closest to each other. This is because the word lines WL1, WL2, and WL3 must be avoided in order to make contact between the storage element and the selection element.

  Therefore, one of the pitches Px and Py has a value larger than the value when the memory elements are arranged in the closest packing.

A. Cell layout
FIG. 20 shows a cell layout of the magnetic random access memory according to the third embodiment. 21 is a sectional view taken along line XXI-XXI in FIG. 20, FIG. 22 is a sectional view taken along line XXII-XXII in FIG. 20, and FIG. 23 is a sectional view taken along line XXIII-XXIII in FIG.

  The memory elements are arranged in a matrix with a pitch Px in the row direction and a pitch Py in the column direction. One of the pitch Px and the pitch Py has, for example, a value larger than the value when these storage elements are arranged in the same layer in the closest density, that is, at a cell density similar to that of the cross-point cell array structure. .

  In this example, the pitch Px is determined by a minimum processing dimension (design rule) determined by the lithography technique, and the pitch Py is larger than the pitch Px.

  The unit block is composed of 3 × 3 storage elements.

  One ends of the three storage elements m11, m12, and m13 in the row direction are connected to each other by a strip-shaped conductive layer (for example, a metal plate) ST1. The strip-shaped conductive layer ST1 is connected via a contact plug CP1 to a selection element (MOS transistor) Tr1 disposed immediately below.

  Further, one ends of the three storage elements m21, m22, and m23 in the row direction are connected to each other by a strip-shaped conductive layer (for example, a metal plate) ST2. The strip-shaped conductive layer ST2 is connected via a contact plug CP2 to a selection element (MOS transistor) Tr2 arranged immediately below.

  Furthermore, one ends of the three storage elements m31, m32, and m33 in the row direction are connected to each other by a strip-shaped conductive layer (for example, a metal plate) ST3. The strip-shaped conductive layer ST3 is connected via a contact plug CP3 to a selection element (MOS transistor) Tr3 disposed immediately below it.

  The selection elements Tr1, Tr2, Tr3 are stacked in three stages corresponding to the number of strip-like conductive layers ST1, ST2, ST3 in the unit block.

  The sizes of the selection elements Tr1, Tr2, Tr3 are set to Px (row direction) × 2Py (column direction). As shown in FIG. 24, the selection elements Tr1, Tr2, and Tr3 are arranged with their positions shifted so as not to overlap each other.

  Further, in order to secure a contact between the storage element and the selection element, the selection elements Tr1, Tr2, and Tr3 are shifted from each other in the column direction by the pitch Py.

  The gates of the MOS transistors as the selection elements Tr1, Tr2, Tr3 are word lines WL1, WL2, WL3. The word lines WL1, WL2, WL3 are arranged between the strip-shaped conductor layers St1, ST2, ST3 in plan view.

  According to such a cell layout, it is possible to realize a high density of the storage elements because all the storage elements are connected to one selection element at a time, and the selection elements are stacked in a plurality of stages. .

  Further, since the conductive layers (auxiliary strips) SST1, SST2, and SST3 in the first and second embodiments are not used, the wiring resistance from the storage element to the selection element is reduced, and a high-performance magnetic random access memory is obtained. Can do.

B. Operation Since the read operation and the write operation are the same as those in the first embodiment, the description thereof is omitted here.

c. Summary
According to the magnetic random access memory of FIGS. 20 to 23, since the storage element and the selection element are connected only by the contact plug, the wiring resistance from the storage element to the selection element can be reduced. Therefore, improvement in read selectivity and high integration can be realized, and further high performance can be realized.

d. Other
The third embodiment is effective as a technique that can ensure a certain degree of high integration in a case where the wiring resistance between the storage element and the selection element becomes a problem. When the problem of the wiring resistance can be solved by another technique such as a material, it is preferable to arrange the memory elements in the closest manner as in the first and second embodiments described above.

(5) Fourth embodiment
The first and second embodiments are examples where the size of the selection element can be set to the minimum when the memory elements are arranged in the most dense manner.

  That is, if the selection element is a MOS transistor, when the pitch Px, Py = Pmin (minimum pitch determined by the minimum processing dimension by lithography technology), if the regions necessary for the gate, source and drain are taken into consideration, the selection element The minimum size is Px × 3Py.

  However, in the future, it will be difficult to form the selection element with the minimum size.

  Therefore, in the fourth embodiment, the size of the selection element is not fixed, but the pitches Px and Py of the storage element array and the size nPx × mPy of the selection element (n, m = 1, 2, 3,...) We propose a cell layout when

  This cell layout is characterized by a strip-shaped conductor layer in order to ensure that at least the number of selection elements to be stacked when the above conditions are given, and to ensure contact between the storage element and the selection element. There is a connection method between a storage element and a selection element in consideration of the size of the selection element such as how many storage elements should be connected.

  Hereinafter, [A]. No.1 when multiple selection elements corresponding to one unit block are stacked at the same position, [B]. No.1 when multiple selection elements corresponding to one unit block are stacked at the same position. 2, [C]. Three cases in which a plurality of selection elements corresponding to one unit block are stacked while being shifted from each other will be described.

[A]. When multiple selection elements corresponding to one unit block are stacked at the same position No.1
FIG. 25 is a conceptual diagram showing the number Z of stacked selection elements and the number X of storage elements connected to the strip-shaped conductor layers when the pitch of the array of storage elements and the size of the selection elements are given.

  Assume that the array of storage elements is arranged with a pitch Px in the row direction and a pitch Py in the column direction. The pitches Px and Py are values when, for example, the memory elements are arranged most closely based on the minimum processing dimension by the lithography technique.

  The size Lx × Ly of the selection element is represented by nPx × mPy (n, m = 1, 2, 3,...).

  In this case, the stacking stage number Z of the selection elements is set to m or more, and the number X of storage elements connected by the strip-like conductor layers is set to (n + 1) or more. The size of the unit block is (n + 1) × m or more.

  The relationship among n, m, Z, and X is as shown in Table 1.

  If the number Z of stacked stacks of selection elements and the number X of connection of storage elements are set as described above, even if the array of storage elements is arranged as closely as the cross-point cell array structure, the storage elements And the selective element can be reliably contacted.

  Hereinafter, how to make contact between the memory element and the selection element will be described.

    First, when the size of the selection element is 2Px × 3Py, the number of stacking stages Z of the selection elements is 3, the number of connection X of the storage elements is 3, and the size of the unit block is 3 × 3 think about.

  First, as shown in FIGS. 26 and 27, the strip-shaped conductor layer ST1 in the unit block is a selection element (MOS transistor) arranged in the uppermost stage by contact plugs CP11 and CP12 and a conductor layer (auxiliary strip) SST1. Connected to Tr1. The conductor layer (auxiliary strip) SST1 is provided to avoid other selection elements adjacent to the selection element Tr1.

  Next, as shown in FIGS. 28 and 29, the strip-shaped conductor layer ST2 in the unit block is a selection element arranged in the middle stage by contact plugs CP21, CP22, CP23 and conductor layers (auxiliary strips) SST21, SST22. (MOS transistor) Connected to Tr2. The conductor layers (auxiliary strips) SST21 and SST22 are provided to avoid other selection elements adjacent to the selection element Tr2.

  Next, as shown in FIG. 30 and FIG. 31, the strip-shaped conductor layer ST3 in the unit block is selected at the lowest stage by the contact plugs CP31, CP32, CP33 and the conductor layers (auxiliary strips) SST31, SST32. It is connected to an element (MOS transistor) Tr3. The conductor layers (auxiliary strips) SST31 and SST32 are provided to avoid other selection elements adjacent to the selection element Tr3.

  According to such a cell layout, three memory cells can be connected to one selection element at a time for all the memory elements. Therefore, improvement in read selectivity and high integration of memory elements can be realized at the same time.

    b. Next, when the size of the selection element is 3Px × 5Py, the number of stacking stages Z of the selection elements is 5, the number of connection X of the storage elements is 4, and the size of the unit block is 4 × 5 think about.

  First, as shown in FIGS. 32 and 33, the strip-shaped conductor layer ST1 in the unit block is a selection element (MOS transistor) arranged at the uppermost stage by contact plugs CP11 and CP12 and a conductor layer (auxiliary strip) SST1. Connected to Tr1. The conductor layer (auxiliary strip) SST1 is provided to avoid other selection elements adjacent to the selection element Tr1.

  Next, as shown in FIGS. 34 and 35, the strip-shaped conductor layer ST2 in the unit block is arranged at the fourth level from the bottom by the contact plugs CP21, CP22, CP23 and the conductor layers (auxiliary strips) SST21, SST22. The selected element (MOS transistor) Tr2 is connected. The conductor layers (auxiliary strips) SST21 and SST22 are provided to avoid other selection elements adjacent to the selection element Tr2.

  Next, as shown in FIGS. 36 and 37, the strip-shaped conductor layer ST3 in the unit block is arranged at the third level from the bottom by the contact plugs CP31, CP32, CP33 and the conductor layers (auxiliary strips) SST31, SST32. The selected element (MOS transistor) Tr3 is connected. The conductor layers (auxiliary strips) SST31 and SST32 are provided to avoid other selection elements adjacent to the selection element Tr3.

  Next, as shown in FIGS. 38 and 39, the strip-shaped conductor layer ST4 in the unit block is arranged in the second stage from the bottom by the contact plugs CP41, CP42, CP43 and the conductor layers (auxiliary strips) SST41, SST42. The selected element (MOS transistor) Tr4 is connected. The conductor layers (auxiliary strips) SST41, SST42 are provided to avoid other selection elements adjacent to the selection element Tr4.

  Next, as shown in FIGS. 40 and 41, the strip-shaped conductor layer ST5 in the unit block is selected at the lowest stage by the contact plugs CP51, CP52, CP53 and the conductor layers (auxiliary strips) SST51, SST52. It is connected to an element (MOS transistor) Tr5. The conductor layers (auxiliary strips) SST51 and SST52 are provided to avoid other selection elements adjacent to the selection element Tr5.

  According to such a cell layout, four memory cells can be connected to one selection element at a time for all the memory elements. Therefore, improvement in read selectivity and high integration of memory elements can be realized at the same time.

c. Other
According to the example of the present invention, even when a selection element having a size other than the two examples described above is used, contact between the storage element and the selection element can be ensured.

[B]. When multiple selection elements corresponding to one unit block are stacked at the same position No.2
FIG. 42 is a conceptual diagram showing the number Z of stacked selection elements and the number X of storage elements connected to the strip-shaped conductor layer when the pitch of the array of storage elements and the size of the selection elements are given.

  Assume that the array of storage elements is arranged with a pitch Px in the row direction and a pitch Py in the column direction. The pitches Px and Py are values when, for example, the memory elements are arranged most closely based on the minimum processing dimension by the lithography technique.

  The size Lx × Ly of the selection element is represented by nPx × mPy (n, m = 1, 2, 3,...). However, it is set as n> = m.

  In this case, the number Z of stacked stacks of the selection elements is (m + 1) or more, and the number X of storage elements connected by the strip-shaped conductor layers is n or more. The size of the unit block is n × (m + 1) or more.

  This example No. 2 has the same preconditions as the example No. 1 described above, but the number Z of stacked stacks of the selected elements is increased by one to (m + 1) or more, and the memory by the strip-shaped conductor layer The number of connected elements X is reduced by one to n or more.

  This example No. 2 is effective when it is desired to reduce the number of storage elements connected to the strip-shaped conductor layer as much as possible.

  If the number Z of stacked stacks of selection elements and the number X of connection of storage elements are set as described above, even if the array of storage elements is arranged as closely as the cross-point cell array structure, the storage elements And the selective element can be reliably contacted.

  Hereinafter, how to make contact between the memory element and the selection element will be described.

    First, when the size of the selection element is 4Px × 3Py, the number of stacking stages Z of the selection elements is 4, the number of connection X of the storage elements is 4, and the size of the unit block is 4 × 4 think about.

  First, as shown in FIGS. 43 and 44, the strip-shaped conductor layer ST1 in the unit block is a selection element (MOS transistor) arranged at the uppermost stage by the contact plugs CP11 and CP12 and the conductor layer (auxiliary strip) SST1. Connected to Tr1. The conductor layer (auxiliary strip) SST1 extends in the column direction in order to avoid a selection element other than the selection element Tr1.

  In this example, since n ≧ m is set, other selection elements other than the selection element Tr1 can be easily bypassed by the conductor layer (auxiliary strip) SST1.

  Next, as shown in FIGS. 45 and 46, the strip-shaped conductor layer ST2 in the unit block is arranged in the third row from the bottom by the contact plugs CP21, CP22, CP23 and the conductor layers (auxiliary strips) SST21, SST22. The selected element (MOS transistor) Tr2 is connected. The conductor layers (auxiliary strips) SST21, SST22 extend in the column direction in order to avoid other selection elements other than the selection element Tr2.

  In this example, since n ≧ m is set, other selection elements other than the selection element Tr2 can be easily bypassed by the conductor layers (auxiliary strips) SST21 and SST22.

  Next, as shown in FIGS. 47 and 48, the strip-shaped conductor layer ST3 in the unit block is arranged in the second stage from the bottom by the contact plugs CP31, CP32, CP33 and the conductor layers (auxiliary strips) SST31, SST32. The selected element (MOS transistor) Tr3 is connected. The conductor layers (auxiliary strips) SST31 and SST32 extend in the column direction in order to avoid selection elements other than the selection element Tr3.

  In this example, since n ≧ m is set, other selection elements other than the selection element Tr3 can be easily bypassed by the conductor layers (auxiliary strips) SST31 and SST32.

  Next, as shown in FIGS. 49 and 50, the strip-shaped conductor layer ST4 in the unit block is selected at the lowest stage by the contact plugs CP41, CP42, CP43 and the conductor layers (auxiliary strips) SST41, SST42. It is connected to an element (MOS transistor) Tr4. The conductor layers (auxiliary strips) SST41 and SST42 extend in the column direction in order to avoid selection elements other than the selection element Tr4.

  In this example, since n ≧ m is set, other selection elements other than the selection element Tr4 can be easily bypassed by the conductor layers (auxiliary strips) SST41 and SST42.

  According to such a cell layout, four memory cells can be connected to one selection element at a time for all the memory elements. Therefore, improvement in read selectivity and high integration of memory elements can be realized at the same time.

    b. Next, when the size of the selection element is 4Px × 4Py, the number of stacked Z stages of the selection element is 5, the number of connection X of the storage elements is 4, and the size of the unit block is 4 × 5 think about.

  First, as shown in FIG. 51 and FIG. 52, the strip-shaped conductor layer ST1 in the unit block is selected by the contact plugs CP11 and CP12 and the conductor layer (auxiliary strip) SST1. The MOS transistor is connected to Tr1. The conductor layer (auxiliary strip) SST1 extends in the column direction in order to avoid a selection element other than the selection element Tr1.

  In this example, since n ≧ m is set, other selection elements other than the selection element Tr1 can be easily bypassed by the conductor layer (auxiliary strip) SST1.

  Next, as shown in FIGS. 53 and 54, the strip-shaped conductor layer ST2 in the unit block is arranged at the third level from the bottom by the contact plugs CP21, CP22, CP23 and the conductor layers (auxiliary strips) SST21, SST22. The selected element (MOS transistor) Tr2 is connected. The conductor layers (auxiliary strips) SST21, SST22 extend in the column direction in order to avoid other selection elements other than the selection element Tr2.

  In this example, since n ≧ m is set, other selection elements other than the selection element Tr2 can be easily bypassed by the conductor layers (auxiliary strips) SST21 and SST22.

  Next, as shown in FIGS. 55 and 56, the strip-shaped conductor layer ST3 in the unit block is arranged in the second stage from the bottom by the contact plugs CP31, CP32, CP33 and the conductor layers (auxiliary strips) SST31, SST32. The selected element (MOS transistor) Tr3 is connected. The conductor layers (auxiliary strips) SST31 and SST32 extend in the column direction in order to avoid selection elements other than the selection element Tr3.

  In this example, since n ≧ m is set, other selection elements other than the selection element Tr3 can be easily bypassed by the conductor layers (auxiliary strips) SST31 and SST32.

  Next, as shown in FIGS. 57 and 58, the strip-shaped conductor layer ST4 in the unit block is selected at the lowest stage by the contact plugs CP41, CP42, CP43 and the conductor layers (auxiliary strips) SST41, SST42. It is connected to an element (MOS transistor) Tr4. The conductor layers (auxiliary strips) SST41 and SST42 extend in the column direction in order to avoid selection elements other than the selection element Tr4.

  In this example, since n ≧ m is set, other selection elements other than the selection element Tr4 can be easily bypassed by the conductor layers (auxiliary strips) SST41 and SST42.

  Next, as shown in FIGS. 59 and 60, the strip-shaped conductor layer ST5 in the unit block is connected to a selection element (MOS transistor) Tr5 arranged at the uppermost stage by a contact plug CP5.

  Here, no conductor layer (auxiliary strip) is used for the contact between the strip-shaped conductor layer ST5 and the selection element Tr5. Therefore, the direction of the source / drain of the selection element (MOS transistor) Tr5 is opposite to the direction of the source / drain of the selection elements (MOS transistors) Tr1 to Tr4.

  According to such a cell layout, four memory cells can be connected to one selection element at a time for all the memory elements. Therefore, improvement in read selectivity and high integration of memory elements can be realized at the same time.

c. Other
According to the example of the present invention, even when a selection element having a size other than the two examples described above is used, contact between the storage element and the selection element can be ensured.

[C]. When a plurality of selection elements corresponding to one unit block are stacked while being shifted from each other (including the cases of FIGS. 9 to 24).
FIG. 61 is a conceptual diagram showing the number Z of stacked selection elements and the number X of storage elements connected to the strip-shaped conductor layer when the pitch of the array of storage elements and the size of the selection elements are given.

  Assume that the array of storage elements is arranged with a pitch Px in the row direction and a pitch Py in the column direction. The pitches Px and Py are values when, for example, the memory elements are arranged most closely based on the minimum processing dimension by the lithography technique.

  The size Lx × Ly of the selection element is represented by nPx × mPy (n, m = 1, 2, 3,...).

  In this case, the stacking stage number Z of the selection elements is set to m stages or more, and the number X of storage elements connected by the strip-like conductor layers is set to (n + m−1) or more. The size of the unit block is (n + m−1) × m or more.

  Regarding the number X of storage element connections, since the size of the selection element in the row direction is n × Px, at least n storage elements are required. However, this alone cannot ensure contact between the storage element and the selection element.

  Therefore, if the stacked m selection elements are shifted by a pitch Px in the row direction in order to ensure contact between the storage element and the selection element, the number of connections X of the storage elements is added to n. Furthermore, it is necessary to add only the number (= m−1) obtained by subtracting 1 from the number Z of stacked stacks of selected elements.

  Therefore, the number X of storage element connections is (n + m−1) or more.

  In this case, the number of conductor layers (auxiliary strips) necessary for making contact between the storage element and the selection element is one or less.

  Table 2 shows the relationship among n, m, Z, and X.

  If the number Z of stacked stacks of selection elements and the number X of connection of storage elements are set as described above, even if the array of storage elements is arranged as closely as the cross-point cell array structure, the storage elements And the selective element can be reliably contacted.

  Hereinafter, how to make contact between the memory element and the selection element will be described.

  Consider a case where the size of the selection element is 4Px × 3Py, the number of stacked stages Z of the selection elements is 3, the number of connection X of the storage elements is 4, and the size of the unit block is 4 × 3.

  First, as shown in FIGS. 62 and 63, the strip-shaped conductor layer ST1 in the unit block is connected to the selection element (MOS transistor) Tr1 arranged in the uppermost stage by the contact plug CP1. The conductor layer (auxiliary strip) is not used for contact between the strip-shaped conductor layer ST1 and the selection element Tr1.

  Next, as shown in FIGS. 64 and 65, the strip-shaped conductor layer ST2 in the unit block is a selection element (MOS transistor) arranged in the middle stage by the contact plugs CP21 and CP22 and the conductor layer (auxiliary strip) SST2. Connected to Tr2. The conductor layer (auxiliary strip) SST2 is provided to avoid other selection elements other than the selection element Tr2.

  Next, as shown in FIGS. 66 and 67, the strip-shaped conductor layer ST3 in the unit block is composed of a selection element (MOS transistor) arranged at the lowest stage by contact plugs CP31 and CP32 and a conductor layer (auxiliary strip) SST3. ) Connected to Tr3. The conductor layer (auxiliary strip) SST3 is provided to avoid selection elements other than the selection element Tr3.

  According to such a cell layout, four memory cells can be connected to one selection element at a time for all the memory elements. In addition, the contact between the memory element and the selection element can be reliably performed by using one or less conductor layers (auxiliary strips). Therefore, improvement in read selectivity and high integration of memory elements can be realized at the same time.

c. Other
According to the example of the present invention, even when a selection element having a size other than the above example is used, the contact between the storage element and the selection element can be reliably obtained.

(6) Fifth embodiment
The fifth embodiment relates to a method of manufacturing a semiconductor memory according to the first to fourth embodiments and a device structure formed by the method.

  First, according to the example of the present invention, it is necessary to stack select elements (for example, MOS transistors) in a plurality of stages on a semiconductor substrate.

  In order to stack the selection elements in a plurality of stages, in addition to a method of sequentially forming selection elements by a so-called damascene process, a plurality of selection elements formed on different semiconductor substrates are bonded by a bonding technique. , Methods of bonding to each other can be used.

  When the latter bonding technique is used, the size of the contact between the contact plugs must be determined in view of the bonding margin.

  68 to 72 show examples of the device structure in the case where the laminated structure of the selection elements is formed by the bonding technique.

  A feature of this structure is that contact plugs or conductor layers connected to the selection elements Tr2 to Tr4 other than the uppermost selection element Tr1 have a size in consideration of a bonding margin.

  For example, as shown in FIG. 69, the strip-shaped conductor layer ST1 in the unit block is a selection element (MOS transistor) arranged at the top by contact plugs CP11, CP12, CP13 and conductor layers (auxiliary strips) SST11, SST12. ) Connected to Tr1. The conductor layer (auxiliary strip) SST11 is provided to avoid a selection element other than the selection element Tr1.

  Further, as shown in FIG. 70, the strip-shaped conductor layer ST2 in the unit block is the third step from the bottom by contact plugs CP21, CP22, CP23, CP24 and conductor layers (auxiliary strips) SST21, SST22, SST23, SST24. Is connected to a selection element (MOS transistor) Tr2. The conductor layer (auxiliary strip) SST21 is provided to avoid a selection element other than the selection element Tr2.

  Here, the contact plugs CP23, CP24 and the conductor layers SST22, SST23, SST24 have a size in consideration of a bonding margin. For example, an area of 2Px × 2Py is secured for these.

  As shown in FIG. 71, the strip-shaped conductor layer ST3 in the unit block includes contact plugs CP31, CP32, CP33, CP34, CP35 and conductor layers (auxiliary strips) SST31, SST32, SST33, SST34, SST35, SST36. Are connected to a selection element (MOS transistor) Tr3 arranged in the second stage from the bottom. The conductor layer (auxiliary strip) SST31 is provided to avoid a selection element other than the selection element Tr3.

  Here, the contact plugs CP33, CP34, CP35 and the conductor layers SST32, SST33, SST34, SST35, SST36 have a size in consideration of a bonding margin. For example, an area of 2Px × 2Py is secured for these.

  72, the strip-shaped conductor layer ST4 in the unit block includes contact plugs CP41, CP42, CP43, CP44, CP45 and conductor layers (auxiliary strips) SST41, SST42, SST43, SST44, SST45, SST46, By SST47, it is connected to the selection element (MOS transistor) Tr4 arranged at the lowest stage.

  Here, the contact plugs CP42, CP43, CP44, CP45 and the conductor layers SST41, SST42, SST43, SST44, SST45, SST46, SST47 have a size in consideration of a bonding margin. For example, an area of 2Px × 2Py is secured for these.

  As described above, if the bonding technique is used, the number of manufacturing steps increases, but the selection elements (for example, MOS transistors) arranged in each stage do not need to be formed by the latest microfabrication technique. Further, when all the selection elements arranged in each stage are formed by a damascene process, a high level technique is required, but this is not necessary.

  Note that the size of the contact point in consideration of the bonding margin depends on the alignment technique.

  In this example, the size of the contact contact by bonding is 2Px × 2Py. However, it may be larger than this size, and it is fully conceivable that it may become smaller than this size due to technological progress.

(7) Other
In the example of the present invention, as the size of the selection element is larger, the effect related to higher integration of the storage element becomes more remarkable. For example, it is assumed that the selection element is a MOS transistor and the size thereof is Lx (= 1 μm) × Ly (= 4 μm) = 4 μm ² .

  If the size of the storage element of a spin injection magnetic random access memory, which is the next generation memory, is 200 nm × 300 nm, the pitch Px in the row direction of the storage element is set to 200 nm and the pitch Py in the column direction is set to 300 nm. Therefore, n = 5 and m = 13.

  Therefore, the memory elements are stacked in 13 stages or more.

  In this case, for example, 65 times (in the case of 13 stages) or more (in the case of more than 13 stages) can be achieved with a higher degree of integration than a cell array structure in which the memory elements and the selection elements correspond to 1: 1. .

  Further, for example, as compared with the cell array structure in which the memory element and the selection element correspond to m: 1, 13 times (in the case of 13 stages) or more (in the case of more than 13 stages) can be highly integrated.

  By the way, even if the microfabrication technology has advanced greatly, the size of the selection element cannot be the same as the size of one storage element. If it is assumed that the size of the selection element is slightly smaller than the size of the storage element, for example, 0.6 μm × 0.3 μm (600 nm × 300 nm), n = 2 and m = 2.

  Even in this case, for example, compared with the cell array structure in which the memory element and the selection element correspond to 1: 1, the integration can be three times or more.

  Further, for example, the integration density can be doubled or more than that of a cell array structure in which the memory element and the selection element correspond to m: 1.

  However, the above is based on the premise that problems such as electromigration and a high dielectric constant thin film have been solved in miniaturizing the selection element.

  According to the example of the present invention, it is possible to realize a higher S / N ratio and higher speed as compared with the cross-point type cell array structure, and it is possible to realize a cell density (high integration) comparable to that of the cross-point type cell array structure.

  Further, the main point of the example of the present invention is that, in addition to realizing a cell density comparable to that of the cross-point type cell array structure, the degree of integration of the memory elements is improved by stacking the selection elements in multiple stages. . In this case, the memory elements may be arranged at a wider pitch than the closest packing, and the number Z of stacked stacks of selection elements and the number X of memory element connections are increased as much as possible.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention.

  For example, the selection element is not limited to a MOSFET based on silicon (Si), and may be formed based on another material or structure such as an organic substance or carbon nanotube, or a bipolar transistor. Even in the case of a diode or a diode that requires a larger size than a memory element, the same effect can be achieved by applying the example of the present invention.

  The memory element may be a magnetoresistive effect element, a phase change element utilizing a phase transition between crystalline and amorphous, a ferroelectric element, or the like.

  Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

The circuit diagram which shows the example of the cell array structure of a magnetic random access memory. The top view which shows the layout of the selection element and memory | storage element in 1 block. Sectional drawing which shows the structure of the selection element and memory element in 1 block. The top view which shows the layout of the selection element and memory | storage element in 1 block. Sectional drawing which shows the structure of the selection element and memory element in 1 block. The figure which shows the concept of the example of this invention. The figure which shows the concept of the example of this invention. The circuit diagram which shows the example of the cell array structure of a magnetic random access memory. The top view which shows the cell layout in connection with 1st Embodiment. Sectional drawing which follows the XX line of FIG. Sectional drawing which follows the XI-XI line of FIG. Sectional drawing which follows the XII-XII line | wire of FIG. The figure which shows the positional relationship of a unit block and a selection element. The figure which shows the connection relation of a memory element and a selection element. The top view which shows the cell layout in connection with 2nd Embodiment. Sectional drawing which follows the XVI-XVI line | wire of FIG. Sectional drawing which follows the XVII-XVII line | wire of FIG. Sectional drawing which follows the XVIII-XVIII line of FIG. The figure which shows the positional relationship of a unit block and a selection element. The top view which shows the cell layout in connection with 3rd Embodiment. Sectional drawing which follows the XXI-XXI line | wire of FIG. Sectional drawing which follows the XXII-XXII line | wire of FIG. Sectional drawing which follows the XXIII-XXIII line | wire of FIG. The figure which shows the positional relationship of a unit block and a selection element. The top view which shows the cell layout in connection with 4th Embodiment. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the cell layout in connection with 4th Embodiment. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the cell layout in connection with 4th Embodiment. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. The top view which shows the cell layout in connection with 5th Embodiment. Sectional drawing which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element. Sectional drawing which shows the example of a connection of a memory element and a selection element.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11: Memory cell array, 12: Memory element, 13A: Row coder & word line driver, 13B: Column decoder, 14: Column decoder & column selection line driver, 15A, 15B: Write driver / sinker, 16: Read circuit (sense) WL1-WL5: word line, BL1-BL4: bit line, RSW: selection element, CSW1, CSW2: column selection switch, SL1-SL3: source line, ST1-ST4: strip-like conductor layer, SST1- SST3: Conductor layer (auxiliary strip).

Claims (9)

A plurality of storage elements arranged in a matrix with a pitch Px in the row direction and a pitch Py in the column direction;
A plurality of selection elements arranged immediately below the plurality of storage elements, the size Lx in the row direction being n × Px, and the size Ly in the column direction being m × Py;
A plurality of first conductive layers connecting one ends of the X memory elements arranged in the row direction to each other;
The plurality of selection elements are arranged in m or more different layers, and the number of X storage elements is n + 1 or more. A plurality of storage elements arranged in a matrix with a pitch Px in the row direction and a pitch Py in the column direction;
A plurality of selection elements arranged immediately below the plurality of storage elements, the size Lx in the row direction being n × Px, and the size Ly in the column direction being m × Py;
A plurality of first conductive layers connecting one ends of the X memory elements arranged in the row direction to each other;
The plurality of selection elements are arranged in different layers of m + 1 stages or more, and the X memory elements are n (however, only when n ≧ m) or more. A plurality of storage elements arranged in a matrix with a pitch Px in the row direction and a pitch Py in the column direction;
A plurality of selection elements arranged immediately below the plurality of storage elements, the size Lx in the row direction being n × Px, and the size Ly in the column direction being m × Py;
A plurality of first conductive layers connecting one ends of the X memory elements arranged in the row direction to each other;
The plurality of selection elements are arranged in different layers of m stages or more, and the X memory elements are n + m−1 or more.   4. The semiconductor memory according to claim 1, wherein the pitch Px and the pitch Py have values when the plurality of storage elements are arranged closest in the same layer. 5.   The semiconductor memory according to claim 4, wherein the pitch Px and the pitch Py are determined by a minimum processing dimension determined by a lithography technique.   4. The device according to claim 1, wherein each of the plurality of first conductive layers is connected to one of the plurality of selection elements via a second conductive layer. 5. Semiconductor memory.   The semiconductor memory according to claim 6, wherein the second conductive layer extends in the column direction.   4. One of the pitch Px and the pitch Py has a value larger than a value when the plurality of memory elements are arranged in the same layer in the closest density. 2. The semiconductor memory according to item 1. The semiconductor memory according to claim 7 , wherein the first and second conductive layers have a strip shape in plan view .

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