JP4399177B2 - Plasma etching method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma etching method, and more particularly, to a plasma etching method capable of etching a workpiece into an intended shape.
[0002]
[Prior art]
Along with the high performance and miniaturization of semiconductor devices, multilayer wiring technology has become a necessary technology in semiconductor device manufacturing. As a method for forming a wiring layer in a semiconductor integrated circuit, a refractory metal thin film such as an aluminum (Al) alloy or tungsten (W) is formed on an insulating film, and then the same as the wiring pattern on the wiring thin film by a photolithography process. A method is known in which a resist pattern having a shape is formed and a wiring pattern is formed by a dry etching process using the resist pattern as a mask. However, in the method using Al alloy or the like, there is a problem that the wiring resistance increases remarkably with the miniaturization of the wiring, the wiring delay of the signal to propagate increases accordingly, and the performance of the semiconductor device decreases. In particular, in a high-performance logic LSI, a big problem has arisen as a performance impediment factor.
[0003]
For this reason, after embedding a wiring metal having copper (Cu) as a main conductor layer in a groove formed in an insulating film made of a low dielectric constant material, the metal outside the groove is removed using a CMP method (chemical mechanical polishing method). A method of forming a wiring pattern in the groove by removing (so-called damascene method) or a dual damascene method (wiring grooves for wiring formation and connection holes (holes) for forming interlayer connection wirings are formed. Later, for example, a damascene method in which a wiring having copper (Cu) as a main conductor and an interlayer connection wiring are simultaneously formed in the wiring groove and the connection hole has been used.
[0004]
FIG. 6 is a diagram for explaining a conventional dual damascene method. In the figure, 100 is a wafer, 1 is a silicon carbide film formed on the surface of the wafer 100, for example, 2 is a low dielectric constant dielectric material film, for example, an organic silica glass (OSG) film. 3 is a cap oxide film, 4 is a connection hole for forming an interlayer connection wiring, and 5 is a wiring groove for forming a wiring pattern.
[0005]
In order to form the wiring trench for wiring formation and the connection hole 4 for interlayer connection wiring formation by the dual damascene method, first, the OSG film 2 reaches the lower layer wiring (formed on the lower layer side of the silicon carbide film 1). A connection hole 4 is formed. In forming the connection hole 4, first, a patterned cap oxide film is formed on the OSG film 2, and the OSG film is etched by, for example, a dry etching method using this as a mask. Next, this connection hole is filled with an antireflection material, and then a wiring groove 5 is formed in the OSG film 2. As in the case of forming the connection hole 4, the wiring groove 5 is formed by forming a photoresist film patterned in the groove pattern on the OSG film 2 and etching the OSG film 2 using this photoresist film as a mask. . The reason why the antireflection material is embedded in the connection hole 4 before the formation of the wiring groove 5 is that the photoresist film for forming the wiring groove is accurately exposed and the processing accuracy is improved. That is, if the connection hole 4 is not buried, the surface of the photoresist film formed on the connection hole is not flat reflecting the hole shape. This is because, when exposure is performed using such a non-flat photoresist film, exposure light is scattered and a groove pattern cannot be formed accurately.
[0006]
However, as shown in FIG. 6, the OSG film 2 is etched using the photoresist film patterned in the groove pattern as a mask in a state in which the antireflection material is embedded in the connection hole 4 before the wiring groove 5 is formed. When removing the antireflection embedded in the connection hole, the fence-like defect 6 (formed around the connection hole 4 is caused by a shift in etching characteristics between the antireflection material embedded in the connection hole 4 and the OSG film 2. Protrusion defect).
[0007]
As countermeasures against the occurrence of such defects, a method using a special material such as a silicon-based material as an antireflection material (for example, see Patent Document 1), or selecting a fluorine-based gas as an etching gas, and optimally preparing this gas There is a known method of deterrence by doing so.
[0008]
[Patent Document 1]
USP 6329118
[0009]
[Problems to be solved by the invention]
However, as a countermeasure against the occurrence of defects, the method used as a special antireflection material such as the silicon-based material has a problem in terms of cost because a general-purpose antireflection material cannot be used. In addition, the method of selecting a fluorine-based gas as the etching gas and adjusting the gas ratio may adversely affect the processing characteristics for other portions.
[0010]
The present invention has been made in view of these problems, and provides a plasma etching method capable of etching a workpiece into an intended shape without adversely affecting the processing characteristics of other portions.
[0011]
[Means for Solving the Problems]
The present invention employs the following means in order to solve the above problems.
[0012]
A plasma etching method used in a dual damascene method to form a wiring hole for wiring formation and a connection hole for forming an interlayer connection wiring in a low dielectric constant dielectric material film formed on a wafer surface, The plasma etching method includes a step of forming a connection hole in the dielectric material film using a cap oxide film as a mask, a step of forming an organic antireflection film in the connection hole and on the cap oxide film, and the organic the photoresist formed on the antireflection film as a mask, the organic reflection etching the organic antireflective film oxygen and chlorine as the etching gas, the photoresist as a mask, boron trichloride and chlorine as the etching gas preventing film, including the cap oxide film and the dielectric material film forming the etched interconnect trench.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram for explaining a plasma etching apparatus used for etching according to the present invention. In the figure, 21 is a vacuum processing chamber, 22 is a quartz window, and 23 is a mounting electrode. Reference numeral 24 denotes a sample such as a wafer, which is placed on the placement electrode 23. A high frequency power source 25 applies a bias voltage to the wafer 24. An antenna 26 radiates a high-frequency electric field supplied from a UHF power source into the vacuum processing chamber 21 through the quartz window 22. A solenoid coil 27 forms a magnetic field in the vacuum processing chamber 1. A gas dispersion plate 28 uniformly introduces the gas supplied from the mass flow controller into the vacuum processing chamber 1 according to the etching recipe. 29 is a UHF power source, and 30 is a mass flow controller, which measures and supplies a processing gas such as chlorine gas (Cl ₂ ), boron trichloride gas (BCl ₃ ), oxygen gas (O ₂ ). Reference numeral 31 denotes a matching circuit for matching the impedance of the power supply circuit of the UHF power supply 29.
[0014]
In the process, first, after evacuating the vacuum processing chamber 21 to a vacuum, a predetermined gas is introduced into the vacuum processing chamber 21 via the mass flow controller 30 according to a recipe, and the inside of the vacuum processing chamber 21 is adjusted to a predetermined pressure. Press. Next, a predetermined magnetic field is formed in the vacuum processing chamber 21 by the solenoid coil 27, and a high frequency electric field is introduced into the vacuum processing chamber 21 from the UHF power source 29 via the antenna 26, and plasma is generated in the vacuum processing chamber 21. generate. Thereafter, a predetermined bias power is applied to the sample 24 through the mounting electrode 3 by the high frequency power source 25. Thereby, a predetermined plasma process can be performed on the sample 24.
[0015]
2, 3, 4, and 5 are views for explaining the plasma etching process according to the present embodiment. FIG. 2 shows an antireflection material layer formed on the OSG film formed on the surface of the wafer 100. It is a figure which shows the state which formed the photoresist in mask shape on the material layer. In FIG. 2, 1 is, for example, a silicon carbide film formed on the surface of the wafer 100, and 2 is a dielectric material film having a low dielectric constant. For example, an organic silica glass (OSG) film doped with a methyl group is used. 3 is a cap oxide film, and 4 is a connection hole for forming an interlayer connection wiring. Reference numeral 7 denotes an antireflection material layer (made of, for example, a BARC material). The antireflection material layer 7 includes an antireflection material layer 71 formed in the connection hole 4 and an antireflection material layer 72 formed on the cap oxide film layer 3. Become. Reference numeral 8 denotes a photoresist formed on the antireflection material layer 72, which is previously patterned into a shape in which a portion for forming a wiring groove is removed by a dual damascene method.
[0016]
Next, the wafer 100 shown in FIG. 2 is carried into the processing chamber of the plasma etching apparatus shown in FIG.
[0017]
FIG. 3 is a diagram illustrating a process of etching the antireflection material 7 using the photoresist 8 shown in FIG. 2 as a mask and oxygen and chlorine as etching gases. Chlorine as the etching gas is highly reactive with organic films such as the antireflection film 7. Therefore, when etching is performed using the etching gas, the antireflection material at the boundary with the cap oxide film 3 is selectively etched, and the facet f (a frustoconical surface) shown in FIG. It is formed.
[0018]
FIG. 4 is a diagram illustrating a process of etching the antireflection material layer 71, the cap oxide film 3 and the OSG film 2 using the photoresist 8 shown in FIG. 3 as a mask and boron trichloride and chlorine as etching gases. In this case, the upper part of the connection hole 4 of the OSG film 2 is further etched due to the angular dependence of the reactivity between the boron trichloride gas as the etching gas and the OSG film 2. Thereby, a tapered portion g can be obtained at the upper portion of the connection hole 4 of the OSG film 2.
[0019]
FIG. 5 is a diagram for explaining a process of further etching the antireflection material layer and the low dielectric constant film using the photoresist 8 shown in FIG. 4 as a mask and boron trichloride and chlorine as etching gases. In this step, the etching is started with the shape shown in FIG. 4, that is, the shape in which the tapered portion g is formed above the connection hole 4 of the OSG film 2 as the initial shape. In this case, the etching rate at the interface between the antireflection material layer 71 and the OSG film 4 is balanced with the etching rate at the other surface, and the etching proceeds with the tapered portion g shown in FIG. 4 held. Become. For this reason, the wiring groove | channel 5 in which the fence-like defect 6 (refer FIG. 6) does not exist can be obtained.
[0020]
After the step shown in FIG. 5, the antireflection material layer 71 is removed, and a metal such as copper (Cu) is deposited as a conductor material in the connection hole 4 and the wiring groove 5 after the removal, and the surplus surface is further removed. The copper is removed by CMP (Chemical Mechanical Polishing) and planarized. At this time, CMP can be stopped on the surface of the cap oxide film 3. Thereby, the copper wiring by the dual damascene method is formed in the wiring groove 5 and the connection hole 4. The OSG film 2 is made of, for example, a product name Coral manufactured by Novellus, a product name Black Diamond manufactured by Applied Materials, a product name Aurora manufactured by ASM, and the CVD film formation and element composition thereof. It can comprise with the material described as.
[0021]
As described above, according to the present embodiment, in the step of etching the antireflection material layer 7, the cap oxide film 7 and the OSG film 2 (FIGS. 2-3, 3-4), oxygen gas and chlorine gas, In addition, an initial shape of etching is created using boron trichloride gas and chlorine gas, and etching is further advanced using boron trichloride gas and chlorine gas based on this initial shape (FIGS. 4 to 5). As a result, a wiring groove free from fence-like defects can be obtained.
[0022]
At this time, the etching rate was higher than the performance obtained when a fluorine-based process gas was used. Thus, by appropriately combining the shape dependence of the etching rate of boron trichloride gas and chlorine-based gas, without using an expensive antireflection film material, and without adversely affecting the processing characteristics for other parts The workpiece can be etched into the desired shape.
[0023]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a plasma etching method capable of etching a workpiece into an intended shape without adversely affecting the processing characteristics for other portions.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a plasma etching apparatus used for etching according to the present invention.
FIG. 2 is a diagram illustrating a plasma etching process.
FIG. 3 is a diagram illustrating a plasma etching process.
FIG. 4 is a diagram illustrating a plasma etching process.
FIG. 5 is a diagram illustrating a plasma etching process.
FIG. 6 is a diagram illustrating a conventional dual damascene method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon carbide film 2 OSG film 3 Cap oxide film 4 Connection hole 5 Wiring groove 6 Fence-like defect 7, 71, 72 Antireflection material layer 8 Photoresist 21 Vacuum processing chamber 22 Quartz window 23 Electrode 24 Sample 25 High frequency power supply 26 Antenna 27 Solenoid coil 28 Gas dispersion plate 29 UHF power supply 30 Mass flow controller 31 Matching circuit 100 Wafer

Claims (1)

A plasma etching method used in a dual damascene method to form a wiring hole for wiring formation and a connection hole for forming an interlayer connection wiring in a low dielectric constant dielectric material film formed on a wafer surface,
The plasma etching method includes a step of forming a connection hole in the dielectric material film using a cap oxide film as a mask;
Forming an organic antireflection film in the connection hole and on the cap oxide film;
Etching the organic antireflection film using a photoresist formed on the organic antireflection film as a mask and oxygen and chlorine as etching gases; and
The photoresist as a mask, the three said organic anti-reflective film boron chloride and chlorine as the etching gas, a plasma, which comprises the cap oxide film and the dielectric material film is formed is etched wiring trench process Etching method.

Images