JP4391464B2 - Device for storing binary tree structure information and device for storing heap structure information - Google Patents

Description

  The present invention relates to an apparatus for storing binary tree structure information and an apparatus for storing heap structure information, and more particularly to an apparatus and heap for storing binary tree structure information related to realization by parallel processing of a sorter using a heap. The present invention relates to an apparatus for storing structure information.

  Conventionally, various queuing systems that are widely used for communication quality control in the communication field have improved scalability, such as support for higher communication lines and increased queue count. Therefore, a high speed and large capacity sorter is required. The sorter mentioned here is a device that identifies the information with the highest priority from the information given priority. In the wide range of information processing fields such as scheduling, encoding, placement and routing, and numerical calculation. in use.

  FIG. 10 is an explanatory diagram illustrating an example of a priority queue. As shown in FIG. 10, in the queuing system, the most basic priority queue (priority queue) has a priority defined for the queue and queues packets based on the priority corresponding to the received packet. And a queuing system based on a service rule that selects a queue with the highest priority from queues that can transmit packets.

  The priority queue is practically used if the corresponding priority is several levels. However, when the priority is set to several thousand levels or high-speed lines are supported, the priority queue is the most queue that can transmit packets. The process of selecting a queue with a high priority is a bottleneck. For this reason, when sequentially checking whether a packet can be transmitted from the queue with the highest priority to the queue with the lowest priority, processing at a speed that can handle thousands of priorities and high-speed lines is It becomes difficult. In order to solve this problem, it is necessary to realize a sorter corresponding to a large number of priorities at high speed.

  FIG. 11 is an explanatory diagram illustrating an example of a cyclic queue. As shown in FIG. 11, the cyclic (round robin) type queue has a circular order relationship with respect to the queue, classifies packets into queues based on protocol information included in the received packets, This is a queuing system based on a service rule that selects a queue that is closest in order to the queue that performed the previous transmission from the queues that can be transmitted.

  When the number of queues is several thousand levels or for high-speed lines, the cyclic queue is a process that selects the queue that is closest in order to the queue that sent the packet from the queues that can send packets. Becomes a bottleneck. When it is sequentially confirmed whether or not a packet can be transmitted, starting from a queue that has transmitted, it is difficult to perform processing at a speed that can handle thousands of queues and high-speed lines. Since the order relation of queues can be regarded as a priority, a sorter corresponding to a large number of priorities is required to solve this problem.

  FIG. 12 is an explanatory diagram illustrating an example of a tagging queue. As shown in FIG. 12, the tagging queue is a queuing system based on WFQ (Weighted Fair Queuing), Virtual Clock, Jitter-EDD (Early Due Date), and the like. Although there are differences in the details of these methods, the packets are classified into queues based on the protocol information contained in the received packets, the transmission timing of the received packets is calculated, and the value is assigned to the packet as a tag. Thus, based on a service rule for selecting a queue storing a packet having a tag with the earliest transmission timing from among the first packets in the queue.

When the number of queues is set to several thousand levels or the high-speed line correspondence is also applied to the tagging type queue, processing for selecting a queue storing a packet having a tag with the earliest transmission timing becomes a bottleneck. When the tag values of the packets at the head of the queue are sequentially compared, it is difficult to perform processing at a speed that can handle thousands of queues and high-speed lines. Since the value of the transmission timing can be regarded as a priority, it is necessary to realize a sorter corresponding to a large number of priorities in order to solve this problem.
As is clear from the above, in order to improve the scalability of the queuing system, it is necessary to implement a sorter that selects the highest priority from a plurality of priority information in correspondence with many priorities and at high speed. Become.

In the prior art, a sorter that selects the highest priority from a plurality of priority information can be realized by a priority encoder.
FIG. 13 is an explanatory diagram illustrating an example of a priority encoder. As shown in FIG. 13, the priority encoder is a combinational logic circuit in which a priority corresponding to an input signal is determined in advance and the highest priority value is output from the priority indicated by the input signal.

FIG. 13 shows an example of a priority encoder that encodes and outputs the highest priority value into 3 bits from eight levels of priority input. The priority encoder is logically implemented by hardware for linear search, and requires a multi-input or multi-stage OR circuit. For this reason, the time from the input of priority until the highest priority is output is proportional to the number of priorities, and the number of priorities that can be practically used is at most a dozen levels.
Since it is necessary to deal with a large number of priorities, it is difficult to deal with priority encoders. In the conventional technique, a sorter based on a binary tree is often used.

  FIG. 14 is an explanatory diagram showing an implementation example of the sorter hardware using a binary tree. As shown in FIG. 14, the sorter based on the binary tree arranges the priority information at the node of the lowest layer (the lowest hierarchy in the figure) of the binary tree, and the comparator at the nodes of the other layers. Place. Then, the comparator inputs priority information from the lower layer, and outputs priority information having a higher priority to the upper layer. As a result, the output of the comparator placed at the node of the highest layer has the highest priority. The priority information shown in FIG. 14 is described as having a higher priority as the value is lower.

  In a sorter using a binary tree, the time from when priority information is input to when the highest priority information is output is proportional to (log2 number of nodes of binary tree). For this reason, the sorter based on the binary tree can cope with a large number of priorities as compared with the priority encoder, and the number of priorities that can be practically used is several thousand, when applied to a queuing system. Corresponding communication speeds are about several hundred M to 1 Gbps. However, at present, a line having a communication speed of 10 G to 40 Gbps is practically used, and a high-speed sorter is required.

Algorithm acceleration includes parallel processing and pipeline processing. The speeding up by parallel processing means shortening the execution time of the algorithm by physically executing simultaneously the processes that do not depend on the execution order among the various processes constituting the algorithm, that is, the processes that can be executed simultaneously. Is the method. Therefore, whether or not the algorithm can be processed in parallel depends on the target algorithm. If the processes that make up the algorithm are sequential processes, that is, the processes depend on the execution order, and there are no processes that can be executed simultaneously, parallel processing cannot be performed.
Since the sorter based on the binary tree needs to sequentially compare the priority information from the lower layer to the upper layer, it is logically impossible to increase the speed by parallel processing.

The speeding up by pipeline processing is a method of improving the apparent processing capacity per unit time by dividing the processing that constitutes the algorithm into several stages and operating each stage processing independently. . It should be noted that pipeline processing does not reduce algorithm execution time. Whether the algorithm can be pipelined depends on the target algorithm. In pipeline processing, it is necessary that the processing of each divided stage can be executed independently.
Therefore, if the algorithm cannot be divided into several stages that can operate independently, for example, if a variable referenced in the initial stage of the algorithm is updated in the final stage of the algorithm, it can be pipelined. Can not.

  Since the sorter based on the binary tree needs to sequentially compare the priority information from the lower layer to the upper layer, if the processing is divided into layers and operated independently, the comparison result of the lower layer Is propagated to a higher layer and there is a possibility that higher priority information is input until the highest priority information is output. That is, in this case, the priority information is not always the highest priority when the comparator of the highest layer identifies the priority information. For this reason, the sorter based on the binary tree cannot improve the processing capacity by pipelining.

By the way, when the sorter based on the binary tree is realized by software, the priority information having the higher priority is used as the comparison result instead of the comparator in the implementation example of the sorter based on the binary tree (see FIG. 14). Be placed. For this reason, when the sorter based on the binary tree is realized by software, there is a problem that a memory of about twice the number of corresponding priority information is required.
Non-Patent Document 1 discloses a sorter using a heap as a method for solving this problem and realizing a sorter with a memory having a corresponding number of priority information. The heap is composed of a heap structure which is a kind of data structure based on a binary tree and an algorithm for inputting / outputting priority information to / from the heap structure.

  FIG. 15 is an explanatory diagram illustrating an example of a heap structure. In FIG. 15, circles indicate priority information, and links indicate the vertical relationship between the priority information. In the priority information, the lower the value, the higher the priority. Priority information above certain priority information is called “parent”, and lower priority information is called “child”.

  FIG. 16 is an explanatory diagram showing the parent-child relationship of priority information in the heap structure. As shown in FIG. 16, one priority information can have a maximum of two priority information as children. In the heap structure, when the priority information has a child, the priority information is arranged so that the priority information is equal to or higher than the priority of the child. Therefore, the highest priority information is the highest priority. When certain priority information has two children, it should be noted that the magnitude relationship of priority is not particularly defined between the children. It should also be noted that information with the same priority is not necessarily located in the same layer. There are many implementation methods for the heap structure, but when the implementation is implemented by an array, priority information is identified by an address.

FIG. 17 is an explanatory diagram showing an example of a heap structure realized by an array. As shown in FIG. 17, the address of the highest priority information is set to 1, and hereinafter, addresses are sequentially assigned from the upper layer to the lower layer and from the left priority information to the right. As a result, in the realization of the heap structure by the array, the priority information is arranged left justified from the lower address to the upper address. In FIG. 17, the priority information of address 1 is the leftmost priority information, priority information of address 12 is the rightmost priority information, address 13 is the leftmost free information, and address 15 is the rightmost free information. Call.
Insertion processing that inputs priority information to the heap structure by the array, and deletion processing that outputs the highest priority information from the heap structure, the priority information of the parent is higher than the priority of the child in the heap structure of the array The priority information is rearranged so as to maintain the relationship in which the priority information is arranged left-justified.

An algorithm for inserting priority information into the heap structure is realized by searching for an appropriate insertion address of input priority information. An algorithm for inserting priority information is shown below.
(A) The initial value of the insertion position is the leftmost empty information.
(B) When the priority of the input priority information is equal to or lower than the priority of the parent of the insertion position, or when the insertion position is the highest priority information, the input priority information is moved to the insertion position. Stop. (C) When the priority of the input priority information is higher than the priority of the parent of the insertion position, the priority information of the parent of the insertion position is moved to the insertion position, and the next insertion position is changed to the parent (before movement). The position of
(D) Repeat (b) and (c) until stopped.
18 is an explanatory diagram illustrating an example of an algorithm when information of priority 7 is inserted into the heap structure illustrated in FIG. 17, and FIG. 19 is an explanatory diagram illustrating the heap structure after information is inserted in FIG. FIG.

The algorithm for deleting the highest priority information from the heap structure is realized by deleting the highest priority information and searching for an appropriate insertion address of the rightmost priority information. The algorithm for deleting priority information is shown below.
(A) The highest priority information is deleted and output. As a result, when the number of priority information stored in the heap structure becomes zero, the process is stopped.
(B) The rightmost priority information is deleted and used as priority information to be inserted.
(C) The initial value of the insertion position is the highest priority information.
(D) When the priority of the priority information to be inserted is equal to or higher than the priority of all the children at the insertion position, or when the priority information at the insertion position has no children, the priority information to be inserted is moved to the insertion position. Then stop.
(E) If the priority of the priority information to be inserted is lower than the priority of at least one child, move the child (the one with higher priority when there are two children) to the insertion position, and then insert the next The position is the child position (before movement).
(F) Repeat (d) and (e) until stopped.

20 is an explanatory diagram showing an example of an algorithm for deleting information having the highest priority from the heap structure shown in FIG. 17, and FIG. 21 is an explanatory diagram showing the heap structure after information is deleted in FIG. It is.
As described above, the heap sorter requires about half the memory required for the sorter based on the binary tree, which increases the use efficiency of resources. In addition, when the heap structure is realized as an array, priority information is arranged from the lower address to the upper address in a left-justified manner, so it becomes very easy to manage the free area of the memory, and high-speed operation is possible. In the point.

Whether a binary tree sorter is implemented in hardware or software, it is necessary to manage whether priority information is stored for each node on which binary tree priority information is placed. is there. For example, when the value stored in the priority information is a specific value (for example, the highest value), it is determined that the priority information is not stored, or the value of a specific bit constituting the storage of the priority information ( For example, it is necessary to determine that priority information is not stored by the most significant bit).
Furthermore, in order to quickly identify a node in which priority information is not stored, it may be necessary to manage the address of a node in which priority information is not stored using a FIFO (First In First Out) queue or the like. Such processing greatly hinders speeding up when dealing with a large number of priorities.

On the other hand, when the heap structure is realized as an array, the priority information is arranged left-justified. Therefore, the management of the free area of the array memory sets the pointer indicating the start position of the free area to the memory, and the pointer It is sufficient if the memory in the subsequent areas is free. For this reason, the sorter by heap is suitable for mounting by hardware from the point that the use efficiency of resources such as memory is high and the management of the free area of the memory is very easy.
The heap sorter described above has several thousand priority levels that can be practically used, and the communication speed that can be handled when applied to a queuing system is about 1 Gbps. Currently, the communication speed is 10 G to 40 Gbps. Lines are put into practical use, and heap sorters are also required to be sped up.

  However, in a sorter using a heap based on the above operating principle, the algorithm for inserting priority information and the algorithm for deleting priority information cannot be executed in an overlapping manner, so it is logical to improve processing capacity by pipelining. Is impossible. This is because when the priority information is inserted into the heap structure, the movement of the priority information from the upper layer to the lower layer is sequentially performed from the lower layer to the upper layer. This is because the movement of the priority information from the lower layer to the upper layer when the priority information is deleted from the heap structure is sequentially executed from the upper layer to the lower layer.

  In order to solve this problem, Patent Literature 1, Patent Literature 2, and Non-Patent Literature 2 disclose a method of correcting the heap sorter algorithm into a pipeline. Since Patent Document 1 and Patent Document 2 logically describe the same device from different viewpoints, the following description will be given with reference to Patent Document 2. Non-Patent Document 2 discloses techniques related to claims 1 to 9 and 14 to 17 of Patent Document 2.

  FIG. 22 is an explanatory diagram showing an algorithm for deleting the highest priority information from the sorter by heap described in Patent Document 2, and FIG. 23 shows a state after deletion of the heap structure shown in FIG. It is explanatory drawing which shows. As shown in FIG. 22, the algorithm for deleting the highest priority information from the heap sorter described in Patent Document 2 first deletes and outputs the highest priority information. If there is a child of the deleted priority information, the operation of deleting the child with the higher priority, outputting it to the upper layer, and moving is repeated from the upper layer to the lower layer.

  FIG. 24 is an explanatory diagram showing an algorithm for inserting priority information in a heap sorter described in Patent Document 2 in a heap structure. FIG. 25 is a diagram after insertion of the heap structure shown in FIG. It is explanatory drawing which shows a state. As shown in FIG. 24, in the algorithm for inserting priority information into the sorter by heap described in Patent Document 2, the priority information input first is compared with the highest priority information and input. If the priority of the information is higher, the input priority information is inserted at the position of the compared information, and the compared priority information is output to the lower layer. Otherwise, the input priority information is input to the lower layer. Output to. In the following layers, one of the priority information children compared in the upper layer is selected, compared with the priority information output from the upper layer, and the same processing is sequentially repeated.

As a method of selecting priority information to be compared from child information of priority information compared in an upper layer in layers other than the highest layer, basically two methods are shown. One is that each node of the heap structure stores a difference between the number of priority information stored under the left child node of the node and the number of priority information stored under the right child node. In this method, the child with the smaller number of priority information stored under it is selected as the priority information to be compared (claims 10 to 13 of Patent Document 2). The algorithm shown in the heap structure of FIG. 24 is described based on this method.
Another method is to select a node in which the priority information is not stored in the lowest layer by some method, and the priority information from the node to the highest node is used as the priority information to be compared. This is a selection method (see claims 4 to 9 of Patent Document 2).

As is clear from the above, the priority information insertion processing and deletion processing in the sorter using the heap described in Patent Document 2 are executed sequentially from the highest layer to the lower layer for each layer. The apparent processing capability per unit time can be improved by pipeline processing by overlapping processing for each layer.
Japanese Patent Laid-Open No. 10-336215 Japanese Patent Laid-Open No. 10-336216 JP 2004-23809 A J. et al. W. J Williams. “Heathsort,” CACM, Vol. 7, no. 6, June 1964. Tuan Ha-douch, and Serafim Soares Moreira, “The heap-sort based ATM cells spacer,” 1999 2nd International Conference on ATM, ICATM '99, June 1999.

  However, since the sorter based on the heap described in Patent Document 2 has modified the sorter algorithm based on the heap described in Non-Patent Document 1, the arrangement of the priority information is not left-justified. For this reason, the sorter using a heap described in Patent Document 2 manages whether or not priority information is stored for each node on which heap structure priority information is arranged, as with a binary tree sorter. ing. Specifically, in paragraph number 0005 of Patent Document 2, if the value stored in the priority information is a specific value (for example, the highest value), it is determined that the priority information is not stored, Disclosed is a method for determining that priority information is not stored based on the value of a specific bit (for example, the most significant bit) constituting the storage of degree information.

  The former method presents a major problem when this sorter is used in a tagged queuing system. As described above, the tagging type queuing system assigns packet transmission timing to a packet as a tag. For this reason, when a specific value cannot be used as the packet transmission timing, it is necessary to modify the transmission timing calculation method accordingly.

Further, the transmission timing is expressed by a numerical value having a finite word length, whether it is virtual time or real time. For this reason, as disclosed in Patent Document 3, in the implementation of this queuing system, when the value of the transmission timing given to the packet exceeds the maximum value as time elapses, the wraparound returns to the initial value. The phenomenon will occur. In order to solve this problem, it is necessary to compare the values of transmission timings and modify various parameters according to the occurrence of wraparound. At this time, if a specific value cannot be used as the transmission timing, there arises a problem that the correction processing accompanying the wraparound becomes complicated.
In the latter method, since one bit of priority information is used for identifying the presence / absence of information, there is a problem that the range of numerical values that can be expressed by priority information is halved and resource use efficiency is lowered.

Further, in the insertion processing of the sorter by heap described in Patent Document 2, the priority information to be compared is selected from the child information of the priority information compared in the upper layer. A method of storing, in each node of the heap structure, the difference between the number of priority information stored under the left child node of the node and the number of priority information stored under the right child node It is unrealistic to use.
In this case, it is necessary to provide a counter that counts the difference in the number of stored information at each node other than the top level of the heap structure. If the heap structure is made to support thousands of priorities, the amount of resources required for implementation is enormous. It will become something.

In addition, the method of selecting a node in which priority information is not stored in the lowest layer using a FIFO queue or the like described in claims 4 to 9 of Patent Document 2 increases resources required for implementation, It will be a big hindrance to speedup. Furthermore, in this method, as described in claim 5 of Patent Document 2, when a node for which the lowest priority information is not stored is selected for insertion processing, the node continues until the insertion processing ends. Must not be selected again. This is because if the same node is selected in a short time, the movement of the priority information to the lower layer may overflow.
For this reason, as described in claim 5 of Patent Document 2, nodes for which priority information is not stored must be managed separately from the node selected for insertion processing and the other nodes. Furthermore, the implementation is inevitably complicated.

Further, as described above, pipeline processing improves the apparent processing capability, but does not reduce the algorithm execution time. For this reason, if a node for which the lowest priority information is not stored is selected for insertion processing, a considerable amount of time until the insertion processing ends, for example, if the heap structure is associated with 4095 priority, The node cannot be selected for a new insertion process until all 12 layers have been processed.
For this reason, as described in paragraph No. 0064 of Patent Document 2, when the priority information stored in the heap structure is almost full, insertion processing may not be performed, and the heap structure is completely used. The problem that it is not possible arises.

  As is clear from the above, the sorter using a heap described in Patent Document 2 corrects the algorithm of the sorter using heap described in Non-Patent Document 1 in order to realize pipelining. As a result, the large feature of the sorter by the heap described in Non-Patent Document 1 that the management of the free area of the memory is very easy is lost, and many resources and complicated processing are required for the realization. Therefore, there is a problem that it becomes a great obstacle to speeding up.

  An object of the present invention is to realize an apparatus for storing information of a binary tree structure necessary for parallelizing a sorter algorithm using a heap described in Non-Patent Document 1, and further described in Non-Patent Document 1. With the parallel processing algorithm that takes advantage of the features that the use efficiency of resources such as memory in the sorter based on the heap and the management of the free space of the memory are very easy, the sorter execution time by the heap is shortened. By providing an apparatus for storing binary tree structure information and an apparatus for storing heap structure information that can store a large number of priorities with a small number of resources and that can store high-speed heap structure information. is there.

In order to achieve the above object, an apparatus for storing information of a binary tree structure according to the present invention is composed of N memory devices, and the layers corresponding to each of the memory devices are layer 0 to layer N-1. The memory device corresponding to layer 0 stores a single piece of information, and the memory device corresponding to layer i where (1 ≦ i ≦ N−1) identifies the information with an i-bit address, A division operator whose quotient is an integer value rounded down to the nearest decimal point is “/”, the information identified by address 0 or address 1 of the memory device corresponding to layer 1 is the first information, and the layer 0 corresponds When the memory device information is the second information, the second information is a parent of the first information, the first information is a child of the second information, and ( Memory device corresponding to layer j satisfying 2 ≦ j ≦ N−1) When the information identified by the address A is the third information and the information identified by the address A / 2 of the memory device corresponding to the layer j−1 is the fourth information, the fourth information is Distributed memory means for identifying a correspondence relationship between a parent and a child in information of a binary tree structure based on a second relationship in which the third information is a child of the fourth information; , (B) is input to the address of the memory device of the distributed memory means corresponding to the layer L satisfying (1 ≦ L ≦ N−1), corresponding to the layer k satisfying (1 ≦ k ≦ L−1). Corresponding to layer 1 from the information of address B of the memory device of the distributed memory unit corresponding to layer L by inputting B / 2 ^(Lk) to the address of the memory device of the distributed memory unit, respectively. Address B / 2 of the memory device of the distributed memory means ^(L− It is characterized in that it comprises address input means for simultaneously selecting information in the parent-child correspondence relationship up to ¹⁾ .

  An apparatus for storing heap structure information according to the present invention stores heap structure information in which the information stored in the binary tree structure information according to claim 3 or 4 is a heap structure. When the number of pieces of information stored in the memory device of the distributed memory unit corresponding to layer 0 is 1 when outputting information from the distributed memory unit, the device corresponds to layer 0. The information stored in the memory device of the distributed memory means is deleted and output, and as a result, the number of information stored in the memory device of the distributed memory means corresponding to layer 0 to layer N-1 is all zero The output of information from the distributed memory means is terminated, and the number of information stored in the memory device of the distributed memory means corresponding to the layer S satisfying (1 ≦ S ≦ N−1) is one or more. State If the number of pieces of information stored in the memory device of the distributed memory unit corresponding to the layer S + 1 is 0 or the layer S is the layer N-1, the layer S corresponds to the layer S. If the value of the number of information stored in the memory device of the distributed memory means is C, the information at the address C-1 of the memory device of the distributed memory means corresponding to the layer S is deleted and inserted as information. Information output means and the number of information stored in the memory device of the distributed memory means corresponding to the layer T satisfying (1 ≦ T ≦ N−1) as a result of deletion of information by the information output means is 1 or more And the number of pieces of information stored in the memory device of the distributed memory means corresponding to layer T + 1 is 0, or the layer T is layer N-1, the layer T versus If the number of information stored in the memory device of the distributed memory means is larger than the value of the address corresponding to the layer T generated by the address generating means, the address corresponding to the layer T generated by the address generating means is Input to the address of the memory device of the distributed memory means corresponding to the layer T; otherwise, the address corresponding to the layer T-1 generated by the address generating means is set to the distributed memory corresponding to the layer T-1 First comparison information selecting means for inputting the address of the memory device of the means, and simultaneously selecting the information of the memory device of the distributed memory means corresponding to layer T to layer T or layer T-1 by the address input means And when the information is selected by the first comparison information selecting means, the information is selected from the memory device of the distributed memory means. All the read information is read and compared with the information to be inserted. If the priority of the information to be inserted is higher than the read information, the priority is higher, otherwise the priority is lower, or the information is inserted from the read information. If the priority of the information is equal or higher, the priority is higher, otherwise the priority is lower. As a result of the comparison, the information to be inserted has lower priority than the information read from the layer U. If the information to be inserted has higher priority than the read information, or the memory device information of the distributed memory means corresponding to the layer U + 1 is not selected, or the layer U is the layer N-1, the layer 1 The information read out from the memory device of the distributed memory means corresponding to layer 0 is written, and if (U ≧ 2), the layer from layer 2 to layer U The read information is written in the memory device information of the distributed memory unit corresponding to the layer U-1 from the layer 1 selected by the first comparison information selection unit, and the first comparison information selection unit When the information to be inserted is written in the information of the memory device of the distributed memory unit corresponding to the layer U selected by the above-described information, and the information to be inserted has higher priority than the information read from the layer 1 as a result of comparison, Alternatively, when information is not selected by the first comparison information selection unit, the first information movement unit writes the information to be inserted into the information of the memory device of the distributed memory unit corresponding to the layer 0. It is characterized by being configured.

  According to the present invention, since the sorter by heap is realized by parallel processing that physically executes simultaneously executable processes, the execution time is greatly shortened and the speed is increased. Further, like the sorter using a heap described in Non-Patent Document 1, it has a feature that the use efficiency of resources such as a memory is high and a management of a free area of the memory is very easy. As a result, a device for storing the binary tree structure information necessary for parallelizing the sorter algorithm based on the heap described in Non-Patent Document 1 is realized. Further, the heap described in Non-Patent Document 1 is realized. By using a parallel processing algorithm that takes advantage of the high efficiency of using resources such as memory and the ability to manage free memory space very easily, the sorter execution time by heap can be shortened with less resources. It is possible to store information of a high-speed heap structure corresponding to a large number of priorities.

The best mode for carrying out the present invention will be described below with reference to the drawings.
An apparatus for storing information of a binary tree structure according to an embodiment of the present invention includes N memory devices, and when the memory devices respectively correspond to layers 0 to N-1, The memory device corresponding to layer 0 stores a single piece of information, and the memory device corresponding to layer i satisfying (1 ≦ i ≦ N−1) identifies information by an i-bit address, Is a division operator whose quotient is the integer value obtained by truncating, “0”, the address 0 of the memory device corresponding to layer 1 or the information identified by address 1 is the first information, and the memory device corresponding to layer 0 The second information is the parent of the first information, the first information is a child of the second information, and (2 ≦ address of the memory device corresponding to layer j where j ≦ N−1) When the information identified by A is the third information and the information identified by the address A / 2 of the memory device corresponding to the layer j−1 is the fourth information, the fourth information is the third information. Distributed memory means for identifying the correspondence relationship between the parent and the child in the binary tree structure information based on the second relationship in which the third information is a child of the fourth information; When B is input to the address of the memory device of the distributed memory means corresponding to the layer L satisfying 1 ≦ L ≦ N−1), the distribution corresponding to the layer k satisfying (1 ≦ k ≦ L−1) By inputting B / 2 ^(L−k) to the addresses of the memory devices of the memory means, the information corresponding to the layer 1 is obtained from the information of the addresses B of the memory devices of the distributed memory means corresponding to the layer L. It reaches the address B / 2 ^(L-1) of the memory device of the distributed memory means. The present invention is characterized by comprising address input means for simultaneously selecting information in the parent-child correspondence relationship.

  An apparatus for storing heap structure information according to an embodiment of the present invention is an apparatus for storing heap structure information in which information stored in the apparatus for storing binary tree structure information is a heap structure. When the number of pieces of information stored in the memory device of the distributed memory means corresponding to layer 0 is 1 when outputting information from the distributed memory means, the distributed memory corresponding to layer 0 When the information stored in the memory device of the means is deleted and output, and as a result, the number of information stored in the memory device of the distributed memory means corresponding to the layer 0 to the layer N-1 is all zero The output of information from the distributed memory means is terminated, and the number of information stored in the memory device of the distributed memory means corresponding to the layer S satisfying (1 ≦ S ≦ N−1) becomes one or more. In case When the number of pieces of information stored in the memory device of the distributed memory unit corresponding to the layer S + 1 is 0, or the layer S is the layer N-1, the distributed memory corresponding to the layer S If the value of the number of information stored in the memory device of the means is C, the information output means for deleting the information of the address C-1 of the memory device of the distributed memory means corresponding to the layer S and making it information to be inserted And the number of pieces of information stored in the memory device of the distributed memory unit corresponding to the layer T satisfying (1 ≦ T ≦ N−1) is 1 or more as a result of deletion of information by the information output unit And when the number of pieces of information stored in the memory device of the distributed memory unit corresponding to the layer T + 1 is 0, or when the layer T is the layer N−1, the information corresponding to the layer T If the number of pieces of information stored in the memory device of the distributed memory means is larger than the value of the address corresponding to the layer T generated by the address generating means, the address corresponding to the layer T generated by the address generating means is Input to the address of the memory device of the distributed memory means corresponding to T, otherwise the address corresponding to the layer T-1 generated by the address generating means is the address of the distributed memory means corresponding to the layer T-1. First comparison information selection means for inputting the address of the memory device and simultaneously selecting information of the memory device of the distributed memory means corresponding to layer T to layer T or layer T-1 by the address input means; When the information is selected by the first comparison information selection means, all the information selected from the memory device of the distributed memory means If the priority of the information to be inserted is higher than the read information, the priority is lower. Otherwise, the priority of the information to be inserted is higher than the read information. If the degree is high or equal, high priority is given, otherwise low priority is given, and as a result of comparison, the information to be inserted has lower priority than information read from layer U, and information read from layer U + 1 If the information to be inserted has high priority, or the information of the memory device of the distributed memory means corresponding to layer U + 1 is not selected, or layer U is layer N-1, read from layer 1 Information is written in the information of the memory device of the distributed memory means corresponding to layer 0. When (U ≧ 2), the information is read from layers 2 to U Information is written in the memory device information of the distributed memory unit corresponding to layer U-1 from layer 1 selected by the first comparison information selection unit, and by the first comparison information selection unit When the information to be inserted is written in the information of the memory device of the distributed memory means corresponding to the selected layer U and the information to be inserted has higher priority than the information read from layer 1 as a result of comparison, or When information is not selected by the first comparison information selection unit, the first comparison information selection unit includes a first information moving unit that writes the information to be inserted into the information of the memory device of the distributed memory unit corresponding to the layer 0. It is characterized by comprising.

An outline of a parallelized algorithm when inserting priority information into a sorter by heap according to the present invention will be described below.
FIG. 1 shows an outline of a parallelized algorithm when priority information is inserted into a sorter by heap according to the present invention, (a) is an explanatory diagram for determining an insertion position, and (b) is an insertion position. It is explanatory drawing of the movement to. FIG. 1 shows an example in which information of priority 7 is inserted into the heap structure shown in FIG.

  As shown in FIG. 1A, in the present invention, when priority information is inserted, first, information having a parent-child relationship from the leftmost empty information to the highest priority information is selected. The insertion priority is determined by simultaneously comparing the selected priority information of each layer excluding the leftmost empty information and the input information. Next, as shown in FIG. 1B, the selected priority information below the insertion position is moved to the lower layer, and the input information is moved to the insertion position.

FIG. 2 shows an outline of a parallelized algorithm for removing the highest priority from a sorter by heap according to the present invention, (a) is an explanatory diagram of determination of an insertion position, and (b) is an insertion It is explanatory drawing of the movement to a position. FIG. 2 shows an example in which information having the highest priority is deleted from the heap structure shown in FIG.
As shown in FIG. 2A, in the present invention, the highest priority information is deleted and output. If the number of priority information stored in the heap structure becomes 0 as a result of the deletion, the deletion process is terminated. Otherwise, the rightmost priority information is deleted and moved to the priority information to be inserted. To do. In addition, priority information is selected from the layer next to the highest layer toward the lower layer, and compared with the priority information to be inserted, the insertion position is determined.

  Next, as shown in FIG. 2B, the selected priority information above the insertion position is moved to the upper layer, and the information to be inserted is moved to the insertion position. The specific method of selecting the priority information to be compared with the priority information to be inserted is to select the one with the higher priority when there are two pieces of priority information in the next highest layer (the priority is If the priority information is present, the priority information is selected. If the priority information is not present, the selection is terminated. And in the layers below that, if there is two priority information with the priority information selected in the upper layer as a parent, select the higher priority (optional if the priority is the same) And when one exists, the priority information is selected, and when it does not exist, the selection is terminated.

  As apparent from the above operation, the sorter algorithm based on the heap described in Non-Patent Document 1 is a sequential process, whereas the present invention is a parallel process that physically executes simultaneously executable processes. Since the processing implements a sorter using a heap, the execution time is greatly shortened and the speed is increased. Furthermore, the sorter using a heap based on pipeline processing described in Patent Literature 1, Patent Literature 2, and Non-Patent Literature 2 requires a lot of resources and complicated processing for managing the free area of the memory. On the other hand, the present invention, like the sorter using a heap described in Non-Patent Document 1, has features such as high use efficiency of resources such as memory and very easy management of free areas of memory. The most different point is that it is possible to provide a device that can store a high-speed heap structure information with a small number of resources, corresponding to a large number of priorities.

  FIG. 3 is an explanatory diagram showing an example of the data structure of the apparatus for storing the binary tree structure information according to the present invention. The data structure of the apparatus for storing binary tree structure information according to the present invention in FIG. 3 is an example in which the apparatus for storing binary tree structure information is composed of four layers (claims 1 and 3). The uppermost layer is designated as layer 0, the layers 1 and 2 are designated in this order, and the lowest layer is designated as layer 3.

  As shown in FIG. 3, each layer has a memory device that stores information, and layer i stores 2i pieces of information. The address of the memory for storing information is set to 0 for identifying the leftmost information in the layer, and is sequentially assigned below. Since the maximum number of pieces of information stored in the memory device of the highest layer is 1, it can be realized by a memory device that does not have an address input or by a memory device in which the address input value is only 0. It is self-evident that it is logically equivalent and the claims of the present invention include both cases. The distributed memory means is constituted by these memory devices.

  The distributed memory means stores the binary tree structure information. When there is a layer above the information stored in the address A of the memory device of a certain layer, the distributed memory means stores the information of the memory device of the upper layer. Parent information is stored at address A / 2. Therefore, the parents of the information stored at addresses a and a + 1, where a is an even number, are the same information, and these information are children of the information of the parent.

As shown in FIG. 3, each layer other than the top layer may have a memory device that stores the comparison results, and the layer m stores 2 ^m−1 comparison results. Since the maximum number of comparison results stored in the memory device of layer 1 is 1, even if it is realized by a memory device having no address input or by a memory device in which the value of the address input is only 0, It is logically equivalent and it is obvious that the claims of the present invention include both cases. The comparison result memory means is constituted by these memory devices.

This comparison result memory means corresponds to the binary tree structure information stored in the distributed memory means. The comparison result stored at the address D of the memory device of the comparison result memory means of a certain layer corresponds to the comparison result of the information stored at the addresses 2D and 2D + 1 of the memory devices of the distributed memory means of the same layer.
An apparatus for storing binary tree structure information according to claims 2 and 4 of the present invention is an apparatus for storing binary tree structure information according to claims 1 and 3, respectively. This is a device in which the relationship between the upper and lower bits of the address input bits of the memory device is reversed and is logically equivalent. Therefore, the description is omitted.

  FIG. 4 is an explanatory diagram showing an embodiment of an apparatus for storing binary tree structure information and an apparatus for storing heap structure information according to the present invention. FIG. 4 shows an example in which the device is composed of 6 layers, each layer having a memory device of distributed memory means, and each layer other than the highest layer having a memory device of comparison result memory means. May be.

  In FIG. 4, data_in input is a signal used when information is input to the distributed memory means. The data_out output is a signal used when outputting information having the highest priority from the distributed memory means. The comparison_data_bus is a bus that supplies information to be inserted or information to be input to each layer. push_pop_address_bus is a bus that supplies an address for selecting information to be inserted or information to be compared with the value of the input information to each layer other than layer 0. The pop_address output used by the address input means is an address generator. The address generated by the means is a signal indicating the lower layer.

The empty output is a signal indicating to the upper layer that the number of pieces of information stored in the memory device of the distributed memory means corresponding to the layer that outputs the empty output is empty, and the information output means and the first comparison information Used in selection means. The full output is a signal indicating to the lower layer that the number of pieces of information stored in the memory device of the distributed memory unit corresponding to the layer that outputs the full output is full, and is used by the second comparison information selecting unit. Is done.
The pop output is a signal indicating to the upper layer that the layer that outputs this is the source of information movement, and is used by the first information moving means. The push output is a signal indicating to the lower layer that the layer that outputs this is the source of information movement, and is used by the second information moving means. The pop_data output is a signal indicating moving information to the upper layer, and is used by the first information moving means. The push_data output is a signal indicating information to be moved to the lower layer, and is used by the second information moving means.

The information output means, the first comparison information selection means and the first information movement means according to claim 5 of the apparatus for storing the information of the heap structure of the present invention, similar to the sorter using a heap in Non-Patent Document 1, The second comparison information selecting unit and the second information moving unit according to claim 6 both maintain a relationship in which the priority of the parent is equal to or higher than the priority of the child, and the relationship in which the information is arranged left-justified. To rearrange the information. That is, the information of the apparatus for storing the heap structure information of the present invention is sequentially arranged from the upper layer to the lower layer, and from address 0 in the layer.
Therefore, in the apparatus for storing heap structure information according to the present invention, when the information input / output processing is not performed, if the information count of a certain layer is full, the information count of the further layers is also full. Become. Further, if the number of information of a certain layer is empty, the number of information of the layers below that is also empty.

  Therefore, in the layer having the leftmost empty information, the number of information is not full and the number of information in the layer above it is full, so that (full output = FALSE AND full input = TRUE) is established. However, the uppermost layer has the leftmost empty information if (full output = FALSE) is established. Alternatively, it may be considered that (full input = TRUE) always holds in the highest layer. It is obvious that the claims of the present invention include any case. Further, although it is not necessary to output full in the lowest layer, a signal corresponding to full output is created inside the layer in order to determine that the layer has the leftmost empty information.

  In the layer having the rightmost information, the number of information is not empty, and the number of information in the layer below it is empty, so that (empty output = FALSE AND empty input = TRUE) holds. However, the lowest layer has the rightmost information if (empty output = FALSE) is satisfied. Alternatively, it may be considered that (empty input = TRUE) always holds in the lowest layer. It is obvious that the claims of the present invention include any case. In addition, although it is not necessary to output empty in the highest layer, a signal corresponding to the empty output is created inside the layer in order to determine that the layer has the rightmost information.

  The first comparison information selecting means according to claim 5 of the present invention is a parent-child information from the layer 1 to the layer having the rightmost information or the layer having the rightmost information. When the first information moving means compares the selected information with the information to be inserted, if the latter has a low priority, the first information moving means sets (pop output = TRUE). Here, in the apparatus for storing the information of the heap structure of the present invention, when the information input / output processing is not performed, the parent priority is higher than the child priority. For this reason, when the latter has a low priority as a result of comparison between the selected information of a certain layer and the information to be inserted, the latter has a low priority in the layers beyond that.

  Therefore, the layer that becomes the insertion position of the information to be inserted is a layer in which the information to be inserted as a result of comparison has a low priority, and the information to be inserted as a result of the comparison has a high priority in the layer below it, or In the lower layer, the information is not selected, that is, (pop output = TRUE AND pop input = FALSE). However, in the lowest layer, if (pop output = TRUE) is established, it becomes an insertion position. Alternatively, it may be considered that (pop input = FALSE) is always established in the lowest layer. It is obvious that the claims of the present invention include any case. Further, the layer that becomes the source of information transfer to the upper layer is the layer that becomes (pop output = TRUE), and the layer that becomes the destination of information transfer from the lower layer becomes the layer that becomes (pop input = TRUE).

  When the second comparison information selecting means according to claim 6 of the present invention selects information in a parent-child relationship from the layer 0 to the leftmost empty information, the second information moving means When the input information is compared with information selected by the layer up to the layer having the leftmost empty information, that is, (full output = TRUE), and the latter has high priority (push output = TRUE). Here, in the apparatus for storing the information of the heap structure of the present invention, when the information input / output processing is not performed, the parent priority is higher than the child priority. For this reason, if the latter is a high priority as a result of comparison between selected information of a certain layer and input information, the latter is also a high priority in the layers below it.

  Therefore, the layer that is the insertion position of the information to be input is (1) the information that is input as a result of the comparison has a high priority, and the information that is input as a result of the comparison has a low priority in the layer above it. Layer, that is, (push input = FALSE AND push output = TRUE), or (2) the leftmost layer that has empty information, and the information input as a result of comparison is low in the layer above it. It becomes a layer to be a priority, that is, (push input = FALSE AND layer having leftmost empty information).

In the case of (1), the selected information below the layer is moved to the lower layer. However, in layer 0, if (push output = TRUE) or (the layer having the leftmost empty information) is established, the input information is inserted. Alternatively, it may be considered that (push input = FALSE) always holds in layer 0. It is obvious that the claims of the present invention are encompassed in any case. Also, the layer from which information is transferred to the lower layer is the layer that becomes (push output = TRUE), and the layer from which information is moved from the upper layer is the layer that is to be (push input = TRUE) Become.
In addition, when the priority is the same as a result of comparison between the information selected by the first information moving means and the second information moving means and the information to be inserted or the information to be inputted, either the low priority or the high priority is selected. It is obvious that the claims of the present invention include any case.

  FIG. 5 shows a memory device of distributed memory means, an address input means, a memory device of comparison result memory means in the device for storing binary tree structure information and the heap structure information shown in FIG. FIG. 6 is an explanatory diagram showing an example of wiring between the address generating means. In FIG. 5, the memory device of the distributed memory means is based on claim 1 or claim 3, and the memory device of the comparison result memory means is expressed as a comparison result memory.

  As shown in FIG. 5, the address input means is composed of push_pop_address_bus connecting each layer, and the input to the bus is the three-state buffer, the number of information of each layer, and the output of the memory device of the comparison result memory means. It is selected from the address generation means used. Also, for example, when B is input to the address of the memory device of the layer 4 distributed memory means, B / 2 is input to the address of the memory device of the layer 3 distributed memory means, and the memory of the layer 2 distributed memory means B / 4 is input to the address of the device, B / 8 is input to the address of the memory device of the distributed memory means of layer 1, and information having a parent-child correspondence relationship from layer 4 to layer 1 is simultaneously selected.

  Further, as shown in FIG. 5, the address generation means is composed of a pop_address signal between each layer. The comparison result stored in the memory device of the comparison result memory means shown in FIG. 5 is obtained when the even address side of the information stored in the memory device of the corresponding distributed memory means has high priority, or the odd address side. 0 when no information is stored, 1 when the odd address side has high priority, or 1 when the information is not stored on the even address side, and 0 or 1 otherwise. Of course, the stored comparison results may be stored in other expressions, and it is obvious that the claims of the present invention include such cases. In the device for storing heap structure information according to the present invention, information is stored left-justified, so information is stored on the odd address side, but there is no information stored on the even address side. do not do.

  In FIG. 5, when an address E is input from the upper layer to the address of the memory device of the comparison result memory means of a certain layer, the data output of the memory device is assigned to the least significant bit of the input address and the lower order Output to layer. As a result, if storage of the address 2E of the memory device of the corresponding distributed memory means has high priority, or if no information is stored in 2E + 1, the address 2E is generated and output, and storage of the address 2E + 1 has high priority In the case, the address 2E + 1 is generated and output. Otherwise, the address 2E or 2E + 1 is generated and output.

Further, as shown in FIG. 5, since the value of the bits other than the least significant bit of the address generated by a certain layer is the same as the value of the address generated by the upper layer, the address generating means generates from each layer. The least significant bit of the selected address is input to push_pop_address. For this reason, when the address value generated by a certain layer is input to push_pop_address_bus, the least significant bit of the address generated by each layer above that layer is input as shown in FIG. good.
Of course, if the value of the address generated by each layer is connected to each push_pop_address_bus via the three-state buffer and the value of the address generated by a certain layer is input to the push_pop_address_bus, the signal is sent by the three-state buffer of that layer. It is self-evident that the claims of the present invention encompass any method of implementation.

FIG. 6 shows an example of the logical correspondence between the input / output of push_pop_address_bus, the address input of the memory device of the distributed memory means, the number of priority information of each layer, the address input of the comparison result memory and the data output shown in FIG. It is explanatory drawing which shows. Here, the bits 0 to 4 of the input / output from the push_pop_address_bus are bits indicating the correspondence with the bus.
As shown in FIG. 6, bit 4 of the bus is input to address input A0 of the memory device of the distributed memory means of layer 1, A1 of layer 2, A2 of layer 3, A3 of layer 4, and A4 of layer 5, The other bits of the bus are also input.

In the device for storing information of the binary tree structure of the present invention, the value of the number of information stored in the memory device of the distributed memory means of each layer is required. In FIG. 6, bit 0 of the number of information indicates the least significant bit. The value of the information number of each layer may be stored for each layer as shown in FIG. Further, the number of information of the entire apparatus that stores the information of the binary tree structure may be stored, and the number of information of each layer may be generated therefrom, and the claims of the present invention encompass any case. That is obvious.
As shown in FIG. 6, bit 4 of the bus includes bit 0 of the number of information of layer 1, bit 1 of the number of information of layer 2, bit 2 of the number of information of layer 3, bit 3 of the number of information of layer 4, Bit 4 of the number of information of layer 5 is connected through a three-state buffer, and other bits of the bus are also connected.

As shown in FIG. 5, when the number of information of each layer is stored for each layer, the number of information that can be stored in the layer i is from 0 to 2 ⁱ . A word length of i + 1 bits is required. However, in the device for storing information of the binary tree structure of the present invention, the number of information is full, that is, it is impossible to input the number of information to the address input means from the layer i where the number of information is 2 ⁱ . As shown in FIGS. 5 and 6, the bits except the most significant bit of the number of information of each layer are connected to push_pop_address_bus via a three-state buffer, and the value of the number of information to be output to the address input means is selected.
Also, as shown in FIG. 6, the output of the memory device of the comparison result memory means of layer 1 is connected to bit 4 of the bus through a three-state buffer. Input to layer A1, layer 4 A2, and layer 5 A3, and other bus bits are also connected.

As described above, the apparatus for storing binary tree structure information according to claims 2 and 4 of the present invention is the binary tree structure according to claims 1 and 3, respectively. Is a device in which the relationship between the upper and lower bits of the address input bits of the memory device is reversed, and is logically equivalent. FIG. 7 shows the logical correspondence between the input / output of push_pop_address_bus, the address input of the distributed memory device, the number of information of each layer, the address input of the comparison result memory and the data output in this case.
FIG. 7 is an explanatory diagram showing an example in which the logical relationship between the input / output of push_pop_address_bus, the address input of the distributed memory device, the number of priority information of each layer, the address input of the comparison result memory and the data output is different. Note that the relationship shown in FIG. 7 is logically equivalent to the relationship shown in FIG.

  When the information stored in the memory device of the distributed memory means is updated, the comparison result of the memory device of the comparison result memory means is also updated. This is because when the information stored in the memory device of the distributed memory means is updated, if the parent information of the updated information has two children, the child information that is not the updated information is read from the memory device. And the result may be written into the memory device of the corresponding comparison result memory means. The address for reading the information to be compared from the memory device of the distributed memory device is an address obtained by inverting the least significant bit of the updated information address (see claim 3), or an address obtained by inverting the most significant bit (claim). 4).

  In the wiring example shown in FIG. 5, the address input used for updating the comparison result memory is not described because it becomes complicated. This is because the address input signal may be selected by adding a selector to the address input of the comparison result memory shown in FIG. 5, and the dual port memory is used to input the address at the time of update from another port. Obviously, the claims of the present invention are not limited to these examples.

  The operation of outputting information from the distributed memory means of the apparatus for storing heap structure information according to claim 5 of the present invention will be described. When the number of information stored in the memory device of the layer 0 distributed memory unit is 1, the information output unit deletes the stored information and outputs it from data_out. As a result, when the number of information stored in the memory devices of the distributed memory means of layer 0 to layer N-1 is all 0, that is, when (empty input = TRUE) in layer 0, information output Otherwise, the rightmost information is deleted from the information of the memory device of the distributed memory means of the layer having the rightmost information, output to comparison_data_bus, and broadcast to each layer as information to be inserted.

  It is not always necessary to delete the rightmost information from the memory device of the distributed memory means, and when the information is written to the memory device of the distributed memory means, the rightmost information is previously stored. Cached in a register or the like and output to comparison_data_bus may be performed from the cache, and it is obvious that the claims of the present invention include such a case.

  FIG. 8 is an explanatory diagram showing details of the information selection method shown in FIG. FIG. 8 shows a state after the rightmost information is deleted, and the number of information of layer 3 is four. In this example, the value of the address generated by the address generation means in layer 3 is 1 (001 in binary notation). As shown in FIG. 8, it should be noted that the number of information of the layer having the rightmost information is not always full. When the value of the generated address is smaller than the value of the number of information of this layer, valid information is stored in the address generated by the address generating means. Therefore, the layers having information to be compared with the information to be inserted are from layer 1 to the layer having the rightmost information.

  However, when the value of the generated address is equal to or greater than the value of the number of information of this layer, as is apparent from FIG. 8, no valid information is stored in the address generated by the address generation means. Therefore, the layer having information to be compared with the information to be inserted is from layer 1 to the layer above the layer having the rightmost information (in the case where the layer having the rightmost information is layer 1, The number of information of 1 is always greater than the address value generated by the layer 1 address generation means).

  In other words, the first comparison information selection means has the number of information stored in the memory device of the distributed memory means of the layer having the rightmost information as a result of the information output means deleting the information, and the address generation means of the layer When the value is larger than the generated address value, the value of this address is input to the address of the memory device of the distributed memory means of this layer. Otherwise, the value of the address generated by the address generation means of the layer is input to the address of the memory device of the distributed memory means of the layer above this layer.

  Thus, information having a parent-child relationship from the layer 1 to the layer having the rightmost information or the layer above the layer having the rightmost information is selected. Although this process is complicated at first glance, in the case of the wiring example shown in FIG. 5, in the layer where the number of priority information is full, the output of the comparison result memory is output to push_pop_address_bus, and the comparison result in the layer having the rightmost information This can be easily realized by determining whether the memory can be output.

  As described above, when the first comparison information selecting unit selects the information, the first information moving unit selects the layer having the rightmost information from the layer 1 or the layer having the rightmost information. The selected information up to the layer is read out and compared with the information to be inserted and inserted into the pop_data. If the latter has low priority, (pop output = TRUE) Shown in layer.

  Based on this, the layer that becomes (pop input = TRUE) inputs information from pop_data and writes it into the selected information or the memory device of the distributed memory means of layer 0. Also, the information to be inserted is written in the information selected by the layer that is the insertion position of the information to be inserted. When the information to be inserted has higher priority than the information read from the layer 1 or when the first comparison information selecting unit does not select the information, the first information moving unit is the layer 0 distributed memory unit. Write the information to be inserted into the memory device information.

The operation when inputting information to the distributed memory means of the apparatus for storing heap structure information according to claim 6 of the present invention will be described.
FIG. 9 is an explanatory diagram showing details of the information selection method shown in FIG. As shown in FIG. 9, in the layer Q having the leftmost empty information (layer 3 in the example of FIG. 9), the number of information in this layer cannot be full. The Q bit is the address of the leftmost empty information memory in the memory device of the distributed memory means of this layer.

  Therefore, this value is input to the address of the memory device of the distributed memory means of this layer, and information having the parent-child relationship of the information of layer 1 is selected from the leftmost free information of layer Q. Since 0 information is also parent information, it is selected. However, when the layer having the leftmost empty information is layer 0, that is, when the information stored in the device is empty, the insertion position of the input information is layer 0, and the comparison with the input information is performed. Since there is no information to perform, no information is selected.

  That is, when the second comparison information selection unit inputs information to the distributed memory unit, the input information is output from data_in to comparison_data_bus and broadcast to each layer. If the number of information stored in the memory device of the distributed memory means of layer 0 is 1, that information is selected, and if there is a layer having the leftmost empty information other than layer 0, the information is stored in that layer. The value of the number of information is input to the address of the memory device of the distributed memory means, and information from the layer 1 to the layer having the leftmost empty information is selected by the address input means.

As described above, when the second comparison information selecting unit selects information, the second information moving unit moves from the layer 0 to the layer having the leftmost empty information, that is, (full output = TRUE) is read out, the information selected by the layer is read out and compared with the information input and input to push_data. If the latter has high priority, it is set as (push output = TRUE) and becomes the source of information movement This is shown in the lower layer. Based on this, the layer of (push input = TRUE) inputs information from push_data and writes it into the selected information.
Further, the input information is written in the information selected by the layer that is the insertion position of the input information. When the second comparison information selecting unit does not select information, the second information moving unit writes the input information to the information of the memory device of the distributed memory unit of layer 0.

  As is apparent from the above, the present invention provides a device for storing binary tree structure information necessary for parallelizing a conventional sorter algorithm using a heap, and further, a memory or the like in a conventional sorter using a heap. By providing a device for storing heap structure information based on a parallel processing algorithm that takes advantage of the features of high resource usage efficiency and the features that make it very easy to manage free memory space, the execution time is shortened. Therefore, it is possible to realize a sorter using a high-speed heap that supports a large number of priorities with fewer resources.

It should be noted that, for various logical relationships described in the claims of the present invention, for example, addition / reduction of layers corresponding to the memory device from layer 1 to layer N, a memory device start address of 1, and the like All devices based on essentially the same logical relationship as the present invention obtained by performing subtraction, multiplication, division, inversion of logical values, inversion of upper and lower bits, or any combination thereof are included in the present invention. It is self-evident.
The present invention has been specifically described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. It is.

As described above, according to the apparatus for storing the information of the binary tree structure according to the present invention, it is constituted by N memory devices, and the memory devices respectively correspond to layers 0 to N−1. The memory device corresponding to layer 0 stores single information, and the memory device corresponding to layer i satisfying (1 ≦ i ≦ N−1) identifies the information with an i-bit address, and A division operator that uses an integer value obtained by rounding down the following as a quotient is “/”, the address 0 of the memory device corresponding to layer 1 or the information identified by address 1 is the first information, and the memory corresponding to layer 0 When the device information is the second information, the second information is a parent of the first information, the first information is a child of the second information, and (2 ≦ j ≦ N−1), the memory device corresponding to layer j In the case where the information identified by address A is the third information and the information identified by address A / 2 of the memory device corresponding to layer j−1 is the fourth information, the fourth information is the third information. Distributed memory means for identifying a correspondence relationship between a parent and a child in the binary tree structure information based on a second relationship in which the third information is a child of the fourth information; When B is input to the address of the memory device of the distributed memory unit corresponding to the layer L that satisfies (1 ≦ L ≦ N−1), the layer k that corresponds to (1 ≦ k ≦ L−1) By inputting B / 2 ^(Lk) to the addresses of the memory devices of the distributed memory means, it corresponds to the layer 1 from the information of the address B of the memory devices of the distributed memory means corresponding to the layer L. To the address B / 2 ^(L-1) of the memory device of the distributed memory means The present invention is characterized in that it comprises address input means for simultaneously selecting information having a correspondence relationship between the parent and child.

In addition, when the memory device includes N memory devices, and the layers corresponding to each of the memory devices are changed from layer 0 to layer N-1, the memory device corresponding to layer 0 stores a single piece of information (1 A memory device corresponding to layer i satisfying ≦ i ≦ N−1) identifies information by an i-bit address, and sets a remainder operator for obtaining a remainder of an integer value as “%” as a memory corresponding to layer 1 When the information identified by the device address 0 or address 1 is the first information and the memory device information corresponding to the layer 0 is the second information, the second information is the parent of the first information. In addition, the first information includes information identified by the first relationship that is a child of the second information and the address A of the memory device corresponding to the layer j that is (2 ≦ j ≦ N−1). The third information is the memory device corresponding to layer j-1. If the information identified by less A% 2 ^(j-1) and the fourth information, the information of said fourth parent information of the third information of said third said fourth information A distributed memory means for identifying a correspondence relationship between a parent and a child in the binary tree structure information based on the second relationship to be a child, and the distribution corresponding to the layer L that is (1 ≦ L ≦ N−1) When B is input to the memory device address of the memory means, B% ^2k is input to each of the memory device addresses of the distributed memory means corresponding to the layer k satisfying (1 ≦ k ≦ L−1). Thus, information on the correspondence relationship between the parent and the child from the information of the address B of the memory device of the distributed memory means corresponding to the layer L to the address B% 2 of the memory device of the distributed memory means corresponding to the layer 1 With address input means for selecting at the same time It is characterized by that.

In addition, when the memory device is composed of N−1 memory devices and the layers corresponding to the memory devices are changed from layer 1 to layer N−1, the memory device corresponding to layer 1 stores a single comparison result. The comparison result is a comparison result corresponding to the information identified by the address 0 and address 1 of the memory device of the distributed memory unit corresponding to the layer 1, and the layer m satisfying (2 ≦ m ≦ N−1). The corresponding memory device identifies the comparison result by an address of m−1 bits, and the comparison result identified by the address D is identified by the address 2D and address 2D + 1 of the memory device of the distributed memory means corresponding to the layer m. When the information stored in the memory device of the distributed memory unit is updated, the comparison result corresponding to the information is updated. Based on the comparison result stored in the memory device of the comparison result memory unit corresponding to layer 1 and the memory device of the distributed memory unit corresponding to layer 1 If the information identified by address 0 has high priority, or there is no information identified by address 1, the generated address is 0, which is identified by address 1 of the memory device of the distributed memory means corresponding to layer 1 If the information to be generated has high priority or there is no information identified by address 0, the generated address is 1, otherwise the generated address is either 0 or 1 (2 ≦ p to ≦ N-1) and comprising addresses of a memory device of the comparison result memory means corresponding to the layer p, enter the address E _p-1 corresponding respectively to the layer p-1 Based on the comparison result selected by the, it generates each address corresponding to the layer p, information high priority identified by the address 2E _p-1 of the memory device of the distributed memory means corresponding to the layer p, or address If there is no information identified by 2E _p−1 +1, the generated address is 2E _p−1 , which is identified by the address 2E _p−1 +1 of the memory device of the distributed memory means corresponding to layer p. If the information has high priority or there is no information identified by address 2E _p-1 , the generated address is 2E _p-1 +1, otherwise the generated address is 2E _p-1 or 2E _p It is characterized by comprising an address generating means which is either ₋₁ +1.

In addition, when the memory device is composed of N-1 memory devices, and the layer corresponding to each of the memory devices is changed from layer 1 to layer N-1, the memory device corresponding to layer 1 stores a single comparison result, The comparison result is a comparison result corresponding to information identified by address 0 and address 1 of the memory device of the distributed memory unit corresponding to layer 1, and corresponds to layer m satisfying (2 ≦ m ≦ N−1). Each of the memory devices identifies the comparison result with an address of m−1 bits, and the comparison result identified with the address D is the address D and the address D + 2 ^m−1 of the memory device of the distributed memory means corresponding to the layer m. The comparison result corresponding to the information identified by the information is obtained, and when the information stored in the memory device of the distributed memory means is updated, the comparison result corresponding to the information is updated. And the memory device of the distributed memory unit corresponding to layer 1 is generated based on the comparison result stored in the memory device of the memory unit of the memory unit and the comparison result memory unit corresponding to layer 1. If the information identified by address 0 has high priority, or there is no information identified by address 1, the generated address is 0, which is identified by address 1 of the memory device of the distributed memory means corresponding to layer 1 If the information to be generated has high priority or there is no information identified by address 0, the generated address is 1, otherwise the generated address is either 0 or 1 (2 ≦ p The address Ep-1 corresponding to the layer _p-1 is input to the address of the memory device of the comparison result memory means corresponding to the layer p satisfying .ltoreq.N-1. Each of the addresses corresponding to the layer p is generated based on the comparison result selected, and the information identified by the address E _p-1 of the memory device of the distributed memory means corresponding to the layer p is given high priority or If there is no information identified by E _p−1 +2 ^m−1 , the generated address is E _p−1 , and the address E _p−1 +2 ^m of the memory device of the distributed memory means corresponding to layer p ^{If the} information identified by ^-1 is high priority or there is no information identified by the address E _p-1 , the generated address is E _p-1 +2 ^m-1 , otherwise it is generated. The address is characterized by comprising address generating means that is either E _p-1 or E _p-1 +2 ^m-1 .

  An apparatus for storing heap structure information according to the present invention stores heap structure information in which the information stored in the binary tree structure information according to claim 3 or 4 is a heap structure. When the number of pieces of information stored in the memory device of the distributed memory unit corresponding to layer 0 is 1 when outputting information from the distributed memory unit, the device corresponds to layer 0. The information stored in the memory device of the distributed memory means is deleted and output, and as a result, the number of information stored in the memory device of the distributed memory means corresponding to layer 0 to layer N-1 is all zero The output of information from the distributed memory means is terminated, and the number of information stored in the memory device of the distributed memory means corresponding to the layer S satisfying (1 ≦ S ≦ N−1) is one or more. State If the number of pieces of information stored in the memory device of the distributed memory unit corresponding to the layer S + 1 is 0 or the layer S is the layer N-1, the layer S corresponds to the layer S. If the value of the number of information stored in the memory device of the distributed memory means is C, the information at the address C-1 of the memory device of the distributed memory means corresponding to the layer S is deleted and inserted as information. Information output means and the number of information stored in the memory device of the distributed memory means corresponding to the layer T satisfying (1 ≦ T ≦ N−1) as a result of deletion of information by the information output means is 1 or more And the number of pieces of information stored in the memory device of the distributed memory means corresponding to layer T + 1 is 0, or the layer T is layer N-1, the layer T versus If the number of information stored in the memory device of the distributed memory means is larger than the value of the address corresponding to the layer T generated by the address generating means, the address corresponding to the layer T generated by the address generating means is Input to the address of the memory device of the distributed memory means corresponding to the layer T; otherwise, the address corresponding to the layer T-1 generated by the address generating means is set to the distributed memory corresponding to the layer T-1 First comparison information selecting means for inputting the address of the memory device of the means, and simultaneously selecting the information of the memory device of the distributed memory means corresponding to layer T to layer T or layer T-1 by the address input means And when the information is selected by the first comparison information selecting means, the information is selected from the memory device of the distributed memory means. All the read information is read and compared with the information to be inserted. If the priority of the information to be inserted is higher than the read information, the priority is higher, otherwise the priority is lower, or the information is inserted from the read information. If the priority of the information is equal or higher, the priority is higher, otherwise the priority is lower. As a result of the comparison, the information to be inserted has lower priority than the information read from the layer U. If the information to be inserted has higher priority than the read information, or the memory device information of the distributed memory means corresponding to the layer U + 1 is not selected, or the layer U is the layer N-1, the layer 1 The information read out from the memory device of the distributed memory means corresponding to layer 0 is written, and if (U ≧ 2), the layer from layer 2 to layer U The read information is written in the memory device information of the distributed memory unit corresponding to the layer U-1 from the layer 1 selected by the first comparison information selection unit, and the first comparison information selection unit When the information to be inserted is written in the information of the memory device of the distributed memory unit corresponding to the layer U selected by the above-described information, and the information to be inserted has higher priority than the information read from the layer 1 as a result of comparison, Alternatively, when information is not selected by the first comparison information selection unit, the first information movement unit writes the information to be inserted into the information of the memory device of the distributed memory unit corresponding to the layer 0. It is characterized by being configured.

Furthermore, the information memorize | stored in the apparatus which memorize | stores the information of the binary tree structure as described in any one of Claim 1 to 4 the information memorize | stored in the heap structure whose information is a heap structure, or Claim 5 When the information stored in the memory device of the distributed memory unit corresponding to layer 0 is 1 when the information is input to the distributed memory unit. The information of the memory device of the distributed memory means corresponding to layer 0 is selected, and the number of information stored in the memory device of the distributed memory means corresponding to layer Q corresponding to (1 ≦ Q ≦ N−1) is 2 ^{If the} number of information stored in the memory device of the distributed memory means corresponding to the layer Q-1 is less than ^Q and the number of ^{pieces of} information stored in the memory device is 2 ^Q-1 , the distributed memory means corresponding to the layer Q Add memory device The value of the number of information stored in the memory device of the distributed memory unit corresponding to layer Q is input to the memory device, and the address input unit stores the value of the memory device of the distributed memory unit corresponding to layer Q from layer 1 to layer Q. A second comparison information selecting means for selecting information simultaneously, and when the information is selected by the second comparison information selecting means, the information is selected from the memory devices of the distributed memory means from layer 0 to layer Q-1. If the priority of the information to be input is higher than that of the read information, the priority is low, otherwise the priority of the information to be input is higher than that of the read information. If it is equal or higher, the priority is higher, otherwise the priority is lower. As a result of the comparison, the input information has higher priority than the information read from the layer R, and the If the input information has a lower priority than the information read from the R-1 or the layer R becomes the layer 0, the information read from the layers from the layer R to the layer Q-1 is compared with the second comparison. The distributed memory corresponding to the layer R selected by the second comparison information selecting means and written in the memory device information of the distributed memory means corresponding to the layer Q from the layer R + 1 selected by the information selecting means When the input information is written in the memory device information of the means and the input information has a lower priority than the information read from the layer Q-1 as a result of comparison, the information is selected by the second comparison information selection means. The input information is written in the memory device information of the distributed memory means corresponding to the layer Q, and the information is selected by the second comparison information selecting means. If no, the information of the memory device of the distributed memory means corresponding to the layer 0, and characterized by being configured and a second information moving means for writing information to said input.

  As a result, a sorter using a heap is realized by parallel processing in which processes that can be executed at the same time are executed simultaneously, so that the execution time is greatly shortened and high speed is realized. Further, like the sorter using a heap described in Non-Patent Document 1, it has a feature that the use efficiency of resources such as a memory is high and a management of a free area of the memory is very easy. As a result, a device for storing the binary tree structure information necessary for parallelizing the sorter algorithm based on the heap described in Non-Patent Document 1 is realized. Further, the heap described in Non-Patent Document 1 is realized. By using a parallel processing algorithm that takes advantage of the high efficiency of using resources such as memory and the ability to manage free memory space very easily, the sorter execution time by heap can be shortened with less resources. It is possible to store information of a high-speed heap structure corresponding to a large number of priorities.

The outline | summary of the parallelized algorithm at the time of inserting priority information in the sorter by heap by this invention is shown, (a) is explanatory drawing of determination of an insertion position, (b) is the movement of an insertion position. It is explanatory drawing. The outline of the parallelized algorithm at the time of deleting the highest priority from the sorter by heap by this invention is shown, (a) is explanatory drawing of determination of an insertion position, (b) is a movement to an insertion position It is explanatory drawing of. It is explanatory drawing which shows the example of the data structure of the apparatus which memorize | stores the information of the binary tree structure concerning this invention. It is explanatory drawing which shows the Example of the apparatus which memorize | stores the information of the binary tree structure concerning this invention, and the apparatus which stores the information of a heap structure. Memory device of distributed memory means, address input means, memory device of comparison result memory means, and address generation means in the apparatus for storing binary tree structure information and the heap structure information shown in FIG. It is explanatory drawing which shows the example of wiring between. FIG. 5 is an explanatory diagram showing an example of the logical correspondence between the input / output of push_pop_address_bus, the address input of the memory device of the distributed memory means, the number of priority information of each layer, the address input of the comparison result memory and the data output shown in FIG. It is. It is explanatory drawing which shows the example from which the logical relationship of the input / output of push_pop_address_bus, the address input of a distributed memory device, the priority information number of each layer, the address input of a comparison result memory, and a data output differs. It is explanatory drawing which shows the detail of the selection method of the information shown to Fig.2 (a). It is explanatory drawing which shows the detail of the selection method of the information shown to Fig.1 (a). It is explanatory drawing which shows an example of a priority queue | queue. It is explanatory drawing which shows an example of a cyclic | annular queue. It is explanatory drawing which shows an example of a tagging type | mold queue. It is explanatory drawing which shows an example of a priority encoder. It is explanatory drawing which shows the implementation example by the hardware of the sorter by a binary tree. It is explanatory drawing which shows an example of a heap structure. It is explanatory drawing which shows the parent-child relationship of the priority information in a heap structure. It is explanatory drawing which shows an example of the heap structure implement | achieved by the arrangement | sequence. It is explanatory drawing which shows the example of the algorithm in the case of inserting the information of the priority 7 into the heap structure shown in FIG. It is explanatory drawing which shows the heap structure after inserting information in FIG. It is explanatory drawing which shows the example of the algorithm which deletes the information with the highest priority from the heap structure shown in FIG. It is explanatory drawing which shows the heap structure after deleting information in FIG. It is explanatory drawing which shows the algorithm at the time of deleting the highest priority information described in the patent document 2 from the sorter by heap. It is explanatory drawing which shows the state after deletion of the heap structure shown in FIG. It is explanatory drawing which shows the algorithm at the time of inserting priority information in the sorter by heap described in patent document 2 with a heap structure. It is explanatory drawing which shows the state after insertion of the heap structure shown in FIG.

Claims (6)

When the memory device is composed of N memory devices, and each of the memory devices corresponds to a layer 0 to a layer N−1, the memory device corresponding to the layer 0 stores a single piece of information (1 ≦ i Each of the memory devices corresponding to layer i satisfying ≦ N−1) identifies information by an i-bit address,
A division operator whose quotient is an integer value rounded down to the nearest decimal point is “/”, the information identified by address 0 or address 1 of the memory device corresponding to layer 1 is the first information, and the layer 0 corresponds When the memory device information is the second information, the second information is a parent of the first information, the first information is a child of the second information, and ( The information identified by the address A of the memory device corresponding to the layer j satisfying 2 ≦ j ≦ N−1) is the third information, and is identified by the address A / 2 of the memory device corresponding to the layer j−1. When the information is the fourth information, the fourth information is based on the second relation that becomes the parent of the third information, and the third information becomes the child of the fourth information. Distributed memory means for identifying the correspondence between the parent and child in the information of the tree structure;
When B is input to the address of the memory device of the distributed memory unit corresponding to the layer L that satisfies (1 ≦ L ≦ N−1), the layer k that corresponds to (1 ≦ k ≦ L−1) By inputting B / 2 ^(Lk) to the addresses of the memory devices of the distributed memory means, it corresponds to the layer 1 from the information of the address B of the memory devices of the distributed memory means corresponding to the layer L. A binary tree comprising: address input means for simultaneously selecting information in a correspondence relationship between a parent and a child up to an address B / 2 ^(L-1) of the memory device of the distributed memory means A device that stores structural information. When the memory device is composed of N memory devices, and each of the memory devices corresponds to a layer 0 to a layer N−1, the memory device corresponding to the layer 0 stores a single piece of information (1 ≦ i Each of the memory devices corresponding to layer i satisfying ≦ N−1) identifies information by an i-bit address,
The remainder operator for calculating the remainder of the integer value is “%”, the address 0 of the memory device corresponding to layer 1 or the information identified by address 1 is the first information, and the information of the memory device corresponding to layer 0 is In the case of second information, the second information is a parent of the first information, the first information is a child of the second information, and (2 ≦ j ≦ N -1) is the information identified by the address A of the memory device corresponding to the layer j, which is the third information, and is identified by the address A% 2 ^(j-1) of the memory device corresponding to the layer j-1. When the information is the fourth information, the fourth information is based on the second relation that becomes the parent of the third information, and the third information becomes the child of the fourth information. Distributed memory means for identifying the correspondence between the parent and child in the information of the tree structure;
When B is input to the address of the memory device of the distributed memory unit corresponding to the layer L satisfying (1 ≦ L ≦ N−1), it corresponds to the layer k satisfying (1 ≦ k ≦ L−1). The distributed memory means corresponding to layer 1 can be obtained from the information of the address B of the memory apparatus corresponding to layer L by inputting B% 2 ^k to the addresses of the memory devices of the distributed memory means. An apparatus for storing binary tree structure information, comprising: address input means for simultaneously selecting information corresponding to a parent-child relationship up to address B% 2 of the memory device of FIG. When N-1 memory devices are configured and the layers corresponding to the memory devices are changed from layer 1 to layer N-1, the memory device corresponding to layer 1 stores a single comparison result, and The comparison result is a comparison result corresponding to information identified by address 0 and address 1 of the memory device of the distributed memory means corresponding to layer 1, and corresponds to layer m satisfying (2 ≦ m ≦ N−1). Each memory device identifies a comparison result with an address of m−1 bits, and the comparison result identified with address D is identified with address 2D and address 2D + 1 of the memory device of the distributed memory means corresponding to layer m. When the comparison result corresponding to the information is obtained and the information stored in the memory device of the distributed memory means is updated, the comparison result corresponding to the information is updated. And,
Based on the comparison result stored in the memory device of the comparison result memory means corresponding to layer 1, an address corresponding to layer 1 is generated and identified by address 0 of the memory device of the distributed memory means corresponding to layer 1 If the information to be processed has high priority or there is no information identified by address 1, the generated address is 0, and the information identified by address 1 of the memory device of the distributed memory means corresponding to layer 1 is If there is no information identified with high priority or address 0, the generated address will be 1, otherwise the generated address will be either 0 or 1,
Comparison result selected by inputting the address _Ep-1 corresponding to the layer p-1 to the address of the memory device of the comparison result memory means corresponding to the layer p satisfying (2≤p≤N-1). Each of the addresses corresponding to the layer p is generated, and the information identified by the address 2E _p-1 of the memory device of the distributed memory means corresponding to the layer p is high priority, or the address 2E _p-1 +1 If there is no information to be identified, the generated address is 2E _p-1 , and the information identified by the address 2E _p-1 +1 of the memory device of the distributed memory means corresponding to layer p has high priority, or address _2E if information identified by _p-1 is not present, the address to be generated _{2E p-1} +1 becomes otherwise, the address generated 2E Device for storing information of a binary tree structure according _-1 or 2E _{p-1 +1} by being configured a one to become the address generating means to claim 1, characterized in. When the memory device is composed of N−1 memory devices, and each of the memory devices corresponds to the layer 1 to the layer N−1, the memory device corresponding to the layer 1 stores a single comparison result, and the comparison The result is a comparison result corresponding to the information identified by address 0 and address 1 of the memory device of the distributed memory means corresponding to layer 1, and the memory corresponding to layer m satisfying (2 ≦ m ≦ N−1). The device identifies the comparison result with an address of m−1 bits each, and the comparison result identified with the address D is identified with the address D and the address D + 2 ^m−1 of the memory device of the distributed memory means corresponding to the layer m. When the information stored in the memory device of the distributed memory means is updated, the comparison result corresponding to the information is updated. Step and
Based on the comparison result stored in the memory device of the comparison result memory means corresponding to layer 1, an address corresponding to layer 1 is generated and identified by address 0 of the memory device of the distributed memory means corresponding to layer 1 If the information to be processed has high priority or there is no information identified by address 1, the generated address is 0, and the information identified by address 1 of the memory device of the distributed memory means corresponding to layer 1 is If there is no information identified with high priority or address 0, the generated address will be 1, otherwise the generated address will be either 0 or 1,
Comparison result selected by inputting the address _Ep-1 corresponding to the layer p-1 to the address of the memory device of the comparison result memory means corresponding to the layer p satisfying (2≤p≤N-1). The address corresponding to the layer p is generated based on the information, and the information identified by the address E _p-1 of the memory device of the distributed memory means corresponding to the layer p is high priority, or the address E _p-1 +2 ^m If the information identified by ⁻¹ does not exist, the generated address is E _p−1 , and is identified by the address E _p−1 +2 ^m−1 of the memory device of the distributed memory means corresponding to the layer p. If the information has high priority or there is no information identified by the address E _p−1 , the generated address is E _p−1 +2 ^m−1 , otherwise the generated address The apparatus for storing information of the binary tree structure according to claim 2, further comprising: an address generation unit that is either E _p-1 or E _p-1 +2 ^m−1 . A device for storing information on a heap structure in which the information stored in the device for storing information on the binary tree structure according to claim 3 or 4 is a heap structure,
When outputting information from the distributed memory means, if the number of information stored in the memory device of the distributed memory means corresponding to layer 0 is 1, the memory of the distributed memory means corresponding to the layer 0 If the information stored in the device is deleted and output, and as a result, the number of information stored in the memory device of the distributed memory means corresponding to layer 0 to layer N-1 is all zero, the distributed Finish outputting information from the memory means,
The distribution corresponding to the layer S + 1 when the number of information stored in the memory device of the distributed memory means corresponding to the layer S corresponding to (1 ≦ S ≦ N−1) is 1 or more. When the number of information stored in the memory device of the memory means is 0, or when the layer S is layer N-1, the number of information stored in the memory device of the distributed memory means corresponding to the layer S If the value is C, the information output means for deleting the information of the address C-1 of the memory device of the distributed memory means corresponding to the layer S and making it information to be inserted;
This is a case where the number of pieces of information stored in the memory device of the distributed memory unit corresponding to the layer T satisfying (1 ≦ T ≦ N−1) is 1 or more as a result of deletion of information by the information output unit. And when the number of pieces of information stored in the memory device of the distributed memory means corresponding to the layer T + 1 is 0, or when the layer T is the layer N-1, the distributed memory corresponding to the layer T If the number of pieces of information stored in the memory device of the means is larger than the value of the address corresponding to the layer T generated by the address generation means, the address corresponding to the layer T generated by the address generation means is assigned to the layer T. Input to the address of the memory device of the corresponding distributed memory means, otherwise the address corresponding to the layer T-1 generated by the address generating means is the layer T-1 First, the address of the memory device of the distributed memory means corresponding to layer T to layer T or layer T-1 is simultaneously selected by the address input means by inputting the address of the memory device of the corresponding distributed memory means. Comparison information selection means,
When information is selected by the first comparison information selection means, all the information selected from the memory device of the distributed memory means is read out, compared with the information to be inserted, and the insertion is performed from the read information. If the priority of information to be high is high priority, otherwise low priority, or if the priority of the information to be inserted is higher than or equal to the read information, high priority, otherwise low priority,
As a result of comparison, the information to be inserted has a lower priority than the information read from the layer U, and the information to be inserted has a higher priority than the information read from the layer U + 1. When the corresponding memory device information of the distributed memory means is not selected or the layer U is layer N-1, the information read from the layer 1 is read from the memory device of the distributed memory means corresponding to the layer 0. In the case of (U ≧ 2), the information read from the layers from the layer 2 to the layer U is written in the information, and the distribution corresponding to the layer 1 to the layer U-1 selected by the first comparison information selection unit The distributed memory means corresponding to the layer U respectively written to the information of the memory device of the memory means and selected by the first comparison information selecting means The information of the memory device, writes the information to the insert,
As a result of the comparison, if the information to be inserted has higher priority than the information read from layer 1, or if the information is not selected by the first comparison information selection unit, the distributed memory corresponding to layer 0 An apparatus for storing information of a heap structure, comprising: first information moving means for writing information to be inserted into information of a memory device of the means. The apparatus which memorize | stores the information of the heap structure whose information memorize | stored in the apparatus which memorize | stores the information of the binary tree structure as described in any one of Claim 1 to 4 is a heap structure, or the heap of Claim 5 A device for storing structural information,
When the number of pieces of information stored in the memory device of the distributed memory unit corresponding to layer 0 is 1 when inputting information to the distributed memory unit, the memory device of the distributed memory unit corresponding to layer 0 Select information for
The distributed memory in which the number of ^{pieces of} information stored in the memory device of the distributed memory unit corresponding to the layer Q satisfying (1 ≦ Q ≦ N−1) is less than 2Q and corresponding to the layer Q−1 When the number of ^{pieces of} information stored in the memory device of the means is in the state of ^2Q-1 , the address of the memory device of the distributed memory means corresponding to layer Q is set to the memory device of the distributed memory means corresponding to layer Q. Second comparison information selection means for inputting the value of the number of stored information and simultaneously selecting information of the memory devices of the distributed memory means corresponding to layer 1 to layer Q by the address input means;
When information is selected by the second comparison information selection means, the information selected from the memory devices of the distributed memory means from layer 0 to layer Q-1 is read and compared with the input information, If the priority of the information to be input is higher than the read information, the priority is high, otherwise low priority, or if the priority of the information to be input is higher than the read information, high priority, otherwise low priority,
As a result of the comparison, the input information has a higher priority than the information read from the layer R, and the input information has a lower priority than the information read from the layer R-1, or the layer R In the case of layer 0, the information read from the layers R to Q-1 is read from the memory device of the distributed memory unit corresponding to the layer R + 1 to the layer Q selected by the second comparison information selecting unit. Each of the information is written, and the input information is written in the information of the memory device of the distributed memory unit corresponding to the layer R selected by the second comparison information selection unit,
As a result of the comparison, when the input information has a lower priority than the information read from the layer Q-1, information on the memory device of the distributed memory unit corresponding to the layer Q selected by the second comparison information selection unit To write the information to be input,
When information is not selected by the second comparison information selection unit, the second comparison unit includes a second information moving unit that writes the input information to the information of the memory device of the distributed memory unit corresponding to the layer 0. An apparatus for storing information of a heap structure characterized by being configured.

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