JP4385912B2 - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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JP4385912B2
JP4385912B2 JP2004289864A JP2004289864A JP4385912B2 JP 4385912 B2 JP4385912 B2 JP 4385912B2 JP 2004289864 A JP2004289864 A JP 2004289864A JP 2004289864 A JP2004289864 A JP 2004289864A JP 4385912 B2 JP4385912 B2 JP 4385912B2
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liquid crystal
crystal display
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大 今西
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Victor Company of Japan Ltd
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本発明は、液晶表示装置に係り、特に経時変化に対し良好な階調表示を行うことが可能な液晶表示装置に関する。   The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of performing good gradation display with respect to changes over time.

近年、ディスプレイは大型化,薄型化がすすんでおり、特に液晶を用いた方式のディスプレイの普及が目覚しい。その中でアクティブマトリクス方式の液晶表示装置として、例えば特許文献1または2等に開示されているものが知られている。
ここで従来の一般的な液晶表示装置について説明する。図3は液晶表示装置を示す概念図、図4は液晶表示装置の光学系を示す概念図である。図3及び図4において、”2”は液晶表示パネルであり、後述するようにこの内部に入射光を変調する液晶が封入されている。”4”は液晶駆動回路であり、これに入力される映像信号を画像処理部4Aで処理してデータ信号を形成し、また駆動制御部4Bにより駆動制御信号を形成して、上記データ信号と共に上記液晶表示パネル2へ供給される。図4に示すように、上記液晶表示装置では、光源6より出射した光を偏光ビームスプリッタ8で偏光させて反射し、これを液晶表示パネル2への入射光として入射させる。そして、この液晶表示パネル2では、上記入射光に対してデータ信号に基づいて変調(偏光)を加えて反射させ、その変調された反射光は偏光ビームスプリッタ8を通過してスクリーン10へ投射したり、光測定の時には受光器に入射させるようになっている。
In recent years, displays are becoming larger and thinner, and the use of liquid crystal displays is particularly widespread. Among them, as an active matrix liquid crystal display device, for example, one disclosed in Patent Document 1 or 2 is known.
Here, a conventional general liquid crystal display device will be described. FIG. 3 is a conceptual diagram showing a liquid crystal display device, and FIG. 4 is a conceptual diagram showing an optical system of the liquid crystal display device. In FIG. 3 and FIG. 4, “2” is a liquid crystal display panel, and a liquid crystal that modulates incident light is sealed therein as described later. “4” is a liquid crystal drive circuit, and a video signal inputted thereto is processed by the image processing unit 4A to form a data signal, and a drive control signal is formed by the drive control unit 4B, together with the data signal. The liquid crystal display panel 2 is supplied. As shown in FIG. 4, in the liquid crystal display device, the light emitted from the light source 6 is polarized and reflected by the polarization beam splitter 8, and is incident on the liquid crystal display panel 2 as incident light. In the liquid crystal display panel 2, the incident light is modulated (polarized light) based on the data signal and reflected, and the modulated reflected light passes through the polarization beam splitter 8 and is projected onto the screen 10. In the case of light measurement, the light is incident on a light receiver.

具体的には、上記液晶駆動回路4において、映像信号は信号変調やデジタル化、画質処理等の画像処理が行われ、駆動制御信号と共に液晶表示パネル2を最適駆動するためのデータ信号が出力される。通常、液晶駆動回路4における信号処理は、デジタル化された信号により処理が施され、A/D変換、D/A変換等の特性上、この液晶駆動回路4の設計によって、液晶表示装置の表示階調数が決まる。その後、このデータ信号は駆動制御信号と共に液晶表示パネル2へ伝達される。   Specifically, in the liquid crystal drive circuit 4, the video signal is subjected to image processing such as signal modulation, digitization, and image quality processing, and a data signal for optimally driving the liquid crystal display panel 2 is output together with the drive control signal. The Usually, the signal processing in the liquid crystal driving circuit 4 is performed by a digitized signal. Due to the characteristics of A / D conversion, D / A conversion, etc., the display of the liquid crystal display device depends on the design of the liquid crystal driving circuit 4. The number of gradations is determined. Thereafter, this data signal is transmitted to the liquid crystal display panel 2 together with the drive control signal.

次に、液晶表示パネル2の構成について説明する。図5は液晶表示パネルを示す模式図、図6は液晶表示パネルの一部を示す立体斜視図、図7は液晶表示パネルの画素部を示す断面図である。
図5に示すように、液晶表示パネル2は、縦横に格子状(マトリクス状)に配列された複数の画素PXを有している。そして、縦方向へはデータ信号をサンプリングした電圧を伝える複数のデータ線12が並行して配置され、これら各データ線12と直交する方向に複数の走査線14が配置されている。複数のデータ線12と複数の走査線14との交差部は上記画素PXとなり、各画素PXにはスイッチトランジスタTRが配置されている。そして、上記複数のデータ線12は水平アドレス回路16から延び、上記複数の走査線14は垂直アドレス回路18から延びている。そして、スイッチトランジスタTRに関しては、ドレインDがデータ線12に、ゲートGが走査線14に、ソースSが保持容量CS及び画素電極20に並列に、それぞれ接続されている。ここで画素電極20は、上記画素PXに対応してマトリクス状に配列されている。後述するように、上記各画素電極20と、透明な共通になされた共通電極22との間には、液晶層24が介在されている。そして、各保持容量CSは保持容量共通配線26に接続されている。
上記水平アドレス回路16へは、水平アドレス回路制御信号とデータ信号が入力され、各データ線にデータ信号をサンプリングしながら印加する。また、垂直アドレス回路18へは垂直アドレス回路制御信号が入力され、上記データ信号に同期させて走査線14に走査信号を送ることにより、各画素PXが選択されるようになっている。
Next, the configuration of the liquid crystal display panel 2 will be described. 5 is a schematic view showing a liquid crystal display panel, FIG. 6 is a three-dimensional perspective view showing a part of the liquid crystal display panel, and FIG. 7 is a cross-sectional view showing a pixel portion of the liquid crystal display panel.
As shown in FIG. 5, the liquid crystal display panel 2 includes a plurality of pixels PX arranged in a lattice shape (matrix shape) vertically and horizontally. In the vertical direction, a plurality of data lines 12 that transmit a voltage obtained by sampling the data signal are arranged in parallel, and a plurality of scanning lines 14 are arranged in a direction orthogonal to the data lines 12. The intersections of the plurality of data lines 12 and the plurality of scanning lines 14 are the pixels PX, and a switch transistor TR is disposed in each pixel PX. The plurality of data lines 12 extend from the horizontal address circuit 16, and the plurality of scanning lines 14 extend from the vertical address circuit 18. Regarding the switch transistor TR, the drain D is connected to the data line 12, the gate G is connected to the scanning line 14, and the source S is connected to the storage capacitor CS and the pixel electrode 20 in parallel. Here, the pixel electrodes 20 are arranged in a matrix corresponding to the pixels PX. As will be described later, a liquid crystal layer 24 is interposed between each pixel electrode 20 and a transparent common electrode 22. Each storage capacitor CS is connected to the storage capacitor common line 26.
The horizontal address circuit 16 receives a horizontal address circuit control signal and a data signal, and applies the data signal to each data line while sampling. A vertical address circuit control signal is input to the vertical address circuit 18, and each pixel PX is selected by sending a scanning signal to the scanning line 14 in synchronization with the data signal.

次に、上記液晶表示パネル2の断面構造について説明する。図6は上記液晶表示パネルの概略斜視図を示し、図7は画素部の液晶層部分の断面図を示している。図示するように、上記スイッチトランジスタTRや保持容量CS等は例えばシリコンウエハの半導体基板よりなる第1の基板30に形成されている。そして、この第1の基板30上に上記画素電極20がマトリクス状に形成され、更に、この画素電極20を含む第1の基板30の表面全体に配向膜32が形成されている。   Next, the cross-sectional structure of the liquid crystal display panel 2 will be described. FIG. 6 is a schematic perspective view of the liquid crystal display panel, and FIG. 7 is a cross-sectional view of the liquid crystal layer portion of the pixel portion. As shown in the figure, the switch transistor TR, the storage capacitor CS, and the like are formed on a first substrate 30 made of a semiconductor substrate of, for example, a silicon wafer. The pixel electrodes 20 are formed in a matrix on the first substrate 30, and an alignment film 32 is formed on the entire surface of the first substrate 30 including the pixel electrodes 20.

一方、上記第1の基板30に対向する第2の基板34は、例えば透明なガラス板よりなり、この上面には反射防止膜36が形成されている。またこの第2の基板34の下面側全面には、例えばITOよりなる透明な共通電極22が形成され、更に、その下面側全面には配向膜38が積層形成されている。そして、上記第1及び第2の基板30、34は、互いに上記配向膜32、38を対向させて所定の間隔を隔てて、間に液晶層24を封入して接合され、これによって全体が構成されている。そして、上記画素電極20と共通電極22との間で電圧が印加され、また入射光は第2の基板34側から入射する。
ここで上記配向膜32、38の材料として、例えば、ポリイミドのような有機物や二酸化ケイ素のような無機物の2種類があげられる。一般に有機物の方が量産性には優れるが、光が当たり続けると変色するといった問題があり、強い光が当たる液晶表示装置の場合、無機物の方が特性面において優れている。
On the other hand, the second substrate 34 facing the first substrate 30 is made of, for example, a transparent glass plate, and an antireflection film 36 is formed on the upper surface thereof. A transparent common electrode 22 made of, for example, ITO is formed on the entire lower surface side of the second substrate 34, and an alignment film 38 is laminated on the entire lower surface side. The first and second substrates 30 and 34 are bonded to each other with the alignment films 32 and 38 facing each other with a predetermined gap therebetween, and the liquid crystal layer 24 is sealed between them. Has been. A voltage is applied between the pixel electrode 20 and the common electrode 22, and incident light enters from the second substrate 34 side.
Here, as the material of the alignment films 32 and 38, for example, there are two kinds of materials such as an organic material such as polyimide and an inorganic material such as silicon dioxide. In general, organic materials are more mass-productive, but there is a problem that they are discolored when light continues to strike. In the case of liquid crystal display devices that are exposed to strong light, inorganic materials are superior in terms of characteristics.

特開平11−183912号公報JP-A-11-183912 特開2001−249351号公報JP 2001-249351 A

ところで、液晶層24の液晶に加わる電圧は、画素電極20と共通電極22との間の電位差となることが理想的であるが、実際には電気抵抗を持つ配向膜32、38が間に存在することにより、その分、液晶に加わる電圧が低くなる。例えば一般的に、液晶層24は十分な光変調を得るために2μm以上の厚みが必要であり、さらに配向膜32、38も液晶を規則正しく整列させるためには、それぞれ0.05μm程度の膜厚が必要とされる。一般的な液晶の抵抗率は1014Ωcm程度であり、配向膜32、38は絶縁体であるから抵抗率1015Ωcm程度とすると、液晶層24の単位面積あたりの抵抗Rlc=2×1010Ωとなり、配向膜32、38の単位面積あたりの抵抗Ral=5×10 Ωとなり、直列抵抗の関係より、画素電極20と共通電極22の間に加わる電圧のうち約80%が液晶層24に加わることになる。 By the way, the voltage applied to the liquid crystal of the liquid crystal layer 24 is ideally a potential difference between the pixel electrode 20 and the common electrode 22, but actually there are alignment films 32 and 38 having electric resistance between them. As a result, the voltage applied to the liquid crystal is reduced accordingly. For example, in general, the liquid crystal layer 24 needs to have a thickness of 2 μm or more in order to obtain sufficient light modulation, and the alignment films 32 and 38 have a thickness of about 0.05 μm in order to regularly align the liquid crystals. Is needed. Since the resistivity of a general liquid crystal is about 10 14 Ωcm and the alignment films 32 and 38 are insulators, if the resistivity is about 10 15 Ωcm, the resistance Rlc = 2 × 10 10 per unit area of the liquid crystal layer 24. The resistance per unit area of the alignment films 32 and 38 is Ral = 5 × 10 9 Ω, and about 80% of the voltage applied between the pixel electrode 20 and the common electrode 22 is about 24% due to the series resistance. Will join.

ここで問題になるのは、この配向膜32、38の抵抗値の経時変化である。一般に、配向膜は不純物の影響や使用環境等により、容易にその電気抵抗が変化する。特に配向膜の材料として無機物を用いた場合には、雰囲気中の物質に敏感に反応して電気抵抗が低下し易い。ここで経時変化により電気抵抗が下がると、液晶に加わる電圧が変化するため、液晶の光強度も変わることとなり、著しく表示品質が低下する、という問題がある。例えば、特定の環境下で加速度試験を行うと、配向膜の初期の単位面積あたりの抵抗RalがRal=5×10Ωから、 Ral’=5×10Ωに電気抵抗が低下する。すると液晶層に加わる電圧が相 対的に高くなり、表示品質が劣化する。 The problem here is the change over time in the resistance values of the alignment films 32 and 38. In general, the electrical resistance of the alignment film easily changes due to the influence of impurities, the use environment, and the like. In particular, when an inorganic material is used as the material of the alignment film, it reacts sensitively to substances in the atmosphere and the electric resistance tends to decrease. Here, when the electrical resistance is lowered due to a change with time, the voltage applied to the liquid crystal is changed, so that the light intensity of the liquid crystal is also changed, and there is a problem that the display quality is remarkably deteriorated. For example, when an acceleration test is performed in a specific environment, the electrical resistance decreases from Ral = 5 × 10 9 Ω to Ral ′ = 5 × 10 8 Ω per initial unit area of the alignment film. As a result, the voltage applied to the liquid crystal layer becomes relatively high, and the display quality deteriorates.

この点を具体的に説明すると、図8は初期(経時変化前)の配向膜の時の液晶の電圧−相対光強度の特性曲線を示すグラフ、図9は配向膜が経時変化した時の液晶の電圧−相対光強度の特性曲線を示すグラフである。
図8に示すように、液晶層に電圧を印加して行くと、それに従って、相対光強度も増加し、ピークを過ぎてからやや減少する特性を示す。しかし、図9に示すように、配向膜が経時変化すると、特性曲線は実線から破線のように変化する。すなわち、環境試験の前後で特性曲線が上記のように変化する。このことは、最大光量時を100%とすると、液晶の相対光強度で従来50%の明るさであったものが、同じ電圧で90%以上の明るさとなるため、表示階調を著しく損なってしまうことを意味する。
本発明は、以上のような問題点に着目し、これを有効に解決すべく創案されたものであり、本発明の目的は、配向膜が経時変化を起こしても、良好な階調表示を維持でき、もって表示品質を高く維持することが可能な液晶表示装置を提供することにある。
Specifically, FIG. 8 is a graph showing a voltage-relative light intensity characteristic curve of the liquid crystal when the alignment film is in the initial stage (before change over time), and FIG. 9 is a liquid crystal when the alignment film changes over time. It is a graph which shows the characteristic curve of voltage-relative light intensity.
As shown in FIG. 8, when a voltage is applied to the liquid crystal layer, the relative light intensity increases accordingly, and shows a characteristic of slightly decreasing after passing the peak. However, as shown in FIG. 9, when the alignment film changes with time, the characteristic curve changes from a solid line to a broken line. That is, the characteristic curve changes as described above before and after the environmental test. This means that when the maximum light intensity is 100%, the relative light intensity of the liquid crystal is 50% brighter than the conventional light, but the brightness is 90% or more at the same voltage, so the display gradation is significantly impaired. It means to end.
The present invention has been developed in order to effectively solve the above-mentioned problems, and an object of the present invention is to provide a good gradation display even when the alignment film changes with time. An object of the present invention is to provide a liquid crystal display device that can be maintained and can maintain high display quality.

請求項1に係る発明は、複数の画素電極がマトリクス状に配置されて前記画素電極の表面に配向膜が形成された第1の基板と、表面に配向膜が形成された透明な共通電極を有する第2の基板とを、前記配向膜同士を対向させて間に液晶層を介在させて接合し、前記画素電極と前記共通電極との間に複数の表示階調レベルの電圧を印加することにより入射光を変調するようにした液晶表示装置において、前記電圧の印加に対して、前記液晶層の単位面積あたりの抵抗Rlcと前記配向膜の単位面積あたりの抵抗Ralとの関係が、表示階調数nに対して”Rlc/Ral>n”となる関係を有するように構成したことを特徴とする液晶表示装置である。   According to a first aspect of the present invention, there is provided a first substrate in which a plurality of pixel electrodes are arranged in a matrix and an alignment film is formed on a surface of the pixel electrode, and a transparent common electrode having an alignment film formed on the surface. A second substrate having a plurality of display gradation levels applied between the pixel electrode and the common electrode, with the alignment films facing each other with a liquid crystal layer interposed therebetween. In the liquid crystal display device in which incident light is modulated by the above, the relationship between the resistance Rlc per unit area of the liquid crystal layer and the resistance Ral per unit area of the alignment film with respect to the application of the voltage is represented by a display floor. The liquid crystal display device is configured to have a relationship of “Rlc / Ral> n” with respect to the characteristic number n.

本発明に係る液晶表示装置によれば、配向膜が経時変化を起こしても、良好な階調表示を維持でき、もって表示品質を高く維持することができる。   According to the liquid crystal display device of the present invention, it is possible to maintain a good gradation display even when the alignment film undergoes a change over time, thereby maintaining a high display quality.

以下に、本発明に係る液晶表示装置の一実施例を添付図面に基づいて詳述する。
図1は本発明に係る液晶表示装置の液晶表示パネルの画素部を示す断面図、図2は本発明の効果を説明するための液晶の電圧−相対光強度の特性曲線を示すグラフである。
尚、本発明の液晶表示装置の構成は、配向膜の構成を除き、図3〜図7に説明した構成と全く同じであるので、ここではその説明を省略し、図1を参照して配向膜の構成を中心に説明する。図1において、図7に示す構成部分と同一構成部分には同一符号を付してある。
図示するように、スイッチトランジスタTRや保持容量CS等は例えばシリコンウエハの半導体基板よりなる第1の基板30に形成されていいる。そして、この第1の基板30上に画素電極20がマトリクス状に形成され、更に、この画素電極20を含む第1の基板30の表面全体に本発明の特徴とする配向膜40が形成されている。
Hereinafter, an embodiment of a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a sectional view showing a pixel portion of a liquid crystal display panel of a liquid crystal display device according to the present invention, and FIG. 2 is a graph showing a voltage-relative light intensity characteristic curve of liquid crystal for explaining the effect of the present invention.
The configuration of the liquid crystal display device of the present invention is exactly the same as the configuration described with reference to FIGS. 3 to 7 except for the configuration of the alignment film. Therefore, the description is omitted here and the alignment is performed with reference to FIG. The description will focus on the structure of the film. 1, the same components as those shown in FIG. 7 are denoted by the same reference numerals.
As shown in the figure, the switch transistor TR, the storage capacitor CS, and the like are formed on a first substrate 30 made of, for example, a silicon wafer semiconductor substrate. The pixel electrodes 20 are formed in a matrix on the first substrate 30, and the alignment film 40, which is a feature of the present invention, is formed on the entire surface of the first substrate 30 including the pixel electrodes 20. Yes.

一方、上記第1の基板30に対向する第2の基板34は、例えば透明なガラス板よりなり、この上面には反射防止膜36が形成されている。またこの第2の基板34の下面側全面には、例えばITOよりなる透明な共通電極22が形成され、更に、その下面側全面には本発明の特徴とする配向膜42が積層形成されている。そして、上記第1及び第2の基板30、34は、互いに上記配向膜40、42を対向させて所定の間隔を隔てて、間に液晶層24を封入して接合され、これによって全体が構成されている。そして、上記画素電極20と共通電極22との間で電圧が印加され、また入射光は第2の基板34側から入射する。   On the other hand, the second substrate 34 facing the first substrate 30 is made of, for example, a transparent glass plate, and an antireflection film 36 is formed on the upper surface thereof. A transparent common electrode 22 made of, for example, ITO is formed on the entire lower surface of the second substrate 34, and an alignment film 42, which is a feature of the present invention, is laminated on the entire lower surface. . The first and second substrates 30 and 34 are bonded to each other with the alignment films 40 and 42 opposed to each other with a predetermined gap therebetween, and the liquid crystal layer 24 is sealed between them. Has been. A voltage is applied between the pixel electrode 20 and the common electrode 22, and incident light enters from the second substrate 34 side.

ここで本発明では、上記電圧の印加方向に対して、上記液晶層24の単位面積あたりの抵抗Rlcと上記配向膜40、42の単位面積あたりの抵抗Ralとの関係が、表示階調数nに対して”Rlc/Ral>n”となる関係を有するように構成されている。
尚、ここではデータ信号の表示階調数は例えば256階調で出力されるように設計されており、従って、表示階調数は”256”となる。
Here, in the present invention, the relationship between the resistance Rlc per unit area of the liquid crystal layer 24 and the resistance Ral per unit area of the alignment films 40 and 42 with respect to the voltage application direction is the number of display gradations n. Is configured to have a relation of “Rlc / Ral> n”.
Here, the display gradation number of the data signal is designed to be output with, for example, 256 gradations, and therefore the display gradation number is “256”.

上述のように配向膜40、42の単位面積あたりの抵抗を設定した理由は次のようである。すなわち、ある電圧が液晶表示パネルに印加された時、液晶層と配向膜に印加される電圧の比率は、単位面積あたりの液晶の抵抗Rlcと単位面積あたりの配向膜の抵抗Ralとの比率で決まるのは前述した通りである。従って、RlcがRalより十分に高ければ、Ralが変化しても液晶層に印加される電圧に対する影響は小さくて済む。そこで、表示階調数に着目し、経時劣化による電圧の変化が表示階調数の逆数以下、すなわち最小の階調電圧範囲以下とすることで、階調変化の防止を保証することが可能となる。よって上述のような、電圧の比率、すなちRlcとRalの比率を表示階調数に関係づけたものである。換言すれば、上記式の条件を満たすことで、液晶層24に加わる電圧は、表示階調数nの1/n以下の電圧変動しか起こさず、階調にほとんど悪影響を及ぼさないことになる。   The reason why the resistance per unit area of the alignment films 40 and 42 is set as described above is as follows. That is, when a certain voltage is applied to the liquid crystal display panel, the ratio of the voltage applied to the liquid crystal layer and the alignment film is the ratio of the resistance Rlc of the liquid crystal per unit area to the resistance Ral of the alignment film per unit area. It is determined as described above. Therefore, if Rlc is sufficiently higher than Ral, even if Ral changes, the influence on the voltage applied to the liquid crystal layer is small. Therefore, paying attention to the number of display gradations, it is possible to guarantee the prevention of gradation changes by making the voltage change due to deterioration over time less than the reciprocal of the display gradation number, that is, less than the minimum gradation voltage range. Become. Therefore, the voltage ratio, that is, the ratio of Rlc and Ral as described above is related to the number of display gradations. In other words, by satisfying the condition of the above formula, the voltage applied to the liquid crystal layer 24 causes only a voltage fluctuation of 1 / n or less of the display gradation number n, and has almost no adverse effect on the gradation.

ここで、上記配向膜40、42として無機物を用いると、比較的抵抗率の制御が行い易くなる。従って、本発明では蒸着装置にて、配向膜40、42として酸化珪素(SiOx:1.0≦x≦2.0)の膜を形成した。その際、液晶が配向するのに必要な膜厚として0.1μmを前記第1の基板30と前記第2の基板34上にそれぞれ堆積する。この際、使用する液晶の抵抗率は仕様上1.2×1015Ωcmであるが、一般に実際の使用状態では約一桁抵抗が落ちるため、液晶の抵抗率を1.2×1014Ωcmとして、液晶層24の厚みを3.2μmで計算すると、液晶層24の単位面積あたりの抵抗Rlcは3.84×1010Ωとなる。そして本発明のRlc/Ral>nの関係式より、液晶駆動回路4(図3参照)の出力の表示階調数n=256であるから、配向膜40、42の抵抗Ralは1.5x10以下である必要がある。 Here, when an inorganic material is used as the alignment films 40 and 42, the resistivity can be controlled relatively easily. Therefore, in the present invention, a silicon oxide (SiOx: 1.0 ≦ x ≦ 2.0) film is formed as the alignment films 40 and 42 by the vapor deposition apparatus. At that time, 0.1 μm is deposited on the first substrate 30 and the second substrate 34 as the film thickness necessary for aligning the liquid crystal. At this time, the resistivity of the liquid crystal to be used is 1.2 × 10 15 Ωcm in terms of specifications, but generally the resistance of the liquid crystal is 1.2 × 10 14 Ωcm because the resistance drops by about an order of magnitude in actual use. When the thickness of the liquid crystal layer 24 is calculated at 3.2 μm, the resistance Rlc per unit area of the liquid crystal layer 24 is 3.84 × 10 10 Ω. From the relational expression of Rlc / Ral> n according to the present invention, since the display gradation number n = 256 of the output of the liquid crystal driving circuit 4 (see FIG. 3), the resistance Ral of the alignment films 40 and 42 is 1.5 × 10 8. Must be:

そこで各々の配向膜40、42の膜厚は0.1μmであることから、抵抗率が7.5×1012Ωcm以下[=Ral/(0.1μm×2)]の抵抗率の膜となるように、蒸着のレートやSiOxのxの比率を調整する等、適切な成膜条件で所定の膜厚の配向膜40、42形成を行う。この配向膜40、42を成膜後、第1の基板30と第2の基板34の配向膜面同士が向き合う形で対向し、液晶層24の厚みが3.2μmとなるように、一定の間隙で張り合わせる。この間隙を満たすように液晶を注入し、その後、注入に使用した穴を封止する。そして第1の基板30側に対して、液晶駆動回路4からの信号が入力できるように、配線を行うことで液晶表示パネルが作製される。 Therefore, since each of the alignment films 40 and 42 has a thickness of 0.1 μm, the resistivity is 7.5 × 10 12 Ωcm or less [= Ral / (0.1 μm × 2)]. As described above, the alignment films 40 and 42 having a predetermined film thickness are formed under appropriate film forming conditions such as adjusting the deposition rate and the ratio of x in SiOx. After the alignment films 40 and 42 are formed, the alignment film surfaces of the first substrate 30 and the second substrate 34 are opposed to each other so that the thickness of the liquid crystal layer 24 is 3.2 μm. Laminate with a gap. Liquid crystal is injected to fill this gap, and then the hole used for injection is sealed. Then, wiring is performed on the first substrate 30 side so that a signal from the liquid crystal driving circuit 4 can be input, whereby a liquid crystal display panel is manufactured.

この液晶表示パネルを液晶駆動回路4と接続し、実際に動作させた。ガンマ補正等は行わず、電圧に対する液晶の直接的な変調度を示したのが図2である。初期の電圧−相対光強度曲線は実線で示されており、特定の環境下で加速度試験を行った後(配向膜の経時変化後)、従来の電圧−相対光強度曲線は一点鎖線で示され、本発明の電圧−相対光強度曲線は点線で示される。液晶に加わる電圧の変化に対して最も液晶の変調度が敏感な、初期の光量が50%時の電圧に対して、加速度試験後に従来装置は約16%光強度が上昇してしまったものが、本発明装置によれば1%以内で収まっており、良好な表示特性を維持できることが確認できた。
尚、本発明は、具体例として半導体基板上の反射型液晶で説明を行ってきたが、この例に限るものではなく、例えば絶縁性基板上に薄膜トランジスタを形成した基板や、透過型の液晶であっても有効である。
This liquid crystal display panel was connected to the liquid crystal driving circuit 4 and actually operated. FIG. 2 shows the direct modulation degree of the liquid crystal with respect to the voltage without performing gamma correction or the like. The initial voltage-relative light intensity curve is shown by a solid line, and after performing an acceleration test in a specific environment (after aging of the alignment film), the conventional voltage-relative light intensity curve is shown by a one-dot chain line. The voltage-relative light intensity curve of the present invention is indicated by a dotted line. The intensity of liquid crystal modulation is most sensitive to changes in the voltage applied to the liquid crystal, and the light intensity of the conventional device increased by about 16% after the acceleration test with respect to the voltage when the initial light intensity is 50%. According to the device of the present invention, it was within 1%, and it was confirmed that good display characteristics could be maintained.
Although the present invention has been described by using a reflective liquid crystal on a semiconductor substrate as a specific example, the present invention is not limited to this example. For example, the present invention is not limited to a substrate in which a thin film transistor is formed on an insulating substrate or a transmissive liquid crystal. Even if it exists, it is effective.

本発明に係る液晶表示装置の液晶表示パネルの画素部を示す断面図である。It is sectional drawing which shows the pixel part of the liquid crystal display panel of the liquid crystal display device which concerns on this invention. 本発明の効果を説明するための液晶の電圧−相対光強度の特性曲線を示すグラフである。It is a graph which shows the characteristic curve of the voltage-relative light intensity of the liquid crystal for demonstrating the effect of this invention. 液晶表示装置を示す概念図である。It is a conceptual diagram which shows a liquid crystal display device. 液晶表示装置の光学系を示す概念図である。It is a conceptual diagram which shows the optical system of a liquid crystal display device. 液晶表示パネルを示す模式図である。It is a schematic diagram which shows a liquid crystal display panel. 液晶表示パネルの一部を示す立体斜視図である。It is a three-dimensional perspective view which shows a part of liquid crystal display panel. 液晶表示パネルの画素部を示す断面図である。It is sectional drawing which shows the pixel part of a liquid crystal display panel. 初期(経時変化前)の配向膜の時の液晶の電圧−相対光強度の特性曲線を示すグラフである。It is a graph which shows the characteristic curve of the voltage-relative light intensity of the liquid crystal at the time of the alignment film of an initial stage (before time-dependent change). 配向膜が経時変化した時の液晶の電圧−相対光強度の特性曲線を示すグラフである。It is a graph which shows the characteristic curve of the voltage-relative light intensity of a liquid crystal when an alignment film changes with time.

符号の説明Explanation of symbols

12…データ線、14…走査線、16…水平アドレス回路、18…垂直アドレス回路、20…画素電極、22…共通電極、24…液晶層、30…第1の基板(半導体基板)、34…第2の基板(ガラス板)、40,42…配向膜、PX…画素、TR…スイッチングトランジスタ。

DESCRIPTION OF SYMBOLS 12 ... Data line, 14 ... Scan line, 16 ... Horizontal address circuit, 18 ... Vertical address circuit, 20 ... Pixel electrode, 22 ... Common electrode, 24 ... Liquid crystal layer, 30 ... 1st board | substrate (semiconductor substrate), 34 ... Second substrate (glass plate), 40, 42, alignment film, PX, pixel, TR, switching transistor.

Claims (1)

複数の画素電極がマトリクス状に配置されて前記画素電極の表面に配向膜が形成された第1の基板と、表面に配向膜が形成された透明な共通電極を有する第2の基板とを、前記配向膜同士を対向させて間に液晶層を介在させて接合し、前記画素電極と前記共通電極との間に複数の表示階調レベルの電圧を印加することにより入射光を変調するようにした液晶表示装置において、
前記電圧の印加に対して、前記液晶層の単位面積あたりの抵抗Rlcと前記配向膜の単位面積あたりの抵抗Ralとの関係が、表示階調数nに対して”Rlc/Ral>n”となる関係を有するように構成したことを特徴とする液晶表示装置。

A first substrate having a plurality of pixel electrodes arranged in a matrix and having an alignment film formed on the surface of the pixel electrode; and a second substrate having a transparent common electrode having an alignment film formed on the surface. The alignment films are opposed to each other with a liquid crystal layer interposed therebetween, and a plurality of display gradation level voltages are applied between the pixel electrode and the common electrode so as to modulate incident light. In the liquid crystal display device
When the voltage is applied, the relationship between the resistance Rlc per unit area of the liquid crystal layer and the resistance Ral per unit area of the alignment film is “Rlc / Ral> n” with respect to the display gradation number n. A liquid crystal display device characterized by having the following relationship.

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