JP4376176B2 - Receiving machine - Google Patents

Description

  The present invention relates to a receiver of a wireless communication system, and more particularly to a receiver that eliminates a delay time deviation of multicarrier processing at a low cost by controlling the phase of an input clock to an AD converter.

  A conventional receiver in a CDMA (Code Division Multiple Access) system will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of a conventional receiver.

As shown in FIG. 5, the receiver according to the conventional example includes a radio unit 10, an analog / digital converter (ADC) 20, a clock generation unit 30, and a demodulation unit 40.
A baseband signal processing unit 100 is connected to the receiver.

The radio unit 10 includes an antenna 11, a preselecting filter 12, a low noise amplifier 13, a frequency conversion unit 14, a local oscillator 15, an IF filter 16, and an automatic gain control unit 17. ing.
The demodulator 40 includes a quadrature detector 42 and a baseband filter 43.

  In the case of receiving a multicarrier signal, the antenna 11, the preselecting filter 12, and the low noise amplifier 13 can be used in common, but other components are required for each carrier.

The operation in the receiver will be described.
The antenna 11 of the radio unit 10 receives the incoming radio wave, and the preselecting filter 12 attenuates the out-of-band signal with respect to the signal input from the antenna 11.
The low noise amplifier 13 increases the desired signal level by preventing the output signal from the preselecting filter 12 from adding noise as much as possible.

  The frequency conversion unit 14 mixes the radio frequency (RF) output from the low noise amplifier 13 and the carrier frequency (LO) signal output from the local oscillator 15 to make the radio signal a lower intermediate frequency (IF). Convert.

The IF filter (intermediate frequency filter) 16 attenuates unnecessary frequency components generated by the frequency converter 14 and signals from adjacent frequency channels.
The automatic gain control unit 17 performs automatic gain control on the output from the IF filter 16 in order to control a wide range of signal levels input to the receiving antenna 11.

  The AD converter (AD converter: ADC) 20 converts an analog signal output from the automatic gain control unit 17 into a digital signal based on a clock (CLK) input from the clock generation unit 30.

The quadrature detection unit 42 in the demodulation unit 40 performs digital quadrature detection, separates the output from the AD converter 20 into an I component (in-phase component) and a Q component (quadrature component), and the baseband filter 43 converts the original signal into The data is restored and transmitted to the baseband signal processing unit 100.
Then, the baseband signal processing unit 100 processes the data of the I and Q components.

  The clock generation unit 30 supplies a clock (CLK) to the AD converter 20 and the demodulation unit 40 based on the timing signal from the baseband signal processing unit 100.

  In a CDMA system including the above receiver, in recent years, at the interface between the receiver and the baseband signal processing unit 100, multicarrier processing (processing for receiving a plurality of carriers and transmitting them to the baseband signal processing unit) is performed. It was found that the case where the delay time deviation is specified occurs.

  Specifically, from the viewpoint of processing, it is not preferable for the baseband signal processing unit 100 that the delay time differs for each carrier. This is because the baseband processing unit 100 cannot grasp the delay time difference between the carriers.

Further, even if the delay time difference can be grasped, it is necessary to make a complex correction for the delay time deviation between carriers in the baseband signal processing unit.
In this case, since the interface with the baseband processing unit 100 is generally realized at the lowest possible frequency for cost reduction and downsizing, the time resolution is low at the low sampling frequency. In order to realize a complicated signal processing, it is necessary to increase the low frequency to a high frequency and correct based on the delay time deviation between carriers. As a matter of course, this makes the baseband processing unit an expensive / large-scale circuit.

  The cause of the delay time deviation for each carrier will be explained. Generally, analog parts always have a delay deviation due to individual variations and temperature changes. As an example, the delay time deviation of a device used in a cdma2000 receiver is ± 50 nsec for a duplexer (preselecting filter), and +60 nsec / −50 nsec for a SAW (Surface Acoustic Wave) filter (IF filter). The worst case delay deviation is +110 nsec / −100 nsec. This theoretically exceeds the interface global standard (± 102 nsec @ cdma2000) of a transmission amplifying device having a transmission / reception function, called CPRI (Common Public Radio Interface).

Therefore, in the prior art, there is a problem that each analog component has to be expensive and large-scale in order to reduce the delay deviation generated for each carrier.
For example, in the SAW filter, when the out-of-band attenuation near the desired band is large (the filter characteristic is steep), the delay deviation is increased, so that the out-of-band attenuation is relaxed as a countermeasure (the filter characteristic is gently )).

  However, if the out-of-band attenuation is alleviated, the amount of attenuation required by the system is insufficient, and the number of SAW filters must be increased, and in some cases, the number must be increased to increase the circuit scale. It was.

  As a baseband signal demodulator, there is JP-A-6-216896.

JP-A-6-216896

  Therefore, it is necessary to absorb the delay deviation by some means in order to keep the delay deviation in the analog region described above within the standard. As a delay time adjustment method realized in the digital signal domain, as a first solution (Solution 1), the sampling frequency of the AD converter is increased, and as a second solution (Solution 2), a shift register is used. The third solution (solution 3) is to change the coefficient of the baseband filter in the demodulator.

Hereinafter, each solution will be described.
As a solution 1, it is conceivable to increase the sampling frequency of the AD converter. When the sampling frequency is increased, the resolution of the delay time is improved according to the reciprocal of the frequency, and the delay deviation can be absorbed.
However, when a high-speed sampling AD converter is used, the costs of the AD converter and the subsequent circuit increase, and the circuit scale tends to increase.

  As a solution 2, the output signal from the AD converter is branched, one is delayed by using a shift register, the other is not delayed, and either signal is selected based on temperature information and frequency information for both signals, and a quadrature detection unit To output the delay deviation.

Solution 2 will be described with reference to FIG. FIG. 6 is a configuration block diagram of a receiver according to Solution 2. In addition, the same code | symbol is attached | subjected about the component similar to FIG. 5, and description is abbreviate | omitted.
As shown in FIG. 6, the receiver according to Solution 2 is a demodulator 40 that is different from FIG. 5.
The demodulator 40 shown in FIG. 6 includes a shift register 44, a selector 45, a quadrature detector 42, and a baseband filter 43. The quadrature detection unit 42 and the baseband filter 43 are the same as those in FIG.

The digital signal output from the AD converter (ADC) 20 is branched and input to one input terminal of the shift register 44 and the selector 44.
The shift register 44 delays the digital signal from the AD converter 20 and outputs it to the other input terminal of the selector 44.

The selector 44 receives a selection signal based on temperature information and frequency information from a control unit (CPU) (not shown), and selects either a digital signal from the AD converter 20 or a digital signal from the shift register 44 according to the selection signal. Select and output to the quadrature detection unit 42.
The shift register 44, the quadrature detection unit 42, and the baseband filter 43 are operated by the clock (CLK) from the clock generation unit 30.

  The control unit inputs the temperature information of the device from a sensor or the like, and inputs the frequency information of the received signal by a detector or the like. A selection signal is output so as to select a signal input from the shift register 44. If no delay deviation occurs, a selection signal is output so as to select a signal input from the AD converter 20.

  With the configuration and operation of the demodulator 40 as shown in FIG. 6, it is possible to set a delay and absorb the delay deviation, but it is impossible to control the delay time below the operation clock of the shift register 44. The delay setting with high accuracy was impossible.

As Solution 3, it is conceivable to absorb the delay deviation by changing the coefficient of the baseband filter 43 in the demodulator 40.
In the demodulator 40, the baseband filter unit is realized by a configuration of an FIR (Finite Impulse Response) filter, but the delay time can be adjusted by changing the filter coefficient.

  As an implementation example, FIG. 7 shows impulse responses of two different filter coefficients. FIG. 7 is a diagram illustrating an impulse response of the baseband filter. FIG. 8 shows frequency characteristics corresponding to the impulse response of each coefficient, and FIG. 9 shows delay time characteristics. FIG. 8 is a diagram illustrating frequency characteristics of the baseband filter, and FIG. 9 is a diagram illustrating delay time characteristics of the baseband filter.

  Referring to FIG. 8, although the frequency characteristics of the filters corresponding to the two impulse responses are equal, referring to FIG. 9, the delay times of the filters corresponding to the two impulse responses are different. In FIG. 9, the delay time of coefficient 1 is small and the delay time of coefficient 2 is large. That is, the delay time can be controlled by setting the filter coefficient.

  However, when the FIR filter is implemented by hardware such as an LSI (Large Scale Integrated Circuit) or FPGA (Programmable Gate Array: Field Programmable Logic Device), the filter coefficient may be fixed or the filter coefficient As a result, the hardware scale can be reduced by selecting a symmetrical coefficient as follows. However, if the filter coefficient is made variable, the above restriction becomes impossible, and the increase in the circuit scale results in an increase in cost as a device. It is.

  In the above solutions 1 to 3, it is technically possible to absorb the delay deviation, but problems such as an increase in cost and an increase in circuit scale occur.

  The present invention has been made in view of the above circumstances, and while suppressing the delay deviation, controlling the phase of the input clock (sampling clock) to the AD converter suppresses the increase in circuit scale and reduces the cost. An object of the present invention is to provide an improved receiver.

  The present invention for solving the problems of the above conventional example is a receiver for receiving a plurality of carrier signals, which is received by an antenna, attenuates an out-of-band signal of the received signal, and adjusts it to a desired signal level. The radio unit that converts the radio frequency to the intermediate frequency, the AD converter that converts the analog signal output from the radio unit into a digital signal, and the digital signal that operates on the standard clock and outputs the digital signal in phase The demodulator that performs quadrature detection on the component and the quadrature component and restores the signal, the clock generator that generates the standard clock, and the standard clock input from the clock generator based on the input temperature information and carrier frequency information And a control unit that outputs the sampling clock as a sampling clock to the AD converter, and outputs the sampling clock from the AD converter to the input of the demodulation unit. Reading, characterized in that a phase adjustment unit for reading the signal in the standard clock No..

  The present invention is a receiver for receiving a plurality of carrier signals, which is received by an antenna, attenuates an out-of-band signal of the received signal, adjusts it to a desired signal level, and converts a radio frequency to an intermediate frequency. Unit, an AD converter that converts an analog signal output from the radio unit into a digital signal, and a standard clock, and the digital signal output from the AD converter is quadrature detected into an in-phase component and a quadrature component, A demodulator for restoration, a clock generator for generating a standard clock, and an AD converter as a sampling clock by controlling the phase of the standard clock input from the clock generator based on the input temperature information and carrier frequency information A phase control unit that outputs to the demodulator, reads the signal from the AD converter with the sampling clock to the input of the demodulator, and receives the signal with the standard clock. Characterized in that a phase adjustment unit for reading.

  According to the present invention, a receiver for receiving a plurality of carrier signals, which is received by an antenna, attenuates an out-of-band signal of the received signal, adjusts it to a desired signal level, and converts a radio frequency to an intermediate frequency. A radio unit, an AD converter that converts an analog signal output from the radio unit into a digital signal, and a standard clock that operates with a standard clock, and quadrature-detects the digital signal output from the AD converter into an in-phase component and a quadrature component, Based on the input temperature information and carrier frequency information, the demodulator that restores the signal, the clock generator that generates the standard clock, and the standard clock input from the clock generator as the sampling clock A control unit that outputs to the AD converter, and reads the signal from the AD converter using the sampling clock to the input part of the demodulation unit, Since the receiver is provided with a phase adjustment unit for reading out the signal, the delay deviation is absorbed, and the phase of the sampling clock to the AD converter is controlled, thereby suppressing the increase in circuit scale and reducing the cost. There is.

  According to the present invention, a receiver for receiving a plurality of carrier signals, which is received by an antenna, attenuates an out-of-band signal of the received signal, adjusts it to a desired signal level, and converts a radio frequency to an intermediate frequency. A radio unit, an AD converter that converts an analog signal output from the radio unit into a digital signal, and a standard clock that operates with a standard clock, and quadrature-detects the digital signal output from the AD converter into an in-phase component and a quadrature component, Based on the input temperature information and carrier frequency information, the demodulator for restoring the signal, the clock generator for generating the standard clock, and the phase of the standard clock input from the clock generator are used as the sampling clock. It has a phase controller that outputs to the converter, reads the signal from the AD converter with the sampling clock to the input part of the demodulator, Since the receiver is provided with a phase adjustment unit for reading out the signal, the delay deviation is absorbed, and the phase of the sampling clock to the AD converter is controlled, thereby suppressing the increase in circuit scale and reducing the cost. There is.

Embodiments of the present invention will be described with reference to the drawings.
The receiver according to the embodiment of the present invention controls the phase of the sampling clock input to the AD converter based on the temperature information and the carrier frequency information, and writes the AD conversion and phase adjustment unit with the sampling clock. Since the data is output from the phase adjustment unit with the standard clock, the delay deviation can be absorbed, the increase in circuit scale can be suppressed, and the cost can be reduced.

A receiver according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of a receiver according to the first embodiment of the present invention. Parts having the same configuration as in FIG. 6 will be described with the same reference numerals.
As shown in FIG. 1, the receiver (first receiver) according to the first embodiment of the present invention includes a radio unit 10, an analog / digital converter (ADC) 20, a clock generation unit 30, and the like. The demodulator 40 and the controller 50 are included.
A baseband signal processing unit 100 is connected to the receiver.

The radio unit 10 includes an antenna 11, a preselecting filter 12, a low noise amplifier 13, a frequency conversion unit 14, a local oscillator 15, an IF filter 16, and an automatic gain control unit 17. ing.
The demodulator 40 includes a phase adjuster 41, a quadrature detector 42, and a baseband filter 43.

  In the case of receiving a multicarrier signal, the antenna 11, the preselecting filter 12, and the low noise amplifier 13 can be used in common, but other components are required for each carrier.

Next, each part of the first receiver will be specifically described.
The antenna 11 of the wireless unit 10 receives incoming radio waves.
The preselecting filter 12 attenuates the out-of-band signal with respect to the signal input from the antenna 11.
The low noise amplifier 13 amplifies the output signal from the preselecting filter 12 to a desired signal level so as not to add noise.

The frequency conversion unit 14 mixes the radio frequency (RF) output from the low noise amplifier 13 and the carrier frequency (LO) signal output from the local oscillator 15 to make the radio signal a lower intermediate frequency (IF). Convert.
The local oscillator 15 outputs a carrier frequency (LO) signal to the frequency converter 14.

The IF filter (intermediate frequency filter) 16 attenuates unnecessary frequency components generated by the frequency converter 14 and signals from adjacent frequency channels.
The automatic gain control unit 17 performs automatic gain control on the output from the IF filter 16 in order to control a wide range of signal levels input to the receiving antenna 11.

  The AD converter (AD converter: ADC) 20 converts the analog signal output from the automatic gain control unit 17 into a digital signal based on the sampling clock (ADCLK) of the AD converter input from the control unit 50.

  The phase adjustment unit 41 in the demodulation unit 40 receives ADCLK from the control unit 50, inputs an output from the AD converter 20 synchronized with the ADCLK, inputs a clock (CLK) from the clock generation unit 30, and inputs the clock (CLK). The signal is converted to a signal synchronized with CLK and output to the quadrature detection unit 42. Here, in order to distinguish clearly from ADCLK, the clock from the clock generation unit 30 is referred to as a reference clock (reference CLK).

  The phase adjustment unit 41 is realized by, for example, a FIFO (First In First Out) memory or the like. In particular, signal data is input based on ADCLK, and data is output based on reference CLK.

  The quadrature detection unit 42 operates with the standard CLK from the clock generation unit 30, performs digital quadrature detection, and separates the output from the phase adjustment unit 41 into an I component (in-phase component) and a Q component (quadrature component). Output to the band filter 43.

The baseband filter 43 operates with the standard CLK from the clock generation unit 30, restores the original signal, and transmits the original signal to the baseband signal processing unit 100.
Then, the baseband signal processing unit 100 processes the data of the I and Q components.

  The clock generation unit 30 supplies a standard clock (standard CLK) to the control unit 50, the phase adjustment unit 41, the quadrature detection unit 42, and the baseband filter 43 based on the timing signal from the baseband signal processing unit 100.

  The control unit 50 selects normal rotation or inversion of the standard CLK output from the clock generation unit 30 based on temperature information and frequency information input from the outside, and uses the clock as a sampling clock (ADCLK) of the AD converter. Output to the AD converter 20 and the phase adjustment unit 41.

For example, the control unit 50 monitors the delay time of the analog signal input to the AD converter 20 via the radio frequency and the intermediate frequency, and if the delay time is within the set value (delay deviation allowable value), Output CLK with normal rotation.
The set value is a value measured by conducting an experiment or simulation in advance.

  In addition, the control unit 50 is a case where the signal input to the AD converter 20 is delayed from the set value due to the temperature characteristic and the frequency characteristic, and is further delayed by 1/2 clock (0.5 clock) cycle or more. Performs the following calculation, and inverts and outputs CLK in a specific case.

When the set value (delay deviation allowable value) is Y and the delay deviation of the analog signal input to the AD converter 20 is X, if X−0.5 clock cycle <Y, CLK is inverted and output. To do. This is because the amount of delay can be absorbed by sampling with the inverted clock.
However, if X−0.5 clock cycle ≧ Y, CLK is rotated forward and output. This is because when the delay deviation X is sufficiently large and the delay is close to one clock cycle of the reference CLK, the delay amount can be absorbed by sampling with the normal rotation clock.

The operation of the first receiver will be described with reference to FIG. FIG. 2 is an operation time chart of the first receiver.
As shown in FIG. 2, the reference timing signal output from the baseband signal processing unit 100 is shown in the first stage. The period of the reference timing signal is 10 msec.
The second stage shows a reference clock generated by the clock generation unit 30 based on the reference timing signal. In this embodiment, the reference clock is generated so as to be synchronized with the rising edge of the reference timing signal.

In the lower half of FIG. 2, the upper half of FIG. 2 shows the case of a reference with no delay as case 1 (case 1).
Since there is no delay, the control unit 50 performs normal rotation of the standard clock from the clock generation unit 30, that is, the same clock (ADCLK) as the reference clock is input to the AD converter 20, and sampling is performed.

  An input signal to the AD converter 20 is shown in the lower stage of ADCLK, an output signal of the AD converter 20 is shown in the lower stage, and an output signal from the phase adjustment unit 41 that outputs a signal with a standard clock is shown.

  The lower half of FIG. 2 shows a case 2 (case 2) where the allowable delay deviation is exceeded. In this case 2, the input signal to the AD converter 20 is when the delay amount X exceeds the delay deviation allowable value Y due to temperature, frequency characteristics and individual variations of the wireless device (Y <X <1 clock cycle). In this case, X−0.5 clock cycle <Y. However, Y is set to a value of 110 nsec or less in order to satisfy the CPRI standard.

In the above case, the control unit uses the inversion of the reference clock as the AD sampling clock. Therefore, the AD converter 20 samples the AD converter input signal using the inverted clock as ADCLK.
The output data from the AD converter 20 and the output signal from the phase adjustment unit 41 that outputs a signal using the standard clock are shown at the bottom of FIG.

Thereby, the delay deviation in the receiver output can be kept within the allowable value.
When the allowable value Y is not satisfied, for example, it is used together with an n-stage shift register. This shift register may be installed before or after the phase adjustment unit 41. By using the shift register, the relationship of X−0.5 clock cycle−1 clock cycle * n (n is an integer) <Y can be maintained, and even when the delay deviation is larger than one clock period, the delay deviation Can be absorbed.

  According to the first receiver, when the analog signal input to the AD converter 20 is delayed due to the temperature characteristic and the frequency characteristic, the phase adjustment unit 41 converts the received signal from the AD sampling clock (ADCLK) to the reference clock. By switching to, the amount of delay can be absorbed with a resolution of 1/2 clock.

  It is also conceivable to further simplify the operation at the first receiver. For example, when the delay deviation X is 0 ≦ X <¼ clock cycle, the forward rotation clock is 1/4, the clock cycle ≦ X <3/4 clock cycle, the inverted clock is 3/4 clock cycle ≦ X <1 clock. The control unit 50 may output the normal rotation clock at a cycle.

Next, a receiver (second receiver) according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a configuration block diagram of a receiver according to the second embodiment of the present invention.
As shown in FIG. 3, the second receiver is basically the same as the first receiver, except that a phase control unit 60 is provided instead of the control unit 50. It is.
In the second receiver, the difference from the first receiver will be described, and the same configuration and operation will be omitted.

  The phase control unit 60 controls the phase of the standard clock output from the clock generation unit 30 based on temperature information and carrier frequency information input from the outside, and outputs it as a sampling clock (ADCLK) of the AD converter 20.

  When the phase control unit 60 is realized using, for example, a PLL (Phase Locked Loop), when the delay time of the analog signal input to the AD converter 20 via the radio frequency and the intermediate frequency is a reference value (no delay) ), A clock is output with a phase shift amount 0 (zero) of CLK.

If the signal input to the AD converter 20 has a delay time delayed by a delay amount X (X <1 clock cycle) or more from the reference value due to temperature characteristics and frequency characteristics, the phase control amount is set to PLL and the clock is set. Output.
Specifically, the phase control amount is set in advance in the PLL according to the delay amount of the signal input to the AD converter 20 and the clock is output according to the phase control amount corresponding to the actual input signal delay amount. To do.

The operation of the second receiver will be described with reference to FIG. FIG. 4 is an operation time chart of the second receiver.
The upper case 1 (case 1) in FIG. 4 shows a state without delay and is the same as the case 1 in FIG.

The lower part of FIG. 4 is a characteristic part of the second reception operation, and the phase control unit 60 determines the phase of the AD converter operation clock (ADCLK) according to the delay amount (delay deviation X) of the input signal to the AD converter 20. Is controlling.
The output signal of the AD converter 20 is output to the phase adjustment unit in synchronization with the rising edge of the ADCLK. The phase adjustment unit 41 outputs a signal at the standard clock timing.

  The second receiver can hold the relationship of delay deviation X-PLL phase control amount <delay deviation allowable amount Y. If the allowable value Y is not satisfied, the same as the first receiver. For example, it is used in combination with an n-stage shift register. Then, the relationship X-PLL phase control amount-1 clock cycle * n (n is an integer) <delay deviation allowable amount Y can be maintained, and even if the delay deviation exceeds 1 clock cycle, the delay deviation can be absorbed. is there.

  In the second receiver, the delay time can be adjusted to a resolution capable of controlling the phase of the PLL as compared with the first receiver, and the accuracy can be improved.

  The present invention is suitable for a receiver that suppresses an increase in circuit scale and reduces costs by absorbing a delay deviation and controlling the phase of a sampling clock in an AD converter.

It is a block diagram of the configuration of the receiver according to the first embodiment of the present invention. It is an operation | movement time chart of a 1st receiver. It is a block diagram of the configuration of the receiver according to the second embodiment of the present invention. It is an operation | movement time chart of a 2nd receiver. It is a block diagram of a receiver according to a conventional example. FIG. 10 is a configuration block diagram of a receiver according to Solution 2. It is a figure which shows the impulse response of a baseband filter. It is a figure which shows the frequency characteristic of a baseband filter. It is a figure which shows the delay time characteristic of a baseband filter.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Radio part, 11 ... Antenna, 12 ... Pre-selecting filter, 13 ... Low noise amplifier, 14 ... Frequency conversion part, 15 ... Local oscillator, 16 ... IF filter, 17 ... Automatic gain control part, 20 ... AD conversion (ADC: AD converter), 30 ... Clock generation unit, 40 ... Demodulation unit, 41 ... Phase adjustment unit, 42 ... Quadrature detection unit, 43 ... Baseband filter, 44 ... Shift register, 45 ... Selector, 50 ... Control unit 60 ... Phase control unit 100 ... Baseband signal processing unit

Claims (2)

A receiver for receiving a plurality of carrier signals,
A radio unit that is received by an antenna, attenuates an out-of-band signal of the received signal, adjusts to a desired signal level, and converts a radio frequency to an intermediate frequency;
An AD converter that converts an analog signal output from the wireless unit into a digital signal;
A demodulator that operates with a standard clock, quadrature-detects the digital signal output from the AD converter into an in-phase component and a quadrature component, and restores the signal;
A clock generator for generating a standard clock;
Based on the input temperature information and carrier frequency information, and having a control unit for normal rotation or inversion of the standard clock input from the clock generation unit and output to the AD converter as a sampling clock,
A receiver comprising: a phase adjusting unit that reads a signal from the AD converter using the sampling clock and reads the signal using a standard clock at an input portion of the demodulating unit. A receiver for receiving a plurality of carrier signals,
A radio unit that is received by an antenna, attenuates an out-of-band signal of the received signal, adjusts to a desired signal level, and converts a radio frequency to an intermediate frequency;
An AD converter that converts an analog signal output from the wireless unit into a digital signal;
A demodulator that operates with a standard clock, quadrature-detects the digital signal output from the AD converter into an in-phase component and a quadrature component, and restores the signal;
A clock generator for generating a standard clock;
A phase control unit that controls the phase of the standard clock input from the clock generation unit based on the input temperature information and carrier frequency information and outputs the sampling clock to the AD converter as a sampling clock;
A receiver comprising: a phase adjusting unit that reads a signal from the AD converter using the sampling clock and reads the signal using a standard clock at an input portion of the demodulating unit.

Images