JP4347270B2 - Video timing display apparatus and method - Google Patents

Description

The present invention relates generally to video timing, and more particularly to a multi-rate system video timing display apparatus and method that allows a user to quickly, easily and accurately measure the timing between multiple video signals at different rates.

  Conventional methods for confirming the timing between a plurality of video signals have used waveform display and a vector scope. Here, the signal of interest was used as an input and a reference signal was supplied to the “external” reference port. First, the vertical timing was confirmed using a field rate sweep. Next, the horizontal timing was confirmed using a line rate sweep. Finally, SCH (subcarrier-to-horizontal) mode in composite video signal systems is used to ensure that the multiple color frames are in the correct alignment and timing is subcarrier phase Was checked with sufficient accuracy.

  This conventional method takes time for measurement, is difficult, and has a possibility of error. In order to examine the horizontal and vertical timing, the waveform had to be shifted and the feature had to be enlarged. At this time, the system had to be adjusted to a desired timing, and the display had to be manually positioned so that the characteristic portion could be confirmed. Due to the slow rise time of the video sync pulse, the confirmation of the horizontal timing may be inaccurate. Also, during the external reference mode, all monitors cannot accurately display the SCH, which raises questions about color frame alignment. Finally, switching between the internal reference mode and the external reference mode or switching between a plurality of inputs was performed to compare the timing of a plurality of signals.

  Another way to determine the timing offset was to examine the image against an external reference. The advantage of this method is that it can show both horizontal and vertical offsets simultaneously. Unfortunately, however, this method is difficult to obtain high measurement accuracy and is not suitable for confirming color frame alignment well.

  According to the conventional method, the timing reference measurement requires that the input line rate and frame rate be an integer multiple of the reference rate. If this condition is not satisfied, the measurement result is uncertain and cannot be used. An example is a timing difference of 24 Hz video with respect to a reference 30 Hz video as shown in FIG. For each frame with 30 Hz reference, in the next frame with 24 Hz input, the possible delay is one of the four delays d1, d2, d3, d4. This pattern repeats after 5 frames of 30 Hz input signal or after 4 frames of 24 Hz. Each group of these frames consists of a “superframe” in each signal, ie, 5 frames of 30 Hz signal and 4 frames of 24 Hz signal. A 30 Hz signal is simply divided by 4 and one of the resulting phases is selected appropriately, and any of these 4 delays is a random detection timing. Also, some combinations of different rate video signals have different numbers of possible phases. In other common standards, for example, there are two or five such ambiguous phases.

  The SMPTE 318M standard provides a possible way to remove ambiguity from several combinations. The SMPTE 318M standard is extended to transmit a 10-field sequence identification signal superimposed on an NTSC black signal used as a reference. Since the length of this 10-field signal is 5 frames, it properly identifies which of the 5 delays is the correct delay and deletes the other 4 delays. Unfortunately, since many video signals do not carry the SMPTE 318M 10 field identification flag, other methods are still sought.

  In other methods, a large number of possible phases were observed and the smallest offset was selected. These waveforms were displayed as if they were at the right time. This works in many cases, but does not indicate to the user which choice has been made, and could not lock one particular phase of the video signal as a reference and measurement timing for multiple video signals. Thus, it was not possible in practice to time one video signal to another video signal at the same rate due to the known relationship with different rate criteria.

JP 60-1227897 A JP-A-60-254925

Therefore, a display device and method that allow a user to quickly and easily measure timing differences between a plurality of video signals at different rates is desired.

The present invention provides an apparatus for measuring timing between a plurality of video signals of different rates; in each video signal, means for extracting a pulse corresponding to the common reference point from the respective video signals (30, 32) Means for determining an interval between two pulses (34); means for determining a video format of each of the video signals (31, 33); a phase value between the video format and the plurality of video signals from the interval Means (36) for analyzing the phase value to generate a horizontal timing offset and a vertical timing offset for each phase value; and a horizontal timing offset and a vertical timing offset for each phase value. Means (38) for displaying as a timing display. Reference numerals in parentheses merely indicate a relationship with the embodiment. Further, the present invention is a method for displaying timing between a plurality of video signals in a multi-rate system; determining a plurality of phases between a pair of video signals of different rates; the pair of videos A graphic representation of the phase is provided in the form of a timing phase indicator (16, 16 ') relative to a reference indicator (14) associated with one of the signals.

  Thus, the video timing display for multi-rate systems of the present invention allows a user to quickly, easily and accurately measure timing differences between multiple video signals at different rates. The graphic display area within the raster display range displays the vertical and horizontal timing offset of one video signal with respect to another video signal as a reference. The graphic display area includes a reference indicator indicating a reference timing in the graphic display area and a plurality of timing indicators indicating a timing phase of one video signal with respect to the reference in the graphic area. Note that one of these multiple timing indicators is highlighted, which is generally closest to the reference indicator. A numeric display area may be provided in the vicinity of the graphic display area to display the actual vertical and horizontal timing differences in units appropriate for the highlighted timing indicator, with an accuracy of one video clock cycle. Also, the video signal that is the reference source may be shown in the numeric display area, and optionally, a warning when the timing between the two video signals falls outside a predetermined limit may be shown. In a measuring instrument having a tiled raster display, the vector display is shown in relation to the timing display, and the subcarrier phase can be finely discriminated between the analog composite video signals for hue matching.

  Objects, advantages and novel features of the invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.

  FIG. 2 shows a video timing display according to the present invention. In this example, video timing is shown in a two-dimensional display. The graphic display area 12 in the raster display range (display screen) 10 shows vertical timing along one axis and horizontal timing along the other axis. In the center of the graphic display area 12, a reference indicator 14 represents a reference timing position for a video signal used as a reference. Also, the timing indicator 16 is shown to visually depict the timing of each phase of another video signal at a rate different from the reference. A numeric lead-out area 18 adjacent to the graphic display area 12 is provided to provide a vertical offset value for one indicator 16 ′ of a plurality of timing indicators, generally one timing indicator 16 ′ closest to the reference indicator 14. 20 (for example, represented by the number of lines) and a horizontal offset value 22 (for example, represented by time) may be displayed. In general, the numeric lead-out area 18 can display the vertical and horizontal offsets of all timing indicators 16. One timing indicator 16 'is displayed as more emphasized as a primary indicator (for example, shown by a bold line), while the other timing indicators 16 are displayed as less emphasized as a secondary indicator (for example, (Indicated by a thin line). The smaller number of m and n in the general compound formula m × F = n × R determines the total number of timing indicators 16. Note that F is one video frame rate and R is the other video frame rate.

  In FIG. 1, in this example, m and n are 5 and 4, respectively. Here, since the reference is a 30 Hz frame rate and the other video signals are 24 Hz frame rates, 5 × 24 = 4 × 30. A reference source indicator 24 is also shown on the display. This reference source indicator 24 indicates which video signal is used as a reference. In the illustrated embodiment, the reference source is an external reference. The horizontal axis of the graphic display area 12 indicates whether the line timing is advanced or delayed, and the vertical axis timing indicates whether the timing in the frame is advanced or delayed. When the enhanced timing indicator 16 'is aligned with the reference indicator 14, the video signal is precisely timed with the reference. In order to determine the timing between a plurality of video signals with a single value, the line and frame rates of a video signal need not be an integer multiple of the reference rate. This example shows a 5: 4 rate that produces four phases. In practice, however, more than 10 phases may be obtained for display, but any number of phases may be used.

  Standards according to SMPTE 318M may be used. In this case, the relationship defined by the SMPTE 318M sequence is a “correct” timing relationship, and the indicator is the one that is highlighted instead of the indicator closest to the reference indicator 14.

  The reference indicator 14 may be at the center of the graphic display area 12 as shown by a solid line in the form of a cross, for example, or a tick mark extending across the entire width of the graphic display area represents a rough offset scale. Also good. In this case, one tick mark tick mark may be expressed in the vertical direction by the number of lines (Y lines) corresponding to one video standard of a plurality of video signals, and in the horizontal direction by seconds (X microseconds). Good. The timing indicator 16 may be in any suitable form such as a circle as shown in the illustrated method.

  Since the width of the horizontal axis shown in this embodiment is one video line, the scale is +/− 1/2 line. The vertical dimension varies depending on the video signal or the reference format. In the case of interlaced digital video, the vertical dimension (the width of the vertical axis) is 1 frame (2 fields). For composite video signals such as NTSC and PAL, the vertical dimension is one color frame (4 or 8 fields). For progressive video, the vertical dimension is one field.

  Numeric information gives a more accurate result than the graphic display method alone without enlarging the display. Both graphical display and numeric readout are shown in terms of horizontal and vertical dimensions. This is convenient for the user as it shows how to make accurate timing adjustments.

  As indicated by the reference source indicator 24, the timing of a video signal is relative to an external video signal that is a reference. This is a substantially absolute mode and the external video signal is a timing standard for video equipment, for example. The user may select another video signal as a display reference. In that case, the first video signal is compared with the external video signal and the offset is stored as a “baseline”. The video signal input thereafter can be compared with the baseline. In this mode, the baseline timing is represented by the reference indicator 14 and the reference source indicator 24 represents the source of the “accumulated baseline”. This latter mode is useful for timing various video signals input to the switcher. The reason is that in this case the absolute timing for the external video signal is not important. What is important is that all video signals entering the switcher arrive at the same time. Using one of the plurality of video signals to generate an accumulated baseline, the remaining video signals are timed and the display provides a simple way to time to the switcher.

  When measuring the difference between two video signals of the same rate due to their relationship to different rate criteria, the measured difference is not just the smallest difference selected. Instead, as shown in FIG. 4, a reference (emphasized) edge or phase (indicated by "0") used when measuring a baseline with a certain video signal VID1 as a reference is stored, and thereafter Becomes a reference phase used for timing the video signal VID2. To do this, the reference is considered to have a “superframe” and each frame of reference within this superframe limits the phase of the reference. For the example where the reference has 4 frames of the same duration as the 5 frames of the video signal, the timing for VID1 limits the phase of the locked reference (R1), so the subsequent video signal VID2 is timed to the same phase. That is, it is used so that the timing is matched for every fourth reference frame. Using the “closest” timing (indicated by “x”), VID2 is timed with the reference R2, so that VID1 and VID2 are not timed with each other. This mode is invoked when the user needs it, and displays the text “Locked Reference Baseline” in the “Relative Timing” box 24. In this mode, the emphasized timing circle is necessarily not closer to the center, but is limited by the locked reference split relationship. This mode needs to be re-established if the reference loses lock or if a certain time such as one hour has passed. Also, although not shown, the “Display Scaling” option analyzes graphic and numeric readouts to determine horizontal and vertical advanced or delayed values depending on the input or reference raster configuration. Can do.

  In digital switchers, most switchers have some tolerance for their input timing errors, so the display accuracy is higher than necessary. Analog composite switchers are not so much tolerated. In analog applications, the display of the present invention can be used to obtain an accuracy within one video clock cycle, so a vectorscope or other method can be used to provide very fine identification of the carrier phase. This is very useful for “tiled” display measuring instruments. This is because the vector display is displayed simultaneously with the timing display.

  Another application for timing display is automation. Since the timing display gives a numerical result, the timing error can be read without mediating the user and the necessary timing correction can be provided to the input video signal via the automation system. This can greatly reduce the setup time for video production.

  A scale can be added to indicate an acceptable range under less severe conditions. These tick marks are horizontal and vertical bars that define a small window in the graphic display area 12 around the reference indicator 14. If the closest timing indicator 16 'is within the box (window), the timing is OK. Once an acceptable timing range is determined, an alarm can be generated if the timing is outside that range. This alarm is reported by measuring equipment such as SNMP (System Network Management Protocol, ie, annotation (RFC) trap Internet Engineering Task Force (IETF) request) trap, on-screen icon, and termination due to grounding. A method is used to communicate this situation to the user or automation system.

  As shown in FIG. 3, in a particular implementation, there are six parts. The reference and input video signals are input to timing extractors 30 and 32, respectively. These timing extractors 30, 32 detect line 1 of field 1 of both video signals and generate a pulse at this detection time. The counter 34 is used to measure the time difference (interval) d between the pulses extracted from the two video signals. That is, the counter 34 starts counting by one of these pulses. The counter 34 counts a normal video clock cycle derived from the reference video timing extractor 30 (the video clock signal line is not shown). The other of the pulses of the timing extractors 30 and 32 stops the counter 34 from counting. Thus, the counter 34 can measure the time difference d between the pulses extracted from the two video signals. The video formats of the reference and input video signals are detected by format recognition circuits 31 and 33. The deduction calculator 35 uses this detection result. The deductive calculator 35 uses the value d from the counter 34 and the detected format, i.e., a general multiple relationship based on the detected different frame rates, m * F = n * R, for all possible. Calculate the correct timing value.

  At some frame rates, it takes a long time for all phases to occur. This makes the display update rate very slow and difficult to use. Thus, in the method of the present invention, it is only necessary to measure one phase between two video signals. Thus, by using known configurations of different formats of the video signal, the deductive calculator 35 can determine other phases by calculation. The phase value from the deductive calculator 35 is input to the parser 36. The parser 36 analyzes the phase value according to the raster configuration of one video signal and decomposes it into horizontal and vertical advance or delay. The result of the parser 36 is supplied to the measuring device 38 and the timing display shown in FIG. 2 is performed in the raster display area 10 of the measuring device display 38. This result may also be used as an output to an automatic system and automatic timing adjustment may be performed on the input video signal.

  Although the above example is a two-dimensional display, the basic concept of the present invention is to simultaneously display multiple phases between multiple video signals of different frame rates, regardless of the specific display format used. is there. Therefore, the display can be linear (one-dimensional) or multi-dimensional (three or more dimensions).

  Therefore, the present invention obtains a plurality of phase values representing appropriate timing indicators for the reference indicator by using different video signal formats and a count value obtained from a time difference between common reference points in each video signal. • The rate system timing can be displayed.

FIG. 2 shows a conventional timing measurement between a 24 Hz video signal and a 30 Hz video signal as a reference. FIG. 6 is a plan view of a video timing display according to the present invention. FIG. 2 is a simplified block diagram of an apparatus for generating a video timing display according to the present invention. FIG. 5 is a diagram illustrating timing between a plurality of video signals at a rate using a video signal at another rate as a reference according to the present invention.

Explanation of symbols

10 Raster display range (display screen)
12 Graphic display area 14 Reference indicator 16, 16 'Timing indicator 18 Number readout area 20 Vertical offset value 22 Horizontal offset value 24 Reference source indicator 30, 32 Timing extractor 31, 33 Format detector 34 Counter 35 Deduction Calculator 36 Parser 38 Measuring instrument indicator

Claims (2)

An apparatus for measuring timing between a plurality of video signals at different rates,
Means for extracting a pulse corresponding to a common reference point from each video signal in each video signal;
Means for determining the interval between the two above pulses;
Means for determining the video format of each of the video signals;
Means for deriving phase values between the plurality of video signals from the video format and the interval;
Means for analyzing the phase value to generate a horizontal timing offset and a vertical timing offset for each phase value;
A video timing display device comprising: means for displaying the horizontal timing offset and the vertical timing offset for each phase value as a timing display. A method for displaying timing between multiple video signals in a multi-rate system, comprising:
Determining multiple phases between a pair of video signals of different rates;
A video timing display method comprising: displaying a graphic representing the phase in the form of a timing phase indicator for a reference indicator associated with one of the pair of video signals.

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