JP4326370B2 - Sampling circuit - Google Patents

Description

  The present invention relates to a sampling circuit, for example, VPS (Video Program System), PDC (Program Delivery Control), etc. that enable automatic recording adjustment of a VTR, recognition of a broadcasting station, etc. Is used to compare the level of the input signal superimposed in the vertical blanking period with the reference voltage, and in particular, when extracting data signals such as VPS and PDC from the broadcast signal superimposed in the vertical blanking period. The present invention relates to a sampling circuit suitable for use in a level comparator or the like.

  In recent years, as an applied technique using a sampling circuit, a level comparator using a D / A converter has been proposed as shown in the block diagram of FIG. The level comparator shown in FIG. 3 includes a timing generation circuit 10, a control circuit 20, a D / A converter (conversion circuit) 30, and a comparator (comparison circuit) 40.

  The timing generation circuit 10 generates a D / A control permission signal for enabling the control circuit 20 from “LOW” to “HIGH” from a predetermined vertical synchronization signal VSync and horizontal synchronization signal HSync included in the video signal. It becomes. When the D / A control permission signal is generated, the control circuit 20 becomes operable (D / A control is possible). The timing generation circuit 10 has a timer 70, and the timing at which the D / A control permission signal changes from “LOW” to “HIGH” is adjusted by the timer 70.

  The control circuit 20 includes a sampling circuit that samples the output value (CMP output) of the comparator 40 during a period in which D / A control is possible (D / A control permission signal is “HIGH”). In response, a digital value that increases or decreases with a certain difference in value is output to the D / A converter 30.

  The sampling frequency used in the sampling circuit is set to be several times (for example, 4 times) the input clock.

  The level comparator using the D / A converter 30 creates an analog signal that becomes a slice level in accordance with the digital value set in the D / A converter 30, and transmits the analog signal using the created slice level. Comparison with the video signal coming.

  The digital value set in the D / A converter 30 can be finely adjusted. When the clock run-in signal is untuned for some reason, the digital value is increased or decreased to increase the clock included in the video signal. There is an advantage that the run-in signal can be accurately separated.

  However, to increase or decrease the digital value, the clock run-in signal and the slice level comparison result are signed with an integer multiple of the clock run-in signal frequency, and if the clock run-in signal is large, the slice level is increased. On the contrary, if the clock run-in signal is small, processing for decreasing the slice level is performed.

Patent Document 1 describes a technique related to a sampling circuit that makes the number of sampling clocks per horizontal scan constant when converting a video signal into a digital signal, regardless of a change in horizontal scan frequency due to multi-scan. ing.
Japanese Patent Laid-Open No. 9-154033

  FIG. 4 shows a sampling clock synchronized with the bit rate of an input video signal, which is used for detection of input data. The example shown in FIG. 4 is a specific example in which a clock having a quarter cycle of the bit width of the input data is used as the sampling clock for detection of the input data, and the input data and the sampling clock are completely Synchronized with.

  When the sampling clock synchronized with the bit rate of the input video signal shown in FIG. 5 is used for data detection, an error has occurred between the input video signal and the sampling clock for some reason. In such a case, there has been a problem that the synchronization of the timing of data detection is gradually shifted and erroneous data is detected.

  In addition, when the method of increasing the sampling clock is used to reduce the error, a high-speed clock is generated by a PLL or the like, and noise may be mixed from the periphery of the PLL, and the influence of noise. Therefore, there is a problem in that the comparison between the clock run-in signal and the slice level may be adversely affected and the power consumption increases.

A main invention according to the present invention is a frequency dividing circuit that divides a first clock signal to generate a first sampling signal, and a first signal that samples a binary signal having an H level and an L level by the first sampling signal. a sampling unit, based on the binary signal to the frequency which is the H level and L level of the second sampling section for by Ri sampling the first clock signal, successive sampling result of a predetermined number of the second sampling unit Te, and a discrimination circuit for determining whether it is desired sampling timing out sampling in the binary signal is the first sampling unit, in response to an output signal of said identification circuit, the first sampling part wherein the Ru changing the sampling points.

  Further, other features of the present invention will become apparent from the accompanying drawings and the description of the present specification.

  According to the present invention, by including an identification circuit that determines whether or not the input signal is sampled at a desired sampling timing based on the sampling result before or after the sampling point, according to the output signal of the identification circuit The advantage is that the sampling point of the sampling circuit can be changed and the sampling point can be corrected to the optimum position.

  Further, the identification circuit includes a counter that counts whether the sampling result before or after the sampling point is H or L, so that the sampling point can be corrected with high accuracy.

  Details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing a level comparator incorporating a sampling circuit according to the present invention. As shown in the figure, the level comparator has a timing generation circuit 10, a control circuit 20, a D / A converter (conversion circuit) 30, and a comparator (comparison circuit) 40. The level comparator shown in FIG. 1 performs operations equivalent to those of the timing generation circuit 10, the control circuit 20, the D / A converter (conversion circuit) 30, and the comparator (comparison circuit) 40 shown in FIG.

  The control circuit 20 includes a shift register 21, a register 22, an overflow detection circuit 23, a determination circuit 24, a reset circuit 25, a variable frequency dividing clock generation circuit 26, and a digital value output circuit 27.

  The signal from the comparator 40 is sampled in the shift register 21 using a clock. The shift register 21 is a five-stage shift register and can hold five consecutive data. The overflow detection circuit 23 generates an overflow signal every time it counts four times using the clock, outputs the data stored in the shift register 21 to the register 22, and the register 22 holds the data. The determination circuit 24 determines the held data. Depending on the number of the H level and the L level, the variable frequency dividing clock generation circuit 26 is controlled to correct the sampling position of the frequency dividing clock that actually takes in the data to obtain the optimum sampling position.

  Hereinafter, an embodiment will be described with reference to FIG. 2 showing a detailed internal block diagram of the control circuit 20. The shift register 21 shown in FIG. 2 is a five-stage shift register. The output from the comparator 40 is input to the first-stage flip-flop (FF) 210 of the shift register 21, and is shifted in the order of FF210 → FF211 → FF212 → FF213 → FF214 every time the clock rises. The overflow detection circuit 23 is a quinary counter, which starts from the rising edge of the divide-by-4 clock, and is incremented for each clock. 000h (0) → 001h (1) → 010h (2) → 011h (3) → 100h (4) When 100h (4) is reached, the overflow signal is changed from “LOW” to “HIGH” as a flag indicating overflow.

  The overflow signal is input to the register 22, and is used as a timing signal for latching data of the FF220, FF221, FF222, FF223, and FF224. Therefore, the data held in the shift register 21 is transferred to the register 22 by the flag indicating the overflow of the overflow detection circuit 23. As is clear from the connection in FIG. 2, the data of FF210 is held in FF220, the data of FF211 is held in FF221, the data of FF212 is held in FF222, the data of FF213 is held in FF223, and the data of FF214 is It is held in the FF 224. Here, the shift register 21 is a five-stage shift register, but since the overflow detection circuit is a quaternary counter, among the data held in the shift register 21, the data held in the FF 210 is always At the next overflow time, it is held in the FF 214.

  When the overflow signal from the overflow detection circuit changes from “LOW” to “HIGH”, 5-bit data is output from the shift register 21 to the register 22.

  The determination circuit 24 can see the data in which 5-bit data is output to the register 22 from the shift register 21. In the 5-bit data, the ratio of “1” to “0” is “1”: In the case of “0” = 2: 3 or “1”: “0” = 3: 2, the timing at which the comparator latches the data is not greatly deviated. In the variable frequency dividing clock generation circuit 26, It can be determined that there is no need to adjust the clock.

  However, in the 5-bit data, the ratio of “1” to “0” is “1”: “0” = 1: 4, “1”: “0” = 4: 1, “1”: “0”. "= 0: 5," 1 ":" 0 "= 5: 0, the timing at which the comparator latches data is not appropriate, and the variable frequency dividing clock generation circuit 26 needs to adjust the clock. It can be judged that there is.

  In the case of adjustment, the variable frequency dividing clock generation circuit 26 divides the supplied clock by 4 to create a divided frequency clock, and performs a process of advancing or delaying by one cycle of the supplied clock. Do.

  A specific timing operation will be described with reference to FIGS. 4, 5, and 6.

  FIG. 4 shows a case where the input data capture timing is normal. In FIG. 4, the clock is divided by four from the clock to be supplied, and the divided clock is generated, and the input data from the comparator 40 is used as the capture timing using the divided clock. When a clock run-in signal is input, the input data from the comparator 40 has a “LOW” ratio of “HIGH” of 50:50, and the input data capture timing is shown in FIG. As described above, it is desirable to capture the input data at approximately the center of the input data to obtain the captured data. In the waveform shown in FIG. 4, the divided clock by 4 (data capturing clock) is synchronized with the input data, and the input data is latched at almost the center of the input data. At the same time as the rising of the divide-by-4 clock, five consecutive data samples using the clock are acquired. In this state, it can be seen that the ratio of “1” and “0” is “1”: “0” = 3: 2 for five consecutive data.

  FIG. 5 shows a case where the input data capture timing is out of order. In FIG. 5, the input data is out of synchronization with the divide-by-4 clock (data capture clock), and erroneous data is captured. When the synchronization is lost, the timing of capturing the input data gradually deviates from the center, eventually approaches the changing point of the input data, and after several cycles, erroneous data is captured. The erroneous data fetching shown in FIG. 5 occurs due to a synchronization shift between the divided-by-4 clock (data fetching clock) and the input data. In the 5-bit data, “1” and “0” It is desirable to correct the divided-by-4 clock when the ratio becomes “1”: “0” = 4: 1.

  In FIG. 6, in the 5-bit data, when the ratio of “1” and “0” is “1”: “0” = 4: 1, a specific example of correcting the divided clock by 4 Will be explained.

  In section A, 5-bit data is sampled by the clock. In this 5-bit data, the ratio of “1” to “0” is “1”: “0” = 4: 1, and “1” is larger. The position where the input data of the divided-by-4 clock is taken in is earlier, and it is preferable to perform a process of delaying by one cycle of the clock. It can be seen that, by delaying one clock, the erroneous data generated in FIG. 5 does not occur in FIG. In the processing of FIG. 6, one clock is delayed. Conversely, in the case of 5-bit data, if the ratio of “1” to “0” is “1”: “0” = 1: 4, one clock is advanced. Process.

  The 5-bit data determined by the determination circuit 24 is preferably the earliest clock among the supplied clocks. When the data is fetched by using the divided-by-four clock, the 5-bit data is discriminated by 5 bits. Desirably, when a divided by 8 clock is used, discrimination by 9 bits is desired. There is a reason to add 1 bit to the number of divisions and make it an odd number. In the case of an even number, there is a place that is exactly halved, and even a slight deviation within the originally acceptable range is sensitively judged, and the clock that takes in the input data is corrected every cycle. It will be a situation that can not fulfill the purpose.

  When an odd number is used, there is no place that is exactly half, and the determination is based on a value near the middle having a certain width. Even if there is some error near the middle, there is a range that is not corrected.

  The determination circuit 24 determines whether the input data capture timing is correct. The determination circuit 24 and the variable frequency dividing clock generation circuit 26 are connected by a 2-bit control signal. The 2-bit control signal is advanced (0, 0), not changed (1, 0), (0, Three types of states are shown: 1) and delayed (1, 1).

  FIG. 7 shows the inside of the variable frequency division clock generation circuit 26, which is composed of a frequency division counter 261, a timing control circuit 262, a selector 263, and a decoder 264.

  In the variable frequency dividing clock generation circuit 26, the count value from 0 to 3 is output from the frequency dividing counter 261 as an output signal (Φ in FIG. 7).

  The timing control circuit 262 outputs an output signal (Φ0 in FIG. 7) that becomes an H level only when the count value is “0” in accordance with the output signal (Φ in FIG. 7) that is a count value from the divide-by-4 counter 261. The output signal that becomes H level only when the count value is “1” (Φ1 in FIG. 7), the output signal that becomes H level only when the count value is “2” (Φ2 in FIG. 7), and the count value is Only when “3”, an output signal (Φ3 in FIG. 7) that becomes H level is created, and four types of four-frequency-divided clocks are output.

  A control signal from the determination circuit 24 enters the decoder 264 and controls the selector 263. The selector 263 changes the selection to a clock with an earlier cycle of one clock in the early state, maintains the clock as it is when not changing, and selects the clock with the later cycle of one clock when delaying. change.

  With this control, the divided-by-4 clock can be advanced by one cycle or delayed by one cycle depending on the state of the control signal from the determination circuit 24.

  The FF 28 of FIG. 2 latches the CMP output using a divide-by-4 clock that can be advanced or delayed. If the result of latching the CMP output is 1, it is determined that the slice level is low, and the digital value output circuit 27 increases the digital value set in the D / A converter 30 from the previous time.

  Conversely, if the latched result is 0, it is determined that the slice level is high, and the digital value output circuit 27 lowers the digital value set in the D / A converter 30 from the previous time.

  In this embodiment, five consecutive clocks are sampled from the rising edge of the divided-by-4 clock, but this timing may be determined using the falling edge.

  As mentioned above, although embodiment of this invention was described concretely based on the embodiment, it is not limited to this and can be variously changed in the range which does not deviate from the summary.

1 is a level comparator according to the present invention. 2 is an internal block diagram of a control circuit 20 according to the present invention. FIG. It is a conventional level comparator. It is a wave form diagram which shows the case where the taking-in timing of data is normal. It is a wave form diagram which shows the case where the taking-in timing of data has gone out. It is a wave form diagram explaining the operation | movement by this invention. FIG. 6 is an internal block diagram of a variable frequency division clock generation circuit 26 according to the present invention.

Explanation of symbols

  10 timing generation circuit, 20 control circuit, 30 D / A converter, 40 comparator, 21 shift register, 22 register, 23 overflow detection circuit, 24 determination circuit, 25 reset circuit.

Claims (4)

A frequency divider that divides the first clock signal to create a first sampling signal;
A first sampling unit that samples a binary signal having an H level and an L level using the first sampling signal;
A second sampling unit for sampling Ri by said binary signal to said first clock signal,
Based on the number of times at the H level and L level of the sequential samplings result of a predetermined number of the second sampling section, whether the binary signal is desired sampling timing out sampling in the first sampling unit and a discrimination circuit for judging,
Wherein in response to the output signal of the identification circuit, a sampling circuit, characterized in that Ru changing the sampling point of the first sampling unit. The frequency division circuit, by which selects and outputs an earlier or later timing the first sampling signal, according to claim 1, characterized in Rukoto changing the sampling point of the first sampling unit sampling circuit. Wherein when the difference between the number of 1 or less is at H level and L level, the sampling circuit according to claim 1 or claim 2, characterized in that does not alter the sampling point of the first sampling unit. Wherein the predetermined number of times, a sampling circuit according to any one of claims 1 to 3, characterized in that an odd number of said frequency divider dividing ratio of +1.

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