JP4324411B2 - BS digital receiver with PVR device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a BS digital receiver, and more particularly to a BS digital receiver to which a personal video recorder PVR (also called a hard disk video recorder, hereinafter abbreviated as a PVR apparatus) is added.
[0002]
[Prior art]
In recent years, technologies related to BS digital receivers have been greatly developed, and various additional functions have been added. As one of the additional functions, a video recording / reproducing function by a PVR device using a hard disk drive HDD has been proposed (for example, see Patent Document 1). As a characteristic function of the PVR apparatus, there is a time shift function using the high speed of the access speed of the HDD.
[0003]
FIG. 4 shows an example of a BS digital receiver to which a conventionally known PVR device is added. 4, the BS digital receiver includes a BS tuner 411, a demultiplexer DeMUX 401, a host 404, a host memory 405, a decoder 5, a network I / F 403, and a PVR device 420. The PVR device 420 includes a PVR CPU 407, a PVR memory 408, a buffer memory 409, an HDD 410, and a network I / F 406. Both the host memory 405 and the PVR memory 408 are composed of a ROM and a RAM, and each ROM stores a program for controlling the entire BS digital receiver and the PVR device 420.
[0004]
The recording operation of the BS digital receiver will be described. The BS tuner 411 extracts the transport stream TS 413 from the reception signal received by the antenna, and transmits the transport stream TS 413 to the DeMax (DeMUX) 401. The demax 401 converts the transport stream TS 413 from the BS tuner 411 into a partial stream PS 415 and transmits it to the network I / F 403.
[0005]
The network I / F 403 communicates with the network I / F 406 of the PVR device 420. A standard protocol (such as IEEE 1394) is used for this communication. The network I / F 406 of the PVR device 420 stores the partial stream PS415 in the buffer memory 409 in accordance with a request from the PVRCPU 407 of the PVR device 420. The HDD 410 records the partial stream PS in the buffer memory 409.
[0006]
Next, the reproduction operation of the BS digital receiver will be described. The HDD 410 reproduces the partial stream PS and reads it into the buffer memory 409 in accordance with a request from the PVR CPU 407 of the PVR device 420. The PVR device side network I / F 406 reads the PS stream in the buffer memory 409. Similar to the recording, the PVR device side network I / F 406 communicates with the host side network I / F 403. The host-side network I / F 403 outputs the partial stream PS to the demax 401. The demax 401 converts the partial stream PS into AVPES (AV Packetized Elementary Stream), and the decoder 402 decodes the AVPES to generate an output video.
[0007]
A time shift is realized by operating the above recording and reproduction simultaneously (in a time division manner).
[0008]
[Patent Document 1]
JP2002-1000016
[0009]
[Problems to be solved by the invention]
By the way, recently, as a method of assisting channel selection, one screen is divided into a plurality of screens, a plurality of still images of each channel are displayed as each divided screen, and the contents of the plurality of channels are simultaneously viewed to select a channel. Techniques that make it easier have been proposed. However, this technique requires an extra host-side network I / F 403. Furthermore, since it is necessary to support a standard protocol, the CPU bus load is large, and the buffer memory 409 and the PVR memory 408 cannot be integrated. In addition, since the PVR device 420 is controlled via the host-side network I / F 403, there is a problem that the response speed and the bandwidth of the partial stream PS that can be processed are reduced.
[0010]
The present invention has been made in view of these problems, and eliminates the need for a network I / F, reduces the memory capacity of the PVR device, improves the response speed, and records and reproduces at low cost and at high speed. It aims to make possible.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, the present invention adopts the following configuration.
A BS tuner that extracts a transport stream (TS) from a received signal received by an antenna, a demax that converts a transport stream from the BS tuner into an AVPES (AV packetized elementary stream), and outputs the demultiplex, A decoder that decodes the AVPES to generate an output video, a host that controls the BS tuner and designates the packet ID of the transport stream as the demax, and a packet designated by the packet ID by the host as AVTS (AV A BS digital receiver body having a host memory receiving from the DeMax in a transport stream),
A PVR device having an HDD that records and reproduces signals, a PVRCPU that controls the HDD, and a PVR memory that stores recording and reproduction signals of the HDD,
The PVR device is provided with a bridge circuit at the input end thereof for DMA transfer of the AVTS from the host memory,
The bridge circuit directly connects the PVR bus of the PVR device to the host bus of the host without passing through a network I / F, and exchanges the write DMA signal and read DMA signal of the host and the AVTS. A FIFO, the FIFO forms a component that connects the BS digital receiver body and the PVR device;
The PVRCPU performs AVTS DMA transfer control between the FIFO and the PVR memory.
[0013]
In the BS digital receiver, the bridge circuit includes a host read FIFO and a HOST write FIFO for buffering host input / output data, and a PVR device read FIFO and a PVR device write FIFO for buffering input / output data of the PVR device. , A PID filter that inputs a TS stream, an AUX read FIFO that buffers the TS stream, and an event register that exchanges events between the PVR device and the host.
[0014]
By adopting such a configuration, the network I / F is not required, the response speed is improved, and recording and reproduction can be performed at low cost and at high speed.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
A BS digital receiver according to an embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a diagram showing an overall configuration of a BS digital receiver according to an embodiment of the present invention, FIG. 2 is a diagram showing an overall configuration of a PVR device according to this embodiment, and FIG. 3 is a PVR device according to this embodiment. It is a figure which shows the structure of the inside bridge circuit.
[0016]
1, a BS digital receiver according to an embodiment of the present invention includes a BS tuner 100, a demax (demultiplexer, DeMUX) 101, a HOST (host) 103, a host memory (HOST memory) 104, and a decoder 102. And a PVR device 105. Here, in the BS digital receiver, a configuration excluding the PVR device 105 is referred to as a BS digital receiver main body.
[0017]
The host 103 controls the BS tuner 100. Also, the packet ID of the transport stream TS 109 to be acquired is designated as the demax 101. The demax 101 receives the transport stream TS 109 from the BS tuner 100, stores the packet designated by the host 103, and outputs it to the host memory 104 as AVTS (AV Transport Stream).
[0018]
The host 103 DMA-transfers the AVTS 108 from the host memory 104 to the PVR device 105 (Direct Memory Access, direct memory access). At this time, DMA transfer is controlled by a REQ and ACK signal (request, acknowledgment signal) 107 of a host WDMA (Write Direct Memory Access).
[0019]
At the same time, the host 103 transfers the AVTS stored in the PVR device 105 to the demux 101 via the host memory 104. At this time, DMA transfer is controlled by a REQ and ACK signal of a host RDMA (Read Direct Memory Access).
[0020]
The demax 101 decodes the AVTS 108 to generate an output video. Further, the PVR device 105 monitors the transport stream TS 109 from the BS tuner 100 and transmits an event 112 to the host 103 when a broadcast interruption or the like occurs.
[0021]
In this way, the capacity of the HOST memory can be increased by connecting the BS digital receiver body (BS tuner, demax, decoder, host, host memory) and the PVR device integrated with this body as shown in FIG. It can be reduced, and by not using the network I / F, inexpensive and high-speed communication can be performed, and the responsiveness of PVR control can be improved.
[0022]
Next, the PVR apparatus will be described with reference to FIG. 2 showing the detailed configuration of the PVR apparatus 105 according to the present embodiment. In FIG. 2, the PVR device 105 (see FIG. 1) includes a PVRCPU 201, a PVR memory 203, an HDD 202, and a bridge circuit 200.
[0023]
The flow of recording on the HDD 202 will be described below. The bridge circuit 200 inputs the AVTS 208 in accordance with the WDMA REQ signal 207 from the host 103. At this time, the host 103 is notified by the ACK signal 207 of the host WDMA that the data has been acquired.
[0024]
The PVRCPU 201 DMA-transfers the AVTS 208 from the bridge circuit 200 as the PVR-side AVTS 214 to the PVR memory 203 and stores it. At this time, the DMA transfer is controlled by the read DMA REQ and ACK signals 213. Further, the PVRCPU 201 reads the AVTS 208 from the PVR memory 203 and records it in the HDD 202 as a recording TS204.
[0025]
Next, the flow of playback from the HDD 202 will be described. The PVR CPU 201 reads the recording TS 204 from the HDD 202 and stores it in the PVR memory 203. The PVRCPU 201 DMA-transfers the PVR side AVTS 214 from the PVR memory 203 to the bridge circuit 200. At this time, the DMA transfer is controlled by the REQ / ACK signal 210 of the write DMA. The bridge circuit 200 outputs the PVR side AVTS 214 as the AVTS 208 in accordance with the host RDMA REQ signal 216 from the host 103. At this time, the host 103 is notified by the host RDMA ACK signal 216 that the data has been prepared.
[0026]
The PVRCPU 201 requests the bridge circuit 200 to acquire a packet necessary for monitoring the transport stream TS209 from the BS tuner 100. The PVRCPU 201 acquires a packet by DMA transfer from the bridge circuit 200 using the AVTS 208 path. At this time, DMA transfer is controlled by the REQ and ACK signals 215 of the AUX read DMA.
[0027]
In accordance with the monitoring result, an event 218 such as broadcast cancellation, recovery, program attribute change, or the like is set in the bridge circuit 200 as the PVR side event 212. The bridge circuit 200 notifies the host 103 of this PVR side event 212 as an event 218.
[0028]
As described above, by adopting the internal configuration and connection configuration of the PVR device shown in FIG. 2, the memory of the PVR device is made a single memory (the buffer memory shown in FIG. 4 is not required and only the PVR memory is used). The TS stream can be recorded and reproduced at low cost and at high speed with this memory, and the BS tuner TS is monitored to improve the response speed.
[0029]
Next, the bridge circuit will be described with reference to FIG. 3 showing the configuration of the bridge circuit 14 according to the present embodiment. The bridge circuit 200 includes a host write FIFO (First-In First-Out) 300, a PID (Packet Identification) filter 302, a PVR write FIFO 304, a PVR read FIFO 301, an AUX output FIFO 303, a host read FIFO 305, and an event register. 306.
[0030]
The host write FIFO 300 records the AVTS 208 in accordance with the REQ signal 207 of the host WDMA. An ACK signal 207 of the host WDMA notifies the host 103 that the FIFO is empty. The PVR read FIFO 301 acquires the AVTS 208 from the host write FIFO 300 as long as there is a vacancy. The AVTS 208 is output to the PVRCPU 201 in accordance with the read DMA REQ signal 213. At this time, the read DMA ACK signal 213 notifies the PVR device 7 that the FIFO can output data.
[0031]
The PVR write FIFO 304 and the host read FIFO 305 operate in the same manner as the host write FIFO 300 and the PVR read FIFO 301 except that the directions are opposite.
[0032]
The PID filter 302 receives the BS tuner TS 209, selects a TS packet with the set packet ID, and outputs it to the AUX output FIFO 303. The AUX output FIFO 303 outputs the TS packet to the PVRCPU 201 in accordance with the AUX read DMA REQ signal 215. At this time, the ACK signal 215 of the AUX read DMA notifies the PVR CPU 201 that the AUX output FIFO 303 can output data.
[0033]
The data from the AUX output FIFO 303 is output as the PVR AVTS 214, but the PVR CPU 201 exclusively outputs the read DMA REQ and ACK signals and the AUX read DMA REQ and ACK signals 215 to obtain data. Is notified to the bridge circuit 200. The bridge circuit 200 outputs data from the PVR read FIFO 301 when the read DMA REQ / ACK signal 213 is ON, and from the AUX output FIFO 303 when the AUX read DMA REQ / ACK signal 215 is ON.
[0034]
The event register 306 is a register that can be read and written from both the PVRCPU 201 and the host (HOST) 103. Further, an interrupt is generated to the host (HOST) 103 when writing from the PVRCPU 201. Further, an interrupt is generated for the PVRCPU 201 when writing from the host 103. With the above function, the PVR side event 212 from the PVR CPU 201 is notified to the host (HOST) 103 as an event 218. Further, the PVR CPU 11 is notified of the event 218 from the host 103 as the PVR side event 212.
[0035]
In this way, by adopting a bridge circuit in the PVR apparatus shown in FIG. 3, the HOST bus and the PVR bus are directly connected (without going through the network I / F), and high-speed TS stream communication is performed. It is possible to perform a function of inputting the BS tuner TS via the PID filter, and to perform an event passing function.
[0036]
As described above, the main feature of the embodiment of the present invention is that a BS digital receiver uses a network I / F by providing a bridge circuit having a TS stream input function and an event transfer function in the PVR device. In addition, an inexpensive and high-speed PVR function can be added.
[0037]
【The invention's effect】
As described above, according to the present invention, the function of performing high-speed TS stream communication directly connected to each of the HOST bus and the PVR bus, the function of inputting the BS tuner TS via the PID filter, and the event passing function are provided. Can be provided.
[0038]
In addition, it is possible to provide a function for recording and reproducing the TS stream at a low cost and at a high speed with a single memory, and also to monitor the BS tuner TS to improve the response speed.
[0039]
Further, it is possible to provide memory minimization, inexpensive and high-speed communication that does not use the network I / F, and improve the responsiveness of PVR control.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a BS digital receiver according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an overall configuration of a PVR apparatus according to the present embodiment.
FIG. 3 is a diagram illustrating a configuration of a bridge circuit in the PVR apparatus according to the present embodiment.
FIG. 4 is a diagram showing an overall configuration of a BS digital receiver related to the prior art.
[Explanation of symbols]
100 BS tuner 101 Demax (Demultiplexer, DeMUX)
102 Decoder 103 Host (HOST)
104 HOST memory 105 PVR device 107, 207 HOST WDMA REQ, ACK
108,117,208,217 AVTS
109,209,413 BS tuner TS
112,218 Event 116,216 HOST RDMA REQ, ACK
118 Output video 122, 412 Tuner control 200 Bridge circuit 201 PVRCPU
202 HDD
203 PVR memory 204 Recording TS
210 Write DMA REQ, ACK
212 PVR side event 213 Read DMA REQ, ACK
214 PVR AVTS
215 AUX read DMA REQ, ACK
300 HOST light FIFO
301 PVRFIFO
302 PID filter 303 AUX output FIFO
304 PVR light FIFO
305 HOST Lead FIFO
306 Event register 401 Demax (Demultiplexer, DeMUX)
402 Decoder 403 Network I / F
404 HOST (Host CPU)
405 HOST memory 406 PVR network I / F
407 PVRCPU
408 PVR memory 409 Buffer memory 410 HDD
411 BS tuner 412 Tuner control 413 BS tuner TS
414 AVTS
415 Partial stream 416 Control 417 Recording TS
418 output video

Claims (3)

A BS tuner that extracts a transport stream (TS) from a received signal received by an antenna, a demax that converts a transport stream from the BS tuner into an AVPES (AV packetized elementary stream), and outputs the demultiplex, A decoder that decodes the AVPES to generate an output video, a host that controls the BS tuner and designates the packet ID of the transport stream as the demax, and a packet designated by the packet ID by the host as AVTS (AV A BS digital receiver body having a host memory receiving from the DeMax in a transport stream),
A PVR device having an HDD that records and reproduces signals, a PVRCPU that controls the HDD, and a PVR memory that stores recording and reproduction signals of the HDD,
The PVR device is provided with a bridge circuit at the input end thereof for DMA transfer of the AVTS from the host memory,
The bridge circuit directly connects the PVR bus of the PVR device to the host bus of the host without passing through a network I / F, and exchanges the write DMA signal and read DMA signal of the host and the AVTS. A FIFO, the FIFO forms a component that connects the BS digital receiver body and the PVR device;
The BS digital receiver , wherein the PVRCPU performs AVTS DMA transfer control between the FIFO and the PVR memory . In claim 1 ,
The bridge circuit includes a host read FIFO and a host write FIFO for buffering the host input / output data, a PVR device read FIFO and a PVR device write FIFO for buffering the input / output data of the PVR device, and a transformer from the BS tuner. A PID filter that inputs a port stream , an AUX output FIFO that buffers the BS tuner transport stream from the PID filter , and an event register that can read and write events from both the PVRCPU and the host to exchange events. BS digital receiver characterized by. In claim 2,
The BS digital receiver characterized in that the PVRCPU sets events in the event register including broadcast suspension, recovery, and program attribute change by monitoring the BS tuner transport stream and notifies the host .

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