JP4318404B2 - Automatic gain controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an automatic gain control device used in a receiving system of a digital wireless terminal device.
[0002]
[Prior art]
Conventionally, for example, wireless terminal devices have been digitized. In a public wireless communication system, even in the case of a TDMA (Time Division Multiple Access) system, it is a precondition that the wireless terminal device operates in synchronization with the base station. It performs operations such as standby and communication in synchronization with
[0003]
[Problems to be solved by the invention]
However, since the personal or commercial digital wireless communication system has a function of allowing users to directly communicate with each other without going through the base station, the wireless terminal device detects radio waves that arrive irregularly. Must be demodulated. In addition, unlike a system such as a PDC (Personal Digital Cellular) mobile phone that can always be operated at a high gain, called a limiter method, a system that performs multi-level modulation / linear modulation has received signals saturated. Since the information contained in the received signal is destroyed, the gain control cannot be performed on the assumption that the receiving system always operates at a high gain and the change timing of the electric field strength is known. Even in the case of the TDMA system in which communication is performed using a plurality of slots at the same frequency, stable communication must be established simultaneously with a communication partner having a plurality of different received electric field strengths using a plurality of slots allocated to itself. I must.
[0004]
Furthermore, in the system as described above, the gain of the receiving system is adjusted using a general analog automatic gain control (AGC) loop configured to control the gain of the gain control amplifier according to the received electric field strength. When trying to control, there were the following problems. That is, (1) the time constant of the automatic gain control loop must be adjusted in accordance with the operating frequency of the system so that a so-called pumping effect does not occur. (2) The timing of determination when performing high-speed gain control is a frame. It must be controlled by a digital signal processor (DSP) that recognizes the structure, and operation of an analog automatic gain control loop alone is difficult. (3) Electric field strength as in the TDMA system It is not compatible with a method in which a plurality of different radio waves arrive periodically. (4) Received signal strength indicator (RSSI) that is a control signal in a general analog automatic gain control loop is, for example, around 450 kHz. Since a general-purpose circuit using the second intermediate frequency band is used, a filter, a discriminator, and the like are further provided. There is a problem that the number of parts is inevitably increased.
[0005]
The present invention has been made in view of such a situation, and can solve the above-described problems all at once, and at the same time, gain control suitable for receiving operations of digital wireless terminal devices in a plurality of systems. It is an object of the present invention to provide an automatic gain control device that can automatically perform the above.
[0006]
[Means for Solving the Problems]
In order to achieve the above-described object, first, an automatic gain control apparatus according to the present invention orthogonally demodulates a gain control amplification means for amplifying a quadrature modulation signal, and an amplified quadrature modulation signal from the gain control amplification means. Demodulating means for outputting as baseband I and Q signals, analog / digital converting means for digitizing baseband I and Q signals from the demodulating means, and digitized from the analog / digital converting means A square sum signal generating means for generating a square sum signal indicating the sum of squares based on the I signal and the Q signal, and a maximum for detecting a maximum value in a predetermined sampling period of the square sum signal from the square sum signal generating means. A value detection means, and a first reference test for converting the maximum value of the sum of squares signal from the maximum value detection means into set value change amount data corresponding to the maximum value. And second reference table means for converting the set value change amount data from the first reference table means into gain change set value data corresponding to the set value change amount data. The gain change set value data from the reference table means is supplied to the gain control amplification means, and the gain of the gain control amplification means is automatically controlled.
[0007]
Second, the automatic gain control apparatus according to the present invention is the automatic gain control apparatus according to the first aspect, wherein the analog / digital conversion means digitizes the baseband I signal and Q signal from the demodulation means. At the same time, it is characterized by performing a filtering process based on the root Nyquist characteristic.
[0008]
Third, the automatic gain control apparatus according to the present invention is the automatic gain control apparatus according to the first aspect, wherein the square sum signal generation means is a digitized I signal and Q signal from the analog / digital conversion means. Are characterized by having first and second square means for respectively performing a square operation, and addition means for adding the outputs from these square means to generate the square sum signal.
[0009]
Fourth, the automatic gain control apparatus according to the present invention is the automatic gain control apparatus according to the first aspect, wherein the maximum value detecting means includes a square sum signal from the square sum signal generating means and a square sum before one sampling. Comparing / selecting means for comparing a signal and selecting a larger signal, and detecting a maximum value in the predetermined sampling period based on an output from the comparing / selecting means while simplifying a circuit configuration It is said.
[0010]
Fifth, the automatic gain control device of the present invention is the automatic gain control device according to the first aspect, wherein the first reference table means is a transmission rate of a device in which the gain of the gain control amplification means is operated, A plurality of types of reference tables are selected as appropriate according to the operating frequency or the position of the received signal in the frame, and the maximum value of the sum of squares signal from the maximum value detection means is set to the maximum value by the selected reference table It is characterized in that it is converted into corresponding set value change amount data.
[0011]
Sixth, the automatic gain control device according to the present invention is the automatic gain control device according to the fifth aspect, wherein the first reference table means having a plurality of types of reference tables is made into a variable register, and a similar function is provided by one. It is also possible to realize with a table.
[0012]
Seventh, the automatic gain control device according to the present invention is the automatic gain control device according to the first aspect, wherein the second reference table means includes at least one kind according to an element constituting the gain control amplification means. A reference table is provided, and the set value change amount data from the first reference table means is converted into gain change set value data corresponding to the set value change amount data by the reference table, thereby supporting a plurality of types of elements. It is characterized by doing.
[0013]
Eighth, an automatic gain control device according to the present invention is the automatic gain control device according to the seventh aspect, wherein the second reference table means having at least one kind of reference table is made a variable register, and the same function is provided. It can also be realized with two tables.
[0014]
Ninth, the automatic gain control device of the present invention is the automatic gain control device according to the first aspect, wherein the set value change amount data from the first reference table means is held for each slot, The gain of the gain control amplification means is controlled independently corresponding to the slot.
[0015]
Tenth, the automatic gain control apparatus according to the present invention is characterized in that, in the automatic gain control apparatus according to the ninth aspect, the number of the slots is set to 6 or less to correspond to most standards.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the present embodiment, as an example, the present invention is applied to a reception system of a wireless terminal device in a TDMA digital wireless communication system in which users directly communicate with each other without going through a base station.
[0017]
FIG. 1 is a block diagram showing a configuration of a receiving system of a digital wireless terminal device to which the present invention is applied. In FIG. 1, a single superheterodyne receiver (RX) 20 amplifies a radio wave (high-frequency quadrature modulation signal) from a communication partner supplied via an antenna 10 and converts the frequency into an intermediate frequency signal. Gain control for amplifying the intermediate frequency signal from the circuit (FE) 21 and the front end circuit 21 with a gain according to gain change set value data from a control circuit (CONT) 41 in a gate array (GA) 40 described later. An amplifier (GCA) 22 and a demodulator (DEM) 23 that orthogonally demodulates the amplified intermediate frequency signal from the gain control amplifier 22 to baseband I and Q signals are provided. In addition to the receiving unit 20 described above, the receiving system further includes a narrow-band baseband filter having root Nyquist characteristics, as well as converting each of the I signal and Q signal from the demodulator 23 into a digital signal, and filtering thereby. An analog / digital converter (ADC) 30 that performs processing, and a gain change setting supplied to the above-described gain control amplifier 22 based on the digitized baseband I and Q signals from the analog / digital converter 30 A control circuit 41 that generates value data and a gate array 40 that includes the control circuit 41 are provided. Further, a digital signal processor (DSP) 50 having a function of generating various control signals to be supplied to the control circuit 41, and a central processing unit (CPU) 60 having a function of controlling the operation of the entire digital wireless terminal device. And are provided. Here, the gain control amplifier 22, the demodulator 23, the analog / digital converter 30, and the control circuit 41 constitute an automatic gain control device of this embodiment.
[0018]
The control circuit 41 provided in the gate array 40 described above has a configuration as shown in FIG. 2, for example. In FIG. 2, the bit selector 101 that selects the upper 6 bits from the baseband I signal (16 bits) that has been digitized and filtered by the root Nyquist characteristic supplied from the analog / digital converter 30 selects The upper 6 bits are connected to a squaring circuit 102 that performs a square operation and outputs an 11-bit signal. On the other hand, the bit selector 103 that selects the upper 6 bits from the baseband Q signal (16 bits) that is supplied from the analog / digital converter 30 and that has been subjected to filtering processing based on the root Nyquist characteristic is selected. It is connected to a square circuit 104 that performs a square operation on the upper 6 bits and outputs an 11-bit signal. These square circuits 102 and 104 are connected to an adder 105, respectively. The adder 105 adds 11-bit signals supplied from the square circuits 102 and 104, respectively, and adds a 12-bit signal (a square sum signal indicating the sum of squares of the digitized baseband I signal and Q signal). Is output as Here, the square sum signal generation unit 200 is configured by the bit selectors 101 and 103, the square circuits 102 and 104, and the adder 105.
[0019]
The adder 105 is connected to one input terminal of the comparator 106, and a latch circuit 107 that latches the square sum signal before one sampling is connected to the other input terminal of the comparator 106. The comparator 106 compares the square sum signal (12 bits) from the adder 105 with the square sum signal (12 bits) before one sampling from the latch circuit 107, and outputs a signal indicating which signal is larger. This is output as a comparison result. The comparator 106 is connected to a selector 108, and an adder 105 and a latch circuit 107 are further connected to the selector 108. This selector 108 selectively selects one of the square sum signal from the adder 105 and the square sum signal before one sampling from the latch circuit 107 (the larger signal) according to the comparison result from the comparator 106. Is supplied to the latch circuit 107. That is, the latch circuit 107 always latches the larger signal, and detects the maximum value of the square sum signal in a predetermined sampling period. In the present embodiment, the maximum value of the square sum signal is regarded as the carrier level of the received signal. Here, the comparator 106, the latch circuit 107, and the selector 108 constitute a maximum value detection unit 300. Note that the latch circuit 107 is cleared by a clear signal and is driven only by a gate signal for a predetermined sampling period. These clear signal and gate signal are supplied from the digital signal processor 50 described above.
[0020]
The latch circuit 107 is connected to a latch circuit 109 that latches an output from the latch circuit 107. The latch circuit 109 converts the output from the latch circuit 109 (maximum value of the square sum signal) into set value change amount data indicating the change amount of the set value corresponding to the output. It is connected. The first reference table unit 110 includes a high-speed mode reference table 110a for controlling the gain of the gain control amplifier 22 at a high speed and a low-speed mode for controlling the gain of the gain control amplifier 22 at a low speed. The reference table 110b. In the first reference table unit 110, one of the high-speed mode reference table 110a and the low-speed mode reference table 110b is selected and selected by the table selection signal supplied from the digital signal processor 50 described above. The reference table is used to convert the maximum value of the square sum signal from the latch circuit 109 into set value change amount data corresponding to the maximum value. Here, the reference table 110a for the high speed mode and the reference table 110b for the low speed mode have a configuration as shown in FIG. 3, for example. In FIG. 3, for example, when the output of the latch 109 is “0000 0000 01xx” in the high-speed mode, the change amount of the set value is “+3” dB, and the output of the latch 109 is similarly “0000 0000 01xx” in the low-speed mode. In this case, the change amount of the set value is “+1” dB. FIG. 3 also shows the amount of gain change, which is indicated by the gain change set value data output from the second reference table unit 115 described later, and the gain control amplifier 22 described above. It corresponds to the gain.
[0021]
The first reference table unit 110 is connected to an adder 111 that adds an output (set value change amount data) from the reference table unit 110 and an output from a latch circuit 113 described later. The adder 111 is connected to a limiter 112 that limits the addition result to a range determined by the upper limit value and the lower limit value of the change amount of the set value. The limiter 112 is connected to a latch circuit 113 that latches the output from the limiter 112. The sub-slot register 114 temporarily holds the contents held in the latch circuit 113 for each slot, and returns the contents (data) held according to the processing timing of each slot to the latch circuit 113. It has a function. The latch circuit 113 is connected to the adder 111 described above, and converts an output (set value change amount data) from the latch circuit 113 into gain change set value data indicating a gain change amount corresponding to the output. Connected to the second reference table unit 115. The second lookup table unit 115 has two types of lookup tables 115a and 115b for controlling the gain of the gain control amplifier 22 in accordance with the elements constituting the gain control amplifier 22 described above. In the second reference table unit 115, one of the two types of reference tables 115a and 115b is selected by the user according to the elements constituting the gain control amplifier 22, and from the latch circuit 113 by the selected reference table. A process of converting the set value change amount data into gain change set value data corresponding to the data is performed. The second look-up table unit 115 is connected to the gain control amplifier 22, and the gain of the gain control amplifier 22 is automatically controlled on a slot basis when the gain change set value data is supplied. Note that, like the latch circuit 107, the latch circuit 109 and the second reference table unit 115 are driven only in a predetermined sampling period by the gate signal described above. Further, the first and second reference table sections 110 and 115 can realize the same function with one table by making them variable registers. For example, by appropriately loading data in an EEPROM (Electrically Erasable and Programmable Read Only Memory) into the control circuit 41 in the gate array 40, the number of register tables can be reduced. Furthermore, by setting the number of slots in the subslot register 114 to 6 or less, it is possible to support most standards.
[0022]
Next, the operation of the automatic gain control device of this embodiment will be described with reference to FIGS. First, in FIG. 1, a radio wave (a high-frequency quadrature modulation signal) from a communication partner is supplied to a front end circuit 21 via an antenna 10, amplified, and then converted into an intermediate frequency signal. The intermediate frequency signal from the front end circuit 21 is supplied to the gain control amplifier 22 and amplified with a gain corresponding to the gain change set value data from the control circuit 41. The amplified intermediate frequency signal from the gain control amplifier 22 is supplied to the demodulator 23 and is quadrature demodulated into baseband I and Q signals. The baseband I signal and Q signal from the demodulator 23 are supplied to an analog / digital converter 30 where they are converted into digital signals and subjected to a filtering process based on the root Nyquist characteristic. The I signal and Q signal that have been digitized from the analog / digital converter 30 and subjected to the filtering process based on the root Nyquist characteristic are supplied to the control circuit 41.
[0023]
The description will be continued below with reference to FIG. The digitized I signal (16 bits) subjected to the filtering process based on the root Nyquist characteristic from the analog / digital converter 30 is supplied to the bit selector 101, and the upper 6 bits are selected. The selected upper 6 bits from the bit selector 101 are supplied to the squaring circuit 102, subjected to a square operation to be an 11-bit signal, and then supplied to the adder 105. On the other hand, the digitized Q signal (16 bits) subjected to the filtering process based on the root Nyquist characteristic from the analog / digital converter 30 is supplied to the bit selector 103, and the upper 6 bits are selected. The selected upper 6 bits from the bit selector 103 are supplied to the squaring circuit 104, subjected to squaring operation to be an 11-bit signal, and then supplied to the adder 105. In the adder 105, the 11-bit signals respectively supplied from the square circuits 102 and 104 are added and output as a 12-bit square sum signal. The 12-bit square sum signal is supplied to the comparator 106 and compared with the square sum signal before one sampling supplied from the latch circuit 107, and a signal indicating which signal is larger is used as the comparison result as a comparison result. Is output from. The selector 108 selects the larger one of the square sum signal from the adder 105 and the square sum signal before one sampling from the latch circuit 107 according to the comparison result from the comparator 106, and this signal is It is supplied to the latch circuit 107. That is, the latch circuit 107 always latches the larger signal, and detects the maximum value of the square sum signal in a predetermined sampling period.
[0024]
The output from the latch circuit 107 (the maximum value of the square sum signal) is supplied to the latch circuit 109 and latched. An output from the latch circuit 109 is supplied to the first reference table unit 110. Here, the output of the latch circuit 109 from the reference table (one of the reference table 110a for the high speed mode and the reference table 110b for the low speed mode) selected by the table selection signal supplied from the digital signal processor 50. The set value change amount data corresponding to (see FIG. 3) is output as the set value change amount data from the first reference table unit 110. The set value change amount data from the first reference table unit 110 is supplied to the latch circuit 113 via the adder 111 and the limiter 112 and latched. The output from the latch circuit 113 is supplied to the second reference table unit 115. Here, the gain change setting corresponding to the output of the latch circuit 113 from the reference table (one of the two types of reference tables 115a and 115b) selected according to the elements constituting the gain control amplifier 22 by the user. The value data (see FIG. 3) is output as gain change setting value data from the second reference table unit 115. Then, the gain change set value data from the second reference table unit 115 is supplied to the gain control amplifier 22, and the gain of the gain control amplifier 22 is automatically controlled. The contents held in the latch circuit 113 are temporarily held in the sub-slot register 114 for each slot, and the held contents (data) are returned to the latch circuit 113 according to the processing timing of each slot. Accordingly, the gain of the gain control amplifier 22 can be controlled in slot units.
[0025]
As described above, in the automatic gain control apparatus according to the present embodiment, the intermediate frequency signal from the front end circuit 21 is amplified by the gain control amplifier 22, and the amplified intermediate frequency signal from the gain control amplifier 22 is orthogonalized by the demodulator 23. Demodulated and output as baseband I and Q signals, digitized baseband I and Q signals from demodulator 23 with analog / digital converter 30 and digitized from analog / digital converter 30 Based on the I signal and the Q signal, a square sum signal indicating these sums of squares is generated by the square sum signal generator 200, and the maximum value in a predetermined sampling period of the square sum signal from the square sum signal generator 200 is detected as the maximum value. This is detected by the unit 300. Further, the maximum value of the square sum signal from the maximum value detection unit 300 is converted into set value change amount data corresponding to the maximum value by the first reference table unit 110, and the set value from the first reference table unit 110 is converted. The change amount data is converted into gain change set value data corresponding to the set value change amount data by the second reference table unit 115, and the gain change set value data from the second reference table unit 115 is converted into a gain control amplifier. The gain of the gain control amplifier 22 is automatically controlled.
[0026]
In the above-described embodiment, the first reference table unit 110 is provided with two types of reference tables 110a and 110b for the high speed mode and the low speed mode, but the present invention is not limited to this. Two or more types of reference tables may be provided according to the transmission speed of the equipment to be operated, the operating frequency, or the position of the received signal in the frame. Similarly, the second reference table unit 115 is provided with two types of reference tables 115a and 115b, but at least one type of reference table is provided according to the elements constituting the gain control amplifier 22. You can do it.
[0027]
【The invention's effect】
As is clear from the above description, according to the automatic gain control device of the present invention, the problems of the analog automatic gain control loop as described above can be solved at once, and the users can Even a wireless terminal apparatus in a TDMA digital wireless communication system that performs direct communication without going through a base station can automatically perform gain control suitable for the receiving operation.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a receiving system of a digital wireless terminal device to which the present invention is applied.
2 is a block diagram showing a specific configuration example of a control circuit provided in the gate array in FIG. 1. FIG.
FIG. 3 is a diagram illustrating a configuration example of each reference table in FIG. 2;
[Explanation of symbols]
22 Gain Control Amplifier (GCA)
23 Demodulator (DEM)
30 Analog / Digital Converter (ADC)
102, 104 Square circuit 105 Adder 106 Comparator 108 Selector 110 First reference table unit 110a, 110b Reference table 115 Second reference table unit 115a, 115b Reference table 200 Sum of squares signal generation unit 300 Maximum value detection unit

Claims (2)

Gain control amplification means for amplifying the quadrature modulation signal;
Demodulating means for orthogonally demodulating the amplified quadrature modulated signal from the gain control amplifying means and outputting as baseband I and Q signals;
Analog / digital conversion means for digitizing the baseband I and Q signals from the demodulation means;
A sum-of-squares signal generating means for generating a sum of squares signal indicating the sum of the squares thereof based on the digitized I and Q signals from the analog / digital conversion means;
Maximum value detecting means for detecting a maximum value in a predetermined sampling period of the square sum signal from the square sum signal generating means;
First reference table means for converting the maximum value of the square sum signal from the maximum value detection means into set value change amount data corresponding to the maximum value;
Second reference table means for converting the set value change amount data from the first reference table means into gain change set value data corresponding to the set value change amount data;
Supplying gain change set value data from the second look-up table means to the gain control amplification means, and automatically controlling the gain of the gain control amplification means ;
The first reference table means has a plurality of types of reference tables that are appropriately selected according to the transmission speed, operating frequency, or position of the received signal in the frame in which the gain control amplification means operates. An automatic gain control device for converting the maximum value of the sum of squares signal from the maximum value detecting means into set value change amount data corresponding to the maximum value by the selected reference table . 2. The automatic gain control apparatus according to claim 1 , wherein the first reference table means having a plurality of types of reference tables is variable-registered so that the same function can be realized by a single table.

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