JP4309070B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention particularly relates to a nonvolatile semiconductor memory device including a memory cell unit including at least one memory cell transistor and a selection gate transistor connected to the memory cell unit, and a method for manufacturing the same.
[0002]
[Prior art]
FIG. 28 is a cross-sectional view of the memory cell transistor and the select gate transistor in the gate length “L” direction in the conventional NAND type semiconductor memory device.
[0003]
A contact hole 34 formed in a self-aligned manner with respect to the gate electrodes is formed between the gate electrodes of the select gate transistors. A TEOS film 29 is deposited on the gate sidewall of the memory cell transistor in order to improve hot carrier characteristics.
[0004]
On the other hand, in the selection gate transistor, in order to prevent the TEOS film 29 from being etched when the contact hole 34 is opened and the contact filling material and the gate electrode are short-circuited, the TEOS on the gate sidewall is opened before the contact hole 34 is opened. The film 29 is peeled off. Since the impurity ion implantation into the channel region and the source / drain diffusion layer region 28 of the memory cell transistor and the selection gate transistor is performed at the same time, the impurity distribution in the channel region and the source / drain diffusion layer region 28 depends on the memory cell transistor and the selection gate transistor. The same applies to transistors.
[0005]
In a NAND type semiconductor memory device, when “1” data is written into a memory cell (electrons are not injected into the floating gate and the threshold value at the time of erasure is maintained), the memory cell transistor is connected via a selection gate transistor. The initial potential is charged from the bit line, the write voltage is applied to the selected word line, the transfer voltage is applied to the non-selected word line, and the potential of the channel region of the memory cell transistor is boosted using capacitive coupling. Electrons are not injected into the floating gates 5 and 11. For this reason, by reducing the impurity concentration of the channel region, the channel capacitance is reduced, the potential of the channel region is easily boosted, and the “1” data write characteristics are improved.
[0006]
[Problems to be solved by the invention]
However, since the impurity distribution in the channel region of the memory cell transistor and the selection gate transistor is the same, by reducing the impurity concentration in the channel region, the threshold voltage of the selection gate transistor decreases, and the off-leakage current increases. There were circumstances that prevented normal operation.
[0007]
The present invention has been made in view of the above circumstances, and its purpose is to provide various characteristics of memory cell transistors such as data write characteristics, data retention characteristics, and resistance to read stress, and cut-off characteristics of select gate transistors. It is an object of the present invention to provide a non-volatile semiconductor memory device and a method of manufacturing the same that can both be improved.
[0008]
[Means for Solving the Problems]
  To achieve the above object, a nonvolatile semiconductor memory device according to the first aspect of the present invention is provided.IsA memory cell unit including at least one memory cell transistor having a stacked structure of a charge storage layer and a control gate layer formed on a semiconductor substrate, and one of the source / drain diffusion layer regions is a bit line or a source line And a select gate transistor connected to the memory cell unit on the other side.And beforeThe shape of the source diffusion layer region and the shape of the drain diffusion layer region of the selection gate transistor under the gate electrode of the selection gate transistorIs notSymmetricalThe distance over which the gate electrode overlaps with the diffusion layer region connected to the bit line or the source line at a position where the depth from the interface between the semiconductor substrate and the gate insulating film is equal is connected to the memory cell unit. The effective impurity concentration of the diffusion layer region connected to the bit line or the source line is smaller than the distance over which the diffusion layer region and the gate electrode overlap, and the effective impurity concentration of the diffusion layer region connected to the memory cell unit is The effective impurity concentration of the diffusion layer region that is thinner than the effective impurity concentration and connected to the memory cell unit is the same as the effective impurity concentration of the source / drain diffusion layer region of the memory cell transistor, and the memory On the side of the gate electrode of the cell transistor and the side of the gate electrode of the selection gate transistor that faces the memory cell, A first insulating film, a second insulating film formed on the first insulating film, and a third insulating film formed on the second insulating film, and the selection gate On the side of the gate electrode of the transistor facing the contact for connecting the bit line or the source line, the first insulating film and the third insulating film formed on the first insulating film And are stackedIt is characterized by that.
[0009]
According to such a nonvolatile semiconductor memory device according to the first aspect, the effective gate length of the selection gate transistor is increased by making the shape of the source diffusion layer region and the drain diffusion layer region of the selection gate transistor asymmetric. can do. As a result, the short channel effect of the select gate transistor is improved, and the cut-off characteristic is improved. Further, since the short channel effect of the select gate transistor is improved, the impurity concentration in the channel region of the memory cell transistor can be lowered to a conventional level. As a result, the data write characteristics of the memory cell transistor can be improved.
[0010]
  A nonvolatile semiconductor memory device according to the second aspect of the invention is also provided.IsA memory cell unit including at least one memory cell transistor having a stacked structure of a charge storage layer and a control gate layer formed on a semiconductor substrate, and one of the source / drain diffusion layer regions is a bit line or a source line And a select gate transistor connected to the memory cell unit on the other side.The shape of the source diffusion layer region of the selection gate transistor and the shape of the drain diffusion layer region are asymmetric under the gate electrode of the selection gate transistor,At a position where the depth from the interface between the semiconductor substrate and the gate insulating film is equal,The distance between the diffusion layer region connected to the bit line or the source line and the gate electrode is smaller than the distance between the diffusion layer region connected to the memory cell unit and the gate electrode, and the bit line or The impurity concentration of the channel region in contact with the diffusion layer region connected to the source line is higher than the impurity concentration of the channel region in contact with the diffusion layer region connected to the memory cell unit, and the diffusion layer connected to the memory cell unit The impurity concentration of the channel region in contact with the region is the same as the impurity concentration of the channel region in contact with the source / drain diffusion layer region of the memory cell transistor, and the side wall of the gate electrode of the memory cell transistor and the gate of the selection gate transistor On the side of the electrode facing the memory cell, a first insulating film, The second insulating film formed on the first insulating film and the third insulating film formed on the second insulating film are stacked, and the gate electrode of the selection gate transistor, The first insulating film and the third insulating film formed on the first insulating film are stacked on the side facing the contact for connecting the bit line or the source line.It is characterized by that.
[0011]
According to such a non-volatile semiconductor memory device according to the second aspect, the channel region between the source diffusion layer region and the drain diffusion layer region of the selection gate transistor has a region with different impurity concentration, so that the selection is performed. The effective gate length of the gate transistor can be increased. Therefore, the same effect as that of the nonvolatile semiconductor memory device according to the first aspect can be obtained.
[0014]
  In addition, the present invention3Method of Manufacturing Nonvolatile Semiconductor Memory Device According to EmbodimentLaw isForming a gate electrode of a memory cell transistor and a select gate transistor having a channel region of a first conductivity type on a semiconductor substrate; and a first insulation on a sidewall of the gate electrode of the memory cell transistor and the select gate transistor Forming a film; forming a second insulating film on the first insulating film; and opening a gate electrode of the selection gate transistor on a side opposite to the side facing the memory cell transistor. A step of forming a mask having a mask, a step of removing the second insulating film through the opening in the mask, and a step through the opening in the mask.Below the gate electrode of the select gate transistorAnd a step of injecting an impurity of the first conductivity type.
[0015]
  Like this3According to the method for manufacturing a nonvolatile semiconductor memory device according to the above aspect, a mask for removing the second insulating film from the gate electrode of the select gate transistor is used, and the same as the channel region through the opening of the mask. A conductivity type impurity is implanted. Thus, the nonvolatile semiconductor memory device according to the first and second aspects can be manufactured without increasing the mask formation process for impurity implantation, that is, without increasing the manufacturing cost.
[0018]
In the method for manufacturing a nonvolatile semiconductor memory device according to the fourth aspect of the present invention, a memory cell transistor having a channel region of the first conductivity type and a gate electrode of a selection gate transistor on the semiconductor substrate are used as the selection gate. Forming a space between the gate electrodes of the transistors to be wider than a space between the gate electrode of the memory cell transistor and the gate electrode of the selection gate transistor; and an impurity of a first conductivity type in the semiconductor substrate, Injecting at an angle that is not injected between the gate electrode of the memory cell transistor and the gate electrode of the selection gate transistor but is injected between the gate electrodes of the selection gate transistor.
[0019]
According to the method of manufacturing the nonvolatile semiconductor memory device according to the fourth aspect, an impurity having the same conductivity type as that of the channel region is implanted between the gate electrode of the memory cell transistor and the gate electrode of the selection gate transistor. Instead, the implantation is performed at an angle between the gate electrodes of the selection gate transistors. Thus, the nonvolatile semiconductor memory device according to the first and second aspects can be manufactured without increasing the mask formation process for impurity implantation, that is, without increasing the manufacturing cost.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.
[0021]
(First embodiment)
The first embodiment improves the cut-off characteristics of the select gate transistor by injecting impurities of the same conductivity type as the channel into the bit line or source line contact side of the select gate transistor connected to the memory cell unit. It is a thing. The NAND nonvolatile semiconductor memory device according to the first embodiment will be described below in detail along with its manufacturing method.
[0022]
First, as shown in FIG. 1, a buffer oxide film 2 is formed on the surface of a p-type silicon substrate 1. Next, although not shown, a resist is applied to form a resist film. Next, openings corresponding to the well and channel regions are opened in the resist film by using a photolithography method. Next, using the resist film as a mask, n-type impurities such as phosphorus (P) and p-type impurities such as boron (B) are ion-implanted, and an n-type well (not shown) is formed in the p-type silicon substrate 1. A p-type well channel region 3 is formed. Thereafter, the resist film is removed.
[0023]
Next, as shown in FIG. 2, after the buffer oxide film 2 is removed, a gate insulating film 4 of the transistor is formed. The gate insulating film 4 is not limited to a silicon oxide film, and may be a silicon oxynitride film. Next, polysilicon to be a part of the gate electrode (floating gate) and silicon nitride to be a mask for STI (Shallow Trench Isolation) processing are deposited to form a polysilicon film 5 and a silicon nitride film 6. Next, a resist film 7 is formed, and an opening corresponding to the element isolation region is opened in the resist film 7 using a photolithography method.
[0024]
Next, as shown in FIG. 3, the silicon nitride film 6 is etched using the resist film 7 as a mask. Next, after removing the resist film 7, the polysilicon film 5, the gate insulating film 4, and the silicon substrate 1 are sequentially etched using the silicon nitride film 6 as a mask to form STI trenches 8 serving as element isolation regions.
[0025]
Next, as shown in FIG. 4, a thin silicon oxide film 9 is formed on the surface of the trench 8 of the STI. Next, silicon dioxide is deposited, and the STI trench 8 is filled with a silicon oxide film 10. Next, the surface of the silicon oxide film 10 is planarized using the CMP method, and then the silicon nitride film 6 is removed.
[0026]
Next, as shown in FIG. 5, polysilicon to be a part of the gate electrode (floating gate) is deposited to form a polysilicon film 11. Next, although not shown, a resist film is formed, and openings corresponding to the slits separating the memory cells arranged along the word lines are opened in the resist film using a photolithography method. Next, using the resist film as a mask, the polysilicon film 11 is etched to form slits 12. Thereafter, the resist film is removed.
[0027]
Next, as shown in FIG. 6, silicon dioxide (O) / silicon nitride (N) / silicon dioxide (O), polysilicon / tungsten silicide (WSi), and silicon nitride are sequentially deposited. In this manner, the ONO film 13, the polysilicon / WSi laminated film 14 serving as a gate electrode (control gate), and the silicon nitride film 15 serving as a mask for gate electrode processing are formed.
[0028]
Next, although not shown, a resist film is formed, and a pattern corresponding to the gate electrode (control gate and selection gate) is formed on the resist film by photolithography. Next, the silicon nitride film 15 is etched using the resist film as a mask. Next, after removing the resist film, the polysilicon / Wsi laminated film 14, the ONO film 13, the polysilicon film 11, and the polysilicon film 5 are sequentially etched using the silicon nitride film 15 as a mask, and the two-layer gate electrode is formed. Form.
[0029]
7 shows a plan view of a part of the memory cell portion formed by the above method, and FIG. 8 shows a cross section taken along the line A-A 'in FIG.
[0030]
FIG. 7 shows an element region 16, an element isolation region 17, gate electrodes 19 of two opposing select gate transistors, and a gate electrode 18 of a memory cell transistor connected to the select gate transistors.
[0031]
Next, as shown in FIG. 9, the sidewall of the gate electrode of the memory cell transistor and the sidewall of the gate electrode of the select gate transistor are each oxidized to form an oxide film 20. Next, a resist film 21 is formed, and an opening corresponding to a region between the gate electrodes of the selection gate transistor is opened in the resist film 21 using a photolithography method. Next, using the resist film 21 as a mask, a p-type impurity having the same conductivity type as the channel (p-type well channel region 3 in this example), for example, boron (B) is ion-implanted. Note that this ion implantation is preferably performed twice at an angle as shown by an arrow in FIG. 9 in order to implant an impurity under the gate electrode of the selection gate transistor. As a result, a region 22 having a higher p-type impurity concentration than the p-type well / channel region 3 is formed in the p-type silicon substrate 1 (p-type well / channel region 3 in this example) between the gate electrodes of the select gate transistors. It is formed.
[0032]
Next, as shown in FIG. 10, after removing the resist film 21, a resist film (not shown) is formed, and an opening corresponding to the memory cell portion is opened in the resist film using a photolithography method. . Next, using the resist film as a mask, an n-type impurity such as phosphorus (P) is ion-implanted into a region where the source / drain diffusion layer region of the memory cell transistor and the select gate transistor is formed, and the memory cell transistor and the select gate transistor N-type source / drain diffusion layer regions 23 and 24 are formed. Thereafter, the resist film is removed.
[0033]
At this time, a region 22 having a higher p-type impurity concentration than the p-type well channel region 3 in the p-type silicon substrate 1 (p-type well channel region 3 in this embodiment) between the gate electrodes of the select gate transistors. Is formed. For this reason, the effective impurity concentration (concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration) of the n-type source / drain diffusion layer region 23 on the opposite select gate transistor side is the n-type source on the memory cell transistor side. / It becomes thinner than the effective impurity concentration of the drain diffusion layer 24.
[0034]
As shown in FIG. 11, the depth of the pn junction in the source / drain direction is the depth of the pn junction D1 of the n-type source / drain diffusion layer region 23 under the gate electrode 19 of the select gate transistor. However, it becomes shallower than the depth D2 of the n-type source / drain diffusion layer region 24 on the memory cell transistor side.
[0035]
When p-type impurities are not ion-implanted between the gate electrodes of the selection gate transistor, which is a conventional example, the depth is reduced below the gate electrode 19 of the selection gate transistor as shown in FIG. D1 is the same as the depth D2.
[0036]
Further, as shown in FIG. 13, the shape of the n-type source / drain diffusion layer regions 23 and 24 of the selection gate transistor becomes asymmetric, and the p-type silicon substrate 1 (p-type well channel region 3 in this example) and N-type source / drain diffusion layer region 23 connected to the bit line or the source line at a position where the depth from the interface with the gate insulating film 4 is equal (for example, a position along the line BB ′ in FIG. 13); The distance L1 at which the gate electrode 19 overlaps is smaller than the distance L2 at which the n-type source / drain diffusion layer region 24 connected to the memory cell transistor and the gate electrode 19 overlap.
[0037]
In the case where p-type impurities are not ion-implanted between the gate electrodes of the selection gate transistor, which is a conventional example, the distance L1 is the same as L2 as shown in FIG.
[0038]
FIG. 15 shows an impurity concentration distribution at a position along the line B-B ′ in FIG. 10 (or FIG. 13).
[0039]
As shown in FIG. 15, in the select gate transistor, the impurity concentration of the channel region differs in the direction from the n-type source / drain diffusion layer 24 to the n-type source / drain diffusion layer region 23, and the bit line or source line The impurity concentration in the channel region in contact with the n-type source / drain diffusion layer region 23 in contact with n is higher than the impurity concentration in the channel region in contact with the n-type source / drain diffusion layer region 24 in contact with the memory cell transistor.
[0040]
The impurity concentration of the channel region in contact with the n-type source / drain diffusion layer region 24 in contact with the memory cell transistor of the select gate transistor is equal to the impurity concentration in the channel region in contact with the n-type source / drain diffusion layer region 24 of the memory cell transistor. Is the same.
[0041]
FIG. 16 shows an impurity concentration distribution when p-type impurities are not ion-implanted between the gate electrodes of the select gate transistor, which is a conventional example. FIG. 16 shows an impurity concentration distribution at a position along the line B-B ′ in FIG. 28. The position of the B-B ′ line in FIG. 28 is the same as the position of the B-B ′ line shown in FIG. 15.
[0042]
Compared with the conventional example shown in FIG. 16, in the present embodiment shown in FIG. 15, the effective channel length of the select gate transistor is increased.
[0043]
Thus, in this embodiment, the effective channel length of the select gate transistor is increased by ion-implanting the same p-type impurity as that of the channel between the gate electrodes of the select gate transistor. Thereby, the short channel effect of the select gate transistor is improved, and the cut-off characteristic is improved.
[0044]
Further, since the cut-off characteristics of the select gate transistor are improved, the impurity concentration in the channel region of the memory cell transistor can be lowered below the conventional level. As a result, the “1” data write characteristic is improved in the memory cell transistor. That is, for example, in a NAND type nonvolatile semiconductor memory device having a memory cell unit including a plurality of memory cell transistors as in the present embodiment, the resistance to non-selective write stress is further improved.
[0045]
In this embodiment, the threshold voltage of the selection gate transistor and the threshold voltage of the memory cell transistor are set within a range in which the threshold voltage of the selection gate transistor is higher than the threshold voltage of the memory cell transistor. Can be controlled independently. Therefore, it is possible to improve various characteristics of the memory cell transistor such as data retention characteristics and resistance to read stress while maintaining the cut-off characteristics of the selection gate transistor.
[0046]
In other words, the effect of the present embodiment is not particularly limited to the NAND type nonvolatile semiconductor memory device, and if it is a nonvolatile semiconductor memory device having a structure in which the select gate transistor is connected to the memory cell transistor, It is obtained effectively.
[0047]
Next, as shown in FIG. 17, an interlayer insulating film 25 is formed, a resist film (not shown) is formed, and an opening corresponding to the bit line or source line contact hole is opened in the resist film. Next, using the resist film as a mask, the interlayer insulating film 25 is etched to form contact holes 26. Thereafter, the resist film is removed. Next, if necessary, n-type impurities are ion-implanted into the p-type silicon substrate 1 (in this example, the n-type source / drain diffusion layer 23) through the contact hole 26 to form a region 27 having a high n-type impurity concentration. To do.
[0048]
Next, as shown in FIG. 18, a conductor (contact filling material: plug) is formed in the contact hole 26, and then a wiring layer is formed by a generally known method. Through these steps, a bit line or a source line is formed. FIG. 18 particularly shows a structure in which a wiring layer connected to a conductive material is a bit line. An example of the source line is formed using a conductive material, for example. In this way, a bit line or a source line is connected to the n-type source / drain diffusion layer 23. Note that there may be no conductive material, and the contact hole 26 may be directly embedded in the wiring layer. Thereafter, although not shown, a protective film is formed to complete the nonvolatile semiconductor memory device according to the first embodiment.
[0049]
In this embodiment, the p-type impurity is ion-implanted between the gate electrodes of the selection gate transistor, and then the n-type impurity forming the n-type source / drain diffusion layer regions 23 and 24 is ion-implanted. The n-type impurity forming the n-type source / drain diffusion layer regions 23 and 24 may be ion-implanted, and then the p-type impurity may be ion-implanted between the gate electrodes of the selection gate transistor.
[0050]
(Second Embodiment)
In the second embodiment, an insulating film such as a TEOS film is formed on the side walls of the gate electrodes of the memory cell transistor and the select gate transistor, and the bit line or source line contact hole is self-aligned between the gate electrodes of the select gate transistor. The present invention relates to a NAND type nonvolatile semiconductor memory device having a structure in which a TEOS film between a gate electrode of a select gate transistor and a contact hole is peeled off. In such a device, an impurity having the same conductivity type as that of the channel is implanted into the bit line or source line contact hole side of the select gate transistor, thereby improving the cut-off characteristics of the select gate transistor. The apparatus according to the second embodiment will be described below together with its manufacturing method.
[0051]
First, the double-layer gate electrode shown in FIG. 8 is formed by the method described in the first embodiment.
[0052]
Next, as shown in FIG. 19, the side walls of the gate electrodes of the memory cell transistor and the select gate transistor are oxidized to form an oxide film 20. Next, although not illustrated, a resist film is formed, and an opening corresponding to the memory cell portion is opened in the resist film using a photolithography method. Next, using the resist film as a mask, an n-type impurity such as phosphorus (P) is ion-implanted into a region where the source / drain diffusion layer region of the memory cell transistor and the select gate transistor is formed, and the memory cell transistor and the select gate transistor The n-type source / drain diffusion layer region 28 is formed. Thereafter, the resist film is removed. Next, an insulating film 29 such as a TEOS film is formed for the purpose of improving the hot carrier characteristics.
[0053]
Next, as shown in FIG. 20, a resist film 30 is formed, and an opening corresponding to a region between the gate electrodes of the selection gate transistor is opened in the resist film 30 using a photolithography method. Next, in order to prevent a short circuit between the gate electrode of the selection gate transistor and the contact filling material during contact formation, the TEOS film 29 on the sidewall of the gate electrode of the selection gate transistor is removed using the resist film 30 as a mask. Next, using the resist film 30 as a mask, a p-type impurity having the same conductivity type as the channel (p-type well channel region 3 in this example), for example, boron (B) is ion-implanted. Note that this ion implantation is preferably performed twice at an angle as shown by an arrow in FIG. 20 in order to implant an impurity under the gate electrode of the selection gate transistor. As a result, a region 31 having a higher p-type impurity concentration than the p-type well / channel region 3 is formed in the p-type silicon substrate 1 (p-type well / channel region 3 in this example) between the gate electrodes of the select gate transistors. It is formed. For this reason, the effective impurity concentration (concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration) of the n-type source / drain diffusion region 32 on the opposite select gate transistor side is the same as in the first embodiment. It becomes thinner than the effective impurity concentration of the n-type source / drain diffusion layer region 28 on the memory cell transistor side.
[0054]
The depth of the pn junction in the source / drain direction is also shallower in the n-type source / drain diffusion layer region 32 on the opposite select gate transistor side than on the n-type source / drain diffusion layer region 28 on the memory cell transistor side. Become.
[0055]
Therefore, the shape of the n-type source / drain diffusion layer regions 28 and 32 of the selection gate transistor is asymmetrical, and the interface between the p-type silicon substrate 1 (p-type well channel region 3 in this example) and the gate insulating film 4. The distance at which the gate electrode overlaps with the n-type source / drain diffusion layer region 32 connected to the bit line or the source line at a position where the depth from the gate is equal (for example, a position along the line BB ′ in FIG. 20). The distance between the n-type source / drain diffusion layer region 28 connected to the memory cell transistor and the gate electrode is smaller.
[0056]
Also in the NAND-type nonvolatile semiconductor memory device according to the second embodiment, the impurity concentration distribution at the position along the line BB ′ shown in FIG. 20 is the same as that in FIG. 15 of the first embodiment. Thus, the same effects as described in the first embodiment can be obtained.
[0057]
Further, according to the second embodiment, ion implantation is performed using the resist film 30 for peeling the TEOS film 29 as a mask. As a result, a photolithography process only for ion implantation for forming a region having an impurity concentration higher than that of the channel can be omitted, so that the manufacturing cost can be reduced.
[0058]
Note that the ion implantation described with reference to FIG. 20 is performed after the TEOS film 29 is stripped, but may be performed before the TEOS film 29 is stripped.
[0059]
Next, as shown in FIG. 21, after removing the resist film 30, a silicon nitride film 33 is formed as an etching stopper material when the contact hole is opened. Thereafter, an interlayer insulating film 25 is formed. Thereafter, although not shown, a resist film is formed, and an opening corresponding to the bit line or source line contact hole is opened in the resist film. Next, the interlayer insulating film 25 is etched using the resist film as a mask to form a contact hole 34 in a self-aligned manner with respect to the gate electrode of the select gate transistor. Thereafter, the resist film is removed. Next, if necessary, n-type impurities are ion-implanted into the p-type silicon substrate 1 (in this example, the n-type source / drain diffusion layer 32) through the contact holes 34 to form a region 35 having a high n-type impurity concentration. To do.
[0060]
Thereafter, as described with reference to FIG. 18, a conductive material (contact filling material) is formed in the contact hole 34, a wiring layer is formed by a generally known method, and a protective film is formed. The nonvolatile semiconductor memory device according to the second embodiment is completed.
[0061]
(Third embodiment)
The third embodiment relates to a NAND-type nonvolatile semiconductor memory device in which bit line or source line contact holes are formed in a self-aligned manner between gate electrodes of select gate transistors. In such a device, an impurity having the same conductivity type as that of the channel is injected into the bit line or source line contact side of the selection gate transistor through the contact hole, thereby improving the cutoff characteristic of the selection gate transistor. It is. The apparatus according to the third embodiment will be described below together with its manufacturing method.
[0062]
First, the double-layer gate electrode shown in FIG. 8 is formed by the method described in the first embodiment.
[0063]
Next, as shown in FIG. 22, the side walls of the gate electrodes of the memory cell transistor and the select gate transistor are oxidized to form an oxide film 20. Next, although not illustrated, a resist film is formed, and an opening corresponding to the memory cell portion is opened in the resist film using a photolithography method. Next, using the resist film as a mask, an n-type impurity such as phosphorus (P) is ion-implanted into a region where the source / drain diffusion layer region of the memory cell transistor and the select gate transistor is formed, and the memory cell transistor and the select gate transistor N-type source / drain diffusion layer regions 36 are formed. Thereafter, the resist film is removed.
[0064]
Next, as shown in FIG. 23, after forming a silicon nitride film 33 that serves as an etching stopper when the contact hole is opened, an interlayer insulating film 25 is formed.
[0065]
Next, as shown in FIG. 24, although not shown, a resist film is formed, and openings corresponding to the bit line or source line contact holes are opened in the resist film. Next, using the resist film as a mask, the interlayer insulating film 25 is etched to form a contact hole 37 in a self-aligned manner with respect to the gate electrode of the select gate transistor. Thereafter, the resist film is removed. Next, a p-type impurity having the same conductivity type as that of the channel (p-type well channel region 3 in this example), for example, boron (B) is ion-implanted through the contact hole 37. Note that this ion implantation is preferably performed twice at an angle as indicated by an arrow in FIG. 24 in order to implant an impurity under the gate electrode of the selection gate transistor. As a result, a region 38 having a higher p-type impurity concentration than the p-type well / channel region 3 is formed in the p-type silicon substrate 1 (p-type well / channel region 3 in this example) between the gate electrodes of the select gate transistors. It is formed. For this reason, the effective impurity concentration (concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration) of the n-type source / drain diffusion region 39 on the opposite select gate transistor side is the same as in the first embodiment. It becomes thinner than the effective impurity concentration of the n-type source / drain diffusion layer region 36 on the memory cell transistor side.
[0066]
In addition, the depth of the pn junction in the source / drain direction is also shallower in the n-type source / drain diffusion layer region 39 on the opposite select gate transistor side than on the n-type source / drain diffusion layer region 36 on the memory cell transistor side. Become.
[0067]
Therefore, the shape of the n-type source / drain diffusion layer regions 36 and 39 of the select gate transistor is asymmetric, and the interface between the p-type silicon substrate 1 (p-type well channel region 3 in this example) and the gate insulating film 4. The distance at which the gate electrode overlaps with the n-type source / drain diffusion layer region 39 connected to the bit line or the source line at a position where the depth from the gate is equal (for example, a position along the line BB ′ in FIG. 24). The distance between the n-type source / drain diffusion layer region 36 connected to the memory cell transistor and the gate electrode becomes smaller.
[0068]
Also in the NAND-type nonvolatile semiconductor memory device according to the third embodiment, the impurity concentration distribution at the position along the line BB ′ shown in FIG. 24 is the same as that in FIG. 15 of the first embodiment. Thus, the same effects as described in the first embodiment can be obtained.
[0069]
Furthermore, according to the third embodiment, TEOS as described in the second embodiment is performed by performing ion implantation through a contact hole formed in a self-aligned manner with respect to the gate electrode of the select gate transistor. Even when there is no photolithography process for film separation, the cutoff characteristics of the select gate transistor are improved without increasing the photolithography process only for ion implantation for forming a region having a higher impurity concentration than the channel. be able to. For this reason, for example, compared with 1st Embodiment, a manufacturing cost can be lowered | hung.
[0070]
However, even when there is a photolithography process for peeling the TEOS film as described in the second embodiment, it is formed in a self-aligned manner with respect to the gate electrode of the select gate transistor as in the third embodiment. It is also possible to perform ion implantation through the formed contact hole. Also in this case, there is an advantage that the manufacturing cost can be reduced.
[0071]
Next, if necessary, n-type impurities are ion-implanted into the p-type silicon substrate 1 (in this example, the n-type source / drain diffusion layer 39) through the contact holes 37 to form a region 40 having a high n-type impurity concentration. To do.
[0072]
Thereafter, as described with reference to FIG. 18, a conductive material (contact filling material) is formed in the contact hole 37, a wiring layer is formed by a generally known method, and a protective film is formed. The nonvolatile semiconductor memory device according to the third embodiment is completed.
[0073]
(Fourth embodiment)
In the fourth embodiment, the bit line or the source line of the selection gate transistor is at an angle such that the impurity is not injected between the gate electrodes of the memory cell transistor and the impurity is injected only between the gate electrodes of the selection gate transistor. An impurity having the same conductivity type as that of the channel is implanted on the contact side to improve the cut-off characteristics of the select gate transistor.
[0074]
First, the double-layer gate electrode shown in FIG. 8 is formed by the method described in the first embodiment.
[0075]
Next, as shown in FIG. 25, the side walls of the gate electrodes of the memory cell transistor and the select gate transistor are oxidized to form an oxide film 20. Next, although not illustrated, a resist film is formed, and an opening corresponding to the memory cell portion is opened in the resist film using a photolithography method. Next, a p-type impurity having the same conductivity type as the channel (p-type well channel region 3 in this example), for example, boron (B) is ion-implanted. The ion implantation angle θ at this time is as follows.
[0076]
Generally, in a nonvolatile semiconductor memory device, a distance l between gate electrodes of select gate transistors_SGTSince it is necessary to make contact with the bit line or the source line, the distance between the gate electrodes of the memory cell transistor and the distance l between the gate electrode of the memory cell transistor and the gate electrode of the selection gate transistor_{CE LL}Is bigger than. For this reason, as shown in FIG. 25, the gate electrode serves as a shield, and the p-type silicon substrate 1 (between the gate electrodes of the memory cell transistor and between the gate electrode of the memory cell transistor and the gate electrode of the selection gate transistor) In this example, an angle θ1 at which impurities are not implanted exists in the p-type well channel region 3). Similarly, there is an angle θ2 at which impurities are not implanted in the p-type silicon substrate 1 between the gate electrodes of the select gate transistors. Therefore, when the impurity is implanted so that the angle θ of the ion implantation satisfies the condition of “θ1 <θ <θ2”, the impurity can be implanted only into the p-type silicon substrate 1 between the gate electrodes of the select gate transistor. it can.
[0077]
An example of the specific definition of the angle θ1 is that when a straight line perpendicular to the p-type silicon substrate 1 is rotated around the memory cell transistor side wall lowest point of the gate electrode of the selection gate transistor, the straight line is The angle is in a range that intersects the gate electrode of the memory cell transistor.
[0078]
An example of the specific definition of the angle θ2 is that a straight line perpendicular to the p-type silicon substrate 1 is rotated with the lowest point on the side wall of the selection gate transistor opposite to the gate electrode of the selection gate transistor as the rotation center. The angle is in a range where the straight line does not intersect with the gate electrode of the opposing selection gate transistor.
[0079]
Note that this ion implantation is desirably performed twice at an angle of “± θ” as indicated by an arrow in FIG. 25 in order to implant an impurity under the gate electrode of the selection gate transistor. As a result, a region 41 having a higher p-type impurity concentration than the p-type well / channel region 3 is formed in the p-type silicon substrate 1 (p-type well / channel region 3 in this example) between the gate electrodes of the select gate transistors. It is formed.
[0080]
Next, as shown in FIG. 26, using a resist film (not shown) having an opening corresponding to the memory cell portion as a mask, an n-type impurity such as phosphorus (P) is applied to the memory cell transistor and the select gate transistor. Ions are implanted into the region where the source / drain diffusion layer region is formed, thereby forming n-type source / drain diffusion layer regions 42 and 43 of the memory cell transistor and the select gate transistor. Thereafter, the resist film is removed.
[0081]
At this time, a region 41 having a higher p-type impurity concentration than the p-type well channel region 3 in the p-type silicon substrate 1 (p-type well channel region 3 in this embodiment) between the gate electrodes of the select gate transistors. Is formed. Therefore, the effective impurity concentration (concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration) of the n-type source / drain diffusion layer region 43 on the opposite select gate transistor side is the n-type source on the memory cell transistor side. / It becomes thinner than the effective impurity concentration of the drain diffusion layer 42.
[0082]
The depth of the pn junction in the source / drain direction is also shallower in the n-type source / drain diffusion layer region 43 on the opposite select gate transistor side than on the n-type source / drain diffusion layer region 42 on the memory cell transistor side. Become.
[0083]
Therefore, the shape of the n-type source / drain diffusion layer regions 42 and 43 of the selection gate transistor is asymmetric, and the interface between the p-type silicon substrate 1 (p-type well channel region 3 in this example) and the gate insulating film 4. The distance at which the gate electrode overlaps with the n-type source / drain diffusion layer region 43 connected to the bit line or the source line at a position where the depth from the gate is equal (for example, a position along the line BB ′ in FIG. 26). The distance between the n-type source / drain diffusion layer region 42 connected to the memory cell transistor and the gate electrode becomes smaller.
[0084]
Also in the NAND-type nonvolatile semiconductor memory device according to the fourth embodiment, the impurity concentration distribution at the position along the line BB ′ shown in FIG. 26 is the same as that in FIG. 15 of the first embodiment. Thus, the same effects as described in the first embodiment can be obtained.
[0085]
Furthermore, according to the fourth embodiment, by implanting impurities so that the angle of ion implantation θ satisfies the condition of “θ1 <θ <θ2”, ions forming a region having a higher impurity concentration than the channel are formed. The cut-off characteristics of the select gate transistor can be improved without increasing the photolithography process for the purpose of implantation only. For this reason, for example, compared with 1st Embodiment, a manufacturing cost can be lowered | hung.
[0086]
Next, as shown in FIG. 27, an interlayer insulating film 25 is formed. Thereafter, although not shown, a resist film is formed, and an opening corresponding to the bit line or source line contact hole is opened in the resist film. Next, using the resist film as a mask, the interlayer insulating film 25 is etched to form contact holes 26. Thereafter, the resist film is removed. Next, if necessary, n-type impurities are ion-implanted into the p-type silicon substrate 1 (in this example, the n-type source / drain diffusion layer 43) through the contact holes 26 to form a region 44 having a high n-type impurity concentration. To do.
[0087]
Thereafter, as described with reference to FIG. 18, a conductive material (contact filling material) is formed in the contact hole 26, a wiring layer is formed by a generally known method, and a protective film is formed. The nonvolatile semiconductor memory device according to the second embodiment is completed.
[0088]
In this embodiment, an example in which the bit line or source line contact hole 26 is not formed in a self-aligned manner with respect to the gate electrode of the selection gate transistor is shown. However, the bit line or source line contact hole 26 is not formed. It is also possible to form in a self-aligned manner with respect to the gate electrode of the select gate transistor.
[0089]
In this embodiment, a p-type impurity is ion-implanted between the gate electrodes of the selection gate transistors at an angle θ that satisfies the condition of “θ1 <θ <θ2”, and then n The n-type impurity forming the source / drain diffusion layer regions 42 and 43 is ion-implanted. The n-type impurity forming the n-type source / drain diffusion layer regions 42 and 43 is ion-implanted, and then the selection gate. A p-type impurity may be ion-implanted between the gate electrodes of the transistor at the angle θ.
[0090]
As mentioned above, although this invention was demonstrated by 1st-4th embodiment, this invention is not limited to each of these embodiment, In the case of implementation, it changes variously in the range which does not deviate from the summary of invention. Is possible.
[0091]
For example, in the first to fourth embodiments, the element isolation region 17 is formed after the well channel region 3 and the gate insulating film 4 are formed. However, after the element isolation region 17 is formed, the well channel is formed. The region 3 may be formed.
[0092]
Although not shown in the first to fourth embodiments, a side wall is formed on the gate electrode using a generally known method, and an n-type impurity is introduced. The n-type source / drain diffusion layer regions of the memory cell transistor and the select gate transistor may have an LDD (Lightly Doped Drain) structure by deep ion implantation.
[0093]
In the first to fourth embodiments, the nonvolatile semiconductor memory device having a memory cell unit including a plurality of memory cell transistors is exemplified. However, the present invention is not limited to this, and at least one memory is used. Any semiconductor memory device having a memory cell unit including a cell transistor can be applied with the above effects.
[0094]
Of course, the first to fourth embodiments can be implemented individually or in appropriate combination.
[0095]
Further, each of the first to fourth embodiments includes inventions of various stages, and various stages can be achieved by appropriately combining a plurality of constituent elements disclosed in the first to fourth embodiments. It is also possible to extract the invention.
[0096]
【The invention's effect】
As described above, according to the present invention, the non-volatile property that can improve both the various characteristics of the memory cell transistor such as the data write characteristic, the data retention characteristic, and the resistance to the read stress, and the cut-off characteristic of the selection gate transistor. A semiconductor memory device and a manufacturing method thereof can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing one manufacturing process of a nonvolatile semiconductor memory device according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 3 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.
FIG. 7 is a plan view showing a part of the memory cell portion of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
8 is a cross-sectional view taken along line A-A ′ in FIG. 7;
FIG. 9 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.
FIG. 10 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.
FIG. 11 is a sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 12 is a cross-sectional view of a conventional nonvolatile semiconductor memory device.
FIG. 13 is a cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 14 is a cross-sectional view of a conventional nonvolatile semiconductor memory device.
FIG. 15 is an impurity concentration distribution diagram showing an impurity concentration distribution of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
FIG. 16 is an impurity concentration distribution diagram showing an impurity concentration distribution of a conventional nonvolatile semiconductor memory device.
FIG. 17 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.
FIG. 18 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.
FIG. 19 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the second embodiment of the present invention.
FIG. 20 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the second embodiment of the present invention.
FIG. 21 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention;
FIG. 22 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the third embodiment of the present invention.
FIG. 23 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the third embodiment of the present invention.
FIG. 24 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the third embodiment of the present invention.
FIG. 25 is a sectional view showing one manufacturing process of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention;
FIG. 26 is a cross-sectional view showing one manufacturing process of the nonvolatile semiconductor memory device in accordance with the fourth embodiment of the present invention.
FIG. 27 is a sectional view showing one manufacturing process of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention;
FIG. 28 is a cross-sectional view of a conventional semiconductor memory device.
[Explanation of symbols]
1 ... p-type silicon substrate,
2. Buffer oxide film,
3 ... p-type well channel region,
4 ... Gate insulating film,
5 ... polysilicon film,
6 ... silicon nitride film,
7 ... resist film,
8 ... STI groove,
9: Thin silicon oxide film,
10: Silicon oxide film,
11 ... polysilicon film,
12 ... Slit,
13 ... ONO film,
14 ... Polysilicon / WSi laminated film,
15 ... Silicon nitride film,
16: Element region,
17 ... element isolation region,
18 ... Gate electrode of memory cell transistor,
19 ... gate electrode of select gate transistor,
20 ... Oxide film,
21 ... resist film,
22 ... a region having a high p-type impurity concentration,
23, n-type source / drain diffusion layer region in contact with the bit line or the source line,
24 ... n-type source / drain diffusion layer region,
25. Interlayer insulating film,
26 ... contact hole,
27: a region having a high n-type impurity concentration,
28 ... n-type source / drain diffusion layer region,
29. Insulating film such as TEOS film,
30 ... resist film,
31 ... a region having a high p-type impurity concentration,
32... N-type source / drain diffusion layer region in contact with the bit line or the source line,
33 ... Silicon nitride film,
34 ... Contact hole formed in a self-aligning manner,
35 ... a region having a high n-type impurity concentration,
36 ... n-type source / drain diffusion layer region,
37 ... Contact hole formed in a self-aligning manner,
38 ... a region having a high p-type impurity concentration,
39... N-type source / drain diffusion layer region in contact with the bit line or the source line,
40 ... a region having a high n-type impurity concentration,
41 ... a region having a high p-type impurity concentration,
42 ... n-type source / drain diffusion layer region,
43. n-type source / drain diffusion layer region in contact with the bit line or the source line,
44: A region having a high n-type impurity concentration.

Claims (9)

A memory cell unit including at least one memory cell transistor having a stacked structure of a charge storage layer and a control gate layer formed on a semiconductor substrate;
A selection gate transistor in which one of the source / drain diffusion layer regions is connected to the bit line or the source line and the other is connected to the memory cell unit;
Under the gate electrode of the selection gate transistor, the shape of the source diffusion layer region of the selection gate transistor and the shape of the drain diffusion layer region are asymmetric.
The distance between the diffusion layer region connected to the bit line or the source line and the gate electrode at a position where the depth from the interface between the semiconductor substrate and the gate insulating film is equal is connected to the memory cell unit. diffusion layer region and the rather smaller than the distance where the gate electrode overlaps, the effective impurity concentration of the connected diffusion layer region to the bit line or the source line, effective of the connected to the memory cell unit diffusion layer region The effective impurity concentration of the diffusion layer region that is thinner than the impurity concentration and connected to the memory cell unit is the same as the effective impurity concentration of the source / drain diffusion layer region of the memory cell transistor, and the memory cell A side wall of the gate electrode of the transistor and a side of the gate electrode of the select gate transistor facing the memory cell An insulating film, a second insulating film formed on the first insulating film, and a third insulating film formed on the second insulating film are stacked, and the select gate transistor On the side of the gate electrode facing the contact for connecting the bit line or the source line, the first insulating film and the third insulating film formed on the first insulating film are provided. A non-volatile semiconductor memory device, characterized by being stacked . A memory cell unit including at least one memory cell transistor having a stacked structure of a charge storage layer and a control gate layer formed on a semiconductor substrate;
A selection gate transistor in which one of the source / drain diffusion layer regions is connected to the bit line or the source line and the other is connected to the memory cell unit;
Under the gate electrode of the selection gate transistor, the shape of the source diffusion layer region of the selection gate transistor and the shape of the drain diffusion layer region are asymmetric.
The distance between the diffusion layer region connected to the bit line or the source line and the gate electrode at a position where the depth from the interface between the semiconductor substrate and the gate insulating film is equal is connected to the memory cell unit. The impurity concentration of the channel region that is smaller than the distance between the diffusion layer region and the gate electrode and that is in contact with the diffusion layer region connected to the bit line or source line is in contact with the diffusion layer region connected to the memory cell unit. The impurity concentration of the channel region that is higher than the impurity concentration of the channel region and is in contact with the diffusion layer region connected to the memory cell unit is the same as the impurity concentration of the channel region that is in contact with the source / drain diffusion layer region of the memory cell transistor. A sidewall of the gate electrode of the memory cell transistor, and the selection gate transistor On the side of the gate electrode facing the memory cell, a first insulating film, a second insulating film formed on the first insulating film, and a second insulating film are formed on the second insulating film. A third insulating film is stacked, and on the side of the gate electrode of the select gate transistor facing the contact for connecting the bit line or the source line, the first insulating film and the first insulating film are formed. A non-volatile semiconductor memory device , wherein the third insulating film formed on one insulating film is laminated . The effective impurity concentration of the diffusion layer region connected to the bit line or the source line at a position where the depth from the interface between the semiconductor substrate and the gate insulating film is equal is the diffusion layer connected to the memory cell unit. rather thin than the effective impurity concentration in the region, the effective impurity concentration of the diffusion layer region which is connected to the memory cell unit is the same as the effective impurity concentration of the source / drain diffusion layer region of the memory cell transistor The nonvolatile semiconductor memory device according to claim 2 . The deepest part of the diffusion layer region connected to the bit line or the source line under the gate electrode is shallower than the deepest part of the diffusion layer region connected to the memory cell unit. The nonvolatile semiconductor memory device according to claim 3. Contacts for connecting the bit lines or source lines in the diffusion layer regions, the first to fourth aspects any one, characterized in that it is formed in self-alignment with the gate electrode of the select gate transistor The nonvolatile semiconductor memory device according to item . Forming a gate electrode of a memory cell transistor having a first conductivity type channel region and a selection gate transistor on a semiconductor substrate;
Forming a first insulating film on a sidewall of the gate electrode of the memory cell transistor and the selection gate transistor;
Forming a second insulating film on the first insulating film;
Forming a mask having an opening on a side of the gate electrode of the selection gate transistor opposite to the side facing the memory cell transistor;
Removing the second insulating film through the opening of the mask;
Implanting a first conductivity type impurity under the gate electrode of the select gate transistor through the opening of the mask;
Method of manufacturing a nonvolatile semiconductor memory device you characterized by comprising a. Implanting first conductivity type impurity under the gate electrode of the selection gate transistor via an opening of the mask, the non-volatile semiconductor memory device according to claim 6 you and performs at an angle Manufacturing method. A gate electrode of a memory cell transistor and a select gate transistor having a channel region of the first conductivity type on a semiconductor substrate, a space between the gate electrodes of the select gate transistor, a gate electrode of the transistor of the memory cell and the select gate Forming wider than the space between the gate electrodes of the transistor;
The first conductivity type impurity is not injected between the gate electrode of the memory cell transistor and the gate electrode of the selection gate transistor, but at an angle that is injected between the gate electrodes of the selection gate transistor. And the process
Method of manufacturing a nonvolatile semiconductor memory device you characterized by comprising a. 9. The method of manufacturing a nonvolatile semiconductor memory device according to claim 6, wherein the first conductivity type impurity is a P-type impurity .

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