JP4306570B2 - Signal processing apparatus and signal processing method - Google Patents

Description

  The present invention relates to a signal processing apparatus and a signal processing method for receiving data transmitted by multiplexing a digital video signal and a digital audio signal.

  As digital signal transmission standards, there are many standards such as standards by IEC (International Electrotechnical Commission) and IEEE (Institute of Electrical and Electronics Engineers). Among these, for example, the IEEE 1394 standard is attracting attention as being suitable for multimedia applications such as connection between digital video recorders and connection between a digital video camera and a computer.

  The IEEE 1394 standard will be described. In the following description, the IEEE 1394 standard is simply referred to as the 1394 standard.

  In the 1394 standard, transmission is performed using two pairs of twisted pair wires. The transmission method is so-called half-duplex communication in which two pairs of twisted pair wires are used for transmission in one direction. In this communication method, a communication method called DS coding is adopted. This is because data is sent to one side of a twisted pair wire and a signal called a strobe is sent to the other side, and the exclusive OR of the two signals is taken. The clock is reproduced on the receiving side.

  Three types of data rates of the 1394 standard are defined as 98.304 Mbps (S100), 196.608 Mbps (S200), and 393.216 Mbps (S400), and a device corresponding to a higher rate has a slower rate. So-called upward compatibility is defined.

  Each device is allowed to have up to 26 ports, and up to 63 devices can be networked by connecting the ports of each device. In the 1394 standard, a bus initialization process is performed at the time of connection, and a tree structure is automatically configured internally when a plurality of devices are connected. Thereafter, the address of each device is automatically assigned.

  According to the 1394 standard, a signal transmitted from one device is relayed by another device, whereby a signal having the same content can be transmitted to all devices in the network. Therefore, in order to prevent random transmission / reception, each device needs to arbitrate the right to use the bus before starting transmission. In order to obtain the right to use the bus, first, it waits for the bus to be released, and sends a bus use right request signal to the parent device on the tree. Then, the master unit that has received the request relays the signal to a further master unit, and the request signal finally reaches the route that is the highest-level master unit. When the route receives the request signal, the route returns a use permission signal, and the device that has received the permission can communicate. However, if a request signal is issued simultaneously from a plurality of devices at this time, only one device is given a permission signal and other requests are rejected.

  Thus, according to the 1394 standard, it can be said that a plurality of devices use one bus by time division multiplexing while competing for the right to use the bus. However, in data that requires real-time properties such as a video signal and an audio signal, data may be lost if communication is not guaranteed at regular time intervals. Therefore, in the 1394 standard, such data is transmitted using a communication method called isochronous. That is, a management node is selected at the time of the previous bus initialization, and a device that transmits by isochronous communication receives a necessary bandwidth allocation from the management node. The route transmits a cycle start packet every 125 μs, and a device that has been assigned a bandwidth transmits an isochronous packet following the cycle start packet. By performing such processing, a device that has been assigned a bandwidth can always get an opportunity to transmit every 125 μs, and data loss can be prevented.

  In the following description, for example, an AV protocol is referred to as a signal format when digital video and digital audio signals are transmitted by a digital video recorder using 1394 standard isochronous communication. In this signal format, a video signal on a video tape, for example, a compressed video signal or an audio signal is handled as a collection of 80-byte block data called a DIF block.

  In the case of the 525/60 system of the television standard broadcasting system (so-called NTSC system), a 1 DIF sequence is composed of 150 DIF blocks, and the 10 DIF sequence is one video frame. In isochronous communication, one packet is transmitted every 125 μs, so it is sufficient to transmit 29.97 × 10 × 150 × 125 × 10 −6 = 5.619 DIF block per packet. One 6DIF block is defined as one packet. As a result, data for one video frame is transmitted in 250 packets as shown in FIG.

  The structure of one isochronous packet is shown in FIG. In FIG. 10, the first 32 bits of the packet are a packet header defined by the 1394 standard. The data portion after the header CRC and before the data CRC is a portion defined as a data field in the 1394 standard, but to the CIP for representing the information of the audio / video signal at the head of this portion. Is added to the AV protocol.

  The SYT field of the CIP header is a time stamp for applying frame synchronization. In video signal communication, it is necessary to send a frame synchronization signal. Therefore, a time stamp using a cycle time defined in the 1394 standard is sent to the head of a video frame. The cycle time is a counter that counts 24.576 MHz, which is a basic clock of the 1394 standard, and the route transmits its count value in a cycle start packet. Each node then synchronizes the cycle time by copying it to its own cycle time.

  When transmitting a video signal, a value obtained by adding the maximum amount of communication delay to the value of the cycle time at the head of the frame is put in the CIP header as SYT. As a result, as shown in FIG. 11, it is possible to generate a frame synchronization signal delayed by the maximum delay by comparing with the cycle time on the receiving side.

  FIG. 12 shows a configuration example of a digital video recorder for recording / reproducing and inputting / outputting the 1394 standard digital audio / video signal to / from the outside.

  In FIG. 12, a video input / output terminal 100 and an audio input / output terminal 101 are terminals for inputting / outputting analog video signals and analog audio signals.

  The A / D converter and D / A converter 102 digitize the analog video signal input from the video input / output terminal 100, and conversely, digital video supplied from the video compression / decompression circuit 104. Analogize the signal. The A / D converter and D / A converter 103 digitize the analog audio signal input from the audio input / output terminal 101, and conversely, is supplied from the audio interleave / deinterleave circuit 105. For digital audio signals, analogization is performed.

  The video compression / decompression circuit 104 performs compression processing on the digital video signal input from the A / D converter 102, and conversely, the compressed digital video signal supplied from the multiplexer / demultiplexer (MPX / DMPX) 106. Is subjected to expansion processing. The audio interleaving / deinterleaving circuit 105 performs an interleaving process on the digital audio signal input from the A / D converter 103, and conversely, a digital signal subjected to the interleaving supplied from the multiplexer / demultiplexer 106. Deinterleaving is performed on the audio signal.

  The multiplexer / demultiplexer 106 multiplexes the compressed digital video signal from the video compression / decompression circuit 104 and the interleaved digital audio signal from the audio interleave / deinterleave circuit 105, and conversely multiplexes them. When the data is supplied, the compressed digital video signal and the interleaved digital audio signal are separated (demultiplexed) from the multiplexed data.

  A recording / reproduction signal processing (FEC) circuit 107 adds an error correction code to the multiplexed data, modulates the multiplexed data, generates a recording signal, sends it to the magnetic head 108, and conversely reproduces it from the magnetic tape by the magnetic head 108. The reproduced signal is subjected to error correction after being demodulated.

  The digital interface block 109 is a block that performs interface signal processing in accordance with the 1394 standard with an external computer or another digital video recorder under the control of a control microcomputer (microcomputer) 110. A link (LINK) circuit 111 processes the 1394 standard link layer and the AV protocol on the multiplexed data supplied from the multiplexer / demultiplexer 106 or the recording / reproducing signal processing circuit 107. The relay (PHY) circuit 112 performs bus initialization, arbitration of usage rights, signal relay of other devices, and the like. The control microcomputer 110 performs control of the link circuit 111 and the relay circuit 112, acquisition of isochronous communication bandwidth, management of the bus as a limited manager, and the like.

  Here, the format of the digital video signal and the digital audio signal in the 1394 standard is also called a DV format. The DV format further includes a DVCAM format which will be described later.

  Since the DVCAM format is included in the DV format, the specifications are basically the same. However, when focusing on the audio signal, the following points are different between the DV format and the DVCAM format. .

  That is, as shown in FIG. 13, the signal format of the digital audio signal in the 1394 standard includes a sync area where a synchronization signal is arranged, an ID code area where identification information is arranged, an AAUX area where audio auxiliary data is arranged, It consists of an audio data area where an actual digital audio signal is arranged, an outer parity area, and an inner parity area. In the DV format, a digital audio signal arranged in the audio data area is a television as shown in FIG. For each of the John standard broadcasting 525/60 system (NTSC system) and 625/50 system (PAL system), there are 4 channel modes with sampling frequencies of 48 kHz, 44.1 kHz, 32 kHz, and 32 kHz. , The audio signals of each of these modes is in a video signal and asynchronously. In each mode of the 525/60 system and the 625/50 system, an allowable range of the number of samples (bytes) per frame is determined, and an error of about 1% (that is, a sampling frequency) is set as the allowable range. The allowable frequency deviation is about 1%). For example, taking the 32 kHz 4 channel mode of a 525/60 system as an example, the maximum number of samples per frame (bytes) is 1080 samples (3240 bytes), the minimum is 1053 samples (3159 bytes), and the average is 1067.73. A sample (3203.2 bytes) is used.

  On the other hand, the DVCAM format is particularly provided as a format used in, for example, a video camera with a built-in digital video tape recorder, and locks the sampling frequency, as shown in FIGS. The number of audio samples in one frame is fixed for each frame, and information on the number of samples is transmitted for each frame. That is, in the DVCAM format, as shown in FIG. 15, there are 4 channel modes with a sampling frequency of 48 kHz and 32 kHz for each of the 525/60 system and the 625/50 system. In the 48 kHz mode, the first frame is 1600 samples, and the second to fifth frames are 1602 samples. Similarly, in the 32 kHz 4 channel mode of the 525/60 system, the first frame and the eighth frame are 1066 samples, the second to seventh and ninth to 15th frames are 1068 samples, and in the 48 kHz mode of the 625/50 system, All frames are 1920 samples, and all frames are 1280 samples in the 32 kHz 4 channel mode of the 625/60 system. In the DVCAM format, the relationship between the audio signal sampling frequency (fs) and the horizontal video frequency (fH) in each of the 48 kHz and 32 kHz modes of the 525/60 system and the 625/50 system is shown in FIG. As shown, it is fixed, i.e. synchronized.

  In the audio auxiliary data (AAUX) area of the audio signal format shown in FIG. 13, a plurality of auxiliary data are defined as shown in FIG. Since these data are already known as standards, only the main data among the auxiliary data will be described briefly. In the area indicated by AF SIZE in the figure, information on the number of audio samples (audio sample size) in one frame as shown in FIG. 17 is arranged, and in the area indicated by AUDIO MODE in the figure, information indicating the mode. In the figure, CHN indicates information indicating a channel, SMP in the figure indicates information indicating a sampling frequency, and EF in the figure indicates an emphasis / de-emphasis process described later. An emphasis flag is arranged, and information related to copyright is arranged in an area indicated by CGMS in the drawing. Further, in the 32 kHz, 44.1 kHz, and 48 kHz modes of the 525/60 system and the 625/50 system, it is specified that the difference between the AF SIZEs of the channel CH1 and the channel CH2 does not exceed the range shown in FIG.

  As described above, in the DV format, the digital audio signal and the digital video signal are asynchronous, whereas in the DVCAM format, the digital audio signal and the digital video signal are synchronized.

  By the way, in a signal composed of a digital video signal and a digital audio signal such as the DV format and the DVCAM format, for example, an arbitrary editing operation is performed particularly on the digital audio signal, and the edited digital audio signal is converted into a digital video signal. Assume that recording is performed on a recording medium. As an example of such editing, editing that gradually narrows down the level of an audio signal already recorded on a recording medium such as a video tape, that is, for an audio signal reproduced from a video tape by a preceding head, for example. For example, editing such as multiplying by a digital coefficient that reduces the level, then multiplexing with the video signal and re-recording on the video tape by the main head can be considered.

  In the case of such an editing operation, if the digital video signal and the digital audio signal are synchronized as in the DVCAM format, the number of samples of the audio signal matches the frame delimiter of the video signal. Therefore, signal processing is easy and the circuit scale is small.

  On the other hand, when the digital video signal and the digital audio signal are asynchronous as in the DV format, that is, when the number of samples of the audio signal is larger than the video signal frame delimiter (from the maximum in FIG. 14). In order to perform the editing operation as described above, the signal processing in the number of cases is necessary, and the circuit scale becomes large.

  Here, when editing an asynchronous digital audio signal with respect to a digital video signal, the simplest implementation method is to convert the digital audio signal into an analog audio signal, and further convert the analog audio signal into the DVCAM. A method of re-converting into a digital audio signal synchronized with the digital video signal as in the format and then multiplexing with the digital video signal can be considered.

  If the digital audio signal is once converted into an analog audio signal and then converted again into a digital audio signal as described above, the following problems occur.

  That is, distortion, noise, frequency characteristic degradation, and the like occur due to characteristic differences between the digital / analog converter and the analog / digital converter, and quantization distortion occurs due to requantization. When such noise, frequency characteristic deterioration, and distortion occur, sound quality deteriorates.

  Further, in the digital / analog converter and the analog / digital converter, if the total conversion sensitivity is too high, overload distortion occurs in a signal of the maximum level (and a large level near the maximum level), for example. On the contrary, if the conversion sensitivity is low, the quantization noise at the time of requantization increases and the signal level is lowered. Therefore, when performing these digital / analog conversion and analog / digital conversion, accurate level adjustment is required, and particularly when there are a large number of channels, accurate level adjustment is required for each channel. . Providing such a configuration for adjustment increases the cost of the apparatus.

  Therefore, the present invention has been made in view of such a situation, and it is possible to easily synchronize a digital audio signal asynchronous with a digital video signal to the digital video signal, and to prevent deterioration in sound quality. It is an object of the present invention to provide a signal processing device and a processing method that can suppress an increase in size and cost of the device configuration.

The present invention is a signal processing apparatus for receiving data transmitted by multiplexing a digital video signal and a digital audio signal, and generating a clock necessary for reproducing the digital audio signal for the transmitted data. min control signal as auxiliary data peripheral for controlling parameters audio signal reproduction and is added, an extraction means for extracting the frequency division parameter and the control signal from the data received above are used when the above extract Means for generating the clock by dividing the reference signal necessary for reproduction of the digital video signal using the frequency division parameter extracted from the means, and by reading the digital audio signal with the clock. It is added to the control signal to the digital audio signal after rate conversion E Bei a control signal adding means, said control signal is a variety of control signals that are included with the digital audio signal, is intended to include information indicating the emphasis on / off, stereo / bilingual, the sampling frequency.

The signal processing method according to the present invention receives data transmitted by multiplexing a digital video signal and a digital audio signal, and a clock necessary for reproduction of the digital audio signal is received in the transmitted data. control signal as auxiliary data for controlling the frequency division parameter and the audio signal playback is used when generated has been added, the frequency division parameter and the control signal extracted from the data received above, it is the extracted Digital audio after rate conversion by generating the clock by dividing the reference signal necessary for reproduction of the digital video signal using the divided parameter, and reading the digital audio signal by the clock adding the control signal to the signal, the control signal is a digital A variety of control signals that are included with Dio signal, information indicating the emphasis on / off, stereo / bilingual, in which to include the sampling frequency.

  The present invention extracts a frequency division parameter from data transmitted by multiplexing a digital video signal and a digital audio signal, and uses the extracted frequency division parameter to obtain a reference signal necessary for reproduction of the digital video signal. By dividing the frequency, a clock necessary for reproduction of the digital audio signal is generated, so that it is possible to easily synchronize a digital audio signal asynchronous with the digital video signal to the digital video signal. In addition, it is possible to prevent deterioration in sound quality and to suppress an increase in the size and cost of the apparatus configuration.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  An example of a digital signal conversion apparatus which is an embodiment of a signal processing apparatus according to the present invention is shown in FIG.

  The digital signal converter shown in FIG. 1 is supplied with a DV signal in which a DV format digital video signal and digital audio signal are asynchronous (hereinafter referred to as an asynchronous mode DV signal), and the digital signal of the asynchronous mode DV signal is supplied. The video signal and the digital audio signal are converted into a synchronized DV signal (hereinafter referred to as a synchronous mode DV signal) and output.

  In FIG. 1, the asynchronous terminal DV signal in which the digital video signal and the digital audio signal are asynchronous is input to the input terminal 1 from the outside, for example. The terminal 2 is supplied with a frame reference signal (frame reference signal of a video signal) of 29.97 Hz in the case of the 525/60 system (NTSC system) and 25 Hz in the case of the 625/50 system (PAL system). Is done.

  The asynchronous mode DV signal is sent to the input video signal processing circuit 3, the input CH1 audio signal processing circuit 30, and the input CH2 audio signal processing circuit 31. Since the input CH1 audio signal processing circuit 30 and the input CH2 audio signal processing circuit 31 have substantially the same configuration, the internal configuration of the input CH2 audio signal processing circuit 31 is omitted in the example of FIG. .

  The input video signal processing circuit 3 deshuffles and expands the compressed and shuffled video signal included in the asynchronous mode DV signal based on the frame reference signal. This deshuffling and decompressed video signal is sent to the output video signal processing circuit 4. The output video signal processing circuit 4 compresses and shuffles the video signal from the input video signal processing circuit 3. The compressed and shuffled video signal is sent to a multiplexer (MPX) 5.

  On the other hand, the asynchronous mode DV signals supplied to the input CH1 audio signal processing circuit 30 and the input CH2 audio signal processing circuit 31 are input to the internal deinterleave circuit 41 and the ni reading / control signal demodulation circuit 44, respectively.

  The deinterleave circuit 41 separates the digital audio signal shown in FIG. 13 multiplexed with the digital video signal in the asynchronous mode DV signal, and performs deinterleave processing and error correction on the separated digital audio signal. When an error such as missing data is present in the audio signal, high-order digital interpolation using, for example, a Lagrangian polynomial is performed as necessary. The digital audio signal (hereinafter, referred to as digital audio signal DATAi) subjected to the deinterleaving process by the deinterleaving circuit 41 of the input CH1 audio signal processing circuit 30 is sent to the CH1 sample rate conversion circuit 32 for input CH2 audio signal processing. The audio signal DATAi output from the deinterleave circuit 41 in the circuit 31 is sent to the CH2 sample rate conversion circuit 33.

  The ni reading / control signal demodulating circuit 44 demodulates various code information as shown in FIG. 17 added to the audio signal of FIG. 13 and sends it to the microcomputer 8 as shown in FIG. Such a ni value is read from the asynchronous mode DV signal, and the read ni value is sent to the frequency divider 8. Here, the ni value is a value corresponding to the number of samples in each mode of the sampling frequency. As shown in FIG. 2, in the 48 kHz mode of the 525/60 system (NTSC system), the maximum value is 1620 and the minimum value is 1580. In the 44.1 kHz mode, the maximum value is 1489 and the minimum value is 1452. In the 32 kHz mode, the maximum value is 1080 and the minimum value is 1053. In the 625/50 system (PAL system) 48 kHz mode, the maximum value is 1944 and the minimum value is 1896. In the 44.1 kHz mode, the maximum value is 1786 and the minimum value is 1742. In the 32 kHz mode, the maximum value is 1296 and the minimum value. The value is 1264.

  In the microcomputer 8, various code information as shown in FIG. 17 supplied from the ni reading / control signal demodulating circuit 44 of the input CH1 audio signal processing circuit 30 and the input CH2 audio signal processing circuit 31 is output as will be described later. The signals are sent to the CH1 audio signal processing circuit 34 and the output CH2 audio signal processing circuit 35, respectively.

  The CH1 sample rate conversion circuit 32 and the CH2 sample rate conversion circuit 33 have the same configuration. Each of the CH1 sample rate conversion circuit 32 and the CH2 sample rate conversion circuit 33 has an input operation reference clock generated by an input clock generation circuit 10 described later and an input CH1 audio signal. The processing circuit 30 has input rate conversion units 32i and 33i that operate based on an input bit clock BCKi and an input sampling clock LRCKi generated as described later, and is generated by an output clock generation circuit 20 described later. The output rate conversion units 32o and 33o operate based on the output operation reference clock, the output bit clock BCCo and the output sampling clock LRCCo generated by the output CH2 audio signal processing circuit 34 as described later.

  The CH1 sample rate conversion circuit 32 and the CH2 sample rate conversion circuit 33 are connected to the input operation reference clock and the output reference operation clock, the input bit clock BCKI and the input sampling clock LRCKi, and the output bit clock BCCo and the output sampling clock LRCCo. Based on this, the digital audio signal DATAi from the input CH1 audio signal processing circuit 30 and the input CH2 audio signal processing circuit 31 is converted into a sampling rate, thereby synchronizing the digital audio signal of the asynchronous mode DV signal with the digital video signal. Converted to a digital audio signal.

  The digital audio signal DATAo synchronized with the digital video signal by the sample rate conversion processing in the CH1 sample rate conversion circuit 32 and the CH2 sample rate conversion circuit 33 is converted into the corresponding output CH1 audio signal processing circuit 34 and output CH2 respectively. It is sent to the interleave circuit 51 of the audio signal processing circuit 35. Since the output CH1 audio signal processing circuit 34 and the output CH2 audio signal processing circuit 35 have substantially the same configuration, the internal configuration of the output CH2 audio signal processing circuit 35 is omitted in the example of FIG. .

  The output CH1 audio signal processing circuit 34 and the output CH2 audio signal processing circuit 35 reconstruct a DV format digital audio signal from the supplied digital audio signal DATAo and send it to the multiplexer (MPX) 52. The multiplexer 52 multiplexes the code information supplied from the microcomputer 8 with the reconstructed digital audio signal and outputs the multiplexed information. The digital audio signals output from the output CH1 audio signal processing circuit 34 and the output CH2 audio signal processing circuit 35 are multiplexed by a multiplexer (MPX) 7 and sent to the multiplexer 5.

  The multiplexer 5 multiplexes the compressed and shuffled digital video signal from the output video signal processing circuit 4 and the digital audio signal from the multiplexer 7. The synchronous mode DV signal generated by the multiplexing at the multiplexer 5 is output from the output terminal 6.

  The above-described path is the main path for the digital video signal and the digital audio signal, and the path and configuration for synchronizing the digital video signal and the digital audio signal of the asynchronous mode DV signal will be described below.

  The frame reference signal supplied to the terminal 2 includes an input CH1 audio signal processing circuit 30, a deinterleave circuit 41 in the input CH2 audio signal processing circuit 31, video signal processing circuits 3 and 4, an input clock generation circuit 10 and It is sent to the output clock generation circuit 20.

  The input clock generation circuit 10 includes a phase comparator 11, an integration circuit 12, a voltage control oscillator 13, and frequency dividers 14, 15, and 16 as main components that receive the frame reference signal at one input terminal. (Phase-Locked Loop) circuit, and the voltage controlled oscillator 13 generates an input clock signal. This input clock signal is supplied to the CH1 sample rate conversion circuit 32 and the CH2 sample rate conversion circuit 33 as an input operation reference clock, and is also sent to the frequency divider 14 and the frequency divider 15.

  The frequency divider 14 divides the input clock signal by ½, and sends the ½ frequency divided clock to the input CH1 audio signal processing circuit 30 and the input CH2 audio signal processing circuit 31. The frequency divider 15 divides the input clock signal by 1/512 and sends the 1/512 frequency-divided clock to the frequency divider 16.

  The frequency divider 16 is supplied with the ni value read from the DV signal by the ni reading / control signal demodulating circuit 44 of the input CH1 audio signal processing circuit 30, and is supplied with 1/512 minutes from the frequency divider 15. The divided clock is further divided by 1 / ni. The 1 / ni divided clock from the frequency divider 16 is sent to the other input terminal of the phase comparator 11.

  The 1/2 frequency-divided clock sent from the frequency divider 14 to the input CH1 audio signal processing circuit 30 is sent to the frequency divider 42 in the input CH1 audio signal processing circuit 30. In this frequency divider 42, the 1/2 frequency divided clock from the frequency divider 14 is further frequency divided by 1/4 to generate the input bit clock BCKi. The input bit clock BCKi is sent to the frequency divider 43 and the deinterleave circuit 41 in the input CH1 audio signal processing circuit 30, and the input CH2 audio signal processing circuit 31, the CH1 sample rate conversion circuit 32, and the CH2 sample rate conversion. It is sent to the circuit 33.

  A frequency divider 43 in the input CH1 audio signal processing circuit 30 further divides the input bit clock BCKi from the frequency divider 42 by 1/64 to generate an input sampling clock LRCKi. The input sampling clock LRCKi is sent to the deinterleave circuit 41 and also sent to the input CH2 audio signal processing circuit 31, the CH1 sample rate conversion circuit 32, and the CH2 sample rate conversion circuit 33.

  On the other hand, the output clock generation circuit 20 includes a phase comparator 21, an integration circuit 22, a voltage controlled oscillator 23, and frequency dividers 24, 25, and 26, to which the frame reference signal is input to one input terminal. The voltage-controlled oscillator 23 generates an output clock signal. This output clock signal is supplied as an output operation reference clock to the CH1 sample rate conversion circuit 32 and the CH2 sample rate conversion circuit 33 and is also sent to the frequency divider 24 and the frequency divider 25.

  The frequency divider 24 divides the output clock signal by half, and sends the 1/2 frequency-divided clock to the output CH1 audio signal processing circuit 34 and the output CH2 audio signal processing circuit 35. The frequency divider 25 divides the input clock signal by 1/512 and sends the 1/512 frequency-divided clock to the frequency divider 26.

  The frequency divider 26 is supplied with the frame reference signal as a no value, and further divides the 1/512 frequency-divided clock from the frequency divider 25 into 1 / no. That is, the no value is a value of the number of samples determined for each mode of the sampling frequency corresponding to the frame reference signal. As shown in FIG. 3, 1601 in the 48 kHz mode of the 525/60 system (NTSC system). .6, and in the 32 kHz mode, the value is 1067.733. In the 48 kHz mode of the 625/50 system (PAL system), the value is 1920, and in the 32 kHz mode, the value is 1280. The 1 / no frequency-divided clock from the frequency divider 26 is sent to the other input terminal of the phase comparator 21 to which the frame reference signal is supplied to one input terminal.

  The 1/2 frequency-divided clock sent from the frequency divider 24 to the output CH1 audio signal processing circuit 34 is sent to the frequency divider 53 in the output CH1 audio signal processing circuit 34. The frequency divider 53 generates an output bit clock BCCo obtained by further dividing the frequency of the 1/2 frequency-divided clock from the frequency divider 24 by 1/4. The output bit clock BCKo is sent to the frequency divider 54 and the interleave circuit 51 in the output CH1 audio signal processing circuit 34, and the output CH2 audio signal processing circuit 35, the CH1 sample rate conversion circuit 32, and the CH2 sample rate conversion circuit. 33.

  The frequency divider 54 in the output CH1 audio signal processing circuit 34 further divides the output bit clock BCCo from the frequency divider 53 by 1/64 to generate an output sampling clock LRCCo. The output sampling clock LRCCo is sent to the interleave circuit 51 and also sent to the output CH2 audio signal processing circuit 35, the CH1 sample rate conversion circuit 32, and the CH2 sample rate conversion circuit 33.

  As described above, in the digital signal conversion apparatus of the present embodiment, the input CH1 audio signal processing circuit 30 and the input CH2 audio signal processing circuit 31, the input rate conversion unit 32i of the CH1 sample rate conversion circuit 32, and the CH2 sample rate. The input rate conversion unit 33i of the conversion circuit 33 operates based on the input clock generated from the input clock generation circuit 10, while the output CH1 audio signal processing circuit 34, the output CH2 audio signal processing circuit 35, and the CH1 sample rate. The output rate conversion unit 32o of the conversion circuit 32 and the output rate conversion unit 33o of the CH2 sample rate conversion circuit 33 operate on the basis of the output clock generated from the frame reference signal by the output clock generation circuit 20, so that Increase in equipment configuration and cost Asynchronous mode DV signal can be converted to synchronous mode DV signal while the rise is suppressed. Also, since conversion from asynchronous mode DV signal to synchronous mode DV signal is not accompanied by digital / analog conversion or analog / digital conversion, distortion and noise do not occur, there is no influence of frequency characteristics, and sound quality deterioration occurs. There is little to do. Furthermore, there are no adverse effects such as changes in the level of the audio signal and level variations.

  In the embodiment described above, the number of channels of the input digital audio signal and various control signals such as the audio mode attached to the audio signal, that is, information indicating on / off of emphasis, stereo / 2 languages, sampling frequency, etc. In this example, the same number of channels and various control signals are automatically added to the output digital audio signal. However, it is added to the output digital audio signal. It is also possible to arbitrarily change the number of channels and various control signals (manual setting change).

  Next, the digital signal conversion apparatus shown in FIG. 1 can be applied to a system having a configuration as shown in FIGS.

  In the first specific configuration shown in FIG. 4, for example, an asynchronous mode DV signal generated by a DV encoder 61 is converted into a synchronous mode DV signal by a signal converter 62 having the configuration of FIG. This is a system for recording on a recording medium by the device 63. That is, in FIG. 4, the DV encoder 61 generates an asynchronous mode DV signal composed of a digital audio signal and a digital video signal in DV format from, for example, analog audio signals and analog video signals of L (left) and R (right) channels. Generate. The signal converter 62 has the configuration shown in FIG. 1 and converts the asynchronous mode DV signal from the DV encoder 61 into a synchronous mode DV signal. The DV signal recording device 63 records the synchronous mode DV signal supplied from the signal conversion device 62 on, for example, a video tape or a disk.

  The second specific configuration shown in FIG. 5 is that an asynchronous mode DV signal reproduced from, for example, a video tape by the DV recording tape reproducing device 64 is converted into a synchronous mode DV signal by the signal converting device 62 having the configuration of FIG. This is a system for converting and recording on a recording medium by the DV signal recording device 63. That is, in FIG. 5, the DV recording tape reproducing device 64 reproduces the asynchronous mode DV signal from the video tape on which the asynchronous mode DV signal is recorded. The signal converter 62 has the configuration shown in FIG. 1, and converts the asynchronous mode DV signal from the DV recording tape reproducing device 64 into a synchronous mode DV signal. The DV signal recording device 63 records the synchronous mode DV signal supplied from the signal conversion device 62 on, for example, a video tape or a disk.

  A third specific configuration shown in FIG. 6 is an apparatus 65 in which the DV recording tape reproducing unit 66 and the signal conversion unit 67 having the configuration shown in FIG. 1 are integrated. That is, in the apparatus 65 shown in FIG. 6, an asynchronous mode DV signal reproduced from, for example, a video tape by a DV recording tape reproducing section 66 provided in the apparatus is converted into a synchronous mode DV signal by a signal converting section 67 in the apparatus. Convert and output to the outside.

  A fourth specific configuration shown in FIG. 7 is an apparatus 68 in which the signal conversion unit 67 and the DV signal recording unit 69 having the configuration shown in FIG. 1 are integrated. That is, in the device 68 shown in FIG. 7, an asynchronous mode DV signal is supplied from the outside to a signal conversion unit 67 provided inside the device, and the signal conversion unit 67 converts the asynchronous mode DV signal into a synchronous mode DV signal. Convert to The synchronous mode DV signal is recorded on, for example, a video tape, a disk or the like by a DV signal recording unit 69 also provided in the apparatus.

  A fifth specific configuration shown in FIG. 8 is an apparatus 70 in which a DV recording tape reproducing unit 66, a signal converting unit 67, and a DV signal recording unit 69 are integrated. That is, in the apparatus 70 shown in FIG. 8, an asynchronous mode DV signal reproduced from, for example, a video tape by a DV recording tape reproducing unit 66 provided in the apparatus is converted into a synchronous mode DV signal by a signal converting unit 67 in the apparatus. Convert. The synchronous mode DV signal generated by the signal converter 67 is recorded on, for example, a video tape or a disk by a DV signal recording unit 69 provided in the apparatus.

  As described above, the digital signal conversion apparatus according to the present embodiment can be used together with the DV signal recording / reproducing apparatus. Therefore, for example, an arbitrary editing operation is performed on the audio signal of the asynchronous mode DV signal, and the post-editing operation is performed. Even when a digital audio signal is recorded on a recording medium together with a digital video signal, the digital video signal and the digital audio signal can be easily synchronized. Since it is possible to match with the delimiter, good editing is possible. As an example of the editing, as described above, editing that gradually narrows down the level of an audio signal already recorded on a recording medium such as a video tape, that is, audio reproduced from a video tape by a preceding head, for example. It is conceivable to edit the signal by multiplying the signal by a digital coefficient that gradually decreases the level, and then multiplexing the signal with the video signal and re-recording it on the video tape by the main head.

1 is a block circuit diagram showing a schematic configuration of a digital signal conversion apparatus according to an embodiment of the present invention. It is a figure used for description of ni value. It is a figure used for description of no value. 1 is a block circuit diagram showing a first specific configuration example of a digital signal converter to which the present invention is applied. It is a block circuit diagram which shows the 2nd specific structural example of the digital signal converter with which this invention was applied. It is a block circuit diagram which shows the 3rd specific structural example of the digital signal converter to which this invention was applied. It is a block circuit diagram which shows the 4th example of a specific structure of the digital signal converter with which this invention was applied. It is a block circuit diagram which shows the 5th example of a specific structure of the digital signal converter with which this invention was applied. It is a figure used for description of the data structure of one video frame in the signal format based on the IEEE1394 standard. It is a figure used for description of the packet structure in the signal format based on the IEEE1394 standard. It is a figure used for description of the frame synchronization in the signal format based on the IEEE1394 standard. 1 is a block circuit diagram showing a schematic configuration of a digital video recorder that records and reproduces a digital video signal and a digital audio signal in a signal format conforming to the IEEE 1394 standard. It is a figure used for format explanation of an audio signal based on IEEE1394 standard. It is a figure used for description of the mode by the difference in the sampling frequency in DV format. It is a figure used for description of the mode by the difference in the sampling frequency in a DVCAM format. It is a figure used for description of the relationship between the sampling frequency of the audio signal in a DVCAM format, and a horizontal video frequency. It is a figure used for description of audio auxiliary data (code information). It is a figure used for description of AF SIZE of channel CH1 and channel CH2.

Explanation of symbols

3 input video signal processing circuit, 4 output video signal processing circuit, 5, 6, 52 multiplexer, 8 microcomputer, 10 input clock generation circuit, 20 output clock generation circuit, 11, 21 phase comparator, 12, 22 integration circuit, 13, 23 Voltage controlled oscillator, 14, 15, 16, 24, 25, 26, 42, 43, 53, 54 Frequency divider, 30 input CH1 audio signal processing circuit, 31 input CH2 audio signal processing circuit, 32 CH1 sample rate Conversion circuit, 33 CH2 sample rate conversion circuit, 34 output CH1 audio signal processing circuit, 35 output CH2 audio signal processing circuit, 41 deinterleave circuit, 44 ni reading / control signal demodulation circuit, 51 interleave circuit

Claims (6)

A signal processing apparatus for receiving data transmitted by multiplexing a digital video signal and a digital audio signal,
The transmitted data is added with a frequency division parameter used when generating a clock necessary for reproducing the digital audio signal and a control signal as auxiliary data for controlling audio signal reproduction. the frequency division parameter and the control signal extraction means for extracting from data received above,
Means for generating the clock by dividing the reference signal required for reproduction of the digital video signal using the frequency division parameter extracted from the extraction means;
Control signal adding means for adding the control signal to the digital audio signal after rate conversion by reading the digital audio signal at the clock ;
The control signal is various control signals attached to the digital audio signal, and includes a signal indicating on / off of emphasis, stereo / 2 languages, and a sampling frequency . A signal processing apparatus for receiving data transmitted by multiplexing a digital video signal and a digital audio signal,
The transmitted data is added with a frequency division parameter used when generating a clock necessary for reproducing the digital audio signal and a control signal as auxiliary data for controlling audio signal reproduction. Extraction means for extracting the frequency division parameter and the control signal from the received data;
Means for generating the clock by dividing the reference signal required for reproduction of the digital video signal using the frequency division parameter extracted from the extraction means;
Control signal adding means for adding the control signal to the digital audio signal after rate conversion by reading the digital audio signal at the clock;
The control signal adding means, the signal processing device that automatically added to the digital audio signal output of the same as the various control signals extracted by the extracting means. A signal processing apparatus for receiving data transmitted by multiplexing a digital video signal and a digital audio signal,
The transmitted data is added with a frequency division parameter used when generating a clock necessary for reproducing the digital audio signal and a control signal as auxiliary data for controlling audio signal reproduction. Extraction means for extracting the frequency division parameter and the control signal from the received data;
Means for generating the clock by dividing the reference signal required for reproduction of the digital video signal using the frequency division parameter extracted from the extraction means;
Control signal adding means for adding the control signal to the digital audio signal after rate conversion by reading the digital audio signal at the clock;
The control signal adding means, the signal processing device you added to the digital audio signals output by setting changed manually various control signals extracted by the extracting means. Receiving data transmitted by multiplexing a digital video signal and a digital audio signal;
The transmitted data is added with a frequency division parameter used when generating a clock necessary for reproducing the digital audio signal and a control signal as auxiliary data for controlling audio signal reproduction ,
The frequency division parameter and the control signal extracted from the data received above,
The clock is generated by dividing the reference signal necessary for reproduction of the digital video signal using the extracted division parameter,
The control signal is added to the digital audio signal after rate conversion by reading the digital audio signal at the clock ,
The control signal is various control signals attached to a digital audio signal, and includes a signal indicating on / off of emphasis, stereo / 2 languages, and a sampling frequency . Receiving data transmitted by multiplexing a digital video signal and a digital audio signal;
The transmitted data is added with a frequency division parameter used when generating a clock necessary for reproducing the digital audio signal and a control signal as auxiliary data for controlling audio signal reproduction,
Extracting the frequency division parameter and the control signal from the received data;
The clock is generated by dividing the reference signal necessary for reproduction of the digital video signal using the extracted division parameter,
The control signal is added to the digital audio signal after rate conversion by reading the digital audio signal at the clock,
Signal processing method that automatically added to the digital audio signal output of the same as the extracted various control signals. Receiving data transmitted by multiplexing a digital video signal and a digital audio signal;
The transmitted data is added with a frequency division parameter used when generating a clock necessary for reproducing the digital audio signal and a control signal as auxiliary data for controlling audio signal reproduction,
Extracting the frequency division parameter and the control signal from the received data;
The clock is generated by dividing the reference signal necessary for reproduction of the digital video signal using the extracted division parameter,
The control signal is added to the digital audio signal after rate conversion by reading the digital audio signal at the clock,
Signal processing how to added to the digital audio signals output by setting changed manually various control signals of the extracted.

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