JP4303170B2 - Wiring design system for multilayer printed wiring boards - Google Patents

Description

  The present invention relates to a multilayer printed wiring board wiring design method and system for performing wiring assignment and the like in a multilayer printed wiring board, and in particular, wiring of a multilayer printed wiring board that requires high-speed and high-density signals of the same type to have the same characteristics. The present invention relates to a design method and a system thereof.

In wiring design of high-speed and high-density printed wiring boards, it is essential to improve signal quality by aligning signal characteristics. Therefore, as a means of aligning the characteristics of the signal as much as possible, the length of the wiring path can be obtained by running the signal wiring paths of the same signal group in parallel with an appropriate interval with respect to a signal group such as a bus wiring whose characteristics should be aligned. And a method of aligning the shapes.
As a means of designing wiring of such a high-speed and high-density printed wiring board, first, determine one of the signal end points between the components to be connected as the start point, and then the start point pin varies, The lead-out wiring paths from the respective pins are determined so that as many signals as possible can be output while considering the balance with the wiring of other signal groups up to a region where the end points of the wiring are arranged on a straight line. Then, while searching for an area that can be wired side by side to the end point, it is drawn close to the end point part. Finally, the wiring design process is completed by connecting the wiring pattern to the end pin.

  In Japanese Patent Laid-Open No. 9-198423, the wiring start coordinates, the wiring target coordinates, and the component terminal coordinates are input, and the coordinates of the component terminals at both ends of the wiring given by the wiring information, the wiring start coordinates of the wiring, and the wiring It is described that the component terminals are divided into the wiring start side group and the wiring target side group according to the end coordinates, the wiring direction is automatically determined from the wiring start side component terminal to the wiring target side component terminal, and automatic wiring is performed. Has been.

JP-A-9-198423

  As a constraint for satisfying the signal transmission characteristics, it may be necessary to create a wiring path that does not use vias at all. Also, because there are many signals in one bus, or because of the increase in the number of LSI pins, the wiring route cannot be all in the printed wiring board layer, and the wiring design is closed unless distributed to multiple wiring layers. It may not be possible. When designing a wiring for such a multilayer printed wiring board with the prior art, first, in order to generate a lead wiring path from pins scattered in the component, the wiring layers for allocating individual signals and the order in which they are arranged are arranged. It is necessary to decide first.

  However, when connecting the wiring pattern to the pins scattered in the end point component, if the position of the pin of each signal and the arrangement order of the wiring are not correct, the wiring pattern will be remarkably long or the wiring route will be Crossing occurs, and wiring paths cannot be generated, and unwired lines appear.

  Also, when considering distribution to multiple layers, it is necessary to consider the wiring paths of other signal groups, so it is necessary to reassign the wiring paths many times in order to find the optimal wiring path. .

  An object of the present invention is to provide a multilayer printed wiring board wiring design method and system capable of greatly reducing the number of wiring design man-hours in order to solve the above problems.

  In order to achieve the above object, according to the present invention, when assigning wiring paths, the paths are determined in units of signal groups that are handled as a group of a plurality of signals (bundle signals such as buses). At this time, without deciding in what order the signals in the signal group in the assigned wiring path are arranged and in which wiring layer the signals included in the signal group are assigned, the number of signals is determined and the number of signals is determined. Reserve space to be allocated. Then, when the wiring area needs to be adjusted in the wiring route assignment processing of another signal group, the number of signals and the wiring area are changed. Then, after the wiring areas of all the signal groups in the printed wiring board are determined, or when the wiring areas of the highly important signal groups are determined, the wiring path assignments and wiring layers of the signals in each signal group gradually. Make an assignment. As a result, it is possible to obtain the optimum drawing-out path from the electronic component such as LSI and the drawing-in path to the electronic component.

  The present invention is also a wiring design method for a multilayer printed wiring board in which wiring paths between electronic components in the multilayer printed wiring board are assigned, and a signal for selecting a signal group to be handled as an aggregate of a plurality of signals between the electronic components. A wiring layer and a signal number determination step for allocating and determining a plurality of wiring layers drawn from the terminal group of the electronic component in the signal group selected by the signal group selection step and the number of signals to be drawn in each wiring layer And calculating the necessary wiring area width in each wiring layer based on the number of signals in each wiring layer assigned and determined in the wiring layer and signal number determination step, and the predetermined signal group of each wiring layer is calculated. The calculated wiring is assumed by assuming a wiring route from the terminal group as the start point to the terminal group as the end point. A wiring area securing step that secures a wiring area corresponding to the area width, and an overlap between a wiring area of a predetermined signal group and a wiring area of another signal group in each wiring layer secured in the wiring area securing step; A wiring region determining step for correcting and determining the wiring region of the predetermined signal group by obtaining the number of signals corresponding to the overlapping region and reassigning it to another wiring layer when overlapping occurs; and the wiring region A signal wiring path determining step for determining a wiring path of each signal connecting between the terminal groups of the electronic components in each wiring layer based on the wiring area in each wiring layer determined in the determining step. And

  Further, according to the present invention, in the signal wiring path determination step, one or a plurality of electronic components are cut out in a peripheral region of each of the electronic components and cut out in the peripheral region on a virtual wiring board. Arrange so that the boundary surfaces of the paired wiring regions face each other, generate a virtual wiring region between the boundary surfaces of the wiring regions arranged to face each other, and generate a virtual wiring in the generated virtual wiring region Determining the lead wiring of each signal from the terminal group of each electronic component to the boundary surface of the wiring area to obtain the wiring path in the peripheral area, and the wiring path in the peripheral area obtained in the step Returning to the wiring area on the original printed wiring board and connecting the wiring in the wiring area between the boundary surfaces of the wiring area.

  According to the present invention, it is not necessary to repeatedly perform wiring design over and over, so that it is possible to significantly reduce the number of wiring design steps.

  DESCRIPTION OF EMBODIMENTS Embodiments of a wiring assignment method and system according to the present invention will be described with reference to the drawings.

  FIG. 1 is a system configuration diagram of a wiring assignment system according to the present invention. The wiring assignment system 101 inputs the board design database 102 in response to a data input instruction from the operation terminal 103 that performs wiring assignment operations and instructions, and signals between electronic components such as LSIs or connection information of signal groups (between terminals). Component information having a signal information table 105 having signal connection information) and information relating to electronic components mounted on the board (information such as shape and size as well as terminal position and number of terminals according to the type of electronic component) A table 106, a board information table 107 having information on the board (information such as board shape and size, electronic component mounting position and wiring layer), and a bus information table 108 having bus information which is a signal having the same characteristics. And a data input processing unit 104 that generates a wiring information table 109 having wiring route information such as existing wiring routes. That. Furthermore, the wiring assignment system 101 first receives information (connection between electronic components) contained in the signal group using the signal information table 105 and the bus information table 108 in response to an instruction of a signal group to which a wiring area is to be assigned from the operation terminal 103. A wiring processing target signal instruction unit 110 for acquiring information and bus information), and acquiring wiring layer information used for assigning a wiring route to a signal group according to an instruction from the operation terminal 103 from the board information table 107; A wiring condition instructing unit 111 for setting the wiring conditions according to the above, a wiring processing target signal instructed by the wiring processing target signal instructing unit 110, a wiring condition instructed by the wiring condition instructing unit 111, and a wiring information table 109. Based on the information on the wiring route and the assigned wiring route, assign a wiring area to each wiring layer for each signal group, and then perform detailed distribution. Allocating a path constituted by a wiring allocation processing section 112 to store the allocation information in the wiring information table 109.

  The data output processing unit 113 repeats the above-described wiring assignment process, acquires the assigned wiring information from the wiring information table 109, and updates the board information database 102.

  FIG. 5 shows an embodiment of a screen for acquiring an input instruction from the operation terminal 103 of the wiring assignment system according to the present invention. In the wiring assignment system, for example, on the screen of the operation terminal 103, an outer window 501 for displaying the outer shape of the printed wiring board and the arrangement of electronic components shown in FIG. 5A, and the printed wiring board shown in FIG. 5B. A signal information window 502 and a bus information window 503 possessed by electronic components mounted on the computer as basic screens. The signal information window 502 and the bus information window 503 have attribute button information 504 for displaying whether the signal or bus is wired, wiring processing target, or unwired.

  The wiring assignment processing target signal instruction unit 110 shown in FIG. 1 instructs a wiring assignment processing target signal by selecting the signal name or bus name displayed in the signal information window 502 or the bus information window 503. The designated wiring assignment processing target signal is displayed as a wiring assignment processing target signal list 506 in the assignment instruction window 505 shown in FIG. The wiring assignment instruction window 505 includes a wiring assignment processing target signal list 506 and a wiring assignment target layer / wiring assignment restriction instruction 507. The wiring assignment target layer / wiring assignment restriction instruction 507 includes a wiring layer name list 508 that can be used on the printed wiring board displayed in the outline window 501, and a wiring assignment target layer instruction button 509 for specifying the wiring assignment target layer. , An allocation number instruction 510 for instructing the number of allocation signals of each wiring allocation target layer, and a wiring allocation constraint instruction button 511 for displaying a wiring allocation constraint instruction window 512 for instructing wiring allocation restrictions.

  The wiring assignment target layer is instructed by the wiring assignment target layer instruction button 509, and the number of assignments is instructed by the assignment number instruction 510, and when not instructed by the assignment number instruction 510, it is automatically determined in the wiring assignment system. When it is necessary to instruct the wiring assignment restriction for the signal to be assigned to the wiring assignment, the wiring assignment restriction instruction window 512 is displayed by pressing the wiring assignment restriction instruction button 511 as shown in FIG. Then, the wiring width, the distance between signals, the distance between signal groups (signal groups), the number of vias (the number of times of crossing between wiring layers), the wiring prohibition information using through holes, etc. are instructed as conditions for the wiring allocation process. .

  FIG. 6 is a diagram for explaining a data structure created when designated as a wiring assignment processing target signal in the wiring assignment system according to the present invention. 1 is based on the signal and bus name instructed from the operation terminal 103 via the signal information window 502 or the bus information window 503 on the screen shown in FIG. With reference to the signal information table 105, a wiring assignment processing target table 601 shown in FIG. 6A and a signal correspondence table 602 shown in FIG. 6B are generated. The generated wiring assignment processing correspondence table 601 is included in the designated section (for example, single, buses 1 to 3) designated in the signal information window 502 or the bus information window 503 and the designated signal or bus. It is formed by storing the number of signals, the head address of the signal correspondence table 602, the head address of the wiring condition table 603 shown in FIG. 6C, and the address of the use layer instruction table 604 shown in FIG. The In the usage layer instruction table 604, the next address after address 3 (Layer 1) is 4 (Layer 2), and the next address after address 4 is 5 (Layer 3). The next address after address 6 is 7, the next address after address 7 is 8, and the next address after address 8 is 9.

  Further, the wiring condition instructing unit 111 in FIG. 1 uses the wiring assignment processing target layer and the wiring designated by the operation terminal 103 via the wiring assignment processing target layer / wiring assignment restriction instruction 507 on the screen shown in FIG. Based on the allocation constraint instruction, the wiring condition table 603 and the use layer instruction table 604 are generated with reference to the board information table 107.

  The names of all signals included in the bus assignment process or the signals included in the bus can be obtained from the signal correspondence table 602 generated as described above, based on the signal correspondence table start address and the number of signals in the wiring assignment process correspondence table 601. it can. Also, the wiring conditions for the wiring assignment process can be obtained from the wiring condition table 603 generated as described above by the wiring condition table address of the wiring assignment processing correspondence table 601. In addition, the wiring assignment target layer can be obtained from the use layer instruction table 604 generated as described above by using the use layer instruction in the wiring assignment processing correspondence table 601.

  As described above, the wiring allocation processing unit 112 sequentially performs the wiring allocation processing using the operation terminal 103 on the signal instructed in the wiring allocation processing correspondence table 601.

  FIG. 2 is a diagram showing a flowchart of sequential wiring assignment processing in the wiring assignment processing unit 112 using the operation terminal 103 according to the present invention. First, in step S201, one of signal groups to which a wiring path is to be assigned is selected for some or all signal groups designated as wiring processing targets. Next, in step S202, a wiring layer to be drawn is determined for the selected signal group. If there is an instruction for the wiring layer, the designated layer is selected. If there is no instruction, the wiring layer is selected from the available wiring layers. Next, the number of signals to be extracted is determined for each of the wiring layers determined in step S202 (S203). If there is an instruction for the number of drawers, the number of instructions is set. Next, in step S204, the necessary wiring area width is calculated from the number of signals determined in step S203 for each wiring. Next, in step S205, a wiring path (wiring shape) from the pin group serving as the start point of the signal group to be processed to the end pin group is assumed in step S205, and the wiring area corresponding to the wiring area width determined in step S204 is determined. Process to secure. Next, in step S206, it is determined whether or not the wiring area secured in step S205 overlaps with another wiring area. If it does not overlap with other wiring areas, the processing from step S215 is continued. If it overlaps with another wiring area, the process proceeds to step S207, and the wiring area shape of the overlapping portion is changed. Then, in step S208, it is determined whether or not the overlapping of the areas has been resolved. If the area has been resolved, the processing is continued from step S215. If the overlap cannot be resolved, the process proceeds to step S209. In step S209, the number of signals corresponding to the overlapping wiring region is obtained. Next, in step S210, it is determined whether or not the number of signals overlapping the other wiring layers of the own signal group can be reassigned. If reallocation is possible, the process proceeds to step S211. In step S211, the number of overlapping signals is reassigned, and the wiring area is changed. If reassignment is not possible, the process proceeds to step S212, and it is determined whether the signal of the partner signal group with which the wiring areas overlap can be reassigned to another wiring layer. If reallocation is possible, the number of signals is reallocated in step S213. If reassignment is not possible in step S212, the process proceeds to step S214, the number of overlaps is not allocated, and the processing from step S215 is continued.

  In step S215, it is determined whether or not there is no unwired in all the signal groups to which a wiring route is to be assigned. If there is no unwired, the process proceeds to step S216. If there is an unwired line, a signal group (wiring group) having the next unassigned signal is selected in step S217, and the process is repeated from step S202. Further, the operations in A to D (A: intermediate progress display / interrupt point, B: intermediate progress display / interrupt point, C: intermediate progress display / interrupt point, D: intermediate progress display / interrupt point) in FIG. An intermediate process is displayed on the terminal 103, the wiring area is corrected on the operation terminal, and the wiring assignment process can be executed again for the remaining unprocessed signals.

  Finally, in step S216, the wiring path of each signal included in each signal group in which a necessary area for wiring is secured is determined, and the wiring assignment process is terminated.

  That is, the wiring assignment method for a multilayer printed wiring board according to the present invention includes a signal group selection step S201 for selecting a signal group to be handled as a group of a plurality of signals (bundle signals such as buses) between electronic components. In the signal group selected in the signal group selection step S201, a plurality of wiring layers drawn from the terminal group (pin group) of the electronic component and the number of signals to be drawn in each wiring layer are assigned and determined. Based on the number of signals in each wiring layer assigned and determined in step S203 and the wiring layer and signal number determination step S203, a necessary wiring area width in each wiring layer is calculated, and a predetermined value is determined in each wiring layer. Assume the wiring path (wiring shape) from the terminal group that is the starting point of the signal group to the terminal group that is the ending point Therefore, the wiring area securing steps S204 and S205 for securing the wiring area for the calculated wiring area width, the wiring area of the predetermined signal group in each wiring layer secured in the wiring area securing steps S204 and S205, and the like. The overlap of the predetermined signal group is corrected by examining the overlap of the signal group with the wiring area, and if the overlap occurs, the number of signals corresponding to the overlap area is obtained and reassigned to another wiring layer. Wiring region determination steps S206 to S211 to be determined (changed) and the wiring regions in the respective wiring layers determined by the wiring region determination steps S206 to S211 are connected to the terminal groups of the electronic components. A signal wiring path determination step S216 for determining a signal wiring path.

  FIG. 3 is a diagram showing an example of changing the wiring layer assignment in S210 and S212 of FIG. 2 showing a flowchart of the wiring assignment process. The printed wiring board 301 includes wiring layers S1, S2, and S3. On top, electronic components 302, 303, 304, and 305 such as LSI are mounted. The electronic components 302 and 303 have a connection request, and are going to perform wiring using the wiring layers S1, S2, and S3. Therefore, in step S205, the wiring region 306 is secured in the wiring layer S1, the wiring region 307 is secured in the wiring layer S2, and the wiring region 309 is secured in the wiring layer S3. However, since there is a wiring region 308 for connecting the electronic component 304 and the electronic component 305 in the wiring layer S2, it is determined in step S206 that the wiring region 307 and the wiring region 308 overlap. At this time, in step S209, the number of signals corresponding to the area where the wiring areas overlap is calculated, and the calculated number of signals is reduced from the wiring area 307 to form the wiring area 312. In steps S210 and S211, the reduced signals are allocated to the wiring regions in the wiring layers S1 and S3, and changed to the wiring region 310 in the wiring layer S1 and the wiring region 313 in the wiring layer S3. Although not shown in FIG. 3, if the number of signals to be reduced (the number of signals corresponding to the overlapping area) cannot be reassigned to another wiring layer in step S210, the process proceeds to step S212. In step S212, it is checked whether or not the signal of the partner signal group (wiring region 307) can be reassigned to another wiring layer. If possible, the number of signals of the partner is reassigned in step S213, which is impossible. In such a case, the number of overlaps is not allocated in step S214.

  FIG. 4 is an explanatory diagram of the wiring route determination S216 in FIG. Next, an embodiment in which a wiring route is determined for signals included in each signal group for each wiring layer will be described. On the printed wiring board 401, there are electronic components 402 to 405, and a wiring region 408 for a signal group between one or a plurality of electronic components 404 and one or a plurality of electronic components 405 that have been assigned a wiring region. At this time, a component peripheral region 406 including one or a plurality of electronic components 404 and a component peripheral region 407 including one or a plurality of electronic components 405 are cut out and extracted. Next, a virtual board (virtual wiring board) 409 is created, and the extracted area 406 and area 407 are arranged thereon. At this time, the wiring region 408 for each wiring layer is cut into the region 406 and the region 407, and the cutting surface of the wiring region 410 in the region 406 and the wiring region in the region 407 are separated for each wiring layer. It arrange | positions so that the cut surface of 412 may face directly. Then, a virtual wiring area 411 is generated between the wiring area 410 and the wiring area 412 for each wiring layer. Thereafter, wiring from the terminal points of the electronic component 404 and the electronic component 405 of the signal included in the signal group to the cut surface (boundary around the component) of the wiring region 410 and to the cut surface (boundary around the component) of the wiring region 412 The wiring path of (drawer wiring) is considered so that the orientation of the electronic components 404 and 405 and the arrangement of the terminal group are in an appropriate state. The connection relationship of signals before the wiring route search is as indicated by 413 and 414, respectively. Further, a virtual wiring 415 is generated in the virtual wiring area 411. The search for the wiring path can be performed by considering a combination of the signal of the connection relation 413 and the signal of the connection relation 414 and the virtual wiring 415. Then, a route (a route satisfying the wiring assignment constraint condition (wiring condition)) in which the wiring route from the terminal point of the wiring region 410 to the cut surface and the wiring route from the terminal point of the wiring region 412 to the cut surface is consistent in each region is searched. Then, the wiring path 416 and the wiring path 417 are obtained. Next, the obtained wiring route 416 and the wiring route 417 are returned to the wiring region in the original printed wiring board 401, and the drawing wiring process is completed from each electronic component 404, 405 to each cut surface (boundary around each component). A printed wiring board 418 is obtained. Finally, by connecting the wires in the wiring region between the cut surfaces cut at both ends so as to satisfy the wiring conditions, a detailed wiring route 419 is obtained and the processing is completed.

  In addition, the wiring assignment system (wiring design system for a multilayer printed wiring board) according to the present invention includes a signal group selection unit that selects a signal group to be handled as an aggregate of a plurality of signals between electronic components, and the signal group selection unit. In the selected signal group, a plurality of wiring layers to be drawn from the terminal group of the electronic component and the number of signals to be drawn in each wiring layer are assigned and determined, and the wiring layer and the signal number determining unit A necessary wiring area width is calculated in each wiring layer based on the number of signals in each wiring layer determined by assignment, and a terminal group that is an end point from a terminal group that is a starting point of a predetermined signal group in each wiring layer A wiring area securing part that secures a wiring area corresponding to the calculated wiring area width by assuming a wiring route up to and including the wiring area securing part Check the overlap between the wiring area of the predetermined signal group and the wiring area of another signal group in each of the secured wiring layers, and if the overlap occurs, obtain the number of signals corresponding to the overlapping area and Based on the wiring region determining unit that corrects and determines the wiring region of the predetermined signal group by reassigning to the layer, and the wiring region in each wiring layer determined by the wiring region determining unit, And a signal wiring path determining unit that determines a wiring path of each signal connecting the terminal groups of the electronic components in the layer. The wiring assignment target signal instruction unit 110 including the operation terminal 103 includes the signal group selection unit, the wiring layer, and the signal number determination unit.

  The wiring assignment processing unit 112 including the operation terminal 103 includes the wiring area securing unit, the wiring area determining unit, and the signal wiring path determining unit. In addition, the signal wiring path determination unit is configured to cut out one or a plurality of electronic components in each of the electronic components in a peripheral region of the electronic component and form a paired wiring region cut out in the peripheral region on the virtual wiring board. By arranging so that the boundary surfaces of the wiring regions face each other, generating virtual wiring regions between the boundary surfaces of the wiring regions arranged to face each other, and generating virtual wirings in the generated virtual wiring regions, respectively A first portion for determining a lead wiring for each signal from a terminal group of the electronic component to a boundary surface of the wiring region to obtain a wiring route in the peripheral region, and wiring in the peripheral region obtained by the first portion And a second portion for connecting the wiring in the wiring area between the boundary surfaces of the wiring area by returning the path to the wiring area in the original printed wiring board.

  Further, the present invention is characterized in that the wiring areas in the respective wiring layers secured by the wiring area securing section and determined by the wiring area determining section are displayed on the screen.

  According to the embodiments described above, it is necessary to create a wiring route that does not use any via as a constraint for satisfying the signal transmission characteristics, the number of signals is large even with one bus, or the number of LSIs is large. Because of the pinning, the wiring route is not all the wiring route in the printed wiring board layer, and when designing the wiring of the multilayer printed wiring board that has to be distributed to multiple wiring layers, the optimal electronic component And a lead-in route to the electronic component can be provided, and it is not necessary to repeatedly perform the wiring design, so that the wiring design man-hour can be greatly reduced.

It is a figure which shows one Embodiment of the system configuration which implement | achieves the wiring allocation method which concerns on this invention. It is a flowchart which shows one Embodiment of the wiring allocation method which concerns on this invention. It is the figure explaining one Example of wiring area correction which concerns on this invention. It is the figure explaining one Example of wiring allocation from the wiring area | region which concerns on this invention. It is the figure explaining one Example of the display screen of the wiring allocation system which concerns on this invention. It is the figure which showed one Example which manages the signal name used as wiring allocation object from the wiring allocation instruction | indication which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Wiring allocation system, 102 ... Board design database, 103 ... Operation terminal, 104 ... Data input processing part, 105 ... Signal information table, 106 ... Component information table, 107 ... Board information table, 108 ... Bus information table, 109 ... Wiring information table, 110... Wiring allocation processing target signal instruction unit, 111... Wiring condition instruction unit, 112 .. wiring allocation processing unit, 113... Data output processing unit, 301 .. printed wiring board, 302 to 305. 313: Wiring area, 401: Printed wiring board (original printed wiring board), 402 to 405 ... Electronic components, 406, 407 ... Area around the parts, 409 ... Virtual board (virtual wiring board), 410, 412 ... Wiring area 411 ... virtual wiring region, 415 ... virtual wiring, 413, 414 ... connection relationship, 416,417 ... wiring via 418: Printed wiring board, 419: Detailed wiring path, 501 ... Outline window, 502 ... Signal information window, 503 ... Bus information window, 504 ... Attribute button information, 505 ... Wiring assignment instruction window, 506 ... Wiring assignment processing target Signal list, 507 ... Wiring assignment target layer / wiring assignment restriction instruction, 508 ... Wiring layer name list, 509 ... Wiring assignment target layer instruction button, 510 ... Assignment number instruction, 511 ... Wiring assignment restriction instruction button, 512 ... Wiring assignment restriction Instruction window, 601... Wiring assignment processing correspondence table, 602... Signal correspondence table, 603 .. wiring condition table, 604.

Claims (2)

A multilayer printed wiring board wiring design system for assigning wiring paths between electronic components in a multilayer printed wiring board,
A signal group selection unit for selecting a signal group to be handled as an aggregate of a plurality of signals between the electronic components;
A wiring layer and a signal number determination unit for allocating and determining a plurality of wiring layers to be extracted from the terminal group of the electronic component in the signal group selected by the signal group selection unit and the number of signals to be extracted in each wiring layer;
A wiring area width required in each wiring layer is calculated based on the number of signals in each wiring layer assigned and determined by the wiring layer and the signal number determining unit, and a starting point of a predetermined signal group in each wiring layer is calculated. A wiring area securing unit that secures a wiring area corresponding to the calculated wiring area width by assuming a wiring path from the terminal group to be a terminal group to be an end point;
The overlap between the wiring area of the predetermined signal group and the wiring area of the other signal group in each wiring layer secured in the wiring area securing unit is checked, and when the overlap occurs, the number of signals corresponding to the overlapping area is calculated. A wiring area determining unit that determines and corrects a wiring area of the predetermined signal group by reassigning to another wiring layer to obtain;
A signal wiring path determining unit that determines a wiring path of each signal connecting between terminal groups of electronic components in each wiring layer based on the wiring area in each wiring layer determined by the wiring area determining unit; ,
The signal wiring path determination unit cuts one or a plurality of electronic components in each of the electronic components in a peripheral region of the electronic component, and a boundary between a pair of wiring regions cut out in the peripheral region on a virtual wiring board By arranging the planes to face each other, generating a virtual wiring area between the boundary surfaces of the wiring areas arranged to face each other, and generating a virtual wiring in the generated virtual wiring area, each electron A first part for determining a lead wiring for each signal from a terminal group of a component to a boundary surface of the wiring area to obtain a wiring path in the peripheral area, and a wiring path in the peripheral area obtained by the first part. A wiring design of a multilayer printed wiring board, comprising: a second portion that returns to the wiring area on the original printed wiring board and connects the wiring in the wiring area between the boundary surfaces of the wiring area System . Further, the secured by the wiring area securing section, of a multilayer printed wiring board according to claim 1, wherein the wiring area, characterized by being configured to display on the display screen in each of the wiring layers determined by the wiring area determination unit Wiring design system.

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