JP4298023B2 - Nitride semiconductor multilayer deposition substrate and method for forming nitride semiconductor multilayer deposition substrate - Google Patents

Nitride semiconductor multilayer deposition substrate and method for forming nitride semiconductor multilayer deposition substrate Download PDF

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JP4298023B2
JP4298023B2 JP32285998A JP32285998A JP4298023B2 JP 4298023 B2 JP4298023 B2 JP 4298023B2 JP 32285998 A JP32285998 A JP 32285998A JP 32285998 A JP32285998 A JP 32285998A JP 4298023 B2 JP4298023 B2 JP 4298023B2
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nitride semiconductor
buffer layer
deposition substrate
semiconductor multilayer
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JP2000133601A (en
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素顕 岩谷
哲也 竹内
浩 天野
勇 赤▲崎▼
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フィリップス ルミレッズ ライティング カンパニー リミテッド ライアビリティ カンパニー
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/32Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/32308Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
    • H01S5/32341Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP
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    • H01L21/02458Nitrides
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    • H01L21/02494Structure
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02612Formation types
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    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Description

【0001】
【産業上の利用分野】
本発明は半導体素子の製造方法に関し、特にIII族窒化物半導体素子の形成に好適な低結晶欠陥密度を有する族窒化物半導体の多層堆積基板あるいは多層膜とそれらの形成方法とに関する。
【0002】
【従来の技術】
従来、III族窒化物半導体(一般構造式はアルミニウムAl,ガリウムGa,インジュウムIn,,窒素N、組成比x、yを用いてAlxGa1−x−yInyNである。)を用いた直接遷移による高効率短波長レーザの発振が報告されている。このようなレーザを形成するための基板は低結晶欠陥密度でなければならないが、III族窒化物半導体のウェーは・サイズは実用に耐えないほど小さく、サファイア、SiC、スピネル、MgO、GaAs、Si等の異種基板にIII族窒化物半導体を堆積した堆積基板が用いられている。
【0003】
ところが、これら異種基板とIII族窒化物半導体間にはかなりの格子不整合や熱膨張係数差がある。たとえば、サファイア基板とIII族窒化物半導体間とには11〜23%の格子不整合と約2×10−6K−1 の熱膨張係数差がある。このため、該異種基板に堆積したIII族窒化物半導体の薄膜あるいは層の結晶性が悪くなり、該薄膜の電気的あるいは光学的特性が悪かった。
【0004】
そこで、堆積基板の結晶性を改善するための試みがおこなわれている。そのなかでも、異種基板上にIII族窒化物半導体の低温堆積緩衝層と単結晶層とを交互に数層エピタキシャル成長させて多層堆積基板を得る方法は有功である。文献により緩衝層はバッファ層とも呼称される。緩衝層には高温成長(単結晶成長温度での成長)された緩衝層も存在するので、単結晶が成長しない温度で形成した緩衝層を低温堆積緩衝層として区別する。
【0005】
特開平4−297023号公報において、中村は基板上に単結晶が成長しない温度で形成したAlxGa1−xN(但しxは1以下で0超過の数)バッファ層上に窒化ガリウム系半導体の単結晶層をするほうが、AlNバッファ層上に窒化ガリウム系半導体の単結晶層を成長するほうが高品質な窒化ガリウム系半導体の単結晶層を得られる旨主張している。
さらに、基板上にGaN薄膜を成長形成する場合、AlNバッファ層を用いるよりGaNバッファ層を用いるほうが、
「▲1▼ 融点が低いので温度上昇しているとき容易に単結晶化しやすい。このため、バッファ層の厚さを、厚くしてもバッファ層としての効果が期待できる。
▲2▼ バッファ層がGaNなので、その上にGaNのエピタキシャル成長層を成長する場合、同一材料の上に同一材料を成長するため結晶性の向上ができる。等の利点があると考えられる。」考察している。
【0006】
特開平9−199759号公報において、赤崎等は異種物質の基板すなわち異種基板上に単結晶が成長しない温度で形成した低温堆積緩衝層、単結晶が成長する温度で形成した単結晶層とを交互に3層以上積層させ、その上に単結晶が成長する温度で目的とするIII族窒化物半導体層を形成する技術を開示している。AlN低温堆積緩衝層(堆積温度400℃、膜厚50nm)とGaN単結晶層(成長温度1150℃、膜厚300nm、但し最上層の膜厚のみ1.5μm)とを交互に3層ずつ積層した実施例を開示している。最上層GaN単結晶層をKOHでエッチングして電子走査顕微鏡で撮影測定したエッチピット密度が、サファイア基板に1層対堆積後は4×107cm−2、3層対堆積した場合で8×105cm-2であった。
【0007】
特願平9−306215号明細書において、天野等は上記赤碕等の方法を改善して、単結晶が成長しない温度で形成した低温堆積緩衝層を昇温結晶化させるようにした。
しかしながら、依然として堆積基板の結晶性を改善することが望まれている。とくに、多層堆積基板における積層限界の把握や多層堆積基板の品質の制御性の向上、多層堆積基板のコスト低減、用途拡大が望まれている。
【0008】
【発明が解決しようとする課題】
したがって、本発明の目的は族窒化物半導体の多層堆積基板あるいは多層薄膜の結晶性を改善することである。
さらに、多層堆積基板の品質制御性を高め、適切な品質の基板を得る方法を提供し従来技術の問題点を解消あるいは軽減することにある。
【0009】
【課題を解決するための手段】
上記課題を解決するため、本発明者等は多層堆積により成長面内の引張歪が増加しクラック発生にいたる機構を解明して発明をなすに至った。
まず、本発明の窒化物半導体多層堆積基板は、窒化物半導体の低温堆積緩衝層とその直上に堆積した窒化物半導体の単結晶層とから成る層対を複数備える多層堆積基板において、少なくとも一つの前記層対の前記単結晶層が該層対の堆積する前記層対の単結晶層に対しその成長面内で圧縮歪側への歪移行をおこなうことを特徴とする。
【0010】
本発明では、前記層対の層対数を3以上に選んで結晶性を改善できるし、さらに層対数を4以上に選んでさらに結晶性を改善できる。だことを特徴とする請求項1に記載の窒化物半導体多層堆積基板。
【0011】
低抵抗化のため少なくとも一の前記層対にドーピングを施すことも有利である。
【0012】
また、連続する5対以上8対以下の前記層対の全てにおいて前記低温堆積緩衝層がGaNで前記単結晶層をGaNとすれば、から成ることを特徴とする請求項1に記載の窒化物半導体多層堆積基板。
【0013】
本発明の方法は、窒化物半導体の低温堆積緩衝層とその直上に堆積した窒化物半導体の単結晶層とから成る層対を複数備える多層堆積基板を形成する方法であって、
一の前記層対に含まれる単結晶層が成長面内の引張歪を生ずる該一の前記層対を設けるステップと、
該一の前記層対に含まれる単結晶層上に堆積される前記層対の単結晶層が成長表面内の沿う圧縮歪を持たせるステップと、
を備えることを特徴とする。
【0014】
前記引張歪と前記圧縮歪の少なくとも一方は、少なくとも常温で観測され得ることを特徴とする請求項11に記載の窒化物半導体多層堆積基板の形成方法。
歪の大きさは格子定数の測定により決定することができる。
【0015】
また、窒化物半導体多層堆積基板窒化物半導体の低温堆積緩衝層とその直上に堆積した窒化物半導体の単結晶層とから成る層対を複数備える多層堆積基板において、少なくとも二種類の前記層対を有し、該二種類の前記層対の一方は他方より層対数が少なくかつ前記少なくとも一つの前記単結晶層を含むように構成することもできる柔軟性を有する。。
【0016】
【発明の実施の形態】
異種基板あるいは同種基板上に単結晶が成長しない温度で形成した低温堆積緩衝層、単結晶が成長する温度で形成した単結晶層とを交互に多層を成長積層させる上記天野等の技術を援用して実験したところ、次のような知見を得た。
【0017】
「実験1」:
図1を参照して「実験1」を説明する。なお図1、図3、図7は多層堆積基板10、30、50の構造を模式的に示すもので、実際の寸法を用いたものではない。
ステップ1:
(基板の洗浄): (0001)C面を備えたサファイア基板(2インチ基板)11をフッ酸および王水にそれぞれ5分間ずつ浸してエッチングを行い、純水にて5分間リンスする。その後、メタノール、アセトンにて5分間ずつ有機洗浄した後、再度純水にて5分間リンスする。
【0018】
ステップ2:
(基板のクリーニング): 上記工程を室温で経たサファイア基板12をMOVPE(有機金属気相成長法)装置の反応炉内に搬送する。反応炉内を窒素にて充分置換して酸素および水分を取り除いた後に、水素を導入して1100℃で10分間サファイア基板の加熱クリーニングを行う。
【0019】
ステップ3:
(GaN低温堆積緩衝層の形成):その後、サファイア基板12の温度を500℃に設定し、TMGa(トリメチルガリウム)とアンモニアを炉内に約3分間供給してサファイア基板12上に30nmのGaN低温堆積緩衝層14を成長させTMGaの供給を停止する。
【0020】
ステップ4:
(n型GaN単結晶層16の形成): GaN低温堆積緩衝層14の成長終了後、サファイア基板12の温度を約3分で1050℃まで上昇させ約5分経過後、TMGa(トリメチルガリウム)とアンモニアを供給してGaN層16の成長を開始する。毎時2.5μmの成長速度で1μm成長したところで、TMGaの供給を止める。またサファイア基板の温度も再度500℃にまで下げる。この間アンモニアの供給は続けたままである。
【0021】
ステップ5:
( GaN低温堆積緩衝層14とGaN単結晶層16の繰り返し形成):前記ステップ3とステップ4とを所望の回数繰り返し、GaN低温堆積緩衝層14とGaN単結晶層16からなる層対を形成する。図1は層対を2対積層したのちの多層堆積基板10の層構成を示す。
ステップ6:
(最上層GaN単結晶層16の成長表面の観察):多層堆積基板10の温度を室温にさげて、炉から取り出し必要な測定をおこなう。測定は微分干渉顕微鏡による表面の観察とX線回折装置による単結晶層の格子定数の測定である。図2に層対の数に伴う最上層GaN単結晶層16の成長表面を微分干渉顕微鏡で観測する。図2の(A)-(E)は層対数がそれぞれ2、3、6,9,12の場合の最上層GaN単結晶層16の成長表面の微分干渉顕微鏡による観測結果の写真である。
【0022】
また、図5には層対数がそれぞれ2、3、6,9,12の場合の最上層GaN単結晶層16のc軸の格子定数の変化がカーブ1としてプロットされている。図5のグラフの横軸は層対数で縦軸は0.1nmを単位としてc軸の格子定数が目盛られている。表面のc軸の格子定数は層対数1では、バルクの格子定数略0.5185nmより大きいが、層対数が2以上ではバルクの格子定数より小さく層対数が大きくなると共に小さくなる。層対数が2以上では成長面内で引張歪が発生していることを示す。層対数が9以上では最上層GaN単結晶層36にクラックが発生し歪が緩和されてc軸の格子定数はバルクの格子定数と等しくなる。c軸の格子定数の増大(引張歪)は面内の格子定数の減少(圧縮歪)をあらわし、c軸の格子定数の増大(引張歪)は面内の格子定数の減少(圧縮歪)をあらわす。
なお、結晶歪は測定された格子定数の値をバルクの格子定数と比べてその大小により引張歪あるいは圧縮歪と呼称されるのであり、相対的な呼称である。バルクの格子定数が異なる値を有することが判明したときは同じ結晶歪でも呼称が変わる可能性もある。
クラックの発生する引張歪は対応する臨界格子定数値を決定して予測できよう。
【0023】
ここで、一の層対の単結晶層の結晶歪が二の層対の単結晶層では量的に変化した場合、”結晶歪の移行”がおきたと称する。すなわち、格子定数が変化したことを意味する。
一の層対の単結晶層の結晶歪が引張歪で二の層対の結晶歪がより大きい引張歪である場合は結晶歪の”引張側への移行”が起きた、という。すなわち、格子定数が大きくなるように変化したことを意味する。
一の層対の単結晶層の結晶歪が引張歪で二の層対の結晶歪がより小さい引張歪である場合は結晶歪の”圧縮側への移行”が起きた、という。すなわち、格子定数が小さくなるように変化したことを意味する。
一の層対の単結晶層の結晶歪が引張歪で二の層対の結晶歪が圧縮歪である場合は結晶歪の”圧縮側への移行”が起きた、という。すなわち、格子定数が小さくなるように変化したことを意味する。
一の層対の単結晶層に圧縮歪がある場合も、上記と同様に”圧縮側への移行”、”引張り側への移行”という。
【0024】
最上層GaN単結晶層16を切り出して薄膜化し透過電子顕微鏡により貫通転位を観察して計数し、その密度である結晶転位密度を測定した。
図6には層対数に対する最上層GaN単結晶層16の表面の結晶転位密度の変化がカーブ1としてプロットされている。図6のグラフの横軸は層対数で縦軸は結晶転位密度を単位:個毎平方cm(cm−2)で1×107cm−2(1E7)から1×1010cm−2(1E10)までを対数目盛で目盛ったものである。層対数の増加にしたがって結晶転位密度は単調に減少する。
なお、特開平9−199759号公報において、赤崎等が測定して報告したエッチピット密度とここでいう結晶転位密度は異なるものであることに留意したい。
【0025】
「実験2」:
図3に層対数が2の場合をしめした多層堆積基板30を基板12と同様の基板32から形成した。そのため、前記「実験1」の一部ステップ3をAlN低温堆積緩衝層34を形成するためにステップ3mに変更して「実験2」をおこなった。
ステップ3m:
(AlN低温堆積緩衝層34の形成):その後、サファイア基板32の温度を500℃に設定しTMAl(トリメチルアルミニウム)とアンモニアを炉内に約3分間供給してサファイア基板32上に30nmのAlN低温堆積緩衝層34を成長させる。
【0026】
図4の(A)−(E)は層対数がそれぞれ2、3、6,9,12の場合の最上層GaN単結晶層36の表面の微分干渉顕微鏡による観測結果である。いずれの場合もクラックの発生が見られない。また、図5には層対数がそれぞれ2、3、6,9,12の場合の最上層GaN単結晶層16の表面のc軸の格子定数の変化がカーブ2としてプロットされている。格子定数は略0.5188nmで一定で、バルクの格子定数略0.5185nmより大きい。これは最上層GaN単結晶層16の成長表面方向で圧縮歪が発生していることを示す。
図6には層対数に対する最上層GaN単結晶層36の表面の結晶転位密度の変化がカーブ2としてプロットされている。「実験2」においても層対数の増加にしたがって結晶転位密度は減少する。
【0027】
「実験3」:
図7に示すように、基板12と同様の基板52上に「実験1」のステップ1−からステップ5を用いてGaN低温堆積緩衝層54とGaN単結晶層56の層対を3対成長させた後、「実験2」のステップ3mと「実験1」のステップ4とによりAlN低温堆積緩衝層55とGaN単結晶層56の層対を1対成長させ、多層堆積基板50を形成した。
【0028】
図8は最上層GaN単結晶層56の表面の微分干渉顕微鏡による観測結果である。AlN低温堆積緩衝層55とGaN単結晶層56の層対の効果は、最上層GaN単結晶層56の成長表面のc軸の格子定数が0.5188nmに復帰する点と結晶転位密度の減少である。
上記多層堆積基板50上に「実験1」のステップ1−からステップ5を用いてGaN低温堆積緩衝層54とGaN単結晶層56の層対をさらに成長させてクラックなしで結晶転位密度のさらに減少した多層堆積基板を得ることもできる。
【0029】
「考察」:
したがって、特開平4−297023号公報において、中村が指摘したように「 ▲2▼ バッファ層がGaNなので、その上にGaNのエピタキシャル成長層を成長する場合、同一材料の上に同一材料を成長するため結晶性の向上ができる。」としても、「実験1」で明らかになったように、クラック発生により多層堆積基板10は層対数に上限がある。その上限は控えめにみて6、大きくとも8と観てとれる。なお、従来技術の実施例では明確でなかった4層対以上でも上限まではクラック発生なしに堆積できることがわかる。また、図6に観るように上記中村の指摘は層対数1では実証されなかった。
さらに、バッファ層がGaNでなくとも層対数を大きくして結晶欠陥を減らせることがわかる。
【0030】
また、層対数2以上では層対数にたいする結晶転位密度の減少割合の平均はGaN低温堆積緩衝層でもAlN低温堆積緩衝層でも同程度であるが、GaN低温堆積緩衝層を用いた場合に層対の抵抗が小さくできるの点、Al消費がない点が好ましい。したがって、最上層対のみAlN低温堆積緩衝層とする構成や、AlN低温堆積緩衝層に代えてAlNモル分率5%以上90%以下、好もしくは10%以上50%以下程度のAlGaN低温堆積緩衝層をもちいる構成も層対の抵抗を小さくする要請と引張歪側への歪移行を大きくする要請とを案配できるの点で有利である。さらに、最上層対が必ずしも成長面内の圧縮歪を有する構成にする必要はなく、堆積多層基板の用途に応じて最上単結晶層にクラックの生じない範囲で層対を選択すればよい。
開始基板もサファイア基板のみでなくSiC、Si, MgAl2O4基板、AlGaN薄膜又は基板等の上に成長できるので素子特性とコストの案配が可能である。
【0031】
したがって成長堆積する層対の数を増加させて結晶転位密度を低減するため、クラックを生じない層対を選択するか、クラックの生じる前に圧縮歪を生じるか引張歪を減少させる層対を導入するかをおこなう方法と、そのようにして構成された多層堆積基板が本発明に基づくといえる。
【0032】
図5に示すようにクラックが入らない限りはバッファ層の回数が増えるに従って転移密度が減少することもわかっている。以上のように、用いる低温堆積緩衝層の材料を選択することでクラックの発生なしにこの層の回数を任意に選べる、すなわち任意の転位密度の基板を手に入れることができる。
【0033】
「実験の別実施例」
ところで、本願出願人が平成10(1998)年10月16日提出の特許出願:「窒化物半導体レーザ素子」の明細書に記載された本発明の発明者等である竹内等の発明(以下「竹内等の発明」と称する。)では、(0001)C面を備えたサファイア基板上にAlN低温堆積緩衝層と、n型GaN層と、AlGaN低温堆積緩衝層と、n型AlGaNクラッド層を堆積して窒化物半導体レーザ素子を構成している。
該竹内等の発明と前記「考察」に基づき種々の実験と考察がおこなわれた。
【0034】
(ドーピング)
各層対の抵抗率を低減するためドーピングを施すことが有利である。 さらに前記低温堆積緩衝層と前記窒化物半導体単結晶層とに同種のドーパントをドープすれば低温堆積緩衝層に関する抵抗率を低減することができる。
前記低温堆積緩衝層により多くのドーピングをおこない低温堆積緩衝層の抵抗率の低下を促進するのがよい場合が多い。
n型ドーパントとしてはSi、Ge,などが、p型ドーパントとしてMg、Zn, Beがもちいられ、特にSiやMgは低抵抗化の効果と技術的に成熟した技法が適用できるのでこのましい。Siの濃度を高く選べばn型GaN層の比抵抗は低くなるが結晶性が劣化する。また、Siの場合と同様にMgの濃度も高すぎれば結晶性を劣化させうるので注意が必要である。
【0035】
n型AlN低温堆積緩衝層34,55の形成をおこなうには上記ステップ3mにおいてTMAl(トリメチルアルミニウム)、アンモニウムと同時にシランを供給してSiを濃度5x1017〜5x1019cm-3程の範囲でドープするのがよい。一例では5×1018cm−3とした。
n型GaN単結晶層16,36,56やn型GaN低温堆積緩衝層14、54の成長は上記ステップ4やステップ3において、TMGa(トリメチルガリウム)、アンモニアと同時にシランを供給してSiをドープする。濃度は2×1018cm−3を中心に5×1017cm−3から1×1019cm−3の範囲で選ばれる。一例ではドーパントSiの濃度は2×1018cm−3である。
【0036】
また、p型AlN低温堆積緩衝層34,55の形成では、上記ステップ3mにおいてTMAl(トリメチルアルミニウム)、アンモニウムと同時Cp2Mg(ビスシクロペンタジエニルマグネシウム)を供給してMgを濃度1x1018〜5x1020cm-3の範囲でドープする。いちれいでは、約1x1020cm-3のが好ましい。Siの場合と同様にMgの濃度も高すぎれば結晶性を劣化させうるので注意が必要である。
p型GaN単結晶層16,36,56やp型GaN低温堆積緩衝層14、54の成長は上記ステップ4やステップ3において、TMGa(トリメチルガリウム)、アンモニアと同時にCp2Mg(ビスシクロペンタジエニルマグネシウム)を供給してMgを濃度1x1018〜1x1020cm-3の範囲でドープする。いちれいでは、約5x1019cm-3のが好ましい。
【0037】
(低温堆積緩衝層または単結晶層の組成と膜厚)
層対を構成する低温堆積緩衝層の組成は上記圧縮歪を導入できるためにはAlGaN三元化合物でよくAlNモル分率5%以上好ましくは10%以上であれば良いことが判明した。低温堆積緩衝層の抵抗率を小さく保ちたい用途ではAlNモル分率を50%以下に更には抵抗率がかなり重要なら約10%に選ぶのがよい。
低温堆積緩衝層の膜厚は、緩衝効果が安定して得られる所定値以上で、かつ、それ自身および窒化物半導体単結晶層の結晶品質が良好に保たれるように別の所定値以下であるのがこのましい。したがって、該膜厚は2nm以上100nm以下が好ましく、さらにいえば10nm〜50nmのとするのがよい。堆積温度は300℃から700℃の範囲で選択する。
【0038】
単結晶層もGaN層に限らずAlGaN三元化合物層であってもよい。前記竹内等の発明でもAlGaN三元化合物の低温堆積緩衝層上にAlGaN三元化合物の単結晶層を堆積している。
また単結晶層の膜厚は0.1μm〜3μmの範囲が好ましい。薄ければ製造時間が短く有利であるが、薄すぎれば結晶性が劣化する。成長温度は1000℃〜1200℃の範囲で選択する。
【0039】
(成長方法)
上記実験例では専らMOVPE(有機金属気相成長法)装置によった。他の装置により本発明をなすに困難性はないと思料するが、技術の成熟度、操作性、コストを考えるとMOVPE(有機金属気相成長法)装置を使用するのがこのましい。
【0040】
(製造容易性)
前記引張歪と前記圧縮歪とは、少なくとも常温での格子定数測定で観測され得るので量産製造時に抜き取り検査をおこなう場合に格子定数を測定して製造工程の安定性を短時間で測定できるので製造コストの低減に資する。
【0041】
【発明の効果】
本発明の実施により格子欠陥の少ない多層基板が形成できるので、レーザダイオード等の光素子のみならず、多くのIII族窒化物半導体を用いた素子構造、特性の向上がはかられる。
これらの素子を非限定的に例示すれば、AlGaN/GaN変調ドープ電界効果トランジスタ、リッジ導波レーザダイオード、pn接合型PD(光検出ダイオード)、AlN/GaN半導体多薄膜反射膜、AlN/GaNサブバンド間遷移デバイスなどである。
【図面の簡単な説明】
【図1】サファイア基板にGaN低温堆積緩衝層とGaN単結晶層からなる層対を2対堆積した多層堆積基板10の構造図である。
【図2】サファイア基板にGaN低温堆積緩衝層とGaN単結晶層からなる層対を堆積した多層堆積基板の最上層GaN単結晶層の表面の微分干渉顕微鏡による写真である。
【図3】サファイア基板にAlN低温堆積緩衝層とGaN単結晶層からなる層対を2対堆積した多層堆積基板30の構造図である。
【図4】サファイア基板にAlN低温堆積緩衝層とGaN単結晶層からなる層対を堆積した多層堆積基板の最上層GaN単結晶層の表面の微分干渉顕微鏡による写真である。
【図5】多層堆積基板の層対数に対する最上層GaN単結晶層の表面のc軸の格子定数の変化を示すグラフである。
【図6】多層堆積基板の層対数に対する最上層GaN単結晶層の表面の格子転位密度の変化を示すグラフである。
【図7】サファイア基板にGaN低温堆積緩衝層とGaN単結晶層の層対を3対成長させた後、AlN低温堆積緩衝層とGaN単結晶層の層対を1対成長させて形成した多層堆積基板50の構造図である。
【図8】図7の多層堆積基板50の最上層GaN単結晶層の表面の微分干渉顕微鏡による写真である。
【符号の説明】
10、30、50 多層堆積基板、
12、32、52 サファイア基板
14、54 GaN低温堆積緩衝層
16、36、56 GaN単結晶層
34、55 AlN低温堆積緩衝層
[0001]
[Industrial application fields]
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a multilayer deposited substrate or multilayer film of a group nitride semiconductor having a low crystal defect density suitable for forming a group III nitride semiconductor device, and a method for forming them.
[0002]
[Prior art]
Conventionally, high efficiency by direct transition using a group III nitride semiconductor (general structural formula is AlxGa1-xyInyN using aluminum Al, gallium Ga, indium In, nitrogen N, composition ratio x, y) Short wavelength laser oscillation has been reported. The substrate for forming such a laser must have a low crystal defect density, but the group III nitride semiconductor has a size that is small enough to withstand practical use, sapphire, SiC, spinel, MgO, GaAs, Si For example, a deposition substrate in which a group III nitride semiconductor is deposited on a different kind of substrate is used.
[0003]
However, there are considerable lattice mismatches and thermal expansion coefficient differences between these dissimilar substrates and Group III nitride semiconductors. For example, there is a 11-23% lattice mismatch and a thermal expansion coefficient difference of about 2 × 10 −6 K−1 between the sapphire substrate and the group III nitride semiconductor. For this reason, the crystallinity of the thin film or layer of the group III nitride semiconductor deposited on the dissimilar substrate deteriorated, and the electrical or optical characteristics of the thin film deteriorated.
[0004]
Therefore, attempts have been made to improve the crystallinity of the deposited substrate. Among them, a method of obtaining a multilayer deposition substrate by epitaxially growing several layers of a low temperature deposition buffer layer and a single crystal layer of a group III nitride semiconductor alternately on a different substrate is effective. In the literature, the buffer layer is also referred to as the buffer layer. Since the buffer layer also includes a buffer layer grown at a high temperature (growth at a single crystal growth temperature), the buffer layer formed at a temperature at which the single crystal does not grow is distinguished as a low temperature deposition buffer layer.
[0005]
In Japanese Patent Laid-Open No. 4-297030, Nakamura describes a single crystal layer of a gallium nitride semiconductor on an AlxGa1-xN (where x is 1 or less and greater than 0) buffer layer formed at a temperature at which the single crystal does not grow on the substrate. It is claimed that a higher quality gallium nitride semiconductor single crystal layer can be obtained by growing a single crystal layer of gallium nitride semiconductor on the AlN buffer layer.
Furthermore, when growing a GaN thin film on a substrate, it is better to use a GaN buffer layer than to use an AlN buffer layer.
“(1) Since the melting point is low, it is easy to crystallize easily when the temperature rises. Therefore, even if the thickness of the buffer layer is increased, the effect as the buffer layer can be expected.
(2) Since the buffer layer is GaN, when an epitaxial growth layer of GaN is grown thereon, the same material is grown on the same material, so that the crystallinity can be improved. It is thought that there are advantages such as. ”
[0006]
In Japanese Patent Laid-Open No. 9-199759, Akasaki et al. Alternated a substrate of a different material, that is, a low-temperature deposition buffer layer formed at a temperature at which the single crystal does not grow on the heterogeneous substrate and a single crystal layer formed at a temperature at which the single crystal grows. Discloses a technique in which three or more layers are stacked and a target group III nitride semiconductor layer is formed at a temperature at which a single crystal grows thereon. Three layers of AlN low temperature deposition buffer layers (deposition temperature 400 ° C., film thickness 50 nm) and GaN single crystal layers (growth temperature 1150 ° C., film thickness 300 nm, but only the uppermost film thickness is 1.5 μm) are laminated alternately. Examples have been disclosed. Etch pit density measured by electron scanning microscope after etching the top GaN single crystal layer with KOH is 4 × 10 7 cm −2 after deposition of one layer on the sapphire substrate, and 8 × 10 5 cm −3 when three layers are deposited. 2.
[0007]
In the specification of Japanese Patent Application No. 9-306215, Amano et al. Improved the above-mentioned method of red coral and the like so that a low temperature deposition buffer layer formed at a temperature at which a single crystal does not grow is subjected to temperature crystallization.
However, it is still desirable to improve the crystallinity of the deposited substrate. In particular, it is desired to grasp the stacking limit of the multilayer deposition substrate, improve the controllability of the quality of the multilayer deposition substrate, reduce the cost of the multilayer deposition substrate, and expand the application.
[0008]
[Problems to be solved by the invention]
Accordingly, an object of the present invention is to improve the crystallinity of a multilayer nitride substrate or multilayer thin film of a group nitride semiconductor.
Furthermore, it is to improve the quality controllability of the multi-layer deposition substrate, provide a method for obtaining a substrate of appropriate quality, and eliminate or reduce the problems of the prior art.
[0009]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present inventors have clarified the mechanism by which the tensile strain in the growth surface is increased by the multi-layer deposition and leads to the generation of cracks, and have made the invention.
First, a nitride semiconductor multilayer deposition substrate according to the present invention is a multilayer deposition substrate including a plurality of layer pairs each including a low-temperature deposition buffer layer of nitride semiconductor and a single crystal layer of nitride semiconductor deposited immediately above the nitride semiconductor multilayer deposition substrate. The single crystal layer of the layer pair performs strain transfer to the compressive strain side in the growth plane with respect to the single crystal layer of the layer pair deposited by the layer pair.
[0010]
In the present invention, the crystallinity can be improved by selecting the number of layer pairs of 3 or more, and the crystallinity can be further improved by selecting the number of layer pairs of 4 or more. The nitride semiconductor multilayer deposition substrate according to claim 1, wherein:
[0011]
It is also advantageous to dope at least one of the layer pairs to reduce resistance.
[0012]
2. The nitride according to claim 1, wherein the low temperature deposition buffer layer is GaN and the single crystal layer is GaN in all of the layer pairs of 5 to 8 pairs in succession. Semiconductor multilayer deposition substrate.
[0013]
The method of the present invention is a method of forming a multi-layer deposition substrate comprising a plurality of layer pairs consisting of a nitride semiconductor low temperature deposition buffer layer and a nitride semiconductor single crystal layer deposited directly thereon.
Providing the one layer pair in which a single crystal layer included in the one layer pair generates a tensile strain in a growth plane;
The single crystal layer of the layer pair deposited on the single crystal layer included in the one layer pair has compressive strain along the growth surface;
It is characterized by providing.
[0014]
The method for forming a nitride semiconductor multilayer deposition substrate according to claim 11, wherein at least one of the tensile strain and the compressive strain can be observed at least at room temperature.
The magnitude of strain can be determined by measuring the lattice constant.
[0015]
Further, in a multilayer deposition substrate comprising a plurality of layer pairs each comprising a nitride semiconductor low temperature deposition buffer layer and a nitride semiconductor single crystal layer deposited immediately above the nitride semiconductor multilayer deposition substrate, at least two types of the layer pairs are provided. And one of the two types of layer pairs has less flexibility than the other and can be configured to include the at least one single crystal layer. .
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Utilizing the above-mentioned technologies such as Amano, where a low temperature deposition buffer layer formed at a temperature at which a single crystal does not grow on a heterogeneous substrate or the same type substrate and a single crystal layer formed at a temperature at which the single crystal grows are alternately grown. As a result of experiments, the following findings were obtained.
[0017]
Experiment 1”:
Experiment 1” will be described with reference to FIG. 1, 3, and 7 schematically show the structures of the multilayer deposition substrates 10, 30, and 50, and do not use actual dimensions.
Step 1:
(Washing of substrate): A sapphire substrate (2-inch substrate) 11 having a (0001) C surface is etched by immersing it in hydrofluoric acid and aqua regia for 5 minutes each and rinsed with pure water for 5 minutes. Then, after organic washing with methanol and acetone for 5 minutes each, rinsing again with pure water for 5 minutes.
[0018]
Step 2:
(Substrate cleaning): The sapphire substrate 12 that has undergone the above steps at room temperature is transferred into a reaction furnace of a MOVPE (metal organic chemical vapor deposition method) apparatus. After sufficiently replacing the inside of the reaction furnace with nitrogen to remove oxygen and moisture, hydrogen is introduced and the sapphire substrate is heated and cleaned at 1100 ° C. for 10 minutes.
[0019]
Step 3:
(Formation of GaN low temperature deposition buffer layer): Thereafter, the temperature of the sapphire substrate 12 is set to 500 ° C., TMGa (trimethylgallium) and ammonia are supplied into the furnace for about 3 minutes, and the GaN low temperature of 30 nm is formed on the sapphire substrate 12. The deposition buffer layer 14 is grown and the supply of TMGa is stopped.
[0020]
Step 4:
(Formation of n-type GaN single crystal layer 16): After the growth of the GaN low-temperature deposition buffer layer 14, the temperature of the sapphire substrate 12 is increased to 1050 ° C. in about 3 minutes, and after about 5 minutes, TMGa (trimethylgallium) and Ammonia is supplied to start the growth of the GaN layer 16. When 1 μm is grown at a growth rate of 2.5 μm per hour, the supply of TMGa is stopped. The temperature of the sapphire substrate is also lowered to 500 ° C. During this time, the supply of ammonia continued.
[0021]
Step 5:
(Repeated formation of GaN low temperature deposition buffer layer 14 and GaN single crystal layer 16): Step 3 and step 4 are repeated a desired number of times to form a layer pair consisting of the GaN low temperature deposition buffer layer 14 and the GaN single crystal layer 16. . FIG. 1 shows a layer structure of a multilayer deposition substrate 10 after two pairs of layers are stacked.
Step 6:
(Observation of the growth surface of the uppermost GaN single crystal layer 16): The temperature of the multilayer deposition substrate 10 is lowered to room temperature, and the necessary measurements are taken out from the furnace. The measurement is the observation of the surface with a differential interference microscope and the measurement of the lattice constant of the single crystal layer with an X-ray diffractometer. In FIG. 2, the growth surface of the uppermost GaN single crystal layer 16 according to the number of layer pairs is observed with a differential interference microscope. 2A to 2E are photographs of observation results of the growth surface of the uppermost GaN single crystal layer 16 when the number of layer pairs is 2, 3, 6, 9, and 12, respectively, using a differential interference microscope.
[0022]
Also, in FIG. 5, changes in the c-axis lattice constant of the uppermost GaN single crystal layer 16 when the number of layer pairs is 2, 3, 6, 9, 12 are plotted as curve 1. The horizontal axis of the graph of FIG. 5 is the number of layer pairs, and the vertical axis is the c-axis lattice constant in units of 0.1 nm. The c-axis lattice constant of the surface is larger than the bulk lattice constant of about 0.5185 nm when the layer pair number is 1, but when the layer pair number is 2 or more, the lattice constant is smaller than the bulk lattice constant and becomes smaller as the layer pair number becomes larger. If the number of layer pairs is 2 or more, it indicates that tensile strain is generated in the growth plane. If the number of layer pairs is 9 or more, cracks are generated in the uppermost GaN single crystal layer 36, the strain is relaxed, and the c-axis lattice constant becomes equal to the bulk lattice constant. An increase in c-axis lattice constant (tensile strain) indicates a decrease in in-plane lattice constant (compressive strain), and an increase in c-axis lattice constant (tensile strain) indicates a decrease in in-plane lattice constant (compressive strain). Show.
The crystal strain is a relative name because the measured lattice constant value is referred to as tensile strain or compressive strain depending on the magnitude of the lattice constant compared to the bulk lattice constant. When the bulk lattice constants are found to have different values, the designation may change even with the same crystal strain.
The tensile strain at which cracks occur can be predicted by determining the corresponding critical lattice constant value.
[0023]
Here, when the crystal strain of the single crystal layer of one layer pair changes quantitatively in the single crystal layer of the second layer pair, it is referred to as “transition of crystal strain”. That is, the lattice constant has changed.
When the crystal strain of the single crystal layer of one layer pair is the tensile strain and the crystal strain of the second layer pair is a larger tensile strain, it is said that the crystal strain has “shifted to the tensile side”. That is, it means that the lattice constant has changed so as to increase.
When the crystal strain of the single crystal layer of one layer pair is the tensile strain and the crystal strain of the second layer pair is a smaller tensile strain, it is said that the crystal strain has “shifted to the compression side”. That is, it means that the lattice constant is changed so as to be small.
When the crystal strain of the single crystal layer of one layer pair is the tensile strain and the crystal strain of the second layer pair is the compressive strain, it is said that the crystal strain has “shifted to the compression side”. That is, it means that the lattice constant is changed so as to be small.
Even when a single crystal layer of one layer pair has a compressive strain, it is referred to as “transition to the compression side” and “transition to the tension side” as described above.
[0024]
The uppermost GaN single crystal layer 16 was cut and thinned to observe and count threading dislocations with a transmission electron microscope, and the crystal dislocation density, which is the density, was measured.
In FIG. 6, the change in crystal dislocation density on the surface of the uppermost GaN single crystal layer 16 with respect to the number of layer pairs is plotted as curve 1. The horizontal axis of the graph of FIG. 6 is the logarithm of the layer, and the vertical axis is the crystal dislocation density in units of square cm (cm−2) per unit from 1 × 10 7 cm −2 (1E7) to 1 × 1010 cm −2 (1E10). It is a scale. As the number of layer pairs increases, the crystal dislocation density decreases monotonously.
It should be noted that the etch pit density measured and reported by Akasaki et al. In JP-A-9-199759 differs from the crystal dislocation density here.
[0025]
Experiment 2”:
A multilayer deposition substrate 30 shown in FIG. 3 where the number of layer pairs is 2 was formed from a substrate 32 similar to the substrate 12. Therefore, “Experiment 2” was performed by changing Step 3 of “Experiment 1” to Step 3 m in order to form the AlN low temperature deposition buffer layer 34.
Step 3m:
(Formation of the AlN low temperature deposition buffer layer 34): Thereafter, the temperature of the sapphire substrate 32 is set to 500 ° C., TMAl (trimethylaluminum) and ammonia are supplied into the furnace for about 3 minutes, and the AlN low temperature of 30 nm is formed on the sapphire substrate 32. A deposition buffer layer 34 is grown.
[0026]
4A to 4E are observation results of the surface of the uppermost GaN single crystal layer 36 when the number of layer pairs is 2, 3, 6, 9, and 12, respectively, using a differential interference microscope. In either case, no cracks are observed. Also, in FIG. 5, changes in the c-axis lattice constant of the surface of the uppermost GaN single crystal layer 16 when the number of layer pairs is 2, 3, 6, 9, 12 are plotted as curve 2. The lattice constant is constant at about 0.5188 nm and is larger than the bulk lattice constant of about 0.5185 nm. This indicates that compressive strain is generated in the growth surface direction of the uppermost GaN single crystal layer 16.
In FIG. 6, the change in the crystal dislocation density on the surface of the uppermost GaN single crystal layer 36 with respect to the number of layer pairs is plotted as curve 2. Also in “Experiment 2”, the crystal dislocation density decreases as the number of layer pairs increases.
[0027]
Experiment 3”:
As shown in FIG. 7, three pairs of a GaN low temperature deposition buffer layer 54 and a GaN single crystal layer 56 are grown on a substrate 52 similar to the substrate 12 using Step 1 to Step 5 of “Experiment 1”. Thereafter, a pair of AlN low-temperature deposition buffer layer 55 and GaN single crystal layer 56 was grown in Step 3m of “Experiment 2” and Step 4 of “Experiment 1” to form a multilayer deposition substrate 50.
[0028]
FIG. 8 shows the result of observation of the surface of the uppermost GaN single crystal layer 56 by a differential interference microscope. The effect of the layer pair of the AlN low temperature deposition buffer layer 55 and the GaN single crystal layer 56 is that the c-axis lattice constant of the growth surface of the uppermost GaN single crystal layer 56 returns to 0.5188 nm and the crystal dislocation density decreases. is there.
Further growth of the GaN low-temperature deposition buffer layer 54 and the GaN single crystal layer 56 on the multilayer deposition substrate 50 using Step 1 to Step 5 of “Experiment 1” further reduces the crystal dislocation density without cracks. It is also possible to obtain a multilayer deposited substrate.
[0029]
"Discussion":
Therefore, as pointed out by Nakamura in Japanese Patent Laid-Open No. 4-297023, “(2) Since the buffer layer is GaN, when an epitaxial growth layer of GaN is grown thereon, the same material is grown on the same material. As can be seen from “Experiment 1”, the multilayer deposited substrate 10 has an upper limit in the number of layer pairs due to the occurrence of cracks. The upper limit can be taken to be modest and 6 at most. It can be seen that even four pairs or more, which were not clear in the prior art, can be deposited without cracking up to the upper limit. In addition, as seen in FIG. 6, Nakamura's indication was not verified with a layer pair number of 1.
Further, it can be seen that even if the buffer layer is not GaN, the number of layer pairs can be increased to reduce crystal defects.
[0030]
In addition, when the number of layer pairs is 2 or more, the average rate of decrease in crystal dislocation density with respect to the number of layer pairs is the same in both the GaN low temperature deposition buffer layer and the AlN low temperature deposition buffer layer. It is preferable that the resistance can be reduced and that there is no Al consumption. Therefore, only the uppermost layer pair has an AlN low temperature deposition buffer layer, or an AlN low temperature deposition buffer layer with an AlN molar fraction of 5% to 90%, preferably 10% to 50%, instead of the AlN low temperature buffer layer. This configuration is advantageous in that a request for reducing the resistance of the layer pair and a request for increasing the strain transfer to the tensile strain side can be arranged. Furthermore, the uppermost layer pair does not necessarily have to have a compressive strain in the growth plane, and the layer pair may be selected in a range in which no crack occurs in the uppermost single crystal layer according to the use of the deposited multilayer substrate.
Since the starting substrate can be grown not only on the sapphire substrate but also on a SiC, Si, MgAl2O4 substrate, an AlGaN thin film, or a substrate, device characteristics and cost can be arranged.
[0031]
Therefore, in order to increase the number of layer pairs to be deposited and reduce the crystal dislocation density, select layer pairs that do not generate cracks, or introduce layer pairs that generate compressive strain or reduce tensile strain before cracks occur. It can be said that the method of doing this and the multilayer deposition substrate constructed in this way are based on the present invention.
[0032]
As shown in FIG. 5, it is also known that the dislocation density decreases as the number of buffer layers increases as long as cracks do not occur. As described above, by selecting the material of the low temperature deposition buffer layer to be used, the number of layers can be arbitrarily selected without generation of cracks, that is, a substrate having an arbitrary dislocation density can be obtained.
[0033]
“Another Example of Experiment”
By the way, the patent application filed on October 16, 1998 by the applicant of the present application: Inventions of Takeuchi et al. (Hereinafter referred to as “the inventors of the present invention” described in the specification of “nitride semiconductor laser device”). "Invention of Takeuchi et al.") Deposited an AlN low temperature deposition buffer layer, an n-type GaN layer, an AlGaN low temperature deposition buffer layer, and an n-type AlGaN cladding layer on a sapphire substrate with a (0001) C plane. Thus, a nitride semiconductor laser element is configured.
Various experiments and considerations were made based on the invention of Takeuchi et al.
[0034]
(doping)
Doping is advantageous to reduce the resistivity of each layer pair. Furthermore, if the same kind of dopant is doped in the low temperature deposition buffer layer and the nitride semiconductor single crystal layer, the resistivity related to the low temperature deposition buffer layer can be reduced.
In many cases, it is preferable to perform more doping in the low temperature deposition buffer layer to promote a decrease in resistivity of the low temperature deposition buffer layer.
Si, Ge, and the like are used as n-type dopants, and Mg, Zn, and Be are used as p-type dopants. In particular, Si and Mg are preferable because the effect of lowering resistance and technically mature techniques can be applied. Choosing a high Si concentration lowers the resistivity of the n-type GaN layer but degrades the crystallinity. In addition, as in the case of Si, if the Mg concentration is too high, the crystallinity may be deteriorated, so care must be taken.
[0035]
In order to form the n-type AlN low temperature deposition buffer layers 34 and 55, Si is doped in the range of about 5 × 1017 to 5 × 1019 cm−3 by supplying silane simultaneously with TMAl (trimethylaluminum) and ammonium in the above step 3m. Good. In one example, it is 5 × 10 18 cm −3.
In the growth of the n-type GaN single crystal layers 16, 36, 56 and the n-type GaN low temperature deposition buffer layers 14, 54, Si is doped by supplying silane simultaneously with TMGa (trimethylgallium) and ammonia in Step 4 and Step 3 above. To do. The concentration is selected in the range of 5 × 10 17 cm −3 to 1 × 10 19 cm −3 with 2 × 10 18 cm −3 as the center. In one example, the concentration of dopant Si is 2 × 10 18 cm −3.
[0036]
Further, in the formation of the p-type AlN low temperature deposition buffer layers 34 and 55, TMAl (trimethylaluminum), ammonium and Cp2Mg (biscyclopentadienylmagnesium) are supplied at the same time in step 3m, so that Mg has a concentration of 1 × 10 18 to 5 × 10 20 cm −3. Dope within the range. In most cases, it is preferably about 1 × 1020 cm−3. As in the case of Si, care must be taken because the crystallinity can be degraded if the Mg concentration is too high.
The growth of the p-type GaN single crystal layers 16, 36, 56 and the p-type GaN low temperature deposition buffer layers 14, 54 is carried out in the above Step 4 and Step 3 with TMGa (trimethyl gallium) and ammonia together with Cp 2 Mg (biscyclopentadienyl magnesium). ) To be doped with Mg in a concentration range of 1 × 1018 to 1 × 1020 cm−3. On the other hand, it is preferably about 5 × 10 19 cm −3.
[0037]
(Composition and film thickness of low temperature deposition buffer layer or single crystal layer)
It has been found that the composition of the low temperature deposition buffer layer constituting the layer pair may be an AlGaN ternary compound in order to introduce the compressive strain, and may be an AlN molar fraction of 5% or more, preferably 10% or more. For applications where the resistivity of the low temperature deposition buffer layer is desired to be kept small, the AlN mole fraction should be selected to be less than 50% and, if the resistivity is quite important, about 10%.
The film thickness of the low-temperature deposited buffer layer is not less than a predetermined value at which the buffer effect is stably obtained, and not more than another predetermined value so that the crystal quality of itself and the nitride semiconductor single crystal layer are kept good. There is this like this. Therefore, the film thickness is preferably 2 nm or more and 100 nm or less, and more preferably 10 nm to 50 nm. The deposition temperature is selected in the range of 300 ° C to 700 ° C.
[0038]
The single crystal layer is not limited to the GaN layer but may be an AlGaN ternary compound layer. In the invention of Takeuchi et al., A single crystal layer of the AlGaN ternary compound is deposited on the low temperature deposition buffer layer of the AlGaN ternary compound.
The film thickness of the single crystal layer is preferably in the range of 0.1 μm to 3 μm. If it is thin, the production time is short, which is advantageous, but if it is too thin, the crystallinity deteriorates. The growth temperature is selected in the range of 1000 ° C to 1200 ° C.
[0039]
(Growth method)
In the above experimental examples, the MOVPE (metal organic vapor phase epitaxy) apparatus was used exclusively. Although it seems that there is no difficulty in making the present invention with other apparatuses, it is preferable to use a MOVPE (metal organic vapor phase epitaxy) apparatus in view of the maturity of the technology, operability, and cost.
[0040]
(Ease of manufacturing)
Since the tensile strain and the compressive strain can be observed at least by measuring the lattice constant at room temperature, it is possible to measure the lattice constant when performing a sampling inspection during mass production, so that the stability of the manufacturing process can be measured in a short time. Contributes to cost reduction.
[0041]
【The invention's effect】
By implementing the present invention, a multilayer substrate with few lattice defects can be formed, so that not only an optical element such as a laser diode but also an element structure and characteristics using many group III nitride semiconductors can be improved.
Non-limiting examples of these devices include AlGaN / GaN modulation-doped field effect transistors, ridge waveguide laser diodes, pn junction PDs (photodetection diodes), AlN / GaN semiconductor multi-thick reflective films, and AlN / GaN sub-layers. For example, an interband transition device.
[Brief description of the drawings]
FIG. 1 is a structural diagram of a multilayer deposition substrate 10 in which two pairs of layers composed of a GaN low temperature deposition buffer layer and a GaN single crystal layer are deposited on a sapphire substrate.
FIG. 2 is a differential interference microscope photograph of the surface of the uppermost GaN single crystal layer of a multilayer deposition substrate in which a layer pair consisting of a GaN low temperature deposition buffer layer and a GaN single crystal layer is deposited on a sapphire substrate.
FIG. 3 is a structural diagram of a multilayer deposition substrate 30 in which two pairs of layer pairs composed of an AlN low temperature deposition buffer layer and a GaN single crystal layer are deposited on a sapphire substrate.
FIG. 4 is a photograph taken by a differential interference microscope of the surface of the uppermost GaN single crystal layer of a multilayer deposition substrate in which a layer pair consisting of an AlN low temperature deposition buffer layer and a GaN single crystal layer is deposited on a sapphire substrate.
FIG. 5 is a graph showing changes in the lattice constant of the c-axis on the surface of the uppermost GaN single crystal layer with respect to the number of layer pairs of the multilayer deposition substrate.
FIG. 6 is a graph showing a change in lattice dislocation density on the surface of the uppermost GaN single crystal layer with respect to the number of layer pairs of the multilayer deposition substrate.
FIG. 7 shows a multilayer formed by growing three pairs of a GaN low temperature deposition buffer layer and a GaN single crystal layer on a sapphire substrate and then growing a pair of AlN low temperature deposition buffer layer and a GaN single crystal layer pair. 3 is a structural diagram of a deposition substrate 50. FIG.
8 is a photograph of the surface of the uppermost GaN single crystal layer of the multilayer deposition substrate 50 of FIG. 7 using a differential interference microscope.
[Explanation of symbols]
10, 30, 50 multilayer deposition substrate,
12, 32, 52 Sapphire substrate 14, 54 GaN low temperature deposition buffer layer 16, 36, 56 GaN single crystal layer 34, 55 AlN low temperature deposition buffer layer

Claims (19)

第1の材料からなる基板と、
前記基板上に位置する積層の層対であって、
該層対が、
低温堆積窒化物半導体からなる緩衝層と、
該緩衝層上で直接成長する単結晶GaNの単結晶層とを有し、
緩衝層がAlGaNまたはAlNから成る少なくとも1つの前記層対が、前記緩衝層がAlGaNまたはAlNから成る少なくとも1つの前記層対が上に位置する、緩衝層がGaNから成る他の層対の前記単結晶層の平面内歪みが圧縮歪みである単結晶層の平面内歪みを持つように構成されていることを特徴とする窒化物半導体多層堆積基板。
A substrate made of a first material;
A stacked layer pair located on the substrate,
The layer pair is
A buffer layer made of a low temperature deposited nitride semiconductor;
A single crystal layer of single crystal GaN grown directly on the buffer layer,
The at least one layer pair, the buffer layer of which consists of AlGaN or AlN, is located above the at least one layer pair, of which the buffer layer is made of AlGaN or AlN, and the other layer pair of which the buffer layer is made of GaN. A nitride semiconductor multilayer deposition substrate, wherein the in-plane strain of the crystal layer is configured to have the in-plane strain of a single crystal layer which is a compressive strain.
前記積層が3つの層対を有することを特徴とする請求項1に記載の窒化物半導体多層堆積基板。The nitride semiconductor multilayer deposition substrate according to claim 1, wherein the stack includes three layer pairs. 前記積層が4つの層対を有することを特徴とする請求項1に記載の窒化物半導体多層堆積基板。The nitride semiconductor multilayer deposition substrate according to claim 1, wherein the stack includes four layer pairs. 前記緩衝層がAlGaNまたはAlNから成る少なくとも1つの前記層対における前記緩衝層がAlNモル分率5%から100%の間のAlGaNから成ることを特徴とする請求項1ないし3のいずれか1つの請求項に記載の窒化物半導体多層堆積基板。4. The buffer layer according to claim 1, wherein the buffer layer in the at least one layer pair made of AlGaN or AlN is made of AlGaN having an AlN molar fraction of between 5% and 100%. The nitride semiconductor multilayer deposition substrate according to claim. 他の層対の緩衝層がGaNから成ることを特徴とする請求項4に記載の窒化物半導体多層堆積基板。5. The nitride semiconductor multilayer deposition substrate according to claim 4, wherein the buffer layer of the other layer pair is made of GaN. GaNからなる緩衝層を有する隣接した層対の数が6未満であることを特徴とする請求項5に記載の窒化物半導体多層堆積基板。6. The nitride semiconductor multilayer deposition substrate according to claim 5, wherein the number of adjacent layer pairs having a buffer layer made of GaN is less than six. 前記層対の大部分の緩衝層がAlNモル分率が10%と90%の間であるAlGaNから成ることを特徴とする請求項1ないし3のいずれか1項に記載の窒化物半導体多層堆積基板。4. The nitride semiconductor multilayer deposition according to claim 1, wherein a majority of the buffer layer of the layer pair is made of AlGaN having an AlN mole fraction of between 10% and 90%. 5. substrate. 前記AlNモル分率が10%と50%の間であることを特徴とする請求項4または7のいずれかに記載の窒化物半導体多層堆積基板。The nitride semiconductor multilayer deposition substrate according to claim 4, wherein the AlN molar fraction is between 10% and 50%. 前記AlNモル分率がほぼ10%であることを特徴とする請求項8に記載の窒化物半導体多層堆積基板。9. The nitride semiconductor multilayer deposition substrate according to claim 8, wherein the AlN molar fraction is approximately 10%. 多層堆積基板を形成する方法であって、
第1の材料からなる基板を提供するステップと、
前記基板上に積層の層対を形成するステップとを備え、
該層対のそれぞれが、
単結晶成長が生じる温度よりも低い温度で低温堆積窒化物半導体の緩衝層を堆積させるステップと、
前記緩衝層上に直接単結晶GaNの単結晶層を成長させるステップであって、
前記積層の層対を形成する場合において、緩衝層がAlGaNまたはAlNから成る少なくとも1つの層対が上に位置する、緩衝層がGaNから成る他の層対の前記単結晶層の平面内歪みが圧縮歪みである単結晶層の平面内歪みを持つように形成するステップとを含むプロセスによって形成されることを特徴とする窒化物半導体多層堆積基板の形成方法。
A method of forming a multi-layer deposition substrate comprising:
Providing a substrate of a first material;
Forming a stacked layer pair on the substrate,
Each of the layer pairs is
Depositing a low temperature deposited nitride semiconductor buffer layer at a temperature below that at which single crystal growth occurs;
Growing a single crystal layer of single crystal GaN directly on the buffer layer,
In the case of forming the layer pair of the stacked layers, the in-plane strain of the single crystal layer of the other layer pair in which the buffer layer is made of GaN, on which at least one layer pair of the buffer layer is made of AlGaN or AlN is positioned. Forming a single crystal layer that has compressive strain so as to have an in-plane strain, and forming a nitride semiconductor multilayer deposition substrate.
前記積層を形成するに当たり、3つの層対を有する積層が形成されることを特徴とする請求項10に記載の窒化物半導体多層堆積基板の形成方法。The method for forming a nitride semiconductor multilayer deposition substrate according to claim 10, wherein in forming the stack, a stack having three layer pairs is formed. 前記積層を形成するに当たり、4つの層対を有する積層が形成されることを特徴とする請求項10に記載の窒化物半導体多層堆積基板の形成方法。The method for forming a nitride semiconductor multilayer deposition substrate according to claim 10, wherein in forming the stack, a stack having four layer pairs is formed. 前記緩衝層を形成するに当たり、AlNモル分率5%から100%の間のAlGaNから成る半導体材料からなる層が、前記緩衝層がAlGaNまたはAlNから成る少なくとも1つの前記層対における前記緩衝層として堆積されることを特徴とする請求項10ないし12のいずれか1項に記載の窒化物半導体多層堆積基板の形成方法。In forming the buffer layer, a layer made of a semiconductor material composed of AlGaN having an AlN molar fraction of 5% to 100% is used as the buffer layer in at least one layer pair in which the buffer layer is composed of AlGaN or AlN. 13. The method for forming a nitride semiconductor multilayer deposition substrate according to claim 10, wherein the nitride semiconductor multilayer deposition substrate is deposited. 前記緩衝層を形成するに当たり、GaNから成る半導体材料からなる層がそれぞれ他の層対の緩衝層として堆積されることを特徴とする請求項13に記載の窒化物半導体多層堆積基板の形成方法。14. The method for forming a nitride semiconductor multilayer deposition substrate according to claim 13, wherein in forming the buffer layer, layers made of a semiconductor material made of GaN are each deposited as a buffer layer of another layer pair. 前記積層を形成するに当たり、前記積層が、GaNからなる緩衝層を有する隣接した層対の数が6未満となるように、形成されることを特徴とする請求項14に記載の窒化物半導体多層堆積基板の形成方法。15. The nitride semiconductor multilayer according to claim 14, wherein in forming the stack, the stack is formed such that the number of adjacent layer pairs having a buffer layer made of GaN is less than six. Method for forming a deposition substrate. 前記緩衝層を堆積させるにあたり、AlNモル分率が10%と90%の間であるAlGaNから成る半導体の層がそれぞれ大部分の前記層対の緩衝層として堆積されることを特徴とする請求項13に記載の窒化物半導体多層堆積基板の形成方法。A semiconductor layer composed of AlGaN having an AlN mole fraction between 10% and 90% is deposited as a buffer layer of a majority of the layer pairs in depositing the buffer layer. 14. A method for forming a nitride semiconductor multilayer deposition substrate according to 13. 前記緩衝層を堆積させるにあたり、AlNモル分率が10%と50%の間であることを特徴とする請求項13ないし16のいずれか1項に記載の窒化物半導体多層堆積基板の形成方法。The method for forming a nitride semiconductor multilayer deposition substrate according to any one of claims 13 to 16, wherein an AlN molar fraction is between 10% and 50% in depositing the buffer layer. 前記緩衝層を堆積させるにあたり、AlNモル分率がほぼ10%であることを特徴とする請求項13ないし16のいずれか1項に記載の窒化物半導体多層堆積基板の形成方法。The method for forming a nitride semiconductor multilayer deposition substrate according to any one of claims 13 to 16, wherein an AlN molar fraction is approximately 10% for depositing the buffer layer. さらに、室温(a)及び上昇温度(b)の1つにおいて前記単結晶層の格子定数を測定し、単結晶層の平面内歪みを決定するステップを備えたことを特徴とする請求項10ないし18のいずれか1項に記載の窒化物半導体多層堆積基板の形成方法。The method further comprises the step of measuring the lattice constant of the single crystal layer at one of room temperature (a) and elevated temperature (b) to determine in-plane strain of the single crystal layer. The method for forming a nitride semiconductor multilayer deposition substrate according to any one of 18.
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