JP4284347B2 - Serial data detection circuit - Google Patents

Description

  The present invention relates to a serial data detection circuit used in a high-speed serial communication system using USB or the like, and a received data signal processing apparatus using the serial data detection circuit.

  In recent years, product interfaces have been speeded up, and systems using high-speed serial communication have been developed. For example, there is one using USB as such high-speed serial communication. As the USB standard, there was the USB 1.1 standard, but development of a system using the USB 2.0 standard capable of obtaining a communication speed of 480 Mbps, which is faster than the standard, is progressing. When receiving data with such a system, the presence / absence of connection of the transmission medium and the presence / absence of received data are determined by the value of the amplitude level of the signal. A predetermined signal reproduction process is performed on the data, and when the threshold value is not exceeded, the signal reproduction process is not performed on the received data.

FIG. 10 is a block diagram showing a conventional example of a received data signal processing apparatus compliant with the USB 2.0 standard.
The received data signal processing apparatus 100 in FIG. 10 is a normal receiver 101 that performs normal signal processing for internally converting a pair of serial data signals having opposite signal levels transmitted from the serial transmission lines DP and DM into digital signals. A digital signal processing circuit 102 that performs a predetermined process on the signal output from the normal receiver 101 and outputs the signal, and signal detection that detects whether or not a serial signal has been received from the serial transmission lines DP and DM. Receiver 103.

  Further, the integrating circuit 104 that integrates and outputs the output signal OUTb of the signal detection receiver 103, and the receiver enable signal RE for performing the enable control of the normal receiver 101 by shaping the output signal of the integrating circuit 104. And a Schmitt circuit 105 that generates and outputs to the normal receiver 101. The signal detection receiver 103, the integration circuit 104, and the Schmitt circuit 105 detect whether or not a serial data signal is input from the serial transmission lines DP and DM, and perform drive control of the normal receiver 101 according to the detection result. A serial data detection circuit 106 is configured.

  In a system such as a USB, each node of the serial transmission lines DP and DM is at a low level when in an idle state. At this time, the output of the normal receiver 101 becomes unstable, and a problem may occur in the signal processing of the digital signal processing circuit 102. In order to avoid such problems, a signal detection receiver 103 is provided, and control is performed so that the normal receiver 101 operates only during a period in which the signal detection receiver 103 detects a signal. For this reason, the signal detection receiver 103 is provided with an offset in the threshold value.

  FIG. 11 is a timing chart showing signal examples of the respective units in FIG. The signal detection receiver 103 is a receiver having an offset in the threshold value. When the reception of the serial data signal from the serial transmission lines DP and DM is detected, the signal detection receiver 103 generates a pulse signal corresponding to the data signal and generates an output signal. Output as OUTb. The output signal OUTb is integrated by the integrating circuit 104, then shaped by the Schmitt circuit 105, converted into a binary signal, and output to the normal receiver 101 as a receiver enable signal RE.

  That is, when the serial data detection circuit 106 detects reception of the serial data signal from the serial transmission lines DP and DM, the serial data detection circuit 106 activates the normal receiver 101 by raising the receiver enable signal RE to a high level. When the serial data detection circuit 106 does not detect the reception of the serial data signal, the serial data detection circuit 106 sets the receiver enable signal RE to a low level to stop the operation of the normal receiver 101.

  Here, FIG. 12 is a diagram illustrating a circuit example of the signal detection receiver 103 of FIG. The signal detection receiver 103 in FIG. 12 has the same circuit configuration as the normal type receiver, but the input transistors 111 and 112, which are P-channel MOS transistors (hereinafter referred to as PMOS transistors), are changed to transistors of different sizes. Thus, an offset is provided. A constant bias voltage is applied to the gate of the PMOS transistor 113.

On the other hand, FIG. 13 is a diagram showing another circuit example of the signal detection receiver 103 of FIG.
In the signal detection receiver 103 of FIG. 13, the input transistors 121 and 122, which are PMOS transistors, are PMOS transistors of the same size and form a differential pair. A constant current ia from the constant current source 130 is applied by the PMOS transistors 131 to 133 to a connection portion between the input transistor 121 and an N-channel MOS transistor (hereinafter referred to as an NMOS transistor), and an offset is provided in the threshold value. Yes.

Although different from the present invention, the difference between the differential circuit composed of the first and second transistors to which the serial data signal of the differential signal is inputted and the third and fourth transistors to which the offset signal is inputted. And a level of the connection point between the drain of the first transistor and the drain of the third transistor and the level of the connection point between the drain of the second transistor and the drain of the fourth transistor are provided. A comparator is provided, and when the serial data signal is not given from the comparator, the output level is constant, and when the serial data signal is given, the serial data from which the level changes according to the input data can be obtained. There was a signal detection circuit (see, for example, Patent Document 1).
JP 2001-102878 A

  However, the configuration as shown in FIGS. 12 and 13 has a problem that the characteristics of the transistors in the signal detection receiver 103 change due to variations in process, temperature, etc., and the offset varies. In order to reduce the variation of the offset, a method of increasing the gate area of each input transistor is conceivable. However, this causes a problem that the operation speed of the signal detection receiver 103 is lowered and is suppressed. There was also a limit to the range of offset variation that can be performed.

  The present invention has been made to solve the above problems, and by adjusting the amount of offset current according to the process, temperature, etc., variation in offset can be reduced and high-speed operation can be achieved. An object of the present invention is to obtain a serial data detection circuit compliant with the USB standard or the like.

  The serial data detection circuit according to the present invention is a serial data detection circuit for detecting whether or not a pair of serial data signals having opposite signal levels are input, and is offset with respect to a predetermined one of the serial data signals And a signal having a differential amplifier circuit that outputs a predetermined signal indicating that the serial data signal is detected when the voltage of the other serial data signal is larger than the voltage of the serial data signal provided with the offset. A differential amplification circuit unit that differentially amplifies and outputs each different predetermined constant voltage, outputs an offset with respect to one input voltage, and a voltage of each output signal of the differential amplification circuit unit Control the offset of the differential amplifier circuit unit and control the offset of the differential amplifier circuit in the signal detection circuit unit to be the same That those with an offset control circuit unit.

  According to the serial data detection circuit of the present invention, the offset value of the signal detection circuit unit is determined using the feedback signals of the differential amplifier circuit unit and the offset control circuit unit. Therefore, even when the process, temperature, etc. fluctuate, the fluctuation of the offset value can be reduced, a stable system compliant with the USB standard can be provided, and when serial data is received A signal indicating that the serial data signal is detected can be generated at high speed.

  Specifically, the signal detection circuit unit holds and outputs the output signal of the receiver and uses a flip-flop that makes a signal indicating whether the output signal has detected a serial data signal. Can be accurately detected, and the time required for the detection can be shortened.

  In addition, by using a serial input / serial output type shift register in which the output signal of the receiver is input to the signal detection circuit unit and the output signal indicates whether a serial data signal has been detected, noise, etc. It is possible to prevent erroneous detection of the serial data signal due to the mixing of.

  Specifically, the signal detection circuit unit holds and outputs a signal indicating the result of OR operation of the output signals of the first receiver and the second receiver, and the output signal detects the serial data signal. A flip-flop that makes a signal indicating whether or not it has been used is used. As a result, the serial data signal can be detected accurately and the time required for the detection can be shortened, and the time during which the signal level of the pair of serial data signals becomes constant at a predetermined level is set to a predetermined value. Even if an abnormal state exceeding the above value occurs, the data on the abnormal state can be output to the subsequent circuit, so that the processing on the abnormal state can be performed by the subsequent circuit.

  Whether or not the signal detection circuit unit sequentially holds and outputs a signal indicating the result of the OR operation of the output signals of the first receiver and the second receiver, and whether the output signal detects a serial data signal or not. A serial input / serial output type shift register that produces a signal indicating the above is used. As a result, the serial data signal can be accurately detected, and even if an abnormal state occurs in which the signal level of the pair of serial data signals is constant at a predetermined level exceeds a predetermined value, Since the data of the abnormal state can be output, the subsequent circuit can be processed for the abnormal state. Further, it is possible to prevent erroneous detection of the serial data signal due to the mixing of noise or the like.

  On the other hand, the signal detection circuit unit integrates the output signal of the receiver and converts the signal obtained by the integration into a binary signal to generate a signal indicating whether or not a serial data signal has been detected. . Therefore, an increase in circuit scale can be reduced and an increase in circuit layout area can be reduced.

  Whether or not the signal detection circuit unit synthesizes and integrates the output signals of the first receiver and the second receiver and converts the signal obtained by the integration into a binary signal to detect a serial data signal. A signal indicating this is generated. Therefore, an increase in circuit scale can be reduced and an increase in circuit layout area can be reduced.

  The differential amplifier circuit section and the receiver each include a differential amplifier circuit having the same characteristics with the same circuit configuration and an offset circuit having the same characteristics with the same circuit configuration. From this, even when the process, temperature, etc. fluctuate, fluctuations in the offset value of the receiver can be further reduced.

  On the other hand, the differential amplifier circuit unit, the first receiver, and the second receiver each include a differential amplifier circuit having the same characteristics with the same circuit configuration, and an offset circuit having the same characteristics with the same circuit configuration. From this, even when the process, temperature, etc. fluctuate, fluctuations in the offset value of each receiver can be further reduced.

  In the received data signal processing apparatus of the present invention, in the serial data detection circuit, the offset value of the signal detection circuit unit is determined using the feedback signals of the differential amplifier circuit unit and the offset control circuit unit. Therefore, even when the process, temperature, etc. fluctuate, the fluctuation of the offset value can be reduced, a stable system compliant with the USB standard etc. can be provided, and when serial data is received Since a signal indicating that a serial data signal has been detected can be generated at high speed, reception of the serial data signal can be detected accurately, and accurate signal processing can be performed on the received signal.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a circuit diagram showing an example of a serial data detection circuit according to the first embodiment of the present invention. FIG. 1 shows an example in which the received data signal processing apparatus conforms to the USB 2.0 standard.
In FIG. 1, a received data signal processing apparatus 1 performs normal signal processing for internally converting a pair of serial data signals having opposite signal levels transmitted from serial transmission lines DP and DM into digital signals. Detection of the receiver 2, the digital signal processing circuit 3 that performs a predetermined process on the signal output from the normal receiver 2 and outputs the serial data signal from the serial transmission lines DP and DM The serial data detection circuit 4 is configured.

  When the serial data detection circuit 4 detects that a serial data signal is input from the serial transmission lines DP and DM, the serial data detection circuit 4 raises the receiver enable signal RE to a high level to operate the normal receiver 2. Further, when the serial data detection circuit 4 has not detected that the serial data signal has been input, the serial data detection circuit 4 sets the receiver enable signal RE to a low level to stop the operation of the normal receiver 2.

  The serial data detection circuit 4 includes a receiver 11 composed of a differential amplifier circuit to which serial transmission lines DP and DM are connected to corresponding input ends and a pair of serial data signals are inputted, and an output signal of the receiver 11 Is provided with a D flip-flop 12 input to the clock signal input terminal. The receiver 11 has a predetermined offset in the threshold value. A receiver enable signal RE for controlling the operation of the normal receiver 2 is output from the output terminal Q of the D flip-flop 12, and the power supply voltage VDD is applied to the D input terminal of the D flip-flop 12.

  The serial data detection circuit 4 is input from the integration circuit 13 that integrates the output signal of the receiver 11, the Schmitt circuit 14 that performs waveform shaping of the signal output from the integration circuit 13, and the Schmitt circuit 14. And a pulse generation circuit 15 that generates a pulse in response to the signal to be output and outputs the pulse to the reset signal input terminal R of the D flip-flop 12.

  Further, the serial data detection circuit 4 includes a reference voltage generation circuit 16 that generates and outputs a predetermined reference voltage Vr, and a reference receiver 17 that forms a differential amplifier provided with an offset with respect to the signal input to the inverting input terminal. And an operational amplifier 18 that compares the output voltages Vo1 and Vo2 from the reference receiver 17 and outputs a voltage corresponding to the comparison result to the receiver 11 and the reference receiver 17, respectively. The pulse generation circuit 15 forms a reset signal generation circuit, the reference voltage generation circuit 16 and the reference receiver 17 form a differential amplifier circuit section, and the operational amplifier 18 forms an offset control circuit section.

In the receiver 11, the serial transmission line DP is connected to the non-inverting input terminal, the serial transmission line DM is connected to the inverting input terminal, and the output terminal is connected to the D flip-flop 12 and the integrating circuit 13.
In the reference receiver 17, the reference voltage Vr is input to the inverting input terminal, and the ground voltage is input to the non-inverting input terminal. The output voltage Vo1 of the reference receiver 17 is input to the inverting input terminal of the operational amplifier 18, and the output voltage Vo2 of the reference receiver 17 is input to the non-inverting input terminal of the operational amplifier 18. The output signal of the operational amplifier 18 is output to the receiver 11 and the reference receiver 17 as a control signal Sc for controlling the offset.

Here, FIG. 2 is a diagram illustrating an example of an internal circuit of the receiver 11.
In FIG. 2, the receiver 11 includes a differential amplifier circuit unit 21, an output circuit unit 22, and an offset circuit unit 23.
The differential amplifier circuit section 21 includes PMOS transistors 31 to 33 and NMOS transistors 34 and 35. The PMOS transistors 31 and 32 and the NMOS transistor 34 are connected in series between the power supply voltage VDD and the ground voltage. Yes.

  A series circuit of the PMOS transistor 33 and the NMOS transistor 35 is connected in parallel with the series circuit of the PMOS transistor 32 and the NMOS transistor 34. The NMOS transistors 34 and 35 each have a gate and drain connected to form a diode. The gate of the PMOS transistor 31 is biased by applying a predetermined constant voltage, and the PMOS transistor 31 forms a constant current source. The gate of the PMOS transistor 32 forms a non-inverting input terminal and is connected to the serial transmission line DP, and the gate of the PMOS transistor 33 forms an inverting input terminal and is connected to the serial transmission line DM.

  The output circuit unit 22 includes PMOS transistors 37 and 38 and NMOS transistors 39 and 40. The PMOS transistors 37 and 38 form a current mirror circuit. The NMOS transistor 39 and the NMOS transistor 40 form current mirror circuits, respectively, and the NMOS transistor 34 and 35, respectively. Between the power supply voltage VDD and the ground voltage, a series circuit of a PMOS transistor 37 and an NMOS transistor 39 and a series circuit of a PMOS transistor 38 and an NMOS transistor 40 are respectively connected in parallel. The connection part of the PMOS transistor 37 and the NMOS transistor 39 forms the output terminal of the receiver 11, and the output signal OUT1 is output.

  The gates of the PMOS transistors 37 and 38 are connected to each other and connected to the drain of the PMOS transistor 38. The gate of the NMOS transistor 39 is connected to the gate of the NMOS transistor 34, and the connection is connected to the drain of the NMOS transistor 34. Similarly, the gate of the NMOS transistor 40 is connected to the gate of the NMOS transistor 35, and the connection is connected to the drain of the NMOS transistor 35.

  Next, the offset circuit unit 23 includes PMOS transistors 41 and 42, and a series circuit of PMOS transistors 41 and 42 is connected between the power supply voltage VDD and the drain of the NMOS transistor 35. The gate of the PMOS transistor 41 is connected to the ground voltage, and the control signal Sc from the operational amplifier 18 is input to the gate of the PMOS transistor 42.

  In such a configuration of the receiver 11, the drain current of the NMOS transistor 34 is i1, and the drain current of the NMOS transistor 35 is i2. Furthermore, the current flowing from the offset circuit section 23 to the drain of the NMOS transistor 35 is i3, and the drain current of the PMOS transistor 33 is i4. The current i2 is the sum of the current i3 and the current i4, and the current i3 is for providing an offset to the threshold value of the receiver 11.

  The current i1 is determined by the voltage value of the input voltage from the serial transmission line DP, and the current i4 is determined by the voltage value of the input voltage from the serial transmission line DM. The offset of the threshold value of the receiver 11 increases in proportion to the current value of the current i3, and the offset value can be adjusted by the voltage of the control signal Sc input from the operational amplifier 18. That is, the current i3 increases and the offset increases as the input voltage from the operational amplifier 18 decreases, and the current i3 decreases and the offset decreases as the input voltage from the operational amplifier 18 increases. Thus, the offset of the receiver 11 can be adjusted according to the output signal Sc of the operational amplifier 18.

On the other hand, FIG. 3 is a diagram showing an example of an internal circuit of the reference receiver 17. In FIG. 3, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted here.
In FIG. 3, the reference receiver 17 includes a differential amplifier circuit unit 21 and an offset circuit unit 23. In the differential amplifier circuit unit 21, the ground voltage is input to the gate of the PMOS transistor 32, and the reference voltage Vr is input to the gate of the PMOS transistor 33. An output voltage Vo1 is output from the connection between the PMOS transistor 32 and the NMOS transistor 34, and an output voltage Vo2 is output from the connection between the PMOS transistor 33 and the NMOS transistor 35.

  In this way, the differential outputs output from the reference receiver 17 are respectively input to the corresponding input terminals of the operational amplifier 18, and the reference receiver 17 feeds back the voltage indicating the comparison result from the operational amplifier 18 to adjust the offset. Is called. The operational amplifier 18 adjusts the offset of the reference receiver 17 so that the output voltages Vo1 and Vo2 of the reference receiver 17 are the same. Therefore, the receiver 11 and the reference receiver 17 have threshold values corresponding to the reference voltage Vr, and the threshold values of the receiver 11 and the reference receiver 17 are constant even when the process, temperature, power supply voltage, and the like change.

  On the other hand, the amplitude of the serial data signal defined by the USB 2.0 standard is 400 mV, which is considerably smaller than 3.3 V defined by the USB 1.1 standard. Thus, even when the amplitude of the serial data signal becomes small and it becomes difficult to determine data reception, the serial data detection circuit 4 shown in FIGS. 1 to 3 uses the serial transmission lines DP and DM. Data signal reception determination can be performed accurately. Further, the serial data detection circuit 4 does not need to increase the gate area of the input transistor in order to suppress the variation in offset as in the prior art, and can perform high-speed operation.

  Next, FIG. 4 is a timing chart showing an example of the waveform of each part of the serial data detection circuit 4 shown in FIGS. 1 to 3, and the generation of the receiver enable signal RE in the serial data detection circuit 4 using FIG. An operation example will be described. Note that VP represents a voltage at a connection portion between the PMOS transistor 32 and the NMOS transistor 34 in FIG. 2, and VM represents a voltage at a connection portion between the PMOS transistor 33 and the NMOS transistor 35 in FIG. V1 represents an offset voltage of the differential output, and the offset voltage V1 is a voltage proportional to the reference voltage Vr.

  The output signal OUT1 of the receiver 11 becomes the clock signal of the D flip-flop 12, and the D flip-flop 12 is applied with the power supply voltage VDD at the D input terminal. An enable signal RE is output to operate the normal receiver 2. The signal OUT1 output from the receiver 11 is simultaneously input to the integration circuit 13, integrated by the integration circuit 13, and output to the Schmitt circuit 14.

  The Schmitt circuit 14 outputs to the pulse generation circuit 15 a signal S1 obtained by shaping the waveform of the input signal into a binary signal. While serial data is being input from the serial transmission lines DP and DM, a pulse signal is output from the receiver 11, and during this time, a low level signal is output from the output terminal of the pulse generation circuit 15. When serial data is no longer input from the serial transmission lines DP and DM, the output signal OUT1 of the receiver 11 becomes low level, and a high level pulse signal Sr is output from the output terminal of the pulse generation circuit 15.

  When the input signal S1 falls from the high level to the low level, the pulse generation circuit 15 outputs a predetermined one-shot pulse as the signal Sr to the reset signal input terminal R of the D flip-flop 12. When a high-level pulse is input to the reset signal input terminal R, the D flip-flop 12 causes the receiver enable signal RE from the output terminal Q to fall from the high level to the low level simultaneously with the fall of the pulse, and the normal receiver The operation of 2 is stopped.

  As described above, the serial data detection circuit according to the first embodiment uses the operational amplifier 18 to set the pair of output voltages Vo1 and Vo2 of the reference receiver 17 to which different predetermined constant voltages are input to the same voltage. Thus, the offset adjustment for the differential amplifier circuit 21 of the reference receiver 17 is performed by the offset circuit 23, and the same offset adjustment as that performed for the reference receiver 17 is performed for the receiver 11. Therefore, the offset of the receiver 11 is made constant. By doing so, it is possible to reduce the variation in offset in the serial data detection receiver stipulated in the USB standard and the like, and the serial data signal having a small amplitude as in the USB 2.0 standard and the like can be detected accurately and accurately. It can be done at high speed.

Second embodiment.
In the USB standard, a pair of serial data signals from a serial transmission line is prohibited from being in a high level or low level for a predetermined bit length or more. However, in the first embodiment, when such a state occurs, the operation of the normal receiver 2 is stopped on the assumption that the serial data signal cannot be detected, so that the occurrence of the abnormal state as described above can be detected. Can not. Therefore, the second receiver according to the present invention prevents the operation of the normal receiver 2 from being stopped even when a pair of serial data signals from the serial transmission line is in a high level or a low level for a predetermined bit length or more. The embodiment is as follows.

FIG. 5 is a circuit diagram showing an example of a serial data detection circuit according to the second embodiment of the present invention. In FIG. 5, the same components as those in FIG. FIG. 5 also shows an example in which the received data signal processing apparatus conforms to the USB 2.0 standard.
5 differs from FIG. 1 in that a receiver 51 and an OR circuit 52 are added, and that the circuit configuration of the integrating circuit 13 in FIG. Therefore, the serial data detection circuit 4 of FIG. 1 is replaced with the serial data detection circuit 4a, and the reception data signal processing device 1 of FIG. 1 is replaced with the reception data signal processing device 1a.

In FIG. 5, a received data signal processing device 1a includes a normal receiver 2, a digital signal processing circuit 3, and a serial data detection circuit 4a for detecting whether or not a serial data signal is input from the serial transmission lines DP and DM. It consists of
When the serial data detection circuit 4a detects that a serial data signal is input from the serial transmission lines DP and DM, the serial data detection circuit 4a raises the receiver enable signal RE to a high level and operates the normal receiver 2. If the serial data detection circuit 4a has not detected that the serial data signal has been input, the serial data detection circuit 4a sets the receiver enable signal RE to a low level to stop the operation of the normal receiver 2.

  The serial data detection circuit 4a includes a receiver 51, a receiver 51 configured by a differential amplifier circuit to which serial transmission lines DP and DM are connected to corresponding input ends and a pair of serial data signals are input. An OR circuit 52 that performs an OR operation on the output signals OUT1 and OUT2 of 11 and 51, and a D flip-flop 12 in which the output signal of the OR circuit 52 is input to a clock signal input terminal.

  In this case, the receiver 11 forms a first receiver and the receiver 51 forms a second receiver. Similarly to the receiver 11, the receiver 51 has a predetermined offset in the threshold value. The serial data detection circuit 4a includes an integration circuit 53 that synthesizes and integrates the output signals of the receivers 11 and 51, a Schmitt circuit 14 that performs waveform shaping of the signal output from the integration circuit 53, and outputs the waveform. A pulse generation circuit 15, a reference voltage generation circuit 16, a reference receiver 17, and an operational amplifier 18 are provided.

  The output terminal of the receiver 11 is connected to one input terminal of the OR circuit 52 and the integrating circuit 53. In the receiver 51, the serial transmission line DM is connected to the non-inverting input terminal, the serial transmission line DP is connected to the inverting input terminal, and the output terminal is connected to the other input terminal of the OR circuit 52 and the integrating circuit 53, respectively. Has been. On the other hand, the output signal of the operational amplifier 18 is output to the receivers 11 and 51 and the reference receiver 17 as a control signal Sc for controlling the offset. An example of the internal circuit of the receiver 51 is the same as that of the receiver 11 in FIG. However, in the case of the receiver 51, the serial transmission line DM is connected to the gate of the PMOS transistor 32 in FIG. 2, and the serial transmission line DP is connected to the gate of the PMOS transistor 33 in FIG.

Next, FIG. 6 is a timing chart showing a waveform example of each part of the serial data detection circuit 4a shown in FIG. 5, and an example of the operation of generating the receiver enable signal RE in the serial data detection circuit 4a with reference to FIG. explain. In FIG. 6, each offset voltage of the differential outputs of the receivers 11 and 51 is V1.
A signal obtained by performing an OR operation on the output signals OUT1 and OUT2 of the receivers 11 and 51 by the OR circuit 52 becomes a clock signal of the D flip-flop 12. The signals OUT1 and OUT2 output from the receivers 11 and 51 are simultaneously input to the integration circuit 53, synthesized by the integration circuit 53, integrated, and output to the Schmitt circuit 14.

  7 is a diagram showing an example of an internal circuit of the integrating circuit 53 shown in FIG. 5. In FIG. 7, the integrating circuit 53 includes a PMOS transistor 61, NMOS transistors 62 and 63, and a low-pass filter 64. Has been. A PMOS transistor 61 and an NMOS transistor 62 are connected in series between the power supply voltage VDD and the ground voltage. Further, an NMOS transistor 63 is connected in parallel with the NMOS transistor 62, and the gate of the PMOS transistor 61 is connected to the ground voltage. The output signal OUT1 from the receiver 11 is input to the gate of the NMOS transistor 62, and the output signal OUT2 from the receiver 51 is input to the gate of the NMOS transistor 63. A connection part of the PMOS transistor 61 and the NMOS transistors 62 and 63 is connected to an input terminal of the low-pass filter 64.

  Here, it is assumed that the current drive capability of the NMOS transistors 62 and 63 is larger than that of the PMOS transistor 61, and the on-resistances of the NMOS transistors 62 and 63 are sufficiently smaller than the on-resistance of the PMOS transistor 61. In this way, the signals OUT1 and OUT2 input to the gates of the NMOS transistors 62 and 63 are inverted in signal level and input to the low-pass filter 64, integrated by the low-pass filter 64, and then the Schmitt circuit 14 Is output.

  Since the Schmitt circuit 14 shapes the input signal into a binary signal, inverts the signal level and outputs the signal to the pulse generation circuit 15, the Schmitt circuit 14 forms an inverter circuit in the case of FIG. The integrating circuit 13 shown in FIG. 1 may be configured without the NMOS transistor 63 of FIG. 7, and in this case, the Schmitt circuit 14 of FIG. 1 may be configured as an inverter circuit. .

  While serial data signals are input from the serial transmission lines DP and DM, pulse signals are output from the receivers 11 and 51, respectively, and during this period, a low level signal Sr is output from the output terminal of the pulse generation circuit 15. . When serial data signals are no longer input from the serial transmission lines DP and DM, the output signals OUT1 and OUT2 of the receivers 11 and 51 become low level, respectively, and a high level pulse signal Sr is output from the output terminal of the pulse generation circuit 15. The

  Further, for example, when a low level signal having a length longer than that defined in the standard is input from the serial transmission line DP, a high level signal having the same length as the low level is input from the serial transmission line DM. Is done. During this time, the low-level signal OUT1 is output from the output terminal of the receiver 11, whereas the high-level signal OUT2 is output from the output terminal of the receiver 51, so that the output signal S1 of the Schmitt circuit 14 is high. The level is maintained, the pulse generation circuit 15 does not output a pulse signal, and the D flip-flop 12 outputs a high-level receiver enable signal RE.

  The same applies when a low-level signal having a length longer than that defined by the standard is input from the serial transmission line DM. In this way, even if the signal level does not invert from the serial transmission lines DP and DM for a time longer than that specified in the standard, the operation of the normal receiver 2 is not stopped by the serial data detection circuit 4a. Can do.

  As described above, the serial data detection circuit according to the second embodiment connects the serial transmission line DP to the non-inverting input terminal of the receiver 11 and the inverting input terminal of the receiver 51, and connects the serial transmission line DM to the receiver 11. A pair of output voltages Vo1 and Vo2 of the reference receiver 17 connected to the inverting input terminal and the non-inverting input terminal of the receiver 51, respectively, and input with different predetermined constant voltages using the operational amplifier 18, are the same voltage. The offset adjustment for the differential amplifier circuit 21 of the reference receiver 17 is performed by the offset circuit 23 and the same offset adjustment as that performed for the reference receiver 17 is performed for the receivers 11 and 51, respectively. The offsets of the receivers 11 and 51 are constant. It was as to become.

  By doing this, the same effect as in the first embodiment can be obtained, and an abnormal state where a pair of serial data from the serial transmission line is at a high level or a low level over a predetermined bit length Even if this occurs, the normal receiver can be operated and the data of the abnormal state can be output to the subsequent circuit, so that the processing of the abnormal state can be performed by the subsequent circuit.

  In the first and second embodiments, the case where the D flip-flop 12 has one stage has been described as an example. However, at least one D flip-flop is connected in series in the subsequent stage of the D flip-flop 12. They may be connected to form a serial input / serial output type shift register. For example, when the shift register is formed using three D flip-flops 12, 12a, 12b, the output terminal Q of the D flip-flop 12 is connected to the clock signal input terminal of the D flip-flop 12a, and the D flip-flop 12a The output terminal Q is connected to the clock signal input terminal of the D flip-flop 12b.

  A signal output from the output terminal Q of the D flip-flop 12b is output to the normal receiver 2 as a receiver enable signal RE. In the D flip-flops 12, 12a, 12b, the power supply voltage VDD is applied to each D input terminal, and the signal Sr from the pulse generation circuit 15 is input to each reset signal input terminal R. By doing so, the time required for detection of the serial data signal becomes longer, but it becomes difficult to erroneously output the receiver enable signal RE when the receiver reacts due to factors such as noise. Further, the number of stages of the D flip-flops may be set according to the system using the received data signal processing device.

  In the first and second embodiments, the D flip-flop 12 is used. However, the output signal S1 of the Schmitt circuit 14 can be used as the receiver enable signal RE without using the D flip-flop. In this case, FIG. 1 is as shown in FIG. 8 and FIG. 5 is as shown in FIG. 9, and the time required for detection of the serial data signal becomes longer. The scale can be reduced.

FIG. 3 is a circuit diagram illustrating an example of a serial data detection circuit in the first embodiment of the present invention. It is the figure which showed the example of the internal circuit of the receiver 11 in FIG. It is the figure which showed the example of the internal circuit of the reference receiver 17 in FIG. 4 is a timing chart showing an example of waveforms at various parts of the serial data detection circuit 4 shown in FIGS. It is the circuit diagram which showed the example of the serial data detection circuit in the 2nd Embodiment of this invention. 6 is a timing chart showing an example of waveforms at various parts of the serial data detection circuit 4a shown in FIG. FIG. 6 is a diagram illustrating an example of an internal circuit of the integration circuit 53 illustrated in FIG. 5. FIG. 7 is a circuit diagram showing another example of the serial data detection circuit in the first embodiment of the present invention. It is the circuit diagram which showed the other example of the serial data detection circuit in the 2nd Embodiment of this invention. It is the block diagram which showed the example of the conventional reception data signal processing apparatus. FIG. 11 is a timing chart showing an example of signals of each part in FIG. 10. FIG. It is the figure which showed the circuit example of the receiver 103 for signal detection in FIG. FIG. 11 is a diagram illustrating another circuit example of the signal detection receiver 103 in FIG. 10.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a Reception data signal processing apparatus 2 Normal receiver 3 Digital signal processing circuit 4, 4a Serial data detection circuit 11, 51 Receiver 12 D flip-flop 13, 53 Integration circuit 14 Schmitt circuit 15 Pulse generation circuit 16 Reference voltage generation circuit 17 Reference Receiver 18 Operational amplifier 21 Differential amplifier circuit unit 22 Output circuit unit 23 Offset circuit unit 52 OR circuit

Claims (1)

In a serial data detection circuit for detecting whether or not a pair of serial data signals having opposite signal levels are input,
An offset is provided with respect to one of the predetermined serial data signals, and when the voltage of the other serial data signal becomes larger than the voltage of the serial data signal with the offset, a predetermined serial data signal is detected. A signal detection circuit unit having a differential amplifier circuit for outputting a signal;
A differential amplification circuit section that differentially amplifies and outputs different predetermined constant voltages, and provides an offset with respect to one input voltage;
Offset control circuit unit for controlling the offset of the differential amplifier circuit unit and controlling the offset of the differential amplifier circuit in the signal detection circuit unit so that the voltages of the output signals of the differential amplifier circuit unit are the same. When,
A serial data detection circuit comprising:

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