JP4282560B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor substrate, particularly a semiconductor substrate used in a semiconductor device having a strained Si layer as an active region.

  The performance of Si semiconductor elements, especially MOSFET transistors, has been improving year by year with the progress of large scale integrated circuits (LSIs). However, in recent years, limitations to lithography technology miniaturization, approach to carrier mobility to the theoretical mobility of Si, etc. have been pointed out, and the difficulty in further increasing the performance of MOSFETs has increased.

  In general, as a measure for improving the performance of a semiconductor device, there is a method for realizing higher performance by using a crystal different from Si, such as a GaAs semiconductor crystal or SiC semiconductor crystal having a theoretical mobility faster than that of Si. It is being considered.

  However, GaAs semiconductor crystals and SiC crystals are difficult to mix with Si device manufacturing processes that are widely used at present, so a great deal of time and effort is required for element development. Requires a complete review and replacement of the production line.

  Therefore, development of a high-performance Si-based semiconductor element that can be realized with a shorter development period and lower investment efficiency while making full use of the Si device manufacturing process technology and manufacturing equipment know-how that are currently widely used is eagerly desired.

  For this reason, research has been conducted on improving the electron mobility of Si and improving the performance of Si-MOSFETs. As one of the methods for improving the mobility of Si, a technique for applying strain to the Si layer has attracted attention. In general, when strain is applied to a semiconductor layer, the band structure is changed, and scattering of carriers in the channel is suppressed, so that an improvement in electron mobility can be expected.

  Specifically, a mixed crystal layer made of a material having a larger lattice constant than Si, for example, a SiGe mixed crystal layer containing 20 atm% Ge (hereinafter, simply referred to as a SiGe layer) on the Si substrate is thickened (several). μm) and a thin Si layer (several nm) is formed on this lattice-relaxed SiGe layer, a strained Si layer is formed which is strained by the difference in lattice constant between SiGe and Si.

It has been reported that when such a strained Si layer is used for a channel of a MOSFET, a significant improvement in electron mobility can be achieved, which is about 1.76 times that when an unstrained Si layer is used for a channel. (For example, see Non-Patent Document 1)
As another method for improving the electron mobility of Si, there is a method for shortening the channel length of the MOSFET. However, if the channel length is shortened, the effect of stray capacitance increases, and it becomes difficult to improve the electron mobility as expected.

  In order to solve this problem, a structure in which a channel layer is provided in an SOI (silicon on insulator) layer in which an Si layer is formed on an Si substrate via an insulating film has been attracting attention. Since this structure is completely isolated by the insulating film, it is expected that the stray capacitance can be reduced and the element can be easily separated, and further lower power consumption and higher integration can be realized.

  Therefore, attempts have been made to apply a strained Si layer that can be expected to improve electron mobility to a semiconductor element structure applied to an SOI structure that facilitates reduction of stray capacitance and element isolation. This structure will be described with reference to FIG.

First, as shown in FIG. 1A, an SOI substrate in which a SiO ₂ insulating film 2 and a 10 nm to 30 nm SOI layer 3 are formed in advance on a Si substrate 1 is prepared, and Ge having a lattice constant larger than that of Si is prepared on this SOI substrate. The SiGe layer 4 having a concentration of 20% is formed sufficiently thicker than the SOI layer 3.

  Next, as shown in FIG. 1B, the SOI layer 3 is plastically deformed by the tensile strain (STRAIN) applied from the SiGe layer 4 to the SOI layer 3 by annealing at 1100 ° C. in a nitrogen atmosphere for 1 hour. ease. At the same time, the lattice relaxation of the SiGe layer 4 is also achieved. Due to this plastic deformation, dislocations 33 such as threading dislocations and misfit dislocations are generated in the SOI layer 3.

  Next, by forming a thin Si film on the lattice-relaxed SiGe layer 4, the strained Si layer 5 having tensile strain can be formed.

  Conventionally, it has been considered that most of the dislocations 33 generated in the SOI layer 3 are generated in the lattice relaxed SOI layer 3 and confined in this layer, and therefore do not propagate into the lattice relaxed SiGe layer 4.

However, when annealing is performed in a nitrogen atmosphere for 1 hour under a condition of 1100 ° C. for lattice relaxation, it propagates to the surface of the SiGe layer 4 at a density of about 1/10 μm ² , and this defect is present in the strained Si layer 5. It has been found that the crystallinity is degraded. A semiconductor element such as a MOSFET is formed on the strained Si layer 5 thereafter, but the crystallinity of the strained Si layer 5 may greatly deteriorate the characteristics of the semiconductor element. This is expected to become more prominent as semiconductor elements are miniaturized.

  In addition, defects generated when the lattice relaxation of the SiGe layer 4 may be amplified even in a high-temperature treatment process such as a subsequent gate or electrode formation process or crystallinity recovery annealing after ion doping. There is a possibility that the crystallinity of the layer 5 is deteriorated.

  In order to prevent dislocations 33 generated in the SOI layer 3 and causing lattice relaxation from propagating to the SiGe surface, the SiGe layer 4 must be formed to have a thickness of several μm or more.

However, it is necessary to suppress the thickness from the SiO ₂ insulating layer 2 to the strained Si layer 5 that is the channel layer as much as possible in order to sufficiently exhibit the effect of the SOI substrate structure that suppresses the influence of the stray capacitance. Therefore, this method, in which the SiGe layer 4 of several μm must be formed, cannot sufficiently exert the effect of the SOI substrate structure.
J. et al. Welser, J.M. L. Hoyl, S .; Tagkagi, and J.A. F. Gibbons, IEDM 94-373

  As described above, according to the conventional method, a semiconductor device including a strained Si layer serving as a channel layer formed on an SOI substrate has a large thickness on the SOI substrate insulating film in order to suppress defects. If the film thickness on the substrate insulating film is reduced, defects are amplified.

  Therefore, the present invention can achieve both a reduction in the thickness of the SOI substrate insulating layer and a reduction in defects in the strained layer serving as the channel layer, while applying sufficient strain to the channel layer to reduce the cost of a higher performance semiconductor device. It is an object of the present invention to provide a method for manufacturing a semiconductor substrate that can be formed in a simple manner.

To achieve the above objective,
The manufacturing method of the first semiconductor substrate of the present invention,
Forming an insulating film on the surface of the first semiconductor substrate ;
Forming a first semiconductor layer on a second semiconductor substrate surface ;
Said first insulating formed on the semiconductor substrate surface film, a first semiconductor layer formed on the second surface of the semiconductor substrate, a step of bonding,
A part of the second semiconductor substrate is removed, the first semiconductor substrate, the insulating film, the lattice-relaxed first semiconductor layer, and the second semiconductor substrate to which a tensile lattice strain is applied Forming a stack of the remainder, and
A method for manufacturing a semiconductor substrate, comprising:

The second method for manufacturing a semiconductor substrate of the present invention includes:
Forming a first insulating film on the surface of the first semiconductor substrate ;
Sequentially forming a first semiconductor layer and a second insulating film on a second semiconductor substrate;
A first insulating film formed on the first surface of the semiconductor substrate, a second insulating film formed over said first semiconductor layer on the second semiconductor substrate, a step of bonding ,
A part of the second semiconductor substrate is removed, and the first semiconductor substrate, the first and second insulating films, the lattice-relaxed first semiconductor layer, and the tensile lattice strain are applied. Forming a laminated substrate of the remaining part of the second semiconductor substrate ;
A method for manufacturing a semiconductor substrate, comprising:

Further, the third method for manufacturing a semiconductor substrate of the present invention,
Forming an insulating film on the surface of the first semiconductor substrate;
Forming a first semiconductor layer on a second semiconductor substrate surface;
Bonding the insulating film formed on the surface of the first semiconductor substrate and the first semiconductor layer formed on the surface of the second semiconductor substrate;
Removing a second semiconductor substrate to form a stack of the first semiconductor substrate, the insulating film, and the lattice-relaxed first semiconductor layer;
Forming a second semiconductor layer to which a tensile lattice strain is applied on the first semiconductor layer;
A method for manufacturing a semiconductor substrate, comprising:

In the present invention, the lattice constant of the second semiconductor layer is smaller than that of the first semiconductor layer. A typical material for the first semiconductor layer is SiGe, and a typical material for the second semiconductor layer is Si.
By the way, the covalent bond radii of Si and Ge are 1.17 and 1.22, respectively.
When the SiGe layer and the Si layer are laminated in this order on the Si substrate by a normal epitaxial growth technique, the lattice of the SiGe layer 4 ′ is deformed to be vertically long in alignment with the lattice of the lower Si layer 3, as shown in FIG. The tensile strain in the vertical direction in the figure is generated in the SiGe layer 4 '. The Si layer 5 ′ formed on the SiGe layer 4 ′ is not subjected to sufficient tensile strain.
Further, for example, in JP-A-11-121377, B having a dopant concentration of 10 ²⁰ to 10 ²¹ atoms / cm ³ is added to the SiGe layer by utilizing the fact that the covalent bond radius of B (boron) is 0.88. It is a thing. This technique eliminates the need for CMP after cutting in the hydrogen stripping method when forming an SOI substrate. FIG. 2B schematically shows lattice matching in this technique, in which a B-added SiGe layer 4 ″ is stacked on a Si layer, and a Si layer 5 ′ is further stacked. The B-added SiGe layer 4 ″ is used as an etching stopper and is removed later. In the above document, the Si layer 5 ′ can be used as a device layer, but this Si layer contains B thermally diffused from the SiGe (B) layer 4 ″ during the process and has a residual compressive strain. Become. No strain is applied to the Si layer 5 'as the device layer.

  Further, in order to form a strained Si layer as a device layer, it can be achieved by a method of forming a three-layer structure of Si / SiGe / Si as shown in FIG. 1A and FIG. There was a problem of propagating. In the semiconductor device and the semiconductor substrate of the present invention, as shown in FIG. 2C, the lattice-relaxed SiGe layer 4 is formed on and substantially in contact with the silicon oxide film 2, and the Si layer 5 is formed thereon by a bonding method or the like. To do. At this time, due to the lattice-relaxed SiGe layer 4 in the Si layer 5, sufficient tensile strain is generated in the lateral direction of the figure. Further, since the SOI layer 3 in which the dislocation 33 is generated as shown in FIG. 2A is not provided, there is no problem that the crystallinity of the strained Si layer 5 is deteriorated.

  In addition, the manufacturing method of the present invention does not require the use of a high-temperature annealing process as in the prior art in order to lattice relax the SiGe layer. For this reason, threading dislocations and the like are introduced into the SOI layer by high-temperature annealing, and they do not reach the strained Si device layer forming the channel and deteriorate the element characteristics. Therefore, in the present invention, the thickness of the SiGe layer can be made thinner than that of the prior art, and the total thickness of the SiGe layer and the Si layer on the insulating layer can be reduced to about 2/3 of the conventional thickness. . Accordingly, high-quality and sufficient strain without defects can be applied to the semiconductor device layer without losing the effect of the SOI structure.

  In the present invention, the thickness of the first semiconductor layer is 80 nm or less, the thickness of the second semiconductor layer is 10 nm or more and 50 nm or less, and the total thickness of the first semiconductor layer and the second semiconductor layer is 100 nm or less. It is desirable that Thereby, a good strained semiconductor film free from defects can be formed.

  In the semiconductor device and the semiconductor substrate of the present invention, the second semiconductor layer is Si, the first semiconductor layer has a Ge composition on the second semiconductor layer side of less than 100%, and the opposite side of the second semiconductor layer is less than 0%. A large SiGe layer is desirable. More preferably, the second semiconductor layer is Si, and the first semiconductor layer is preferably a SiGe layer having a Ge composition of at least the second semiconductor layer larger than 30 atm%.

  In the present invention, the first semiconductor layer may be a gradient composition, and the interstitial distance of the first semiconductor layer may be nonuniform in the thickness direction. For example, the first semiconductor layer is preferably a SiGe layer having a Ge composition on the second semiconductor layer side of greater than 30 atm%, and the Ge composition on the opposite side of the second semiconductor layer is preferably less than 30 atm%.

  According to the present invention, crystallinity deterioration of a device layer due to defects propagated from a strained layer as a stressor, which has been difficult in the past, is reduced, and the total thickness on the insulating layer on the SOI structure can be made thinner. Is possible. Therefore, deterioration of element characteristics can be suppressed, low power consumption and high integration can be achieved, and high performance of the semiconductor element can be realized.

Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
(First embodiment)
FIG. 3 is a cross-sectional view of a semiconductor substrate for explaining a method of manufacturing a semiconductor substrate according to the first embodiment of the present invention.

  First, as shown in FIG. 3A, a Si oxide film 2 is formed on a Si substrate 1 in advance. The Si oxide film 2 can be formed by a widely used method such as a thermal oxide film such as a dry oxide film or a wet oxide film, a CVD (Chemical Vapor Deposition) film, or a wet oxide film by solution treatment.

  Next, as shown in FIG. 3B, a SiGe layer 4 is formed in advance on another Si substrate 21. The SiGe layer 4 is basically undoped. The SiGe layer 4 must have at least a Ge composition on the Si substrate 21 side of less than 100 atm% and a Ge composition on the surface side of greater than 0 atm%. Further, it is desirable that the SiGe layer 4 is larger than 30 atm% and at least the Ge composition on the Si substrate 21 side is larger than 30 atm% for high performance. This is because when the Ge composition is larger than 30 atm%, the electron mobility in the strained Si layer can be increased. On the other hand, the Ge composition of the SiGe layer 4 is desirably 80 atm% or less.

  The SiGe layer 4 can be formed by CVD (Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), a sputtering process, or the like. When the SiGe layer 4 is formed by CVD, Si raw material gas and Ge raw material gas are introduced and stacked on the Si substrate 21 heated to, for example, 550 ° C.

  Next, the upper surfaces 2 s of the Si oxide film 2 and the upper surface 4 s of the SiGe layer 4 are aligned, and the substrates 1 and 21 are bonded together. As an example of the bonding method, pre-annealing of about several hundred degrees (for example, 400 to 700 ° C.) and high temperature annealing (for example, 1100 ° C. for 1 hour in nitrogen) for strengthening the bonding surface are performed. In this process, since the lattice relaxation of the SiGe layer 4 is not performed, no dislocation occurs.

  Next, as shown in FIG. 3C, the Si substrate 21 is peeled off. At this time, the compressive strain received from the Si substrate 21 is released and the SiGe layer 4 is lattice-relaxed.

  At this time, if the Si layer 5 on the surface of the Si substrate 21 is left extremely thin, the SiGe layer 4 is lattice-relaxed and tensile strain is introduced into the Si layer 5 at the same time. By doing so, a good strained Si layer 5 free from dislocations, pits and protrusions can be formed.

  Thus, the Si substrate 1, the Si oxide film 2 formed on the Si substrate 1, the lattice relaxed SiGe layer 4 formed on the Si oxide film 2 by bonding, and the lattice relaxed SiGe layer 4 A semiconductor substrate made of the strained Si layer 5 formed on is formed.

  The Si oxide film 2 and the lattice-relaxed SiGe layer 4 are substantially in direct contact with each other, but an interface buffer layer of 0 to 5 nm, preferably 0 to 2 nm may be provided at the interface. An example of the interface buffer layer is one made of Si.

  It is also possible to form the strained Si layer 5 by extending the polishing or peeling process up to the SiGe layer 4, first relaxing the lattice of the SiGe layer 4, and then re-growing the silicon layer very thinly by MBE or CVD. .

  Thus, in order to relax the lattice of the SiGe layer 4 by removing the Si substrate 21 on which the SiGe layer 4 has been formed in advance, the thickness of the strained Si layer 5 formed on the SiGe layer 4 is 10 nm to 80 nm. It is desirable that the total thickness of the SiGe layer 4 and the strained Si layer 5 be 10 to 50 nm and 30 to 100 nm. Thereby, a good strained semiconductor film free from defects can be formed.

  Further, the removal or thinning of the Si substrate 21 is performed by polishing, for example, chemical polishing or chemical mechanical polishing for reducing the thickness using a chemical solution or an abrasive, or PACE (plasma assisted chemical) that can improve the uniformity of the thickness after the thinning. (dry etching) method or the like may be used. Alternatively, a hydrogen peeling method in which hydrogen is injected into the SiGe layer 4 or the Si substrate 21 in advance and then peeled off from the surface where hydrogen is injected, or a thinning method in which the Si substrate 21 is oxidized and then peeled off with an HF solution or the like may be used. .

  In the present invention, when the SiGe thin film 4 having a sufficiently thin thickness of, for example, 50 nm is formed on the Si substrate 21 before the bonding process, the SiGe layer 4 exists as a layer to which compressive strain is applied. However, the effect of applying strain from the Si substrate 21 to the SiGe layer 4 is reduced by thinning or peeling the Si substrate 21 after the compression of the compressed SiGe layer 4. Thus, the SiGe layer 4 can release the strain. As a result, it functions as a stressor that applies strain to the Si device layer, which is the object of the present invention.

  The position at which the Si substrate 21 is removed varies depending on process specifications such as the thickness and crystallinity of the Si substrate 21. At this time, for example, when a peeling process after solution etching or hydrogen injection is used, the surface after peeling may be roughened. In particular, in the PACE method, defects due to the process may be introduced from the surface.

  In these cases, when a thin film is annealed in an atmosphere of, for example, hydrogen, argon, nitrogen, oxygen, etc., and a process for recovering the crystal surface or the crystal inside of the Si substrate 21 is added, a more uniform and higher quality is achieved. Realizes a thin film process.

  As the Si substrate 1 and the Si substrate 21, a CZ, FZ, MCZ substrate or the like is used. In particular, when the surface of the Si substrate 21 is used as it is as a Si device layer after thinning or peeling, it is effective to use an FZ substrate with less oxygen precipitation for improving crystallinity.

  It is also possible to make a desired resistance value in advance on the surface of the Si substrate 21 by selecting the density and type of impurities in the Si substrate 21.

  The SOI structure having the strained Si device layer 5 having a desired thickness formed as described above has a total thickness on the Si oxide film insulating layer 2 of about 2/3 as compared with the semiconductor substrate shown in FIG. It is possible to make it thinner. Further, the dislocation density appearing on the surface of the SiGe layer 4 is reduced by 10% or more, and a higher quality strained Si device layer 5 can be formed.

  FIG. 12 is a cross-sectional view of a MISFET (MOSFET) formed in the strained silicon layer 5 described above. This MISFET is formed as follows. First, the surface of the strained Si layer 5 is thermally oxidized to form a thin gate oxide film 101 having a thickness of about 10 nm. Next, for example, n-type impurity ions for adjusting the threshold voltage are implanted into the channel region through the gate oxide film 101 to form an n-type channel region.

  Next, after the polysilicon film 2 to be the gate electrode 102 is formed on the gate oxide film 101 by the low pressure CVD method, the polysilicon film is patterned by RIE (Reactive Ion Etching) to form the gate electrode 102.

  Next, n-type impurity ions such as phosphorus ions are selectively implanted using the gate electrode 102 as a mask, and then annealed at, for example, about 800 ° C., so that the n-type source region 103 and the n-type drain region 104 are gated. It is formed on the electrode 102 in a self-aligning manner. An n-channel MISFET is formed in this way, but a p-channel MISFET can be formed in the same manner by changing the impurity to p-type.

  Since the MISFET formed as described above is formed in the strained Si layer, electron scattering in the channel region is suppressed and the electron mobility is improved. In addition, since the MISFET is formed in a thin SOI layer having a thickness of 100 nm or less, parasitic capacitance is reduced in addition to improvement in electron mobility. As a result, a MISFET excellent in driving force can be obtained.

(Second Embodiment)
FIG. 4 is a sectional view showing a method for manufacturing a semiconductor substrate according to a second embodiment of the present invention.

  In the present embodiment, an epitaxial Si layer 6 is formed on a Si substrate 21 and then a SiGe layer 4 is laminated, and a Si oxide film 9 is formed on the SiGe layer 4 is used as one of the bonded substrates.

  First, as shown in FIG. 4A, a Si oxide film 2 is formed on a Si substrate 1 in advance as in the first embodiment.

  Next, as shown in FIG. 4B, a Si layer 6 that will be an element formation layer is formed in advance on another Si substrate 21 by an epitaxial method, and a SiGe layer 4 is formed on this Si layer 6 as in the first embodiment. Is done. The SiGe layer 4 is basically undoped. The SiGe layer 4 must have at least a Ge composition on the Si layer 6 side of less than 100 atm% and a Ge composition on the opposite side of the Si layer 6 of greater than 0 atm%. Furthermore, it is desirable that the SiGe layer 4 has at least the Si layer 6 side, and more desirably the entire Ge composition is larger than 30 atm% for high performance. This is because when the Ge composition is larger than 30 atm%, the electron mobility in the strained Si layer can be increased. On the other hand, the Ge composition of the SiGe layer 4 is desirably 80 atm% or less.

  Thereafter, a Si oxide film 9 is formed on the SiGe layer 4.

  Next, as shown in FIG. 4C, the two Si substrates 1 and 21 are bonded together in the same manner as in Example 1 together with the upper surface 2s of the Si oxide film 2 and the upper surface 9s of the Si oxide film 9. As a result, as shown in FIG. 4C, the Si oxide film 2 and the Si oxide film 9 are integrated into a Si oxide film 12. After bonding, the Si substrate 12 is peeled off.

  When peeling is performed by hydrogen injection after bonding, hydrogen is injected into the interface between the Si layer 6 and the Si substrate 21 or the Si layer 6 side, and then the Si substrate 21 is peeled off. By doing so, the compressive strain received from the Si substrate 21 is released, and the SiGe layer 4 is lattice-relaxed, and at the same time, strain is introduced into the Si layer 6 serving as an element formation layer.

  Thus, the Si substrate 1, the Si oxide film 12 formed on the Si substrate 1, the lattice relaxed SiGe layer 4 formed on the Si oxide film 12 by bonding, and the lattice relaxed SiGe layer 4 A semiconductor substrate composed of the strained Si layer 6 formed thereon is formed.

  The strained Si layer 6 thus formed realizes an ideal thin film layer having a desired resistance value with less oxygen precipitation and impurities contained in the CZ substrate.

  The Si oxide film 2 and the lattice-relaxed SiGe layer 4 are substantially in direct contact with each other, but an interface buffer layer of 0 to 5 nm, preferably 0 to 2 nm may be provided at the interface. An example of the interface buffer layer is one made of Si.

  In the second embodiment, since the Si layer 6 serving as an element formation layer can be formed in advance so as to exhibit desired electrical characteristics, a regrowth process is not required. Further, after the SiGe layer 4 is formed, the influence on the SiGe layer 4 can be further reduced by forming the silicon oxide film 9 and bonding the oxide films 2 and 9 together.

  In addition, when the process is performed continuously in the atmosphere other than the case where the process proceeds continuously in a clean atmosphere, for example, an oxide film is formed on the SiGe layer 4 and is not intended. In addition, the silicon oxide film 9 in FIG. 4B may be formed.

  Thereafter, as in the first embodiment, the MISFET shown in FIG. 12 is formed in the strained Si layer. Also in the second embodiment, a MISFET with excellent driving force can be obtained.

(Third embodiment)
FIG. 5 is a cross-sectional view of a semiconductor substrate showing stepwise a method of manufacturing a semiconductor substrate according to a third embodiment of the present invention.

  The third embodiment is that the SiGe layer 7 shown in FIG. 5C has a composition distribution in the film thickness direction. That is, as shown in FIG. 6, crystal growth is performed so that the Ge concentration in the SiGe layer 7 is low on the Si substrate 1 side and high on the strained Si layer 8 side. Thereby, the interstitial distance of the SiGe layer 7 becomes non-uniform in the thickness direction.

  At this time, the Ge composition on the Si substrate 1 side needs to be higher than 0%, and the Ge composition on the Si layer 8 side needs to be less than 100 atm%. Specifically, the SiGe layer is such that the Ge concentration on the Si substrate 1 side is higher than 0 atm% and 30 atm% or lower, and the Ge concentration on the strained Si layer 8 side is higher than 30 atm% and lower than 100 atm%, more preferably 80 atm% or lower. It is desirable to control the Ge composition in 7.

  By controlling the composition of the SiGe layer 7 in this way, dislocations generated from the interface between the Si oxide film 2 and the SiGe layer 7 proceed so as to form a loop in the SiGe layer 7, and the SiGe layer 7 and the strained Si layer It does not reach the interface of 8. Therefore, a better strained Si layer 8 can be provided.

  A method for manufacturing a semiconductor substrate will be described below.

  First, as shown in FIG. 5A, a Si oxide film 2 is formed on a Si substrate 1 in advance as in the first embodiment.

  Next, as shown in FIGS. 5B and 6, the SiGe layer 7 is formed on the Si substrate 21. The Ge composition at this time was controlled so that the Ge composition gradually decreased from the Si substrate 21 as described above.

  Next, the two Si substrates 21 are bonded together in the same manner as in the first embodiment so that the upper surface 2s of the Si oxide film 2 and the upper surface 7s of the SiGe layer 7 are aligned.

  Next, as in the first embodiment, the Si substrate 21 is peeled off, and the SiGe layer 7 is lattice-relaxed.

  At this time, if the Si layer on the surface of the Si substrate 21 is left very thin, the SiGe layer 4 is lattice-relaxed and tensile strain is introduced into the Si layer 8 at the same time. By doing so, a good strained Si layer 8 free from dislocations, pits and protrusions can be formed.

  In this way, the Si substrate 1, the Si oxide film 2 formed on the Si substrate 1, the lattice-relaxed SiGe layer 7 formed on the Si oxide film 2 by bonding and the composition of Ge gradually changed, A semiconductor substrate composed of the strained Si layer 8 formed on the lattice-relaxed SiGe layer 7 is formed.

  The Si oxide film 2 and the lattice-relaxed SiGe layer 7 are substantially in direct contact with each other, but may have an interface buffer layer of 0 to 5 nm, preferably 0 to 2 nm at the interface. An example of the interface buffer layer is one made of Si.

  It is also possible to form the strained Si layer 8 by extending the polishing or peeling process to the SiGe layer 7, first relaxing the lattice of the SiGe layer 7, and then re-growing the silicon layer very thinly by MBE or CVD. .

  In this embodiment, since the Ge concentration in the SiGe layer 7 is lower as it is closer to the Si oxide film 2, defects generated at the interface between the Si oxide film 2 and the SiGe layer 7 are confined to the Si oxide film 2 side. A lattice-relaxed SiGe layer is obtained at the interface between the bonded SiGe layer 7 and the strained Si layer 8. As a result, a strained Si layer 8 having tensile strain is formed on the SiGe layer 7 that has been satisfactorily relaxed.

  In addition, the degree of relaxation differs depending on the thickness of each layer in the figure, annealing temperature, annealing time, thickness of the Si substrate layer 21 left by peeling or polishing after bonding, and depending on the process conditions, the compression ratio strain may be It is also possible to form a Si device layer without distortion.

Thereafter, as in the first embodiment, the MISFET shown in FIG. 12 is formed in the strained Si layer. Also in the third embodiment, a MISFET excellent in driving force can be obtained.
(Fourth embodiment)
FIG. 7 is a sectional view showing a method for manufacturing a semiconductor substrate according to a fourth embodiment of the present invention.

  In the fourth embodiment, the Ge concentration in the SiGe layer 7 on the Si substrate 21 shown in FIG. 7B has a concentration gradient in the film thickness direction as shown in FIG. 8, and the portion with the highest Ge concentration is not an interface. Located in the film of the SiGe layer 7. Thereafter, a peeling or thinning process is performed so that a portion with a high Ge concentration gradient becomes the surface, and the surface indicated by the dotted line in FIGS. 7B and 8 becomes the upper surface 7s of the thinned SiGe layer 7. In the semiconductor substrate shown in FIG. 7C obtained by using the substrate in which the composition of the SiGe layer 7 is controlled in this way, the dislocation generated from the interface between the Si oxide film 2 and the SiGe layer 7 ′ has a loop in the SiGe layer 7. It proceeds to form, and does not reach the interface between the SiGe layer 7 ′ and the strained Si layer 8. Therefore, a better strained Si layer can be provided.

  Furthermore, since the crystal growth of the SiGe layer 7 before bonding starts from a low Ge concentration on the Si substrate 21, defects due to mismatching are hardly introduced and a SiGe layer 7 ′ having good crystallinity is obtained.

  Hereinafter, a method for manufacturing a semiconductor substrate will be described.

  First, as shown in FIG. 7A, a Si oxide film 2 is previously formed on a Si substrate 1 in the same manner as in the first embodiment.

  Next, as shown in FIGS. 7B and 8, the SiGe layer 7 is previously formed on the Si substrate 21 so that the Ge composition ratio is 0 atm% → 35 atm% → 0 atm% in the film direction. Subsequently, the SiGe layer 7 'is formed by thinning the film to the central portion where the Ge composition ratio of SiGe7 is the highest. As a result, a surface having a Ge composition ratio of 35 atm% is exposed on the upper surface 7s of the SiGe layer 7 '.

  Next, the two Si substrates 1 and 21 are bonded together in the same manner as in the first embodiment so that the upper surface 2s of the Si oxide film 2 and the upper surface 7 of the SiGe 7 'are aligned. Subsequently, similarly to the first embodiment, the Si substrate 21 is removed, and the lattice relaxation of the SiGe layer 7 'is performed. At this time, if the Si layer on the surface of the Si substrate 21 is left very thin, the SiGe layer 4 is lattice-relaxed and tensile strain is introduced into the Si layer 8 at the same time. By doing so, a good strained Si layer 8 free from dislocations, pits and protrusions can be formed.

  In this way, the Si substrate 1, the Si oxide film 2 formed on the Si substrate 1, the lattice-relaxed SiGe layer 7 formed on the Si oxide film 2 by bonding and the composition of Ge gradually changed, Then, a semiconductor substrate composed of the strained Si layer 8 formed on the lattice-relaxed SiGe layer 7 'is formed. Thereby, the same effect as the third embodiment can be obtained.

  The Si oxide film 2 and the lattice-relaxed SiGe layer 7 'are substantially in direct contact with each other, but may have an interface buffer layer of 0 to 5 nm, preferably 0 to 2 nm at the interface. An example of the interface buffer layer is one made of Si.

  It is also possible to form the strained Si layer 8 by extending the polishing or peeling process to the SiGe layer 7, first relaxing the lattice of the SiGe layer 7, and then re-growing the silicon layer very thinly by MBE or CVD. .

  Thereafter, the MISFET shown in FIG. 12 is formed in the strained Si layer 8 as in the first embodiment. Also in the fourth embodiment, a MISFET excellent in driving force can be obtained.

(Fifth embodiment)
FIG. 9 is a cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor substrate according to a fifth embodiment of the present invention.

  In the fifth embodiment, a SiGe layer including a lattice-relaxed SiGe layer 40 into which dislocations are introduced and a lattice-relaxed SiGe layer 11 is formed on a Si substrate 21. The SiGe layer 40 is a sufficiently thick layer whose Ge concentration changes with crystal growth, and serves as a so-called buffer layer. For example, the SiGe buffer layer 40 has a structure in which the Ge concentration on the Si substrate 21 is 0 atm%, the Ge concentration increases with crystal growth, and has a gradient composition in which the Ge concentration becomes 30 atm% at a thickness of 2 μm.

  A method for manufacturing a semiconductor substrate will be described below.

  First, as shown in FIG. 9A, a Si oxide film 2 is formed on a Si substrate 1 in advance as in the first embodiment.

  Next, as shown in FIG. 9B, the SiGe buffer layer 40 having the Ge composition as described above is formed on another Si substrate 21 to be sufficiently thick, and the lattice is relaxed. At this time, dislocations 33 are generated in the SiGe buffer layer 4 but are sufficiently thick so that the semiconductor layer formed thereon is not affected. Next, the SiGe layer 11 having a good crystal state and a lattice relaxation is formed on the lattice relaxed SiGe buffer layer 4. The growth method of each layer of SiGe follows the first embodiment.

  Next, the two Si substrates 1 and 21 are bonded together in the same manner as in the first embodiment so that the upper surface 2s of the Si oxide film 2 and the upper surface 11s of the lattice-relaxed SiGe layer 11 are aligned.

  Next, the Si substrate 21 and the SiGe buffer layer 40 are removed by polishing or hydrogen implantation. Next, a strained Si layer 8 is formed on the lattice-relaxed SiGe layer 11. (FIG. 9C) Thus, the Si substrate 1, the Si oxide film 2 formed on the Si substrate 1, the lattice-relaxed SiGe layer 11 formed on the Si oxide film 2 by bonding, and the lattice A semiconductor substrate comprising the strained Si layer 8 formed on the relaxed SiGe layer 11 is formed.

  In the SiGe buffer layer 40, defects such as threading dislocations and misfit dislocations caused by lattice mismatch are confined on the Si substrate 21 side in the SiGe buffer layer 40. As a result, on the surface side of the SiGe buffer layer 40, a lattice-relaxed SiGe layer without dislocation is realized.

  The surface-side Ge concentration of the SiGe buffer layer 40 is such that a desired strain is applied to the Si device layer, and is typically greater than 30 atm% and less than or equal to 80 atm%. The distribution need not be uniform. Subsequent to the formation of the SiGe layer 40, the SiGe layer 11 having a composition equivalent to the composition on the surface side of the SiGe buffer layer 4 is grown, whereby the high-quality relaxed SiGe layer 11 with reduced defect density such as dislocation is formed. The

  The problem here is that the crystal growth of the SiGe layer 40 having a thickness of several μm as the buffer layer requires raw materials, growth time, and process cost. As described above, the laminated structure of the strained channel layer and the relaxed SiGe layer can be realized by the thinning process after bonding. However, hydrogen injection may be performed at 40c (FIG. 9B) with a depth cut surface of about 0.3 μm, for example, so that a SiGe layer having a desired thickness is obtained before pasting, and peeling may be performed after pasting. In this way, since the lattice-relaxed SiGe buffer layer remaining after peeling can be reused, the process can be simplified, semiconductor resources can be saved, and the substrate manufacturing cost can be reduced.

  Thereafter, the MISFET shown in FIG. 12 is formed in the strained Si layer 8 as in the first embodiment. Also in the fifth embodiment, a MISFET excellent in driving force can be obtained.

(Sixth embodiment)
FIG. 10 is a cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor substrate according to a sixth embodiment of the present invention.

  In the sixth embodiment, the lattice-relaxed SiGe buffer layer 40 into which dislocations are introduced on the Si substrate 21 shown at time 10B, the lattice-relaxed SiGe layer 11, the strained Si layer 10, and another lattice on the lattice-relaxed SiGe buffer layer 40. After the relaxed SiGe layer 13 is continuously formed, a bonding process is performed.

  First, as shown in FIG. 10A, a Si oxide film 2 is formed on a Si substrate 1 in advance as in the first embodiment.

  Next, as shown in FIG. 10B, similarly to the fifth embodiment, a thick SiGe buffer layer 40 is formed on another Si substrate 21 in advance to relax the lattice. On the lattice-relaxed SiGe buffer layer 40, the lattice-relaxed SiGe layer 11, the strained Si layer 10, and the lattice-relaxed SiGe layer 13 are continuously grown.

  Next, as shown in FIG. 6C, the Si substrates 1 and 21 are bonded together in the same manner as in the first embodiment so that the upper surface 2s of the Si oxide film 2 and the upper surface 13s of the lattice relaxation SiGe film 13 are aligned.

  Next, the Si substrate 21, the lattice-relaxed SiGe buffer layer 40, and the lattice-relaxed SiGe layer 11 are removed by polishing or hydrogen implantation so that the strained Si layer 10 comes to the surface. (FIG. 10C) Thus, the Si substrate 1, the Si oxide film 2 formed on the Si substrate 1, the lattice relaxation SiGe layer 13 formed on the Si oxide film 2 by bonding, and the lattice relaxation. A semiconductor substrate composed of the strained Si layer 10 formed on the SiGe layer 13 is formed.

  In this embodiment, the Si layer 10 on the lattice-relaxed SiGe layer 11 formed on the Si substrate 21 is naturally subjected to tensile strain, and the SiGe layer 13 thereon is a relaxed layer.

  In order to reduce defects generated from the interface between the insulating layer 2 and the SiGe layer 13 after bonding, the lattice-relaxed SiGe layer 13 can be applied with a gradient in the Ge composition as in the third or fourth embodiment. Good.

  In addition, as in the second embodiment, the insulating layer 9 may be formed in advance on the lattice-relaxed SiGe layer 13 and then bonded.

  In the sixth embodiment, the strained Si layer 10 can be directly formed on the SiGe layer 13 having a high relaxation rate, and the Ge concentration in the lattice relaxed SiGe layer 13 is greater than 30 atm% and greater than 100 atm%. The thickness of the SiGe layer 13 and the strained Si device layer 10 on the insulating layer 2 can each be 10 nm or less.

  As a result, the total thickness on the insulating film 2 can be easily suppressed to 40 nm or less, the SOI effect can be sufficiently achieved, and sufficient strain can be applied to the Si device layer 10.

  Thereafter, as in the first embodiment, the MISFET excellent in driving force can also be obtained in the sixth embodiment.

(Seventh embodiment)
FIG. 11 is a cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor substrate according to a seventh embodiment of the present invention.

  In this embodiment, a SiGe substrate 31 is used instead of the Si substrate 21 as one of the bonded substrates, and the lattice-relaxed SiGe layer 11, the strained Si layer 10, the lattice-relaxed SiGe layer 13, and the Si oxide that are regrown on the SiGe substrate 31. The structure in which the film 9 is formed will be described.

  First, as shown in FIG. 11A, a Si oxide film 2 is formed on a Si substrate 1 in advance as in the first embodiment.

  Next, as shown in FIG. 11B, the SiGe layer 11 is formed in advance on the SiGe substrate 31 as in the first embodiment, and the Si layer 10 and the SiGe layer 13 (on the Si layer 10 side) are formed on the SiGe layer 11. The Si oxide film 9 is continuously grown with a Ge composition of greater than 30 atm%).

  Next, the Si substrate 1 and the SiGe substrate 31 are bonded together in the same manner as in the first embodiment so that the upper surface 2s of the Si oxide film 2 and the upper surface 9s of the Si oxide film 9 are aligned. Next, the SiGe substrate 31 and the SiGe layer 11 are removed by polishing or hydrogen injection so that the Si layer 10 comes to the surface.

  In this way, as shown in FIG. 11C, the Si substrate 1, the Si oxide film 12 formed on the Si substrate 1, the lattice-relaxed SiGe layer 13 formed by bonding on the Si oxide film 12, and this A semiconductor substrate made of the strained Si layer 10 formed on the lattice-relaxed SiGe layer 13 is formed.

  In this case, at least one of the Si oxide film 2 or the Si oxide film 9 is sufficient for bonding. Further, in order to obtain an effect of confining defects that may be generated from the bonding surface between the SiGe layer 13 and the insulating layer 9 during the bonding process, the thinning process, or the peeling process, the Ge concentration in the SiGe layer 13 in contact with the insulating layer is set to be lower. It should be non-uniform.

  In the present embodiment, the case where the substrate 31 has the same SiGe composition as that of the layer 11 serving as a stressor is shown, but it is also possible to set the desired concentration by performing composition control in the layer formed on the substrate. .

  Thereafter, the MISFET shown in FIG. 12 is formed in the strained Si layer 10 as in the first embodiment. Also in the sixth embodiment, a MISFET having an excellent driving force can be obtained.

In the first to seventh embodiments, the case where the strain applying layer (first semiconductor layer) is the SiGe layer and the device layer (second semiconductor layer) is the Si layer has been described. What kind of crystal can be used as long as the combination of two layers having different lattice constants so that the lattice constant of the second semiconductor layer is smaller than the lattice constant of the first semiconductor layer so that tensile strain is generated in the semiconductor layer? Specifically, Si, GaAs, SiC, GaN, GaAlAs, InGaP, InGaPAs, Al ₂ O ₃ , BN, BNC, C, Si (impurity B), Si (impurity doped at a high concentration) The effect of the present invention can be obtained by a combination of two kinds of substances such as P), Si (impurity As), SiNx, and ZnSe. However, the concentration of B contained in the first semiconductor layer is preferably less than 1 × 10 ²⁰ .

  In the first to seventh embodiments, Si substrates and SiGe substrates are used as the substrates 1, 21, and 31, but any one of GaAs, ZnSe, SiC, Ge, sapphire, organic glass, inorganic glass, and plastic is used. It may be.

  In the first to seventh embodiments, Si oxide films are used as the insulating films 2 and 9, but other insulating films such as a silicon oxynitride film and a silicon nitride film may be used.

The board | substrate sectional drawing for demonstrating the manufacturing method of the conventional semiconductor substrate. The board | substrate sectional drawing for demonstrating this invention and the manufacturing method of the conventional semiconductor substrate. The board | substrate sectional drawing for demonstrating the manufacturing method of the semiconductor substrate of this invention. The board | substrate sectional drawing for demonstrating the manufacturing method of the semiconductor substrate of this invention. The board | substrate sectional drawing for demonstrating the manufacturing method of the semiconductor substrate of this invention. The figure which shows Ge composition of the SiGe layer in the semiconductor substrate of this invention. The board | substrate sectional drawing for demonstrating the manufacturing method of the semiconductor substrate of this invention. The figure which shows Ge composition of the SiGe layer in the semiconductor substrate of this invention. The board | substrate sectional drawing for demonstrating the manufacturing method of the semiconductor substrate of this invention. The board | substrate sectional drawing for demonstrating the manufacturing method of the semiconductor substrate of this invention. The board | substrate sectional drawing for demonstrating the manufacturing method of the semiconductor substrate of this invention. 4 is a cross-sectional view of an element for explaining a semiconductor device of the present invention. FIG.

Explanation of symbols

1 .... Si substrate 2 .... Insulating layer (Si oxide layer)
3 ... SOI layer 4 ... SiGe layer 5 ... strained Si layer 6 ... strained epitaxial Si layer 7 ... gradient composition SiGe layer 8 ... formed by regrowth Strained Si layer 9 ・ ・ ・ Insulating layer 10 ・ ・ ・ Strained Si layer 11 ・ ・ ・ SiGe layer 12 ・ ・ ・ Insulating layer 13 ・ ・ ・ SiGe layer 21 ・ ・ ・ Si substrate 31 ・ ・ ・・ SiGe substrate 33 ・ ・ ・ ・ dislocation

Claims (10)

Forming an insulating film on the surface of the first semiconductor substrate;
Forming a first semiconductor layer on a second semiconductor substrate surface;
Bonding the insulating film formed on the surface of the first semiconductor substrate and the first semiconductor layer formed on the surface of the second semiconductor substrate;
A part of the second semiconductor substrate is removed, the first semiconductor substrate, the insulating film, the lattice-relaxed first semiconductor layer, and the second semiconductor substrate to which a tensile lattice strain is applied Forming a stack of the remainder, and
A method for manufacturing a semiconductor substrate, comprising:   2. The first semiconductor substrate is a first Si substrate, the first semiconductor layer is a SiGe layer, and the second semiconductor substrate is a second Si substrate. Semiconductor substrate manufacturing method.   The first semiconductor substrate is a first Si substrate, the second semiconductor substrate is a second Si substrate, and the first semiconductor layer is a SiGe layer having a Ge concentration gradient in the film thickness direction. 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the Ge concentration decreases as the distance from the second Si substrate increases.   The first semiconductor substrate is a first Si substrate, the second semiconductor substrate is a second Si substrate, and the first semiconductor layer is a SiGe layer having a Ge concentration gradient in the film thickness direction. After forming on the second Si substrate so that the portion with high Ge concentration is in the film, it is formed by peeling or thinning so that the portion with high Ge concentration becomes the surface. The method for manufacturing a semiconductor substrate according to claim 1. Forming a first insulating film on the surface of the first semiconductor substrate;
Sequentially forming a first semiconductor layer and a second insulating film on a second semiconductor substrate;
Bonding a first insulating film formed on the surface of the first semiconductor substrate and a second insulating film formed on the second semiconductor substrate via the first semiconductor layer; ,
A part of the second semiconductor substrate is removed, and the first semiconductor substrate, the first and second insulating films, the lattice-relaxed first semiconductor layer, and the tensile lattice strain are applied. Forming a laminated substrate of the remaining part of the second semiconductor substrate;
A method for manufacturing a semiconductor substrate, comprising: The first semiconductor substrate is a Si substrate, the first semiconductor layer is a SiGe layer, and the second semiconductor substrate is a Si substrate having an Si layer formed by an epitaxial method formed on an upper surface. 6. The method of manufacturing a semiconductor substrate according to claim 5 , wherein: Forming an insulating film on the surface of the first semiconductor substrate;
Forming a first semiconductor layer on a second semiconductor substrate surface;
Bonding the insulating film formed on the surface of the first semiconductor substrate and the first semiconductor layer formed on the surface of the second semiconductor substrate;
Removing a second semiconductor substrate to form a stack of the first semiconductor substrate, the insulating film, and the lattice-relaxed first semiconductor layer;
Forming a second semiconductor layer to which a tensile lattice strain is applied on the first semiconductor layer;
A method for manufacturing a semiconductor substrate, comprising: The first semiconductor substrate is a first Si substrate, the first semiconductor layer is a SiGe layer, the second semiconductor substrate is a second Si substrate, and the second semiconductor layer is Si 8. The method of manufacturing a semiconductor substrate according to claim 7 , wherein the method is a layer. The first semiconductor substrate is a first Si substrate, the second semiconductor substrate is a second Si substrate, and the first semiconductor layer is a SiGe layer having a Ge concentration gradient in the film thickness direction. 8. The method of manufacturing a semiconductor substrate according to claim 7 , wherein the Ge concentration decreases as the distance from the second Si substrate increases, and the second semiconductor layer is a Si layer. The first semiconductor substrate is a first Si substrate, the second semiconductor substrate is a second Si substrate, and the first semiconductor layer is a SiGe layer having a Ge concentration gradient in the film thickness direction. After forming on the second Si substrate so that the portion with high Ge concentration is in the film, it is formed by peeling or thinning so that the portion with high Ge concentration becomes the surface. 8. The method of manufacturing a semiconductor substrate according to claim 7 , wherein the second semiconductor layer is a Si layer.

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