JP4217287B2 - TFT array substrate and liquid crystal display device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a TFT array substrate on which a thin film transistor is mounted as a switching element, and a liquid crystal display device using the same.In placeIt is related.
[0002]
[Prior art]
  FIG. 13A is a plan view of a gate layer of a TFT array substrate constituting a conventional liquid crystal display device adopting a common auxiliary capacitance method. In the figure, 2 is a gate electrode and wiring, 4 is an auxiliary capacitance electrode, and 19 is a common wiring. In a conventional common auxiliary capacitance type liquid crystal display device aiming at a high aperture ratio, gate electrodes and wirings 2 and common wirings 19 are alternately arranged, and branch-like auxiliary capacitance electrodes 4 are connected to the common wirings 19. ing. The auxiliary capacitance electrode 4 has two roles. One is the role of an electrode for forming an auxiliary capacitor in parallel with the pixel capacitor and holding the charge of the pixel, and the second is the vicinity of the source line due to liquid crystal alignment failure caused by the electric field from the source electrode. It is a role to prevent light leakage. The means for preventing leakage of light using the auxiliary capacitance electrode 4 is effective in increasing the aperture ratio because it can use a photoengraving technique with much higher alignment accuracy than the case of using a light shielding film on the counter substrate. Means. As another conventional method, as shown in FIG. 14A, an auxiliary capacitance on-gate type in which the role of the common wiring 19 is also used by the adjacent gate electrode and the wiring 2 is used quite generally. In this case, the auxiliary capacitance electrode 4 is connected to the adjacent gate electrode and the wiring 2. This method is further advantageous in terms of increasing the aperture ratio. FIGS. 13B and 14B are plan views of the TFT array substrate using the respective gate layer structures when the array process is completed.
[0003]
  Hereinafter, the manufacturing process of the conventional TFT array substrate will be described with reference to the drawings. FIG. 15 is a cross-sectional view showing a manufacturing process of a TFT array substrate adopting the common auxiliary capacitance method shown in FIG. First, a metal film such as a Cr film is formed as a single layer on a glass substrate 1 which is a transparent insulating substrate, resist patterning, etching of the metal film is performed, and the gate electrode and wiring 2 and the common wiring 19 are formed. It is formed (FIG. 15 (a)). Next, a gate insulating film 5, an amorphous silicon film 6, and an n + type amorphous silicon film 7 made of a silicon nitride film are continuously formed by plasma CVD or the like. Further, in order to form a channel portion of the transistor, the amorphous silicon film 6 and the n + -type amorphous silicon film 7 are patterned in an island shape (FIG. 15B). Next, the pixel electrode 8 is formed with a transparent conductive film such as ITO (FIG. 15C), and the source electrode 11 and the drain electrode 12 are formed (FIG. 15D). In this case, Cr or Ti is used for the lower layer as a barrier metal in order to improve the ohmic contact with the semiconductor layer, and a low resistance such as a pure Al film or a single layer film of Al alloy is used for lower resistance in the upper layer. A two-layer film using a metal film is used. Further, in order to prevent corrosion of the ITO film by the developer during photolithography, tungsten or the like may be added as an impurity as an Al alloy. Finally, in order to protect the TFT, it is covered with an insulating film 13 such as a silicon nitride film (FIG. 15E). FIG. 15 (e) corresponds to the cross section AB of FIG. 13 (b).
[0004]
[Problems to be solved by the invention]
  In the liquid crystal display device aiming at high aperture ratio as described above, the signal wiring is proceeding in the direction of thinning. With the thinning of the wiring, the probability of occurrence of disconnection due to foreign matters generated in the process, etching failure due to reduced adhesion of the resist, and the like has increased. FIG. 16 shows a disconnection 14 that occurs in a normal gate layer. Furthermore, in order to apply to monitors, etc., the demand for larger panels and higher definition is increasing year by year. The length and number of signal wires are increasing, and the panel can be installed without causing disconnection 14. It has become difficult to form. Since the disconnection 14 in the gate layer is difficult to repair using redundant wiring provided outside the image display portion, it becomes a linear display defect and becomes a defective product. For this reason, the reduction of the disconnection 14 of the gate wiring 2 has become one of the important issues for improving the manufacturing yield.
  As the gate wiring 2 is made thinner and longer, the use of a low-resistance material such as Al, Al alloy, or Mo as the wiring material is increasing. Since many of these materials have weak chemical resistance, there is a problem that in addition to the disconnection due to the above-described foreign matter and resist adhesion reduction, disconnection due to corrosion occurs when the pixel electrode 8 and the source wiring 11 are formed. It was. Since these have a very high incidence rate compared to the above-mentioned disconnection due to the foreign matter, a decrease in adhesion, etc., they are difficult to manufacture. For this reason, these low-resistance materials are not used alone, but are used with a device such as covering with an insulating film with few defects such as a metal film or an anodized film to prevent corrosion of the film. It was.
[0005]
  In recent years, in order to solve such a problem of gate disconnection, a method as shown in FIG. 17 (a) has been devised (reference: SSKim et al., SID 95 DIGEST, pp. 15-18). . This method employs a ladder-like wiring structure in which the gate electrode / wiring 2 and the redundant wiring 3 are connected by the auxiliary capacitance electrode 4. FIG. 17B shows a plan view of the completed array process by this method. According to this method, as shown in FIG. 18, even if a disconnection 14 occurs in the gate electrode and the wiring 2, the signal flows through the auxiliary capacitance electrode 4 and the redundant wiring 3, so that a linear display defect does not occur. However, in this structure, although the disconnection 14 is effective, since the gate electrode and the wiring 2 and the redundant wiring 3 are close to each other in the entire wiring range, a short circuit occurs due to the pattern defect 15 shown in FIG. There was a problem that the probability increased. This short circuit is also one of the important issues because it is difficult to find the short circuit and repair is difficult.
[0006]
  The present invention has been made to solve the above-mentioned problems, and prevents occurrence of linear display defects due to disconnection or short circuit of the TFT array substrate, and has a high aperture ratio and excellent display quality. To obtain a display deviceTossIs.
[0007]
[Means for Solving the Problems]
  A TFT array substrate according to the present invention includes a plurality of gate wirings formed on a transparent insulating substrate, a plurality of source wirings intersecting with the gate wirings, and thin film transistors provided at each intersection of the gate wiring and the source wiring. A pixel electrode made of a transparent conductive film connected to the gate electrode and a gate wiringAlong the both sides of the adjacent pixel electrodeAn auxiliary capacitor electrode that is a vertically extending branch electrode that forms an auxiliary capacitor with an insulating film sandwiched between a part of the pixel electrode and an adjacent gate wiringWithIt is arranged in parallel with the gate wiring so as to be located at the center, intersects the tip of the branch-shaped auxiliary capacitance electrode, and passes through the auxiliary capacitance electrode.TRedundant wiring connected to the redundant wiring, redundant wiring, and adjacent redundant wiringRugeBetween wiringAlong both sides of the pixel electrodePlaced and perpendicular to the redundant wiringAdjacentA branch-shaped pattern extending to the vicinity of the gate wiring, a part of which is provided in the periphery of the image display unit composed of the light shielding pattern and the pixel electrode, which overlaps a part of the pixel electrode. A connection terminal portion for inputting an external signal is provided.
  The light-shielding pattern is electrically connected to the redundant wiring and forms an auxiliary capacitor with an insulating film interposed between part of the pixel electrodes.
  The light shielding pattern is electrically separated from the redundant wiring.
  Further, the gate wiring, the auxiliary capacitor electrode, the light shielding pattern, and the redundant wiring are each formed of the same material and in the same layer.
[0008]
  In addition, Al, Mo, Cu, or an alloy containing these as a main component is used as a material for the gate wiring.
  In addition, an Al—Nd alloy having an Nd composition of 0.1% or more and less than 5% is used as a material for the gate wiring.
  Furthermore, any one of Cr, W, Ti, and Ta is used as a material for wiring for connecting signal wiring such as gate wiring and source wiring to the connection terminal portion.
  The redundant wiring has a line width of 2 μm or more and 10 μm or less.
  The liquid crystal display device according to the present invention is a liquid crystal display device in which liquid crystal is disposed between any of the TFT array substrates described above and a counter electrode substrate having a transparent electrode and a color filter..
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a manufacturing process of a TFT array substrate using a channel etching type amorphous silicon thin film transistor according to Embodiment 1 of the present invention, and FIG. 2 is a view showing a gate layer of the TFT array substrate according to this embodiment. It is a top view. In the figure, 1 is a glass substrate which is a transparent insulating substrate, 2 is a gate electrode and wiring, 3 is a redundant wiring arranged in parallel and alternately with the gate electrode and wiring 2, and 4 is from the gate wiring 2.Along the both sides of the adjacent pixel electrode 8It is a branch-shaped auxiliary capacitance electrode extending vertically, and the redundant wiring 3 is connected to the adjacent gate wiring 2.WithNearly centerArranged parallel to the gate wiring 2The storage capacitor electrode 4 intersects with the tip of the storage capacitor electrode 4 and is electrically connected to the adjacent one of the gate electrode and the wiring 2. 4a is between the redundant wiring 3 and the other gate wiring 2 adjacent to the redundant wiring.Along both sides of the pixel electrodePlaced in a direction perpendicular to the redundant wiring 3AdjacentThis is a light shielding pattern that is a branch-like pattern extending to the vicinity of the other gate wiring 2. Furthermore, 5 is a gate insulating film, 6 and 7 are amorphous silicon films and n + type amorphous silicon films constituting TFTs, 8 is a pixel electrode made of a transparent conductive film such as ITO, 9 is a terminal electrode, 10 is a contact hole, 11 Denotes a source electrode and a wiring intersecting with the gate wiring 2, 12 denotes a drain electrode, and 13 denotes an insulating film such as a silicon nitride film for protecting the TFT. The pixel electrode 8 is connected to a TFT provided at each intersection of a plurality of gate wirings 2 and source wirings 11, and the auxiliary capacitance electrode 4 has a gate insulating film 5 interposed between a part of the pixel electrodes 8. Auxiliary capacitance is formed by sandwiching. Further, the light shielding pattern 4a is electrically connected to the redundant wiring 3, and the pixel electrode8A storage capacitor is formed by sandwiching an insulating film between a part of the storage capacitor and also serves as a storage capacitor electrode. The auxiliary capacitance electrode 4, the light shielding pattern 4a, the redundant wiring 3, the gate electrode, and the wiring 2 are formed of the same material and in the same layer. In addition, a terminal electrode 9 which is a connection terminal portion for inputting an external signal to the gate wiring 2 and the source wiring 11 is provided around the image display portion constituted by the pixel electrodes 8.
[0010]
  A manufacturing process of the TFT array substrate in the present embodiment will be described with reference to the drawings. First, a metal film such as Cr is formed on the surface of the glass substrate 1 by sputtering to a thickness of about 400 nm. Next, resist patterning is performed using a positive resist. In this case, after exposing with a suitable exposure amount once using a mask having a line width equal to the design pattern, the area of the light shielding portion is larger than the mask again, that is, the line width is thicker than the design pattern. Then, using a mask thicker by about 3 μm, exposure is performed with an exposure energy of about 2 to 10 times the appropriate exposure amount.
  Next, a Cr film is etched using an etchant mainly composed of ceric ammonium nitrate and nitric acid, and the gate electrode and wiring 2, redundant wiring 3 and branch as shown in FIG. 1 (a) and FIG. A shaped auxiliary capacitance electrode 4 and a light shielding pattern 4a are formed. At this time, since nitric acid is contained in the etching solution, the Cr film is processed into a tapered shape, and disconnection of the upper layer when the film thickness becomes 300 nm or more can be prevented.
  Next, a gate insulating film 5, an amorphous silicon film 6, and an n + type amorphous silicon film 7 made of a silicon nitride film are successively formed by PCVD, for example, about 500 nm, 200 nm, and 50 nm, respectively. Further, in order to form a channel portion of the transistor, the amorphous silicon film 6 and the n + amorphous silicon film 7 are patterned in an island shape (FIG. 1B). Next, an ITO film is formed to a thickness of, for example, about 100 nm by sputtering, the pixel electrode 8 and the terminal electrode 9 are formed by patterning, and the contact hole 10 of the terminal portion is further formed (FIG. 1 (c)).
[0011]
  Next, a metal film composed of a three-layer film having a lowermost layer of, for example, Cr or Ti of about 100 nm, a second layer of about Al-0.2 at.% Cu of about 300 nm, and an uppermost layer of about 50 nm of Cr is formed. Then, the three-layer film is etched. Thereafter, the n + amorphous silicon film 7 on the channel is removed by dry etching to form the source electrode, the wiring 11, and the drain electrode 12, and then the resist is removed (FIG. 1 (d)). Finally, in order to protect the TFT, it is covered with an insulating film 13 such as a silicon nitride film, and the insulating film 13 on the pixel electrode 8 and the terminal electrode 9 is removed (FIG. 1 (e)). In this embodiment, a three-layer film is used as the source and drain materials. However, if no particular problem occurs in the wiring resistance, pixel electrode formation process, etc., a single-layer film such as Mo and Cr, a lower layer Cr, and an upper layer are used. A double-layer film such as an Al alloy may also be used.
[0012]
  In the present embodiment, as shown in FIG. 2, the line width of each wiring is 15 μm for the gate wiring 2, 2 μm for the redundant wiring 3, and the widths of the branch-like auxiliary capacitance electrode 4 and the light shielding pattern 4 a. The thickness was set to 6 μm, and the redundant wiring 3 was arranged so as to be located at substantially the center between the adjacent gate wirings 2. When the gate wiring 2 is disconnected, the redundant wiring 3 has a width of about 1 to 2 μm because the resistance of the redundant wiring 3 and the resistance of the entire gate wiring 2 are connected in series. In addition, since the redundant wiring 3 part is a light shielding part, it is preferable that the redundant wiring is as thin as possible from the viewpoint of increasing the aperture ratio. However, considering the etching accuracy of about 1 to 2 μm, the finished dimension is limited to about 2 μm. Therefore, by setting the width of the redundant wiring 3 to 2 μm or more and 10 μm or less, it can function as the redundant wiring 3 and the aperture ratio can be increased, and display unevenness due to crosstalk can be reduced.
[0013]
  In the TFT array substrate manufactured as described above, the gate having the redundant wiring 3 even when the disconnection 14 as shown in FIG. 3 occurs due to defects during patterning or peeling of the resist during etching. Since the layer structure is adopted, the signal can travel through the redundant wiring 3 and does not become a linear defect. Further, even when the pattern defect 15 occurs, a short circuit does not occur unless it occurs near the tip of the light shielding pattern 4a on the branch. As described above, according to the present embodiment, it is possible to reduce defects caused by disconnection and short-circuiting in the gate layer, which have frequently occurred in the past.
[0014]
  In many cases, the size of a pattern defect generated when foreign matter is mixed during photoengraving is many times larger than the actual size of foreign matter. The generation mechanism will be described with reference to FIG. In general, when the resist 17 is applied on the glass substrate 1 on which the metal thin film 22 is formed with the foreign matter 16 attached, the thickness of the resist 17 is set around the foreign matter 16 as shown in FIG. Thicker than the film thickness. Here, when exposure is performed using the mask 18 under the exposure conditions of the resist 17 having a normal film thickness, underexposure occurs in the vicinity of the foreign matter 16 (FIG. 4B), and the resist 17 remains (FIG. 4C). ). In the drawing, the hatched portion indicates the exposed resist 17a. As a result, after etching, the pattern defect 15 is several times as large as the foreign matter 16 as shown in FIG. When such a huge pattern defect 15 occurs, the probability of a short circuit near the tip of the branch-like light shielding pattern 4a increases. Therefore, by performing exposure with an exposure energy of 2 to 4 times the appropriate exposure amount, the size of the pattern defect 15 can be limited to the size of the foreign matter 16 itself.
[0015]
  FIG. 5 is a diagram showing the pattern defect size with respect to the additional exposure energy. By performing the additional exposure about twice, the pattern defect 15 becomes almost the size of the foreign matter 16 itself. FIG. 6 is a diagram for explaining the effect of reducing the pattern defect size by the additional exposure. As shown in the figure, since the thick resist 17 around the foreign material 16 is completely exposed by performing sufficient additional exposure, the size of the pattern defect 15 is reduced, and a short circuit between wirings made of the metal thin film 22 is generated. Probability can be reduced.
  FIG. 7 is a diagram showing the relationship between exposure energy and pattern thinning. In the figure, A shows the relationship between irradiation energy and pattern thinning when additional exposure is performed using a normal mask pattern and B is additional exposure using a mask pattern that is 3 μm thicker than the designed resist pattern. By performing additional exposure using a mask pattern that is about 3 μm thicker than the designed resist pattern, the pattern can be reduced to 0.5 μm or less. Further, the same effect can be obtained by performing exposure once with a normal three times the exposure amount as a pattern design thicker by about 2 μm in consideration of the thinness of the resist in advance from the viewpoint of the throughput of the exposure device.
[0016]
Embodiment 2. FIG.
  FIG. 8 is a cross-sectional view showing a manufacturing process of a TFT array substrate using a channel etching type amorphous silicon thin film transistor according to the second embodiment of the present invention. In the figure, the same and corresponding parts are denoted by the same reference numerals and description thereof is omitted.
  A manufacturing process of the TFT array substrate in the present embodiment will be described with reference to the drawings. First, a metal film such as Mo is formed on the surface of the glass substrate 1 by sputtering to a thickness of about 400 nm. Next, resist patterning is performed using a positive resist. At that time, once exposure is performed with an appropriate exposure amount using a mask pattern to be a designed resist pattern, and then a mask pattern that is thicker by about 3 μm than the designed resist pattern is used again, and exposure is performed with an energy of about 2 to 10 times the appropriate exposure amount. I do.
  Next, the Mo film is etched using an etchant mainly composed of phosphoric acid, acetic acid, and nitric acid, and the gate electrode and wiring 2, redundant wiring 3, and branch-like shape as shown in FIG. 8 (a) and FIG. The auxiliary capacitance electrode 4 and the light shielding pattern 4a are formed. At this time, since nitric acid is contained in the etching solution, the Mo film is processed into a tapered shape, and disconnection of the upper layer when the film thickness becomes 300 nm or more can be prevented. Further, since it is difficult to make a redundant wiring structure for the wiring for connecting the signal wiring such as the gate wiring 2 to the connection terminal portion outside the pixel, a metal film such as Ti is used or the Mo surface layer is formed of Ti. The probability of occurrence of disconnection can be reduced by covering the cover.
[0017]
  Next, a gate insulating film 5, an amorphous silicon film 6, and an n + type amorphous silicon film 7 made of a silicon nitride film are successively formed by PCVD, for example, about 500 nm, 200 nm, and 50 nm, respectively. Further, in order to form a channel portion of the transistor, the amorphous silicon film 6 and the n + amorphous silicon film 7 are patterned in an island shape (FIG. 8B). Next, a metal film of about 400 nm Cr is formed, the source electrode, the wiring, and the drain electrode are patterned, and the metal film is etched. Thereafter, the n + amorphous silicon film 7 on the channel is removed by dry etching to form the source electrode, the wiring 11, and the drain electrode 12, and then the resist is removed (FIG. 8C). Finally, in order to protect the TFT, it is covered with an insulating film 13 such as a silicon nitride film, and the insulating film 13 on the drain electrode 12 and the terminal portion is removed (FIG. 8D). Next, an ITO film is formed to a thickness of, for example, about 100 nm by sputtering, and a pixel electrode 8 and a terminal electrode 9 are formed by patterning (FIG. 8 (e)).
[0018]
  According to this embodiment, since the gate layer structure as shown in FIG. 2 is adopted as in the first embodiment, the embodiment with respect to the disconnection 14 and the pattern defect 15 as shown in FIG. 1 has the same effect. In addition, when Mo, which is a low resistance material, is used as the gate layer, general hydrochloric acid and nitric acid are mainly used when etching the Cr film forming the source electrode, the wiring 11 and the drain electrode 12, and further when etching the ITO of the pixel electrode. The etching solution as a component causes corrosion at the defect portion of the silicon nitride film and easily causes disconnection 14, but in the structure of the present embodiment, it is difficult for a linear defect due to disconnection 14 to occur, so the probability of occurrence of the linear defect is reduced. The effect becomes even higher. Also in the present embodiment, when additional exposure is performed, the probability of occurrence of a short circuit between wirings can be further reduced as in the first embodiment. Further, setting the width of the redundant wiring 3 to about 2 μm in finished dimensions can increase the aperture ratio as in the first embodiment.
  In this embodiment, Mo is used as a material for the gate electrode and the wiring 2; however, an Al, Mo, Cu film, an alloy containing these as main components, or the like may be used. Further, Ti is used as a material for wiring for connecting signal wirings such as the gate wiring 2 and the source wiring 11 to the connection terminal portion, but Cr, W, Ti, Ta, or the like may be used.
[0019]
Embodiment 3 FIG.
  FIG. 9 is a sectional view showing a manufacturing process of a TFT array substrate using a channel etching type amorphous silicon thin film transistor according to the third embodiment of the present invention. In the figure, the same and corresponding parts are denoted by the same reference numerals and description thereof is omitted.
  A manufacturing process of the TFT array substrate in the present embodiment will be described with reference to the drawings. First, an Al—Nd alloy film having an Nd composition of 0.5 at.% Is formed on the surface of the glass substrate 1 by sputtering to a thickness of about 200 nm. Next, resist patterning is performed using a positive resist. At that time, once exposure is performed with an appropriate exposure amount using a mask pattern to be a designed resist pattern, and then a mask pattern that is thicker by about 3 μm than the designed resist pattern is used again, and exposure is performed with an energy of about 2 to 10 times the appropriate exposure amount. I do.
  Next, an Al-based alloy film is etched using an etching solution mainly composed of phosphoric acid, acetic acid and nitric acid, and the gate electrode and wiring 2 as shown in FIG. 9 (a) and FIG. 2, redundant wiring 3 and A branch-shaped auxiliary capacitance electrode 4 and a light shielding pattern 4a are formed. At this time, by appropriately adjusting the nitric acid concentration of the etching solution, the Al alloy film is processed into a tapered shape, and disconnection of the upper layer when the film thickness becomes 300 nm or more can be prevented. In this embodiment, since the film thickness is 200 nm, straight etching may be used. In addition, since it is difficult to make a redundant wiring structure for the wiring portion that leads the signal wiring to the connection terminal portion outside the pixel, Cr or the like is used, or the Al-based alloy surface layer is covered with Cr or the like. The probability of occurrence of disconnection can be reduced.
[0020]
  Next, a gate insulating film 5, an amorphous silicon film 6, and an n + type amorphous silicon film 7 made of a silicon nitride film are successively formed by PCVD, for example, about 500 nm, 200 nm, and 50 nm, respectively. Further, in order to form a channel portion of the transistor, the amorphous silicon film 6 and the n + amorphous silicon film 7 are patterned in an island shape (FIG. 9B). Next, an ITO film is formed to a thickness of, for example, about 100 nm by sputtering, the pixel electrode 8 and the terminal electrode 9 are formed by patterning, and the contact hole 10 of the terminal portion is further formed (FIG. 9C).
  Next, a metal film composed of a three-layer film having a lowermost layer of, for example, Cr or Ti of about 100 nm, a second layer of about Al-0.2 at.% Cu of about 300 nm, and an uppermost layer of about 50 nm of Cr is formed. Then, the three-layer film is etched. Thereafter, the n + amorphous silicon film 7 on the channel is removed by dry etching to form the source electrode, the wiring 11, and the drain electrode 12, and then the resist is removed (FIG. 9D). Finally, in order to protect the TFT, the insulating film 13 such as a silicon nitride film is covered, and the insulating film 13 on the pixel electrode 8 and the terminal electrode 9 is removed (FIG. 9E). In this embodiment, a three-layer film is used as the source and drain materials. However, if no particular problem occurs in the wiring resistance, pixel electrode formation process, etc., a single-layer film such as Mo and Cr, a lower layer Cr, and an upper layer are used. A double-layer film such as an Al alloy may also be used. Further, although an Al—Nd alloy film having an Nd composition of 0.5 at.% Is used as the material of the gate wiring 2, the Nd composition may be 0.1% or more and less than 5%.
[0021]
  According to the present embodiment, since the gate layer structure as shown in FIG. 2 is adopted as in the first and second embodiments, the disconnection 14 and the pattern defect 15 as shown in FIG. Thus, the same effects as those of the first and second embodiments can be obtained, and defects caused by disconnection and short-circuits in the gate layer, which have been frequently generated, can be reduced. In this embodiment, an Al-based alloy of a low resistance material is used as the gate layer. Conventionally, when etching ITO forming the pixel electrode 8, the main component is general hydrochloric acid or nitric acid. Since the etchant is corroded at the defect portion of the silicon nitride film and easily breaks, contact cleaning such as a brush is not performed before patterning in order to prevent this. For this reason, pattern defects 15 are likely to occur, which has been an obstacle to the use of Al-based alloy films. In this embodiment, the probability of occurrence of a linear defect due to the disconnection 14 can be further reduced, and the probability of occurrence of a short circuit between wirings due to the pattern defect 15 can also be reduced, so that an Al-based alloy can be used in a single layer. It was.
[0022]
  In addition, when a general Al alloy such as Al—Cu or Al—Si is used, hillocks are generated on the surface of the Al alloy after a thermal history such as subsequent film formation. When this hillock occurs, the silicon nitride film cannot cover the hillock portion, and corrosion breakage occurs throughout the wiring during the ITO etching. In such a case, even if the redundant wiring 3 as in the present invention is provided, the disconnection 14 occurs in both the gate wiring 2 and the redundant wiring 3, and the effect of the present invention is reduced. In order to prevent such disconnection 14, Al—Nd 0.5 at.% Is used as the Al-based alloy in the present embodiment, and no hillock is generated on the surface. For this reason, the structure of the present invention is effective even in the case of a low-resistance Al-based alloy. Also in the present embodiment, when additional exposure is performed, the probability of occurrence of a short circuit between wirings can be further reduced as in the first and second embodiments. Further, by setting the width of the redundant wiring 3 to about 2 μm in finished dimensions, the aperture ratio can be increased as in the first and second embodiments.
[0023]
Embodiment 4 FIG.
  The fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 10 is a plan view of the gate layer of the TFT array substrate using the channel etching type amorphous silicon thin film transistor according to the fourth embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along line AB in FIG. In the drawings, the same and corresponding parts are denoted by the same reference numerals and description thereof is omitted. The TFT array substrate according to the present embodiment is characterized in that the distal end portion of the branch-like light shielding pattern 4b is electrically separated from the redundant wiring 3.
[0024]
  A manufacturing process of the TFT array substrate in the present embodiment will be described. First, a metal film such as Cr is formed on the surface of the glass substrate 1 by sputtering to a thickness of about 400 nm. Next, resist patterning is performed using a positive resist.
  Next, the Cr film is etched using an etching solution mainly composed of ceric ammonium nitrate and nitric acid, and the gate electrode and wiring 2, redundant wiring 3 and branch-like auxiliary as shown in FIGS. 10 and 11 are used. The capacitor electrode 4 and the light shielding pattern 4b are formed. In the present embodiment, a structure with a gap of about 3 μm is provided so that the tip of the branch-like light shielding pattern 4 b is electrically separated from the redundant wiring 3. Since nitric acid is contained in the etching solution at the time of etching, the Cr film is processed into a tapered shape, and disconnection of the upper layer when the film thickness becomes 300 nm or more can be prevented. In the present embodiment, a Cr film is used as the gate material. However, similar to the second and third embodiments, the same effect can be obtained by using Mo or Al-based alloy which is a low resistance material.
  Next, a gate insulating film 5, an amorphous silicon film 6, and an n + type amorphous silicon film 7 made of a silicon nitride film are continuously formed by PCVD, and the subsequent processes are the same as those in the first embodiment.
[0025]
  According to the present embodiment, when the disconnection 14 as shown in FIG. 12 occurs, since the gate layer structure having the redundant wiring 3 is taken, the signal can travel through the redundant wiring 3, and the linear It will not be a defect. Further, even when a pattern defect 15 occurs at the tip of the branch-shaped light shielding pattern 4b and the tip of the light shielding pattern 4b is electrically short-circuited with the gate electrode and the wiring 2, the redundant wiring 3 is electrically separated. Therefore, it does not become a linear display defect. Thus, according to the present embodiment, it is possible to reduce defects caused by disconnection and short-circuiting in the gate layer, which have been frequently generated in the past.
[0026]
  In the first to fourth embodiments, a positive resist that is often used for manufacturing a TFT array substrate is used. However, a resist residue is hardly generated by using a negative resist only in the gate process. In the case of a negative resist, a short circuit occurs only when the foreign matter 16 itself becomes a mask and an etching residue occurs. Also in this case, since the size of the pattern defect 15 is small, the probability of occurrence of a short circuit between wirings can be reduced.
  In the first to fourth embodiments, the TFT array substrate using the channel etching type amorphous silicon thin film transistor has been described. However, the same effect can be obtained when the channel protective film type amorphous silicon thin film transistor is used. it can.
  In addition, a liquid crystal display device having a high aperture ratio and excellent display quality can be obtained by disposing a liquid crystal between the TFT array substrate according to the first to fourth embodiments and a counter electrode substrate having a transparent electrode and a color filter. It becomes possible to manufacture at a high yield.
[0027]
【The invention's effect】
  As described above, according to the present invention, from the gate wiring,Along the both sides of the adjacent pixel electrodeVertically extending branch auxiliary capacitance electrode and adjacent gate wiringWithArranged in parallel with the gate wiring so as to be located substantially at the center, the branch auxiliary capacitance electrode intersects with the redundant wiring, the redundant wiring, and the redundant wiring adjacent to the redundant wiring.RugeBetween wiringAlong both sides of the pixel electrodePlaced and perpendicular to the redundant wiringAdjacentSince a branch-like light shielding pattern extending to the vicinity of the gate wiring is provided, even if the gate wiring is disconnected due to defects during patterning or resist peeling during etching, the signal is routed through redundant wiring. If a pattern defect occurs in the gate wiring, it will not be short-circuited unless it occurs in the vicinity of the tip of the branch light-shielding pattern. It is possible to prevent the occurrence of display defects and to obtain a liquid crystal display device having a high aperture ratio and excellent display quality.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing method of a TFT array substrate according to a first embodiment of the present invention.
FIG. 2 is a plan view of a gate layer of the TFT array substrate according to the first embodiment of the present invention.
FIG. 3 is a plan view for explaining the operation of the TFT array substrate according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating a pattern defect generation mechanism in a TFT array substrate.
FIG. 5 is a diagram showing a pattern defect size with respect to additional exposure energy.
FIG. 6 is a diagram for explaining a pattern defect size reduction effect by additional exposure.
FIG. 7 is a diagram showing a relationship between exposure energy and pattern thinning.
FIG. 8 is a cross-sectional view showing a method of manufacturing a TFT array substrate according to the second embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a manufacturing method of a TFT array substrate according to a third embodiment of the present invention.
FIG. 10 is a plan view of a gate layer of a TFT array substrate according to a fourth embodiment of the present invention.
FIG. 11 is a cross-sectional view taken along the line AB of the gate layer of the TFT array substrate according to the fourth embodiment of the present invention.
12 is a plan view for explaining the operation of the TFT array substrate according to the fourth embodiment of the present invention. FIG.
13A is a plan view of a gate layer of a conventional common auxiliary capacitance type TFT array substrate, and FIG. 13B is a plan view when an array process is completed.
14A is a plan view of a gate layer of a conventional auxiliary capacitor on-gate TFT array substrate, and FIG. 14B is a plan view when an array process is completed.
FIG. 15 is a cross-sectional view showing a conventional method of manufacturing a common auxiliary capacitance type TFT array substrate.
FIG. 16 is a diagram for explaining a problem of a conventional TFT array substrate.
17A is a plan view of a gate layer of a TFT array substrate using conventional redundant wiring, and FIG. 17B is a plan view when an array process is completed.
FIG. 18 is a diagram for explaining the operation and problems of a TFT array substrate using conventional redundant wiring.
[Explanation of symbols]
  1 glass substrate, 2 gate electrode and wiring, 3 redundant wiring,
4 Auxiliary capacitance electrode, 4a, 4b, light shielding pattern, 5 gate insulating film, 6 amorphous silicon film, 7 n + type amorphous silicon film, 8 pixel electrode, 9 terminal electrode,
10 contact holes, 11 source electrodes and wiring,
12 drain electrode, 13 insulating film, 14 disconnection, 15 pattern defect,
16 foreign matter, 17 resist, 17a exposed resist, 18 mask,
19 Common wiring, 22 Metal thin film.

Claims (9)

A plurality of gate wirings formed on a transparent insulating substrate;
A plurality of source lines crossing the gate line,
A pixel electrode made of a transparent conductive film connected to a thin film transistor provided at each intersection of the gate wiring and the source wiring;
A branch-like electrode extending vertically from both sides of the pixel electrode adjacent to the gate wiring, and forming an auxiliary capacitor with an insulating film sandwiched between a part of the pixel electrode;
Disposed substantially parallel to the gate wiring and to be positioned at the center of the adjacent to Ruge over preparative wiring, the upper Symbol gate wiring intersecting with the distal end of the branch of the auxiliary capacitance electrode through the storage capacitor electrode Connected redundant wiring,
And said redundancy line, are arranged along the opposite sides of the pixel electrodes between the redundant wiring and the adjacent gate lines, like branches extending to the vicinity of the adjacent gate lines in the redundant wiring and a direction perpendicular A light-shielding pattern in which part of the pattern overlaps part of the pixel electrode,
A TFT array substrate comprising a connection terminal portion that is provided in the periphery of an image display portion constituted by the pixel electrode and inputs an external signal to the gate wiring and source wiring.   2. The TFT array substrate according to claim 1, wherein the light shielding pattern is electrically connected to the redundant wiring, and an auxiliary capacitor is formed with an insulating film interposed between the light shielding pattern and a part of the pixel electrode.   2. The TFT array substrate according to claim 1, wherein the light shielding pattern is electrically separated from the redundant wiring.   The said gate wiring, the said auxiliary capacity electrode, the said light-shielding pattern, and the said redundant wiring are each formed in the same layer with the same material, The Claim 1 characterized by the above-mentioned. TFT array substrate.   5. The TFT array substrate according to claim 1, wherein Al, Mo, Cu, or an alloy containing these as a main component is used as a material for the gate wiring.   6. The TFT array substrate according to claim 5, wherein an Al—Nd alloy having an Nd composition of 0.1% or more and less than 5% is used as a material for the gate wiring.   7. The TFT array substrate according to claim 5, wherein any one of Cr, W, Ti, and Ta is used as a material for wiring that connects the gate wiring and the source wiring to a connection terminal portion. .   The TFT array substrate according to claim 1, wherein the redundant wiring has a line width of 2 μm or more and 10 μm or less.   A liquid crystal display device, wherein a liquid crystal is disposed between the TFT array substrate according to any one of claims 1 to 8 and a counter electrode substrate having a transparent electrode and a color filter.

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