JP4214567B2 - Manufacturing method of semiconductor substrate for pressure sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor substrate used in a pressure sensor that electrically detects a pressure applied to a diaphragm based on a stress generated by a pressure difference from a pressure reference chamber.
[0002]
[Problems to be solved by the invention]
Some semiconductor pressure sensors that detect the pressure applied to the diaphragm have a pressure reference chamber inside. In this case, the pressure reference chamber is in a state where the inside is depressurized to a state close to a vacuum, and thereby the detection accuracy of the pressure received by the diaphragm is improved by suppressing the fluctuation of the internal pressure due to the temperature fluctuation or the like. It is what.
[0003]
As a semiconductor substrate used for manufacturing such a semiconductor pressure sensor, a substrate in which a portion corresponding to the pressure reference chamber described above is formed in advance is provided. This is, for example, a method of forming a pressure reference chamber and a diaphragm by using a bonding technique using two single crystal silicon substrates.
[0004]
That is, first, a recess for a pressure reference chamber is formed on a silicon substrate as a support substrate by a method such as etching. This silicon substrate and a separately prepared silicon substrate for diaphragm formation are bonded together by a bonding technique. Next, the bonded silicon substrate for the diaphragm is ground and polished, and the thickness is adjusted until it becomes the thickness of the diaphragm. Accordingly, the pressure reference chamber can be provided on the silicon substrate as the support substrate and the diaphragm can be formed so as to cover the pressure reference chamber.
[0005]
However, in the method of grinding and polishing the diaphragm forming substrate after bonding as described above, the silicon substrate for forming the diaphragm needs to be polished until the desired diaphragm thickness is obtained. It is uneconomical in that most parts of the bonded silicon substrate are removed by grinding and polishing, and polishing itself to leave a thin film part such as a diaphragm is technically effective in terms of controllability. Have difficulty.
[0006]
In the control of the film thickness by the polishing process, it is difficult to polish while directly measuring the film thickness of the silicon substrate to be left by polishing. For example, by measuring the polishing speed and leaving the desired thickness by time management There are a control method and a method of providing a polishing stopper in advance on a silicon substrate to be polished.
[0007]
In the method of providing a polishing stopper, for example, a groove having a predetermined depth is formed on the diaphragm side of the silicon substrate, and the inside of the groove is filled with silicon oxide. When reaching the position where the bottom surface of the object is exposed, the polishing of silicon is automatically stopped because the polishing speed of the oxide film is lower than that of silicon.
[0008]
However, even when polishing is performed with good controllability using such various techniques, as long as the method using polishing is employed, bending is likely to occur at the portion where there is a recess for the pressure reference chamber during polishing. The difficulty remains in uniformly forming the thickness of the diaphragm portion. In addition, it is difficult to make the thickness dimensions of the plurality of diaphragms formed in the substrate uniform.
[0009]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor substrate for a pressure sensor that can form a diaphragm with a uniform thickness with good dimensional accuracy. There is.
[0010]
[Means for Solving the Problems]
  According to the first aspect of the present invention, when the pressure sensor has a structure in which the pressure received by the diaphragm is electrically detected based on the stress generated by the pressure difference from the pressure reference chamber, the semiconductor substrate is An ion implantation layer for peeling is formed at a predetermined depth of a semiconductor-made first substrate for diaphragm formation by an ion implantation layer forming step, and pressure is applied to the second substrate to form a pressure reference chamber by a recess forming step. A recess for the reference chamber is provided, the first and second substrates are bonded together in the bonding step, and the first substrate bonded in the subsequent peeling step is peeled off at the ion implantation layer portion to form the second substrate. Since the diaphragm and the pressure reference chamber are formed by forming the semiconductor layer on the surface, the diaphragm having a desired thickness is formed with high accuracy by controlling the depth of the ion implantation layer. In addition, since processing by a method such as grinding or polishing is not required, it can be manufactured easily and in a short time, and the first substrate can be reused to reduce costs. it can.
  Further, in the recess forming step, a support column that can be selectively etched with the same length as the depth dimension is formed on the bottom surface of the recess for the pressure reference chamber. In the bonding step, the tip portion of the support can be bonded even in the region in the recess, and the semiconductor layer for forming the diaphragm can be reliably peeled in the peeling step. .
  In particular, when the ion implantation layer is formed at a shallow position of the first substrate in order to reduce the thickness of the diaphragm, the semiconductor layer to be peeled is thinned. The diaphragm can be reliably formed as compared with the configuration in the case where there is not. Further, even when the dose of the ion implantation layer formed in the ion implantation layer formation step is insufficient, the semiconductor layer can be reliably peeled and formed.
[0011]
According to the second aspect of the present invention, since the concave portion is formed by etching the surface of the second substrate in the concave portion forming step, the semiconductor layer and the pressure reference chamber to be a diaphragm can be formed. .
[0012]
According to the invention of claim 3, since the semiconductor layer for forming the diaphragm is provided through the bonding process and the peeling process, an oxide film is provided between the second substrate and the semiconductor layer. Thus, the semiconductor layer can be formed in a state of being isolated from the second substrate. For example, in a region of the semiconductor layer that is not a diaphragm portion, a so-called SOI (Silicon On Insulator) structure is formed. A signal processing circuit element can be formed in the semiconductor layer, and the MOS element and the bipolar element can be integrated on the same chip.
[0015]
  Claim4According to the invention, in the concave portion forming step, the column portion formed on the bottom surface of the concave portion is constituted by a plurality of columns, so that the bonding force with the surface of the first substrate can be further increased and the thickness can be increased. When a diaphragm with a small dimension is to be formed, the semiconductor layer can be reliably peeled.
[0016]
  Claim5and6According to the invention, in the recess forming step, the support column is formed by providing the pattern for forming the support column during the etching process for forming the recess on the second substrate, and then the thermal oxidation process is performed to form the support column. Since the portion is made of oxide, it can be selectively etched, so when the first substrate is bonded, it is bonded to the surface of the second substrate and the support provided on the recess. After the semiconductor layer is peeled and formed through the peeling step, the diaphragm can be formed by removing the pillar portions remaining on the diaphragm portion by selective etching with a hydrofluoric acid aqueous solution or the like.
[0018]
  Claim7According to the invention, the second substrate is obtained by removing the semiconductor layer in a predetermined region other than the diaphragm portion of the semiconductor layer formed on the surface of the second substrate by the semiconductor layer removing step performed after the peeling step. Since the element formation region is exposed on the surface of the substrate, even if the film formation of the semiconductor layer for the diaphragm does not allow sufficient element formation, the element is formed on the second substrate side. Therefore, it is possible to increase the degree of design freedom by reducing restrictions for element formation, and to increase the heat dissipation effect of the element to be formed.
[0019]
  Claim8According to the invention, in the recess forming step, the pressure reference chamber recess forms the decompression communicating portion communicating with the outside, and the decompression formed by the decompression communicating portion is performed by the decompression sealing step performed after the peeling step. Since the pressure reference chamber is depressurized and sealed through the communication hole, pressure fluctuation in the pressure reference chamber due to temperature fluctuation is suppressed by reducing the pressure contained in the pressure reference chamber or reducing the gas contained in it as much as possible. Thus, a configuration for performing a more accurate pressure detection operation can be formed easily and with good controllability.
[0020]
  Claim9According to the invention, in the recess forming step, the pressure reducing communication portion is formed as a groove portion along the surface portion of the second substrate, and the surface portion is covered with the semiconductor layer formed after the peeling step. Since the communication hole is formed, the communication hole for pressure reduction can be formed by using the process for forming the diaphragm, and can be easily implemented without adding a special process.
[0021]
  Claim10According to the invention, since the depth dimension of the communication part for decompression is formed to be the same as the depth dimension of the recess in the recess forming step, the process for forming them can be performed by the same etching process. The number of processes can be reduced and it can be easily manufactured.
[0022]
  Claim11According to the invention, in the recess forming step, the pressure reducing communication hole is formed as an opening communicating with the back surface portion of the second substrate. Therefore, in the pressure reducing sealing step, the pressure reference is made from the back surface side of the second substrate. By reducing the pressure in the room and sealing the opening, it is possible to obtain the same characteristics.
[0023]
  Claim12According to the invention, in the reduced pressure sealing process, the film is formed so as to seal the opening of the communication hole for reduced pressure in a reduced pressure atmosphere by the CVD method, so that the reduced pressure sealing is performed without employing a special process. A process can be performed. When a protective film or the like is formed on the final surface, a reduced pressure sealing process can be performed simultaneously with the process of forming the protective film. In this case, for sealing This can be carried out without adding any special process.
[0024]
  Claim13According to the invention, since the non-single-crystal layer such as the amorphous layer or the polycrystalline layer is included in the layer which is bonded to form the semiconductor layer, the surface layer portion of the first substrate is formed of a single crystal. As compared with the case where the bonding step and the peeling step are performed as they are, the semiconductor layer can be formed in a state where the mechanical strength of the semiconductor layer portion formed by peeling is increased.
[0025]
  Claim14Or16According to the invention, the non-single-crystal layer is configured such that the constituent elements thereof include the same kind of constituent elements as the constituent elements of the first semiconductor substrate (4). Alternatively, a polycrystalline layer can be provided, or a non-single-crystal layer made of a compound of the same kind of element or the like can be provided, which makes it easier to form the non-single-crystal layer. When a silicon substrate is used as the semiconductor substrate, an amorphous silicon film or a polycrystalline film that is an amorphous silicon film can be used as the non-single crystal film, or a silicon oxide film, a silicon nitride film, or the like can be used. Thus, as described above, the mechanical strength of the semiconductor layer portion formed by peeling is increased compared to the case where the bonding step and the peeling step are performed while the surface layer portion of the first substrate remains a single crystal. A semiconductor layer can be formed.
[0026]
  Claim17According to the invention, since the non-single crystal layer is formed on the surface of the first semiconductor substrate by the deposition method, for example, a physical film forming method or a chemical film forming method used in a normal semiconductor manufacturing process is used. Thus, a non-single crystal film can be formed, and a non-single crystal layer can be provided easily and inexpensively without using a special process.
[0027]
  Claim18 and 19According to the invention, the non-single-crystal layer is formed on the first semiconductor substrate by the ion implantation method. An amorphous layer can be formed as a non-single-crystal layer in an arbitrary region on the surface or inside.
[0028]
  According to the inventions of claims 20 and 21, the non-single crystal layerButFirstBase ofConsists of the same elements as the plateIs an amorphous silicon filmIn some cases, the heat treatment is performed after the peeling step, and the non-single crystal layer is recrystallized to form the semiconductor layer as a single crystal layer. A single crystal layer can be obtained with the same structure as the semiconductor substrate finally obtained while maintaining strength, and a stable electrical characteristic can be obtained as a diaphragm characteristic of the pressure sensor. Become.
[0029]
According to the invention of claim 22, the concentration of oxygen contained in the first substrate is 1 × 10.¹⁸atoms / cm³Since the above semiconductor substrate is used, the mechanical strength is higher than that of a semiconductor substrate used for normal use, the handling performance in the processing step is improved, and the reliability is improved.
[0030]
  According to the invention of claim 23, when the first substrate and the second substrate are bonded together, the opening of the recess on the second substrateThe side of the quadrilateral that formsPositioning is performed by adjusting in a direction that intersects with the cleavage direction of the first substrate, so that the portion that is located in the region of the concave portion of the second substrate undergoes the separation when it is separated in the separation step. Thus, it is possible to prevent the occurrence of damage such as cleaving, thereby preventing the mechanical strength from being lowered, and the diaphragm portion can be reliably formed.
[0031]
  Claim 2426According to the invention, in the above-described case, the direction of the side of the opening of the recess formed on the second semiconductor substrate is adjusted to a direction in which the first substrate cleavage direction intersects with the largest angle. For example, when the plane orientation of the first semiconductor substrate is (100), the angle is adjusted to a direction that intersects with an angle centered on 22 to 23 °, thereby achieving the above-described effect. It will be possible to make the most of it, and it will be possible to manufacture with good reproducibility in a state where the mechanical strength is increased.
[0032]
  Claim27According to the invention, in the cleaning step performed prior to the bonding step, at least the second semiconductor substrate of the first semiconductor substrate and the second semiconductor substrate to be bonded is subjected to a hydrophobic treatment, Moisture adhering to the surface is removed during the dehydration process, so that it is possible to prevent moisture from remaining on the surface of the substrate and the formed recess as much as possible. It is possible to suppress the remaining or the moisture remaining in the recess and the deterioration of the characteristics.
[0033]
  Claim28According to the invention, since the bonding step is performed in a reduced pressure atmosphere, when the first substrate and the second substrate are brought into close contact with each other, moisture remaining on the surface of the substrate, the recesses, etc. is sufficiently removed in the reduced pressure atmosphere. It becomes possible to carry out after removing by dehydration, and to improve the adhesion. Further, when the concave portion is sealed in a reduced pressure state by this bonding step, it is not necessary to separately perform a step for degassing the concave portion in a later step, and therefore, the number of steps can be reduced. It becomes like this.
[0034]
  Claim29According to the invention, an insulating film separation substrate in which a semiconductor layer is formed on a support substrate via an insulating film is used as the second substrate, and the pressure reference chamber is formed in the semiconductor layer of the insulating film separation substrate. As a result, a diaphragm or a pressure reference chamber can be formed on the insulating film separation substrate, whereby a pressure sensor control circuit can be formed in the insulating film separation region located around the pressure reference chamber. Thus, the element isolation structure can be easily formed and the electrical characteristics such as the breakdown voltage can be improved.
[0035]
  Claim30According to the invention, the second substrate region is removed from the rear surface of the insulating film isolation substrate bonded onto the second substrate by a method such as grinding or polishing using the embedded insulating film as a stopper, and thereafter the embedded insulating film is removed. By selectively removing the film by a method such as etching, only the semiconductor layer can be formed on the second substrate. As a result, the film thickness of the semiconductor layer on the surface of the insulating film separation substrate is increased and the film thickness of the semiconductor layer in the portion that becomes the diaphragm after bonding is formed with the formation accuracy. Therefore, it is possible to relatively easily provide the diaphragm as designed with high accuracy.
  In the above case, an ion implantation layer is formed in the insulating film isolation layer of the insulating film isolation substrate or deeper than the insulating film isolation layer, and the insulating film isolation substrate is ion-implanted after being bonded to the second substrate. It becomes possible to peel at the layer portion. Thereafter, the semiconductor layer can be formed over the second substrate by removing the buried insulating layer. Therefore, it can be easily removed without a process such as grinding or polishing for removing the support substrate portion of the insulating film separation substrate, and the portion of the support substrate after the separation of the insulating film separation substrate is used again. It can be used as a support substrate for an insulating film separation substrate.
[0036]
  Claim31According to the invention, in the above-described case, as a method of forming the insulating separation substrate, the ion implantation layer is formed at a predetermined depth of the third substrate and bonded to the fourth substrate. Since the semiconductor layer is formed by peeling off at a portion, it is possible to obtain an insulating separation substrate on which a semiconductor layer having a desired film thickness is formed with high accuracy, and the semiconductor layer formed on the diaphragm portion is relatively easily accurate. It can be formed with a uniform film thickness.
[0038]
According to the invention of claim 32, in the recess forming step, the recess is formed by etching the surface of the second substrate, so that the semiconductor layer to be a diaphragm and the pressure reference chamber can be formed. .
[0039]
According to the invention of claim 33, since the bonding step is performed in a reduced pressure atmosphere, when the first substrate and the second substrate are brought into close contact with each other, moisture remaining on the surface of the substrate, the recesses, etc. is removed in the reduced pressure atmosphere. Thus, it is possible to carry out after removing by sufficiently dehydrating and to improve the adhesion. Further, when the concave portion is sealed in a reduced pressure state by this bonding step, it is not necessary to separately perform a step for degassing the concave portion in a later step, and therefore, the number of steps can be reduced. It becomes like this.
[0040]
According to the invention of claim 34, as the second substrate, an insulating film separation substrate in which a semiconductor layer is formed on the supporting substrate via an insulating film is used, and the pressure reference chamber is a semiconductor layer of the insulating film separation substrate. Since the diaphragm and the pressure reference chamber can be formed on the insulating film separation substrate, the pressure sensor control circuit is formed in the insulating film separation region located around the pressure reference chamber. As a result, the element isolation structure can be easily formed, and the electrical characteristics such as the breakdown voltage can be improved.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 4E shows a schematic cross section of a sensor chip 1 as a pressure sensor semiconductor substrate. A silicon oxide film 3 is formed on a single crystal silicon substrate 2 as a second substrate as a support substrate. A single crystal silicon film 5 as a semiconductor layer formed as described later using a single crystal silicon substrate 4 (see FIG. 2) as a first substrate for forming a diaphragm is formed with a predetermined film thickness. Thus, the diaphragm 6 is provided.
[0042]
A pressure reference chamber 7 is provided in the central portion of the sensor chip 1 and is depressurized so that the inside is almost in a vacuum state. A pressure reducing communication hole 8 communicating with the pressure reference chamber 7 and opened to the outside is formed in a side portion of the pressure reference chamber 7. As will be described later, the pressure reference chamber 7 is depressurized through the pressure reducing communication hole 8. After that, the opening 8a is sealed with the protective film 9 so as to be decompressed.
[0043]
The diaphragm 6 is formed with a resistor 10 having a piezoresistive effect for pressure detection. The single crystal silicon film 5 located in the periphery of the pressure reference chamber 6 has a MOS transistor constituting a signal processing circuit, etc. These circuit elements 11 are formed, and a detection output is obtained by performing amplification and signal processing of the pressure detection signal detected by the resistor 10.
[0044]
According to the above configuration, when the diaphragm 6 receives a pressure from the outside, a force corresponding to the difference between the pressure and the pressure reference chamber 7 acts to cause distortion. Due to this distortion, the resistance value of the resistor 10 formed on the diaphragm 6 changes due to the piezoresistive effect, which is detected as a voltage change by a bridge-connected circuit, and as a detection signal corresponding to the pressure by a signal processing circuit. Can be output.
[0045]
In this case, since the pressure reference chamber 7 is almost depressurized to a vacuum state, unlike the state in which gas exists, the internal pressure fluctuation due to the temperature change of the measurement environment does not occur, so the pressure detection operation is always highly accurate. Can be done. Further, in the above-described configuration, the diaphragm 6 is constituted by the single crystal silicon film 5 formed as described later using the single crystal silicon substrate 4 as the first substrate, so that a thin film can be formed uniformly and accurately. As a result, the stability and accuracy of pressure detection accuracy can be improved.
[0046]
Next, the manufacturing process of the above-described pressure sensor will be described. FIG. 1 shows an outline of the manufacturing process, which will be described below with reference to this process chart and the process explanatory diagrams of FIGS.
(1) Ion implantation layer forming step (P1)
First, a single crystal silicon substrate 4 as a first substrate is prepared with at least one surface thereof mirror-polished, and hydrogen ions (protons), for example, are implanted by ion implantation into the mirror-polished surface side. A high concentration ion implantation layer 12 is formed (see FIG. 2). In this case, the single crystal silicon substrate 4 has, for example, an oxygen concentration higher than that used for a normal device, 1 × 10 1¹⁸atoms / cm³That's 5x10¹⁸atoms / cm³What is formed in the grade is used, and thereby the mechanical strength is increased. The oxygen concentration is 1 × 10¹⁸~ 1x10²⁰atoms / cm³In the range, preferably 1 × 10¹⁸~ 1x10¹⁹atoms / cm³The range is suitable.
[0047]
The depth for forming the ion implantation layer 12 is set to a predetermined depth dimension according to the acceleration voltage and the dose amount, and is provided corresponding to the thickness dimension of the diaphragm 6 to be formed. The dose of the ion implantation layer 12 is 1 × 10.¹⁶atoms / cm²For example, 5 × 10¹⁶atoms / cm²However, the greater the dose, the better the peelability in the peeling process P4. Note that, by forming an oxide film in advance on the surface where ions are implanted, damage to the surface layer caused by ion implantation can be reduced and impurity contamination can be reduced.
[0048]
(2) Concave formation step (P2)
Next, a single crystal silicon substrate 2 as a second substrate is prepared in a state where at least one surface thereof is mirror-polished, and the recess 2a for the pressure reference chamber 7 is dry-etched on the side where the mirror-polishing is performed. It is formed by processing, or by wet etching with an aqueous solution such as TMAH or KOH (potassium hydroxide solution). Note that, in the subsequent bonding step (P3), when bonding is not performed in a reduced pressure atmosphere such as a vacuum atmosphere, at this time, the groove 2b as the reduced pressure communicating portion is similarly subjected to dry etching treatment or KOH. It is necessary to form the film by a method such as a wet etching process (see FIG. 3).
[0049]
In this case, the concave portion 2a for the pressure reference chamber 7 has an appropriate dimension depending on the range or size of the pressure to be measured, but a square shape having a side of about 10 to 1000 μm, for example, about 100 μm. The depth dimension is set to an appropriate dimension within a range of about 1 to 10 μm. Moreover, the groove part 2b is set to about 10 micrometers in the range whose width dimension is about 1-100 micrometers, for example, and a length dimension is about several hundred micrometers in the range which is about 10-1000 micrometers.
[0050]
Then, an oxide film 3 is formed on the surface of the single crystal silicon substrate 2 by a method such as thermal oxidation or CVD. The oxide film 3 may be simultaneously formed on the side walls and the bottom surface of the recess 2a and the groove 2b of the single crystal silicon substrate 2.
[0051]
(3) Bonding process (P3)
Next, the surface of the single crystal silicon substrate 2 on which the ion implantation layer 12 is formed is bonded to the surface of the single crystal silicon substrate 2 on which the recess 2a is formed (see FIG. 4A). In the substrate cleaning step performed prior to the bonding step P3, the single crystal silicon substrate 4 subjected to the ion implantation is completely removed by removing the anti-contamination oxide film 4a formed on the surface with a hydrofluoric acid aqueous solution or the like. The surface can be decontaminated and flattened, and then H₂SO₄And H₂O₂By washing with a processing solution or the like mixed 4 to 1, a natural oxide film is formed on the surface to make it hydrophilic.
[0052]
For the single crystal silicon substrate 2, after forming the recess 2 a,₂SO₄And H₂O₂Is washed with a processing solution or the like mixed 4 to 1 to form a natural oxide film to make it hydrophilic. Thereafter, the two single crystal silicon substrates 2 and 4 are adhered to each other to perform bonding. As for the substrate cleaning, H is removed without removing the anti-contamination oxide film 4a on the single crystal silicon substrate 4.₂SO₄And H₂O₂It is possible to perform flattening by performing cleaning using a processing solution or the like mixed in a ratio of 4 to 1 and removing contaminants on the surface, and bonding can be performed.
[0053]
In the above case, H₂SO₄And H₂O₂It is also effective to perform a hydrophobizing treatment by washing with a hydrofluoric acid aqueous solution or the like instead of performing a hydrophilizing treatment by washing with a treatment solution or the like mixed 4 to 1. Compared with the case where the hydrophilic treatment is performed, the hydrophobic treatment is reduced in terms of the bonding strength between the substrates, but the bonding itself can be performed. Further, performing this hydrophobization treatment has a great effect of preventing gas remaining in the joint surface by bonding in a vacuum, as well as lowering the adhesion strength.
[0054]
That is, when bonding is performed in a vacuum (in a reduced pressure atmosphere) in a state where the hydrophobic treatment is performed in this manner, it is possible to prevent the occurrence of unbonded regions due to gas or moisture intervening at the interface, A stable product can be manufactured by preventing the diaphragm 6 from being damaged due to a decrease in the degree of vacuum due to moisture remaining in the pressure reference chamber 7 or expansion of moisture. In addition, by performing bonding in a vacuum, it is not necessary to separately perform a reduced pressure sealing process.
[0055]
Further, in the bonding step of the single crystal silicon substrates 2 and 4, the bonding direction of the single crystal silicon substrate 4 is relative to the side of the quadrilateral that forms the opening of the recess 2a on the single crystal silicon substrate 2 side. Since it becomes a disadvantageous condition in terms of strength when it is in a parallel relationship with the direction formed by the cleavage plane when the cleavage is performed, it is preferable to arrange and bond in a direction that intentionally avoids this (FIG. 5). (See (a) and (b)). Thereby, in the peeling process mentioned later, the effect which prevents damaging especially in the part etc. corresponding to the pressure reference chamber 7 with the force received by the impact at that time becomes high.
[0056]
In this case, for example, when the plane orientation of the single crystal silicon substrate 4 is the (100) plane, the plane orientation that is easy to cleave is parallel or orthogonal to the OF direction as shown in FIG. There are (100) planes that appear as lines that do or (110) planes that appear as lines that are inclined by 45 ° in the direction of OF. Therefore, in order not to be parallel to this direction, for example, about 22 to 23 ° (exactly 22.5 ° = 45 ° / 2) as a direction having an inclination so as to form the largest angle with respect to both of them. Setting and pasting together is effective. As a result, the mechanical strength can be increased, and damage can be prevented even during peeling to obtain a product with good quality.
[0057]
(4) Peeling process (P4)
Thereafter, the bonded single crystal silicon substrates 2 and 4 are heat-treated in a nitrogen atmosphere or an oxygen atmosphere. In this heat treatment, for example, a first heat treatment performed at about 500 ° C. in a range of 400 ° C. to 600 ° C. and a second heat treatment performed at about 1000 ° C. and about 1100 ° C. are sequentially performed; There is a method of increasing the temperature at once.
[0058]
By performing this heat treatment, a dehydration condensation reaction occurs on the bonding surfaces of the substrates 2 and 4, and the bonding state can be made stronger. In the hydrogen ion-implanted layer 12, defects are locally concentrated by this heat treatment, and bubbles are generated, so that the surface is separated (see FIG. 4B).
[0059]
As a result, the single crystal silicon film 5 having a film thickness of, for example, about 2 μm (for example, preferably in the range of about 1 to 10 μm) on the surface portion of the single crystal silicon substrate 4 is bonded to the single crystal silicon substrate 2 side. Since it remains in the state, the pressure reference chamber 7 and the diaphragm 6 can be formed. Thereafter, the surface roughness of the peeled single crystal silicon film 5 is reduced by a method such as polishing to improve the smoothness. This polishing process is not always necessary when the next element formation step is not performed.
[0060]
(5) Element formation process (P5)
In the above-described state, the single crystal silicon film 5 is formed on the single crystal silicon substrate 2 that is the second substrate with the oxide film 3 that is an insulating film interposed therebetween. Silicon On Insulator) structure. A resistor 10 having a piezoresistive effect for pressure detection is formed on the single crystal silicon film 5 and various elements 11 such as MOS transistors constituting a circuit for signal processing are formed (FIG. 5C). reference). The resistor 10 is wired so as to form a bridge circuit by a wiring pattern, and the input / output terminals are wired so as to be connected to the signal processing circuit.
[0061]
(6) Depressurization sealing process (P6)
Next, in the bonding step P2, when manufacturing a type that does not perform bonding in a vacuum atmosphere, the inside of the pressure reference chamber 7 needs to be reduced to a vacuum or a predetermined pressure. The reduced pressure sealing process P6 is performed. That is, an opening 8a is formed in the single crystal silicon film 5 at the end opposite to the pressure reference chamber 7 of the decompression communication hole 8 formed by the groove 2b and the single crystal silicon film 5 (FIG. 4D). )reference). In this case, the opening 8a is formed by etching or the like from the surface side of the single crystal silicon film 5.
[0062]
Thereafter, the insulating protective film 9 is formed on the surface of the single crystal silicon film 5 formed as described above by a CVD apparatus or the like, and the opening 8a is simultaneously sealed under reduced pressure. While being placed in the CVD apparatus, the pressure is reduced and exposed to a vacuum atmosphere to reduce the pressure in the pressure reference chamber 7 through the pressure reducing communication hole 8. An insulating protective film 9 such as a silicon nitride film or a silicon oxide film is deposited on the entire surface while the inside is in a vacuum state, thereby simultaneously sealing the inside of the opening 8a. Thereafter, the protective film 9 on the diaphragm 6 is peeled off by photolithography to form the sensor chip 1.
[0063]
According to such a first embodiment, when forming the diaphragm 6 having the pressure reference chamber 7 therein, the single crystal silicon substrate 4 in which the ion implantation layer 12 is formed on the single crystal silicon substrate 2 is formed. Since it is formed by performing heat treatment and peeling after bonding, the diaphragm has a uniform and thin film thickness compared to the conventional method in which the film thickness of the diaphragm is controlled by polishing after bonding. 6 can be formed with good reproducibility, whereby a pressure sensor with high detection accuracy can be provided.
[0064]
In addition, according to the first embodiment, the pressure reference chamber 7 can be formed in a substantially vacuum state by the decompression sealing step P6, so that the pressure in the pressure reference chamber 7 can be set with high accuracy, It is possible to provide a pressure sensor capable of performing a pressure detection operation with high accuracy by preventing a pressure fluctuation in the pressure reference chamber 7 due to a change in environmental temperature as much as possible.
[0065]
In the above embodiment, the sensor chip 1 having the structure in which the oxide film 3 is interposed between the single crystal silicon substrates 2 and 4 has been described. However, instead of this, for example, the structure in which the oxide film 3 is not provided. You can also That is, when the single crystal silicon substrates 2 and 4 are directly bonded to each other instead of the SOI structure and there is no restriction as a signal processing circuit of the sensor chip, the single crystal silicon film 5 is formed as such a configuration. The circuit element 11 can be formed in this part.
[0066]
In addition, when the diaphragm 6 is formed thick, a bipolar element can be formed. When the oxide film 3 is not provided as described above, the heat generated in the signal processing circuit is easily transferred to the single crystal silicon substrate 2 side, which is the second substrate. The effect is enhanced and the operating characteristics are improved.
[0067]
Further, an insulating film separation substrate can be used as the second semiconductor substrate for forming the recess 2a. Thus, the diaphragm 6 and the pressure reference chamber 7 can be formed on the insulating film separation substrate, and a pressure sensor control circuit for processing an electrical signal obtained from these can be provided around the pressure reference chamber 7. When formed in a region, it can be provided in an insulated and isolated state from the underlying support substrate side, facilitating the formation of an element isolation structure and performance in terms of electrical characteristics such as withstand voltage of the circuit element to be formed. Can be improved.
[0068]
(Second Embodiment)
FIG. 7 shows a second embodiment of the present invention. The difference from the first embodiment is that a recess 2a and a groove 2b are formed on the surface of a single crystal silicon substrate 2 as a second substrate. The depth dimension is set to the same dimension. That is, in the recess forming step P2, a photoresist pattern as shown in FIG. 7B is formed on the surface of the single crystal silicon substrate 2, and etching is simultaneously performed in this state, whereby the recess 2a, the groove 2b, The recesses 2c are integrally formed at the same depth.
[0069]
As in this case, when there is no structural limitation in the conditions for pressure measurement, etc., the concave portion 2c and the groove portion 2b in the first embodiment are formed by one photolithography process as the concave portion 2c. Therefore, there is an advantage that the number of processes is reduced.
[0070]
(Third embodiment)
8 to 10 show a third embodiment of the present invention. The difference from the first embodiment is that the peripheral portion of the diaphragm 6 in which the MOS circuit element 11 for the signal processing circuit is formed is shown. A semiconductor layer removing step Q1 is provided after the peeling step P4 so as to remove the portion of the semiconductor layer 5 located.
[0071]
That is, in the first embodiment, a configuration in which a MOS circuit element 11 such as a MOS transistor (which can be formed in a region having a depth of 2 to 3 μm) is formed as an element for a signal processing circuit is targeted. The single crystal silicon film 5 used as 6 could be formed even when the film thickness was relatively thin.
[0072]
However, if a bipolar element 13 (see FIG. 9 (e)) such as a bipolar transistor often used in a signal processing circuit of a sensor is to be formed, in a normal configuration, the depth dimension is about 10 μm. Since it is necessary, especially when the diaphragm 6 is formed thin, there is a case where it is difficult to form a circuit configuration due to restrictions on the junction depth dimension.
[0073]
Therefore, in the third embodiment, a sensor chip 14 having a structure that is not restricted by the thickness of the single crystal silicon film 5 forming the diaphragm 6 is provided. In this configuration, as a region for forming a bipolar circuit element 13 such as a bipolar transistor, a part of the surface 15 of the single crystal silicon substrate 2 which is the second substrate is exposed and formed there.
[0074]
Next, the manufacturing method (refer FIG. 8) of the sensor chip 14 of the said structure is demonstrated. The ion implantation layer forming step P1, the concave portion forming step P2, the bonding step P3, and the peeling step P4 are performed in the same manner as in the first embodiment, and a configuration as shown in FIG. 9A is obtained. Next, in the semiconductor layer removal step Q1, in order to remove the portion of the single crystal silicon film 5 excluding the region of the diaphragm 6, it is patterned into a shape as shown in FIG. The oxide film 3 formed in the lower layer of the film 5 is removed by etching using the etching stopper as an etching stopper. Subsequently, the exposed oxide film 3 is similarly removed by etching. As a result, the surface 15 of the single crystal silicon substrate 2 is partially exposed (see FIG. 9B).
[0075]
Next, in the element formation step P5, the low antibody 10 is formed on the diaphragm 6 in the same manner as described above, and the MOS circuit for the signal processing circuit is formed on the surface 15 of the single crystal silicon substrate 2 exposed in the above step. The element 11 and the bipolar circuit element 13 are formed (see (c) in the figure).
[0076]
Thereafter, the decompression sealing step P6 is performed in the same manner as in the first embodiment to form the opening 8a in the single crystal silicon film 5 at the end of the decompression communication hole 8 (see FIG. 4D). Then, the inside of the pressure reference chamber 7 is reduced to a vacuum state by a CVD method to form the protective film 9 on the entire surface, thereby sealing the opening 8a. Thereafter, the sensor chip 14 is obtained by removing the protective film 9 in the diaphragm 6 portion.
[0077]
According to the third embodiment, the semiconductor layer removing step Q1 is performed to remove the single crystal silicon film 5 around the diaphragm 6 and expose the surface 15 of the single crystal silicon substrate 2. Since the signal processing circuit such as the MOS circuit element 11 and the bipolar circuit element 13 is formed in this portion, the circuit element 11 for the signal processing circuit without being restricted by the film thickness of the single crystal silicon film 5, 13 can be formed. In addition, since the circuit elements 11 and 13 are directly formed on the single crystal silicon substrate 2 in this way, the heat dissipation effect for the heat generated in the circuit is improved.
[0078]
In the third embodiment described above, the sensor chip 14 can be formed with a configuration in which the oxide film 3 is not interposed. In this case, when the single crystal silicon film 5 is etched in the semiconductor layer removing step Q1, there is no oxide film 3 serving as an etching stopper, so that the film thickness of the single crystal silicon film 5 is reduced by the etching process. After the removal, it is preferable to form the circuit elements 11 and 13 in a state in which a portion where a defect near the joint is generated is removed by etching.
[0079]
Further, in the above embodiment, the MOS circuit element 11 is formed in the single crystal silicon film 5 (region having the SOI structure), and only the single crystal silicon film 5 and the oxide film 3 in the region where the bipolar circuit element 13 is formed. The bipolar circuit element 13 may be formed on the surface 15 of the single crystal silicon substrate 2 which is the second substrate exposed by the removal.
[0080]
(Fourth embodiment)
FIGS. 11 to 13 show a fourth embodiment of the present invention. The difference from the first embodiment is that for the pressure reference chamber 7 constituting the sensor chip 16 and the pressure reducing communication hole 8. It is the formation method of this groove part. That is, as shown in FIG. 13E, the sensor chip 16 is provided with a silicon oxide film 17 having a predetermined thickness on the upper surface of the single crystal silicon substrate 2 as the second substrate, and a part thereof is etched. By removing, the recessed part 17a and the groove part 17b are formed. On top of this, a single crystal silicon film 5 is formed in the same manner as described above to provide a diaphragm 6 and a pressure reference chamber 7.
[0081]
Next, a method for manufacturing the sensor chip 16 (see FIG. 11) will be described. The ion implantation layer forming step P1 is performed in the same manner as in the first embodiment. An oxide film forming step R1 is performed on the single crystal silicon substrate 2 as the second substrate prior to the recess forming step P2. An oxide film 17 having a predetermined thickness is formed on the surface of the single crystal silicon substrate 2 by a method such as thermal oxidation or CVD. In this case, since the film thickness of the oxide film 17 is about 2 μm at the maximum in the thermal oxidation method and about 5 μm at the maximum in the CVD method, it is appropriately selected and formed as necessary.
[0082]
Next, in the recess forming step P2, unlike in the first embodiment, openings 17a and 17b serving as recesses and grooves are formed in the oxide film 17 by etching (see FIGS. 12A and 12B). ). Thereafter, in the same manner as described above, the bonding step P3 (see FIG. 13A), the peeling step P4 (see FIG. 13B), the element forming step P5 (see FIG. 13C), and the reduced pressure sealing step P6. (See (d) and (e) of the figure) are carried out sequentially.
[0083]
Thereby, the single crystal silicon film 5 as a semiconductor layer is formed, the diaphragm 6 and the pressure reference chamber 7 are formed, the opening 10a is formed after the resistor 10 and the circuit element 11 are formed, and the opening is formed by the CVD method. Sealing is performed by forming a protective film 9 by reducing the pressure in the pressure reference chamber 8 from 8 a through the pressure reducing communication hole 8 so as to be in a vacuum state. The sensor chip 16 is formed by removing the protective film 9 on the diaphragm 6.
[0084]
According to the fourth embodiment, the recess forming step P2 for forming the recess 17a for the pressure reference chamber 7 and the groove 17b for the pressure reducing communication hole 8 forms the oxide film 17 on the recess 17P. Since the window portion is provided, the sensor chip 16 can be formed through a simple processing process when the depth dimension of the concave portion 17a meets the conditions.
[0085]
(Fifth embodiment)
14 and 15 show a fifth embodiment of the present invention. The difference from the fourth embodiment is that a semiconductor layer removing step Q1 is performed after the peeling step P4. That is, the sensor chip 18 in this embodiment has a configuration in which the bipolar circuit element 13 is provided, as described in the third embodiment.
[0086]
Next, a method for manufacturing the sensor chip 18 (see FIG. 14) will be described. That is, the semiconductor layer removing step Q1 is performed after forming the single crystal silicon film 5 to form the diaphragm 6 and the pressure reference chamber 7 (see FIG. 15A) by performing the peeling step P4 in the same manner as described above. Then, the single crystal silicon film 5 around the diaphragm 6 is removed and the oxide film 17 is removed to form the surface 15 of the single crystal silicon substrate 2 exposed (see FIG. 5B). .
[0087]
Thereafter, through an element formation step P5, a MOS circuit element 11 and a bipolar circuit element 13 are formed on the surface 15 of the single crystal silicon substrate 2 to provide a signal processing circuit (see FIG. 5C). Subsequently, in the decompression sealing step P6, an opening 8a is formed in the communication hole 8 for decompression (see FIG. 4D), a protective film 9 is formed by a CVD method, and the opening 8a is sealed. The sensor chip 18 can be obtained by removing the protective film 9 in the diaphragm 6 portion.
[0088]
According to the fifth embodiment, the heat radiation effect on the circuit elements 11 and 13 to be formed is improved while simplifying the recess forming step P2 for obtaining the pressure reference chamber 7 as a configuration using the oxide film 17. Therefore, a signal processing circuit can be formed on the surface 15 of the single crystal silicon substrate 2.
[0089]
(Sixth embodiment)
FIGS. 16 to 20 show a sixth embodiment of the present invention, and different parts from the first embodiment will be described below. This embodiment is particularly effective when the film thickness of the diaphragm 6 when formed as the sensor chip 19 is thin, or when the dose of the ion implantation layer 12 is insufficient, and the single crystal silicon film is used in the peeling process P4. The single crystal silicon substrate 4 can be surely peeled when peeling 5 is formed.
[0090]
The structure of the completed sensor chip 19 is the same as that of the sensor chip 1 described in the first embodiment, and a different process is performed in an intermediate manufacturing process (see FIG. 16). That is, for the single crystal silicon substrate 4 as the first substrate, the ion implantation layer 12 is formed under predetermined conditions in the ion implantation layer forming step P1 in the same manner as described above (see FIG. 17A).
[0091]
Next, in the recess forming step P2, unlike the above, when forming the recess 2a corresponding to the pressure reference chamber 7 and the groove 2b corresponding to the pressure reducing communication hole 8 on the single crystal silicon substrate 2 as the second substrate. In addition, the portions of the recess 2a and the groove 2b that do not etch silicon are left as the silicon support portions 20. The silicon support 20 is formed, for example, by patterning so as to remain on the bottom surface of the recess 2a and the groove 2b in a prismatic shape of about 0.1 to 3 μm (see FIG. 17B).
[0092]
In this case, as shown in FIG. 20, the groove 2b is formed on both sides of the recess 2a because of an etching process in a later process (in FIG. 17 and FIG. 18, one groove is used to avoid complication). 2b only), a large number of silicon pillars 20 are arranged in the two grooves 2b and the recesses 2a. Here, the silicon support column 20 is formed in a prismatic shape, but may be a cylinder or other shapes.
[0093]
Next, in the thermal oxidation step S1, the single crystal silicon substrate 2 is thermally oxidized to oxidize the silicon of the silicon support 20 until it becomes silicon oxide, thereby forming the silicon oxide support 20a. At this time, the oxide film 3 is also formed on the inner bottom and side walls of the recess 2a and the groove 2b (see FIG. 17C).
[0094]
Thereafter, a single crystal silicon film 5 is formed on the single crystal silicon substrate 2 through a bonding process P3 and a peeling process P4. At this time, in the bonding step P3 (see FIG. 18A), the tip position of the silicon oxide support 20a formed in the recess 2a and the groove 2b of the single crystal silicon substrate 2 is on the same plane as the substrate surface. The surface of the bonded single crystal silicon substrate 4 comes into close contact with the silicon oxide support 20a.
[0095]
When the peeling step P4 is performed in a state where the two single crystal silicon substrates 2 and 4 are attached in this manner, the single crystal silicon film 5 in the portion to be the diaphragm 6 becomes the concave portion 2a and the groove portion on the single crystal silicon substrate 2 side. Since it is in a state of being in close contact with the silicon oxide support portion 20a formed on 2b, when peeling occurs in the ion implantation layer 12 of the single crystal silicon substrate 4, this portion cannot be completely peeled and is cracked around the first substrate. It is possible to avoid a problem that incomplete peeling occurs in a state of being attached to a single crystal silicon substrate 4 side. This contributes as a major factor particularly when the thickness of the single crystal silicon film 5 to be peeled is thin, so that it is an effective structure for reliably carrying out the peeling step P4.
[0096]
In the state where the peeling step P4 is performed as described above to form the single crystal silicon film 5, the silicon oxide support 20a remains in the pressure reference chamber 7 and the pressure reducing communication hole 8. (Refer to (b) in the figure). Then, in this state, the next element formation step P5 is performed to form the low antibody 10 in the diaphragm 6 portion of the single crystal silicon film 5, and the MOS circuit element 11 for the signal processing circuit in the outer peripheral region of the diaphragm 6 (See FIG. 2C).
[0097]
Next, in the column etching step S2, the single crystal silicon film 5 located at the end portions of the two decompression communication holes 8 is removed by an etching process to form an opening 8a (see FIG. 19A). (Only one opening 8a is shown), and an etching solution of silicon oxide such as a hydrogen fluoride solution is circulated through the two openings 8a to selectively select the silicon oxide support 20a and the oxide film 3. Etching to remove (see FIG. 2B). In this case, since the opening 8a is formed at two places, the etching solution easily flows inside.
[0098]
In the reduced pressure sealing process P6, the protective film 9 is formed by evacuating the inside of the pressure reference chamber 7 using a CVD apparatus in the same manner as described above so that the two openings 8a are covered with the protective film 9. And seal. After that, the sensor chip 19 is formed by removing the protective film 9 in the diaphragm 6 portion.
[0099]
According to the sixth embodiment, since the silicon oxide support 20a is formed in the recess 2a and the groove 2b prior to the bonding step P3, the bonding state of the diaphragm 6 portion is excellent in the bonding step P3. Thus, the single crystal silicon film 5 can be surely peeled by avoiding problems such as partially peeling the peeling in the peeling step P4.
[0100]
The silicon oxide support 20a is formed as the silicon support 20 when the single crystal silicon substrate 2 is etched simultaneously with the formation of the recess 2a and the groove 2b, and is formed by thermal oxidation in the thermal oxidation step S1. The number of processes does not increase greatly. Furthermore, since the silicon oxide pillar 20a is selectively removed by the pillar etching step S2 prior to the decompression sealing step P6, the completed sensor chip 19 is not adversely affected.
[0101]
(Seventh embodiment)
FIGS. 21 and 22 show a seventh embodiment of the present invention. The difference from the sixth embodiment is that the semiconductor layer removing step Q1 described in the third embodiment is replaced with the element forming step P5. The circuit elements 11 and 13 of the signal processing circuit are formed on the surface 15 of the single crystal silicon substrate 2 which is the second substrate (see FIG. 21 for the manufacturing process).
[0102]
After performing the ion implantation layer forming step P1, the recess forming step P2, the thermal oxidation step S1, the bonding step P3 and the peeling step P4 (see FIG. 22A) in the same manner as in the sixth embodiment, the semiconductor layer is removed. The surface 15 of the single crystal silicon substrate 2 which is the second substrate is exposed by performing the process Q1 to remove the single crystal silicon film 5 and the oxide film 3 around the diaphragm 6 by etching (FIG. 5B). )reference).
[0103]
Next, in the element formation step P5, the resistor 10 is formed on the surface of the diaphragm 6, and the MOS circuit element 11 which is a circuit element for a signal processing circuit and the bipolar circuit are formed on the exposed surface 15 of the single crystal silicon substrate 2. Element 13 is formed (see FIG. 4C).
[0104]
Thereafter, in the same manner as described above, after the opening 8a is formed in the pressure reducing communication hole 8 in the column etching step S2 (see FIG. 4D), the silicon oxide formed in the recess 2a and the groove 2b is formed. The supporting column 20a is selectively removed by etching (see FIG. 5E), and subsequently, in the reduced pressure sealing step P6, the pressure reference chamber 7 is depressurized so as to be in a vacuum state, and a protective film By forming 9, the opening 8 a is sealed, and the protective film 9 in the diaphragm 6 portion is removed by etching, whereby the sensor chip 21 can be obtained (see FIG. 5F).
[0105]
According to the seventh embodiment, the same effect as that of the sixth embodiment can be obtained, and the thickness of the diaphragm 6 is not limited when the bipolar circuit element 13 is formed. In addition, it is possible to increase the effect of dissipating heat from the signal processing circuit to the back surface side of the single crystal silicon substrate 2 as the second substrate.
[0106]
(Eighth embodiment)
FIGS. 23 to 26 show an eighth embodiment of the present invention. The difference from the sixth embodiment is that the surface of the single crystal silicon substrate 2 as the second substrate is the structure of the sensor chip 22. In order to obtain a configuration in which the oxide film 3 is not formed, a nitride film forming step T1 (see FIG. 23) is provided prior to the recess forming step P2 in the manufacturing process.
[0107]
That is, after the ion implantation layer forming step P1 is performed as described above (see FIG. 24A), the single crystal silicon substrate 2 as the second substrate is mirror-polished in the nitride film forming step T1. A silicon nitride film 23 is formed on the surface. Thereafter, in the recess forming step P2, a part thereof is patterned by a photolithography process, and the recess 2a for the pressure reference chamber 7 and the groove 2b of the communication hole 8 for decompression are the same as described in the second embodiment. Are removed by etching so as to form a concave portion 2c (see FIG. 7) having a shape integrated with each other (see FIG. 24B).
[0108]
At this time, a large number of silicon support portions 20 are formed in the recess 2c, as in the sixth embodiment. Then, by carrying out the thermal oxidation step S1, the silicon pillar 20 is completely made of silicon oxide to form the silicon oxide pillar 20a, and the oxide film 3 is also formed on the bottom and side surfaces of the recess 2c (FIG. c)). In this thermal oxidation step S1, an oxide film is not formed on the portion of the single crystal silicon substrate 2 where the silicon nitride film 23 is formed, using this as a mask.
[0109]
Thereafter, the next bonding step P3 is performed with the silicon nitride film 23 removed by etching (see FIG. 26A). Thereafter, the peeling process P4 (see FIG. 5B) and the element formation process P5 are performed to form the resistor 10 and the MOS circuit element 11 on the single crystal silicon film 5 (see FIG. 5C). Subsequently, the sensor chip 22 can be obtained through the column etching step S2 (see FIG. 26A) and the reduced pressure sealing step P6 (see FIGS. 26B and 20C).
[0110]
In this case, since the structure of the sensor chip 22 is such that the oxide film 3 is not provided on the surface of the single crystal silicon substrate 2, in the column etching step S2, the overetching of the oxide film 3 as in the sixth embodiment is performed. Therefore, it is possible to control to reliably remove the silicon oxide support 20a by etching.
[0111]
According to the eighth embodiment, the same effect as that of the sixth embodiment can be obtained, and the controllability of the etching process in the column etching process S2 can be improved.
[0112]
In the above-described case, the recess forming step P2 is performed with the oxide film first formed on the surface of the single crystal silicon substrate 2 as the second substrate and the silicon nitride film 23 provided thereon. Alternatively, the recess forming step P2 may be performed using a photoresist provided on the silicon nitride film 23 as a mask material.
[0113]
(Ninth embodiment)
27 and 28 show a ninth embodiment of the present invention. The difference from the first embodiment is that the ion implantation layer 12 is formed on the single crystal silicon substrate 4 which is the first substrate. An amorphous film forming step U1 (see FIG. 27) for amorphizing the surface layer portion of the surface to be formed has been performed.
[0114]
That is, after the ion implantation layer 12 is formed on the single crystal silicon substrate 4, in the amorphous film forming step U1, rare gas ions such as silicon ions or argon ions are implanted into the surface layer portion by an ion implantation method. As a result, a silicon amorphous layer 24 which is an amorphous film is formed in a region shallower than the ion implantation layer 12 (see FIG. 28). As a result, the mechanical strength of the portion of the single crystal silicon substrate 4 to be peeled can be increased, and the occurrence of partial cracks or tears can be prevented when peeling in the peeling step P4. become.
[0115]
Further, the formed amorphous layer 24 can be single-crystallized by rearranging the single crystal silicon remaining in the peeled portion as a seed through a high-temperature heat treatment step in the peeling step P4. A single crystal silicon film 5 can be obtained.
[0116]
According to the ninth embodiment, in order to prevent the single crystal silicon film 5 from being broken or torn in the peeling process P4, the amorphous film forming process U1 is performed to improve the mechanical strength. Therefore, the generation of cracks can be reduced as much as possible, and the single crystal silicon film 5 can be reliably peeled and formed.
Note that the above-described amorphous film forming step U1 may be performed before the ion implantation layer forming step P1.
[0117]
(Tenth embodiment)
FIG. 29 shows a tenth embodiment of the present invention. The difference from the ninth embodiment is that the amorphous silicon as an amorphous film is different from the single crystal silicon substrate 4 as the first substrate. The film 25 is formed by being deposited.
[0118]
That is, as shown in FIG. 29, the amorphous silicon film 25 is formed by CVD or PVD (physical deposition) before or after the ion implantation layer forming step P1. Thereby, the same effect as the ninth embodiment can be obtained. In this case, the same effect can be obtained by forming a polycrystalline silicon film, a silicon oxide film, or a silicon nitride film instead of the amorphous silicon film 25. Further, the amorphous silicon film 25 can be single-crystallized in the peeling step P4 as described above.
[0119]
(Eleventh embodiment)
30 and 31 show an eleventh embodiment of the present invention. The difference from the first embodiment is that, as a structure of the sensor chip 26, the pressure reducing communication hole 8 is a single second substrate. It has just been formed as an opening 27 leading out to the back side of the crystalline silicon substrate 2.
[0120]
That is, in this embodiment, the manufacturing process is the same as that of the first embodiment (see FIG. 1), and the ion implantation layer forming process P1 (see FIG. 30A) and the recess forming process P2 are performed in the same manner as described above. Is carried out and the process proceeds to the bonding step P3 (see FIG. 5B). At this time, in the recess forming step P2, apart from the recess 2a for the pressure reference chamber 7, the opening 27 is formed by etching so that the bottom surface of the recess 2a of the single crystal silicon substrate 2 communicates with the back surface.
[0121]
Thereafter, the separation step P4 (see FIG. 15C), the element formation step P5 (see FIG. 31A) and the decompression sealing step P6 (see FIG. 31B and FIG. 15C) are performed to form a sensor chip. 26 is formed. In this case, in the reduced pressure sealing step P 6, the pressure reference chamber 7 is depressurized through the opening 27 to be in a vacuum state, and then sealed with the sealing member 28. Separately, a protective film 9 is formed on the surface of the sensor chip 26 except for the diaphragm 6 portion.
[0122]
Also according to the eleventh embodiment, the same operational effects as described above can be obtained. In the above-described case, as one of the usage forms of the sensor chip 26, for example, when the detection operation is performed by the pressure difference received by the diaphragm 6 by opening the pressure reference chamber 7 to the atmosphere, the sealing member 28 is used. It can also be used as a configuration in which no is provided.
[0123]
(Twelfth embodiment)
FIGS. 32 to 35 show a twelfth embodiment of the present invention. Hereinafter, differences from the first embodiment will be described. In this embodiment, as shown in FIG. 35 (h), a pressure sensor semiconductor substrate 29 is formed with a silicon oxide film 31 as an insulating film on the surface of a single crystal silicon substrate 30 serving as a support substrate. A pressure reference chamber 33 is formed in a predetermined region by a recess 32 formed to a predetermined depth of the silicon oxide film 31 and the silicon single crystal substrate 30.
[0124]
Then, a single crystal silicon thin film 34 as a semiconductor layer is formed on the surface of the single crystal silicon substrate 30 so as to close the pressure reference chamber 33, and a diaphragm 35 is provided. The pressure reference chamber 33 is decompressed and set to a pressure close to a vacuum state. Therefore, the structure is basically the same as that of the sensor chip 1 that is the semiconductor substrate for pressure sensors shown in the first embodiment. In the figure, the single crystal silicon thin film 34 is shown in a state where no pressure measuring resistor or sensor circuit is formed.
[0125]
Next, with reference to the outline of the manufacturing process shown in FIGS. 32 and 33, the manufacturing process of the semiconductor substrate 29 for pressure sensors will be schematically described.
(1) Ion implantation layer forming step V1
First, the process of forming the insulating film separation substrate 36 as the first substrate will be described with reference to the step shown in FIG. 32 and the schematic cross-sectional view of FIG. This insulating film separating plate 36 is used to make it possible to set the thickness dimension of the diaphragm 35 with high accuracy when the single crystal silicon thin film 34 formed by the first substrate is used as the diaphragm 35 ( (See (c) in the figure).
[0126]
First, a single crystal silicon substrate 37 as a third substrate is prepared, and a high-concentration ion-implanted layer 38 in which hydrogen ions (protons) are implanted at a predetermined depth from the surface is formed on the single-crystal silicon substrate 37 (FIG. 34 (a)). In this case, the depth at which the ion-implanted layer 38 is formed is determined by the implantation acceleration voltage. Finally, in order to determine the thickness dimension of the diaphragm 35, it is set in advance to have a desired thickness. It is necessary to keep.
[0127]
Specifically, 220 keV is required to obtain the 2.0 μm diaphragm 35, and in order to obtain the 1.0 μm diaphragm 35, hydrogen ions are implanted at an acceleration voltage of about 120 keV. The ion implantation amount is 1 × 10.¹⁶atoms / cm²Above, preferably 5 × 10¹⁶atoms / cm²The above is necessary. Further, by forming an oxide film 39 on the surface of the single crystal silicon substrate 37 to be ion-implanted by thermal oxidation or a film formation method in advance, it is possible to reduce damage to the surface layer by ion implantation and to prevent impurity contamination.
[0128]
(2) Bonding process V2
Next, the single crystal silicon substrate 37 which is a third substrate and the single crystal silicon substrate 40 which is a fourth substrate which is separately prepared are bonded to each other (see FIG. 34B). In the substrate cleaning step performed prior to the bonding step, the single crystal silicon substrate 37 on which the ion implantation layer 38 is formed has an anti-contamination oxide film 39 formed on the surface using an etching solution such as a hydrofluoric acid aqueous solution. Can be used to completely remove and decontaminate and planarize the surface.₂SO₄(Sulfuric acid) and H₂O₂By washing with a solution in which (hydrogen peroxide solution) is mixed 4 to 1, a natural oxide film is formed on the surface, and a hydrophilic treatment is performed.
[0129]
For the single crystal silicon substrate 40 as the fourth substrate, a silicon oxide film 41 that functions as a buried oxide film (insulating film) of the insulating film isolation substrate 36 is formed in advance, and then H₂SO₄And H₂O₂Is washed with a solution prepared by mixing 4 to 1, a natural oxide film is formed on the surface, and a hydrophilic treatment is performed. Thereafter, the two substrates are bonded to each other. As for the substrate cleaning, the single crystal silicon substrate 37 is made of H without removing the anti-contamination oxide film 39.₂SO₄And H₂O₂It is possible to planarize by removing contaminants on the surface only by washing with a 4: 1 mixed solution, and bonding to the single crystal silicon substrate 40 is also possible.
[0130]
H₂SO₄And H₂O₂Instead of the above-described method of forming a natural oxide film on the surface and performing a hydrophilization treatment, the substrate is subjected to a hydrophobization treatment such as a hydrofluoric acid aqueous solution. It is also effective. This is because the bonding strength is somewhat lowered by performing the hydrophobization treatment, but when a bonding strength of a certain level or more is obtained, the residual moisture on the bonding surface can be reduced as much as possible. This is particularly true when the pressure reference chamber 33 is formed at the same time when bonding is performed in a vacuum atmosphere, particularly by preventing the occurrence of unbonded regions (voids) and residual moisture in the pressure reference chamber 33. Can be pasted together.
[0131]
(3) Peeling process V3
Next, heat treatment is performed in a state where the two substrates are bonded to each other, thereby strengthening the bonding strength of the bonding surface and causing peeling due to an increase in the pressure of implanted hydrogen in the ion implanted layer 38 (FIG. 34 ( c)). The heat treatment temperature at this time needs to be about 400 ° C. to 600 ° C., and the heat treatment apparatus may be an electric furnace or a short time heat treatment by lamp heating. Note that the heat treatment atmosphere can be peeled regardless of whether it is in atmospheric pressure (for example, a nitrogen atmosphere) or in a vacuum.
[0132]
In a portion where the hydrogen ion implantation layer 38 is formed, the single crystal silicon thin film 34 as a semiconductor layer is peeled off, and this is bonded to the single crystal silicon substrate 40 which is the fourth substrate via the oxide film 41. Thus, the structure of the insulating film separation substrate can be obtained. Since sufficient bonding strength cannot be obtained by the above heat treatment at about 400 ° C. to 600 ° C., actually, heat treatment is performed at a temperature of 1000 ° C. or higher, preferably 1100 ° C. or higher after peeling.
[0133]
Further, the surface roughness of the peeled surface is 5 to 10 nm in terms of Ra value, and in order to achieve bonding with the single crystal silicon substrate (second substrate) 30 in the next step, the surface roughness Ra = It is necessary to reduce the thickness to 0.5 nm or less, and it is necessary to achieve surface smoothing by a mechanical polishing method (CMP (Chemical Mechanical Polishing)) or to perform smoothing by etching only the oxide film after thermally oxidizing the peeled surface. is there. As a result, the insulating film separation substrate 36 can be formed as the first substrate.
[0134]
(4) Concave formation step P2
In this step, a step similar to that described in the first embodiment is performed, and a recess 32 is formed by etching in a single crystal silicon substrate 30 as a second substrate (see the right side in FIG. 35 (d)). . However, in this case, in the description of this embodiment, unlike the case of the first embodiment, the process of forming the pressure reference chamber 33 without using the pressure reducing communication portion 2b is adopted, so the subsequent processes are also slightly different. There are changes. However, in this embodiment as well, as in the first embodiment, it is possible to employ a process having a configuration in which the pressure reducing communication portion 2b is provided.
[0135]
(5) Ion implantation layer forming step V4
In this step, an ion implantation layer 42 for peeling is formed in the oxide film 41 formed on the insulating film isolation substrate 36 or at a position deeper than the oxide film 41 (see the left side of FIG. 4D). In this case, the ion implantation layer 42 is formed as a high concentration hydrogen ion implantation layer by implanting, for example, hydrogen ions (protons). Further, since the depth for forming the ion implantation layer 42 is determined by the implantation acceleration voltage, it is set so that the implantation peak is located in the oxide film 41 or in the substrate deeper than that. At this time, the ion implantation amount is 1 × 10.¹⁶atoms / cm²Above, preferably 5 × 10¹⁶atoms / cm²The above is necessary.
[0136]
(6) Bonding process P3
Here, the insulating separation film substrate 36 and the single crystal silicon substrate 30 formed with the recesses 34 are bonded together (see FIG. 35E). In the substrate cleaning process performed prior to the bonding process, H₂SO₄And H₂O₂Is washed with a solution prepared by mixing 4 to 1, a natural oxide film is formed on the surface, and a hydrophilic treatment is performed. For the single crystal silicon substrate 30, an oxide film 31 is formed on the surface in advance, a natural oxide film is formed on the surface, and a hydrophilic treatment is performed. Thereafter, the two substrates are bonded to each other so as to adhere to each other.
[0137]
At this time, the atmosphere in which the bonding is performed may be in atmospheric pressure or in a vacuum. At this time, by performing bonding in a vacuum, it is possible to prevent air remaining in the bonding surface, reduce unbonded regions (voids), and dehydrate the inside of the recess 34 for the pressure reference chamber 33. Therefore, the vacuum sealing process performed after element formation can be made unnecessary. As a result, after the diaphragm 35 is formed, it is possible to prevent the diaphragm 35 from being damaged due to the expansion of moisture.
[0138]
(7) Support substrate thinning step V5
In order to make the insulating film separation substrate 36 into a thin piece, the ion implantation layer 42 is peeled off. In order to cause peeling, heat treatment is performed in a state where the two substrates are bonded to each other, and a pressure increase of implanted hydrogen in the ion implantation layer 42 is generated to cause peeling (see FIG. 35F). In addition, this heat treatment simultaneously enhances the joint strength of the joint surface. The heat treatment temperature and other conditions are almost the same as in the above-described peeling step V3. As a result, a single crystal silicon thin film 34 as a semiconductor layer can be formed on the single crystal silicon substrate 30 with the buried oxide film 34 interposed therebetween.
[0139]
In the state after the peeling, a part of the oxide film 41 and the single crystal silicon substrate 40 remains on the single crystal silicon thin film 34. The part that is finally used after forming the element is the part of the single crystal silicon thin film 34, which is formed irrespective of the peeled surface. There is no need to perform processing.
[0140]
On the other hand, since the peeled single crystal silicon substrate 40 is only separated in the surface layer portion by peeling, most of the peeling is performed in the state of the substrate. It can be reused for purposes or other purposes, and the cost can be reduced.
[0141]
(8) Embedded oxide film removal step V6
Next, by removing the thin film of the single crystal silicon substrate 40 and the oxide film 41 remaining on the peeled surface, a semiconductor layer 34 with high film thickness uniformity is formed. First, as for the removal of the thin film of the single crystal silicon substrate 40, the oxide film 41 is used as a stopper to remove by performing a treatment with an alkaline solution such as TMAH treatment or KOH, or an etching treatment with a mixed solution of nitric acid and hydrofluoric acid (same as above). (Refer figure (g)). The thin film of the single crystal silicon substrate 40 can be similarly removed by mechanical chemical polishing using the oxide film 41 as a stopper.
[0142]
Thereafter, the exposed oxide film 41 is removed by etching with a hydrofluoric acid aqueous solution or the like (see FIG. 11H). As a result, the single crystal silicon thin film 34 as the semiconductor layer can be formed in a state where it is left on the surface. Further, the single crystal silicon thin film 34 can be formed to have a predetermined thickness dimension without acting directly from the outside after the peeling process, and can be obtained with an increased film thickness accuracy. . As a result, the diaphragm 35 and the pressure reference chamber 33 are formed.
[0143]
(9) Element formation process P5
In the above-described state, the single crystal silicon thin film 34 is formed on the single crystal silicon substrate 30 as the second substrate with the insulating film 41 interposed therebetween, so that the substrate structure is SOI (Silicon On Insulator) structure. A resistor having a piezoresistive effect for pressure detection is formed on the single crystal silicon thin film 34, and various elements such as MOS transistors constituting a signal processing circuit are formed. The resistors are wired so as to form a bridge circuit by a wiring pattern, and the input / output terminals are wired so as to be connected to the signal processing circuit.
[0144]
(10) Depressurization sealing process P6
Next, in the bonding step P3, when manufacturing a type that does not perform bonding in a vacuum atmosphere, the inside of the pressure reference chamber 33 needs to be reduced to a vacuum or a predetermined pressure. The reduced pressure sealing process P6 is performed. That is, an opening is formed in the single crystal silicon thin film 34 at the end opposite to the pressure reference chamber 33 of the pressure reducing communication hole formed by the groove and the single crystal silicon film 34. In this case, the opening is formed by etching or the like from the surface side of the single crystal silicon thin film 34.
[0145]
Thereafter, an insulating protective film is formed on the surface of the single crystal silicon thin film 34 formed as described above by a CVD apparatus or the like, and the opening is simultaneously sealed under reduced pressure. For example, the pressure in the pressure reference chamber 33 is reduced through the pressure reducing communication hole by reducing the pressure in a state where it is placed in the CVD apparatus and exposing it to a vacuum atmosphere. An insulating protective film such as a silicon nitride film or a silicon oxide film is deposited on the entire surface while the inside is in a vacuum, thereby simultaneously sealing the inside of the opening. Thereafter, the protective film on the diaphragm 35 is peeled off by photolithography to form a sensor chip.
[0146]
According to such a twelfth embodiment, in addition to the effects of the first embodiment, in the supporting substrate thinning step V5 using the insulating film isolation substrate 36 as the first substrate, a single crystal as a semiconductor layer Peeling is performed with the oxide film 41 left on the silicon thin film 34, and the oxide film 41 is removed in a subsequent process, so that the film thickness of the single crystal silicon thin film 34 can be formed with high accuracy.
[0147]
In addition, since the oxide film separation substrate 36 forms an ion implantation layer 38 therein and peels it in the peeling step V3 to form a portion to be the semiconductor layer 34, the peeled substrate Can be reused, and the cost can be reduced.
[0148]
Furthermore, in this embodiment, when the pressure reference chamber 33 is bonded in the bonding step P3, the pressure reference chamber 33 is sealed in a vacuum state by performing it in a vacuum at the same time. It is also possible to use a manufacturing method that does not employ, and to simplify the process.
[0149]
In this embodiment, the bonding steps V2 and P3 can be performed by a hydrophobic treatment instead of the hydrophilic treatment. Therefore, moisture that tends to remain in the recesses 32 or the like during bonding is removed as much as possible. Breakage of the diaphragm 35 after alignment can be prevented.
[0150]
Also in the above-described embodiment, the diaphragm 35 and the pressure reference chamber 33 are formed on the insulating film separation substrate by previously adopting the insulating film separation substrate for the single crystal silicon substrate 30 as the second substrate on which the recess 32 is formed. Can be formed. As a result, when the pressure sensor control circuit is formed around the pressure reference chamber, it can be formed in the insulating film isolation region, the element isolation structure can be easily formed, and the electrical characteristics such as withstand voltage can be improved. It becomes possible to plan.
[0151]
(13th Embodiment)
FIG. 36 shows a thirteenth embodiment of the present invention. The difference from the twelfth embodiment is that the insulating substrate 44 is used as the second substrate when forming the semiconductor substrate 43 for pressure sensors. I just did it.
[0152]
That is, FIG. 2A shows a schematic cross-sectional view of the semiconductor substrate 43 for pressure sensor, and an insulating film such as a silicon oxide film is formed on the single crystal silicon substrate 40 instead of the second substrate 30. In this state, a single crystal silicon thin film 46 as a semiconductor layer is provided via 45. That is, by adopting a configuration employing the insulating film isolation substrate 44, the single crystal silicon thin film 46 provided in a state where the pressure reference chamber 33 and its peripheral circuit formation region are isolated from the single crystal silicon substrate 40. It will be formed in the part.
[0153]
As a result, when the pressure sensor control circuit is formed around the pressure reference chamber, it can be formed in the insulating film isolation region, which facilitates the formation of the element isolation structure and improves the electrical characteristics such as withstand voltage. It becomes possible to plan. Here, the pressure sensor semiconductor substrate 43 having the configuration shown in FIG. 5A shows a state in which the bottom surface portion of the pressure reference chamber 33 is formed in the single crystal silicon thin film 46, and the element formation region is shown. This is a case where the depth dimension of the recess 32 of the pressure reference chamber 33 is shallow with respect to the film thickness of the single crystal silicon thin film 46 required for formation.
[0154]
On the other hand, the basic structure of the pressure sensor semiconductor substrate 47 shown in FIG. 5B is the same as that of the pressure sensor semiconductor substrate 43, and the depth dimension of the pressure reference chamber 33 is the film of the single crystal silicon thin film 46. The thickness is set to be the same as the thickness, and the bottom surface of the pressure reference chamber 33 is different from the top surface of the insulating film 45. As the pressure sensor semiconductor substrates 43 and 47, those suitable for forming conditions of pressure sensors and circuit elements formed as necessary can be adopted.
[0155]
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
Instead of the insulating protective film 9, polycrystalline silicon may be formed as a material for sealing the opening 8a.
The inside of the pressure reference chamber 7 may be formed in a state where the pressure is reduced to a predetermined pressure level in addition to the case where the state is a vacuum state.
The film thickness of the diaphragm 6, the size of the pressure reference chamber 7, or the size of the communication hole 8 for decompression can also be set to appropriate dimensions according to the pressure range to be measured.
[Brief description of the drawings]
FIG. 1 is a schematic process explanatory diagram showing a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of a first substrate after an ion implantation layer forming step.
FIG. 3 is a schematic cross-sectional view and a top view of a second substrate after a recess formation step
FIG. 4 is a schematic cross-sectional view in each process after the bonding process.
FIG. 5 is a diagram showing the relationship between the direction of the substrate shown in the bonded state and the shape of the opening of the recess.
FIG. 6 is a view showing a silicon substrate having a plane orientation (100), its cleavage direction and a recommended bonding direction.
FIG. 7 is a view corresponding to FIG. 3, showing a second embodiment of the present invention.
FIG. 8 is a view corresponding to FIG. 1, showing a third embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view in each step after the peeling step.
FIG. 10 is a schematic cross-sectional view and a top view after a semiconductor layer removing step.
FIG. 11 is a view corresponding to FIG. 1, showing a fourth embodiment of the present invention.
12 is equivalent to FIG.
FIG. 13 is a view corresponding to FIG.
FIG. 14 is a view corresponding to FIG. 1, showing a fifth embodiment of the present invention.
15 is equivalent to FIG.
FIG. 16 is a view corresponding to FIG. 1, showing a sixth embodiment of the present invention.
FIG. 17 is a schematic cross-sectional view in each step (Part 1).
FIG. 18 is a schematic cross-sectional view in each step (Part 2).
FIG. 19 is a schematic sectional view in each step (No. 3).
FIG. 20 is a top view showing an arrangement state of support columns formed in a recess.
FIG. 21 is a view corresponding to FIG. 1, showing a seventh embodiment of the present invention.
FIG. 22 is equivalent to FIG.
FIG. 23 is a view corresponding to FIG. 1, showing an eighth embodiment of the present invention.
FIG. 24 is a schematic cross-sectional view in each step (Part 1).
FIG. 25 is a schematic cross-sectional view in each step (No. 2).
FIG. 26 is a schematic sectional view in each step (No. 3).
FIG. 27 is a view corresponding to FIG. 1, showing a ninth embodiment of the present invention.
FIG. 28 is a schematic cross-sectional view illustrating an amorphous film forming process U1.
FIG. 29 is a view corresponding to FIG. 26, showing a tenth embodiment of the present invention.
30 is a schematic cross-sectional view (No. 1) of each step showing an eleventh embodiment of the present invention. FIG.
FIG. 31 is a schematic sectional view in each step (No. 2).
FIG. 32 is a view corresponding to FIG. 1 showing a twelfth embodiment of the present invention (part 1).
FIG. 33 is a view corresponding to FIG. 1 (part 2).
FIG. 34 is a schematic sectional view in each step (No. 1).
FIG. 35 is a schematic sectional view in each step (No. 2).
FIG. 36 is a schematic sectional view showing a thirteenth embodiment of the present invention.
[Explanation of symbols]
Reference numerals 1, 14, 16, 18, 19, 21, 22, 26 are sensor chips (semiconductor substrate for pressure sensor), 2 is a single crystal silicon substrate (second substrate), 2 a is a recess for a pressure reference chamber, and 2 b is a pressure reduction. Communication hole groove portion, 2c is a recess, 3 is an oxide film, 4 is a single crystal silicon substrate (first substrate), 5 is a single crystal silicon film (semiconductor layer), 6 is a diaphragm, 7 is a pressure reference chamber, 8 Is a pressure reducing communication hole, 8a is an opening, 9 is an insulating protective film, 10 is a resistor, 11 is a MOS circuit element, 12 is an ion implantation layer, 13 is a bipolar circuit element, 15 is the surface of the second substrate, 17 Is an oxide film, 20 is a silicon pillar, 20a is a silicon oxide pillar, 23 is a silicon nitride film (nitride film), 24 is an amorphous layer (amorphous film), 25 is an amorphous silicon film (amorphous film), 27 is an opening, 29 is a semiconductor for a pressure sensor Substrate, 30 is a second substrate, 31 is a silicon oxide film, 32 is a recess, 33 is a pressure reference chamber, 34 is a single crystal silicon thin film (semiconductor layer), 35 is a diaphragm, 36 is an insulating film isolation substrate, and 37 is a single substrate Crystalline silicon substrate (third substrate), 38 is an ion implantation layer, 40 is a single crystal silicon substrate (fourth substrate), 42 is an ion implantation layer, 43 and 47 are semiconductor substrates for pressure sensors, and 44 is an insulating film isolation. A substrate, 45 is an insulating film, and 46 is a single crystal silicon thin film (semiconductor layer).

Claims (34)

A semiconductor substrate (1, 14, 16, 18, 19, 21) used for a pressure sensor that electrically detects the pressure applied to the diaphragm (6) based on the stress generated by the pressure difference from the pressure reference chamber (7). , 22, 26),
An ion implantation layer forming step (P1) for forming an ion implantation layer (12) for separation at a predetermined depth of a first substrate (4) made of semiconductor for forming the diaphragm (6);
In order to form the pressure reference chamber (7), a recess (2a) for the pressure reference chamber (7) is provided in the second substrate (2), and the depth is the same as the depth dimension on the inner bottom surface of the recess (2a). A recess forming step (P2) for forming a column portion (20, 20a) that can be selectively etched in
A bonding step (P3) for bonding the first and second substrates (4, 2);
The bonded first substrate (4) is peeled off at the ion implantation layer (12) portion to form a semiconductor layer (5) on the surface of the second substrate (2), whereby the diaphragm (6 And a peeling step (P4) for forming the pressure reference chamber (7). In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 1,
In the recess forming step (P2), the recess (2a) is formed by etching the surface of the second substrate (2). In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 1 or 2,
In the bonding step (P3), the bonding is performed with the first substrate (4) in a state where an oxide film (3) is provided on the surface of the second substrate (2). A method for manufacturing a semiconductor substrate for a sensor. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 3,
In the concave portion forming step (P2), the column portion (20, 20a) formed on the inner bottom surface of the concave portion (2a) is constituted by a plurality of columns . In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 4,
In the recess forming step (P2), the support column (20) is formed by providing a pattern for forming the support column (20) during the etching process for forming the recess (2a) on the second substrate (2). In addition, after that, a thermal oxidation step (S1) is performed to change the support portion (20) into an oxide (20a) so that a selective etching process can be performed. . In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 5 ,
A method for manufacturing a semiconductor substrate for a pressure sensor , comprising a post etching step (S2) for removing the post portion (20a) by a selective etching process after the peeling step (P4) . In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 6,
After the peeling step (P4), the semiconductor layer (5) in a predetermined region other than the diaphragm (6) portion of the semiconductor layer (5) formed on the surface of the second substrate (2) is removed. A semiconductor substrate for a pressure sensor, characterized in that a semiconductor layer removing step (Q1) is provided for exposing the element forming region to the surface (15) of the second substrate (2). Method. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 7 ,
In prior Symbol concave portion forming step (P2), comprises the step of the recess of the pressure reference chamber (7) for (2a) to form a reduced pressure for communicating portion communicating with the outside (2b),
After the peeling step (P4), the pressure reducing sealing step of sealing the pressure reference chamber (7) by reducing the pressure through the pressure reducing communication hole (8) formed by the pressure reducing communication portion (2b). (P6) is provided . A method for manufacturing a semiconductor substrate for a pressure sensor. In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 8 ,
In the concave portion forming step (P2), the pressure reducing communication portion (2b) is formed as a groove portion (2b) along the surface portion of the second substrate (2), and is formed after the peeling step (P4). A method for producing a semiconductor substrate for a pressure sensor , wherein the pressure reducing communication hole (8) is formed by covering a surface portion with the semiconductor layer (5) to be formed . In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 8 or 9,
In the concave portion forming step (P2), the pressure reducing communication portion (2b) is a concave portion (2c) formed in the same depth as the depth of the concave portion (2a) . A method for manufacturing a semiconductor substrate. In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 8 ,
In the recess forming step (P2), the pressure reducing communication hole (8) is formed as an opening (27) communicating with the back surface of the second substrate (2). A method for manufacturing a substrate. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 8 to 11,
In the reduced pressure sealing step (P6), the film (9) is formed so as to seal the opening (8a) of the reduced pressure communication hole (8) in a reduced pressure atmosphere by a CVD method. Manufacturing method of semiconductor substrate for pressure sensor. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 12 ,
The first substrate (4) is formed so that a portion to be the semiconductor layer (5) includes non-single crystal layers (24, 25) made of an amorphous layer or a polycrystalline layer. A method for manufacturing a semiconductor substrate for a pressure sensor. In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 13 ,
The method for manufacturing a semiconductor substrate for a pressure sensor, wherein the non-single crystal layer (24, 25) includes a constituent element that is the same type as the constituent element of the first substrate (4) . In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 14 ,
The first substrate (4) is a silicon substrate,
The method for manufacturing a semiconductor substrate for a pressure sensor, wherein the non-single crystal layers (24, 25) are formed as an amorphous film or a polycrystalline film . In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 14 ,
The method of manufacturing a semiconductor substrate for a pressure sensor, wherein the non-single crystal layers (24, 25) are formed using any one of an amorphous silicon film, a silicon oxide film, and a silicon nitride film. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 13 to 16,
The method for manufacturing a semiconductor substrate for a pressure sensor, wherein the non-single crystal layers (24, 25) are provided on the surface of the first substrate (4) using a deposition method. A semiconductor substrate (1, 14, 16, 18, 19, 21) used for a pressure sensor that electrically detects the pressure applied to the diaphragm (6) based on the stress generated by the pressure difference from the pressure reference chamber (7). , 22, 26),
An ion implantation layer forming step (P1) for forming an ion implantation layer (12) for separation at a predetermined depth of a first substrate (4) made of semiconductor for forming the diaphragm (6);
A recess forming step (P2) for forming recesses (2a, 2c) for the pressure reference chamber (7) in the second substrate (2) to form the pressure reference chamber (7);
A bonding step (P3) for bonding the first and second substrates (4, 2);
The diaphragm (6) is formed by peeling the bonded first substrate (4) at the ion implantation layer (12) portion to form a semiconductor layer (5) on the surface of the second substrate (2). And a peeling step (P4) for forming the pressure reference chamber (7),
It said first substrate (4) is an amorphous layer or Ranaru non-single crystal layer (24, 25) are formed so as to be included in the a portion to be the semiconductor layer (5),
The method of manufacturing a semiconductor substrate for a pressure sensor, wherein the non-single crystal layers (24, 25) are formed by ion implantation with respect to the first substrate (4). In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 13 or 14 ,
The method for manufacturing a semiconductor substrate for a pressure sensor, wherein the non-single crystal layers (24, 25) are formed by ion implantation with respect to the first substrate (4). A semiconductor substrate (1, 14, 16, 18, 19, 21) used for a pressure sensor that electrically detects the pressure applied to the diaphragm (6) based on the stress generated by the pressure difference from the pressure reference chamber (7). , 22, 26),
An ion implantation layer forming step (P1) for forming an ion implantation layer (12) for separation at a predetermined depth of a first substrate (4) made of semiconductor for forming the diaphragm (6);
A recess forming step (P2) for forming recesses (2a, 2c) for the pressure reference chamber (7) in the second substrate (2) to form the pressure reference chamber (7);
A bonding step (P3) for bonding the first and second substrates (4, 2);
The diaphragm (6) is formed by peeling the bonded first substrate (4) at the ion implantation layer (12) portion to form a semiconductor layer (5) on the surface of the second substrate (2). And a peeling step (P4) for forming the pressure reference chamber (7),
The first substrate (4) is formed so that a non-single crystal layer (24, 25) made of an amorphous layer is included in a portion to be the semiconductor layer (5),
The non-single crystal layer (24, 25), when the elements constituting is a constituent element consists of an element of the same type luer mol fastest silicon film of said first substrate (4), wherein the delamination step (P4) A semiconductor substrate for pressure sensor, wherein the non-single crystal layer (24, 25) is recrystallized by performing a heat treatment after the step to form the semiconductor layer (5) as a single crystal layer. Method. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 14 to 19,
Wherein when the non-single-crystal layer (24, 25) is a luer mol fastest silicon film is composed of elements of said first substrate (4) and allogeneic, by performing heat treatment after the delamination step (P4), A method of manufacturing a semiconductor substrate for a pressure sensor, wherein the non-single crystal layer (24, 25) is recrystallized to form the semiconductor layer (5) as a single crystal layer. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 21,
The method of manufacturing a semiconductor substrate for a pressure sensor, wherein the first substrate (4) is a semiconductor substrate having an oxygen concentration of 1 × 10 ¹⁸ atoms / cm ³ or more. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 12 ,
In the bonding step (P3), the side direction of the quadrilateral that forms the opening of the recess (2a) for the pressure reference chamber (7) formed on the second substrate (2) and single crystal silicon is used. The second substrate (2) and the first substrate (4) are bonded to each other by adjusting the direction so that the cleavage direction of the first substrate (4) intersects. Manufacturing method of semiconductor substrate for pressure sensor. In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 23,
The side direction of the quadrilateral that forms the opening of the recess (2a) for the pressure reference chamber (7) formed on the second substrate (2) and the cleavage direction of the first substrate (4) are the most. A method for manufacturing a semiconductor substrate for a pressure sensor, wherein the semiconductor substrate for pressure sensor is adjusted in a direction that intersects with a large angle. A semiconductor substrate (1,14,16,18,19 used in pressure sensors to electrically detected based pressure experienced diaphragm (6) more generated stress on the pressure difference between the pressure reference chamber (7), 21, 22, 26)
An ion implantation layer forming step (P1) for forming an ion implantation layer (12) for peeling at a predetermined depth of a first substrate (4) made of semiconductor for forming the diaphragm (6);
A recess forming step (P2) for forming recesses (2a, 2c) for the pressure reference chamber (7) in the second substrate (2) to form the pressure reference chamber (7);
A bonding step (P3) for bonding the first and second substrates (4, 2);
The diaphragm (6) is formed by peeling the bonded first substrate (4) at the ion implantation layer (12) portion to form a semiconductor layer (5) on the surface of the second substrate (2). And a peeling step (P4) for forming the pressure reference chamber (7),
In the bonding step (P3), the direction of the side of the opening of the recess (2a) for the pressure reference chamber (7) formed on the second substrate (2) and the first substrate (4) The second substrate (2) and the first substrate (4) are bonded to each other by adjusting the direction so as to intersect with the cleavage direction.
The side direction of the quadrilateral that forms the opening of the recess (2a) for the pressure reference chamber (7) formed on the second substrate (2) and the cleavage direction of the first substrate (4) are the most. A method of manufacturing a semiconductor substrate for a pressure sensor, wherein the semiconductor substrate for pressure sensor is adjusted in a direction that intersects with a large angle . In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 24 or 25 ,
When the plane orientation of the first substrate (4) is (100),
The side direction of the quadrilateral that forms the opening of the recess (2a) for the pressure reference chamber (7) formed on the second substrate (2) and the cleavage direction of the first substrate (4) ( A method of manufacturing a semiconductor substrate for a pressure sensor, characterized in that the semiconductor substrate for pressure sensor is adjusted to a direction that intersects with an angle centered at 22 to 23 ° with respect to each of a (100) plane direction and a (110) plane direction. . In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 26,
In the cleaning step performed prior to the bonding step (P3) , at least the second substrate (2) of the first substrate (4) and the second substrate (2) to be bonded is hydrophobic. A method of manufacturing a semiconductor substrate for a pressure sensor, characterized in that moisture adhering to the surface is removed during the dehydration process by performing the treatment . In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 27,
In the bonding step (P3), the first substrate (4) and the second substrate (2) are adhered to each other in a reduced pressure atmosphere to bond them together. Method for manufacturing semiconductor substrate. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 1 to 28 ,
An insulating film isolation substrate (44) is used as the second substrate, and the pressure reference chamber (33) is formed in a semiconductor layer (46) of the insulating film isolation substrate (44). A method for manufacturing a semiconductor substrate for a sensor. In a method for manufacturing a semiconductor substrate (29, 43, 47) used in a pressure sensor , wherein a pressure received by a diaphragm (35) is electrically detected based on a stress generated by a pressure difference from a pressure reference chamber (33) .
A recess forming step (P2) of providing a recess (34) for the pressure reference chamber (33) in the second substrate (30) to form the pressure reference chamber (33);
A semiconductor layer (34) having a predetermined film thickness for forming the diaphragm (35) is formed on the first substrate (40) via an insulating film (41), and in the insulating film (41) or insulated. A bonding step (P3) for bonding the insulating film separation substrate (36) in which the ion implantation layer (42) for peeling is formed deeper than the film (41) and the second substrate (30);
The insulating film separation substrate (36) that has been bonded is peeled off at the ion implantation layer (42) portion so that the insulating film separation substrate (36) is thinned and the first substrate (40) or the insulation is formed on the surface. After exposing the film (41), a semiconductor layer (34) is formed on the surface of the second substrate (30) by removing the first substrate (40) and the insulating film (41), and A method of manufacturing a semiconductor substrate for a pressure sensor, comprising forming a diaphragm (35) and a pressure reference chamber (33) . In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 30 ,
The insulating film separating the substrate (36),
An ion implantation layer forming step (V1) for forming an ion implantation layer (38) for separation at a predetermined depth from one surface side of the third substrate (37);
A step (V2) of bonding the third substrate (37) and a fourth substrate (40) separately prepared through an insulating film (41);
Peeling off the bonded third substrate (37) with the ion implantation layer (38) to form a semiconductor layer (34) on the fourth substrate (40) through an insulating film (41). Step (V3),
A smoothing step of smoothing the surface of the peeled semiconductor layer (34);
A method for manufacturing a semiconductor substrate for a pressure sensor, wherein In the manufacturing method of the semiconductor substrate for pressure sensors according to claim 30 or 31 ,
In the recess forming step (P2), the recess (32) is formed by etching the surface of the second substrate (30). In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 30 to 32,
In the bonding step (P3), the insulating film separation substrate (36) and the second substrate (30) are brought into close contact with each other in a reduced pressure atmosphere. In the manufacturing method of the semiconductor substrate for pressure sensors according to any one of claims 30 to 33,
A method of manufacturing a semiconductor substrate for a pressure sensor, wherein an insulating film separation substrate (44) is used as the second substrate.

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