JP4212404B2 - System clock control apparatus and system clock control method for stream receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a system clock control device that controls a system clock used when processing a stream signal, and more particularly to a system clock control device and control method used for decoding an MPEG2 stream signal.
[0002]
[Prior art]
In digital television broadcasting currently in operation, video and audio signals are compressed by MPEG (Moving Picture Experts Group) 2 system, multiplexed with metadata such as program information, and further packetized as TS (Transport Stream) signals. A transmission method is adopted.
[0003]
On the receiving side, an MPEG-TS signal is obtained from the received signal, video data and audio data constituting a desired program are extracted from the multiplexed stream, and these are decoded and converted into uncompressed digital video signals and audio signals. Further, after being converted into an analog signal, it is encoded into a standard television signal of, for example, NTSC (National Television System Committee) system, supplied to a monitor for viewing.
[0004]
Naturally, the video and audio of the program are closely related. For example, when a person speaks, it is unnatural if the movement of the mouth does not match the audio. For this reason, in order to synchronize video and audio, means for generating STC (System Time Clock) is provided on each of the transmitting side and the receiving side, and SCR (System Clock) is used as a time stamp for synchronizing both STCs. Reference) and PCR (Program Clock Reference) are defined and sent as metadata from the transmission side.
[0005]
On the receiving side, SCR and PCR are separated and extracted from the TS signal, and the extracted SCR and PCR are applied as a reference signal of a circuit that generates an STC in a PLL (Phase Locked Loop) format, and the 27 MHz STC synchronized with the transmitting side Get. In the MPEG2 system, two data streams, TS and PS (Program Stream), are defined. The TS is used in a transmission system in which a data error may occur during transmission such as broadcasting. PCR is applied as a time stamp for use. PS is used in transmission systems such as DVD (Digital Versatile Disk) that are less likely to cause errors, and SCR is applied as an STC synchronization time stamp.
[0006]
Further, in the MPEG2 system, in addition to the above PCR, time stamp information called DTS (Decoding Time Stamp) indicating decoding start time and PTS (Presentation Time Stamp) indicating display time are defined, and these are also used as meta information. Control is performed so that overflow or underflow does not occur in a buffer that is transmitted and used to temporarily store video data and audio data before being sent to the MPEG2 decoder.
[0007]
In an environment where the quality of a transmission system such as a broadcast or playback device is high and TS packets are not frequently lost, a PLL circuit that generates STC is, for example, an MPEG2 standard (ISO / IEC 13818-1: 1994 ( E) It is possible to apply the circuit described in Fig. D-2). The circuit is shown in FIG.
[0008]
That is, the clock reference generation circuit 200 includes a VCO (Voltage Controlled Oscillator) 201 and obtains a 27 MHz system clock as its output. The control loop of the VCO 201 includes a counter 202 that loads a PCR or SCR value, counts the output of the VCO 201 and outputs an STC, a subtractor 203 that compares the counter 202 output with the PCR or SCR, An LPF (Low Pass Filter) / gain controller 204 converts the output into a DC signal and supplies it to the VCO 201 as an oscillation control signal.
[0009]
When it is assumed that a receiver including such an STC generation circuit 200 is connected to a home network (particularly, a wireless local area network (LAN)) to receive content, although not as much as the Internet, There is a possibility that transmission of SCR or PCR will be delayed due to loss of TS packet data or packet retransmission, and the buffer of the MPEG2-TS decoder will overflow or underflow, thereby impairing the MPEG2 decoding process. .
[0010]
As a measure for absorbing the time delay of TS packet data, it is conceivable to stabilize the buffer remaining amount of the MPEG2-TS decoder at a high value. However, the buffer capacity of the MPEG2-TS decoder is simply increased and stored in the buffer. If the amount of data is increased, there will be a problem that the decoding start time will be delayed, which is not a fundamental solution.
[0011]
In addition, when distribution by the network is considered, there is a possibility that a PCR packet satisfying the condition of STC frequency: 27 MHz ± 30 ppm which is the standard of the MPEG2 system cannot be transmitted on the transmission side. For example, when 2 hours of content of 24 bps (bits per second) is transmitted over a network such as the Internet, it is not possible to transmit a PCR with an accuracy capable of keeping the STC within 27 MHz ± 30 ppm. Suppose.
[0012]
Assuming that the accuracy of PCR is 27 MHz ± 300 ppm, the jitter of PCR, which is the reference signal of PLL, appears as STC jitter as it is, so audio and video are affected during the decoding process of MPEG2, A direct phenomenon such as a change in the pitch of the sound or an unnatural movement of the video will appear.
[0013]
In streaming performed on a PC (Personal Computer), data is transferred using RTP (Real-time Transport Protocol), and the time on the transmitting side and the receiving side is set using SNTP (Simple Network Time Protocol). Synchronizing is done. However, when time transfer is performed using SNTP on the Internet, the time accuracy (error) between the server and the client is about 500 μsec in the LAN, and about 20 msec via the WAN (Wide Area Network). It is possible that the accuracy deteriorates and the accuracy further decreases due to network congestion.
[0014]
In order to cut off the influence of PCR, when a free-running clock that is not related to the transmission side is generated on the receiver side and used as an STC, the clock is not synchronized between the transmission side and the reception side. Buffering is required, and not only is the reproduction time delayed, but in the worst case, frames may be dropped in the decoded video signal, or sound may be cut off in the audio signal.
[0015]
Conventionally, in the MPEG2 system, various proposals for generating an STC on the receiving side have been made. For example, Patent Document 1 discloses that an STC is generated by adjusting the timing of a PCR packet when the bit rate of a stream is different. The invention that was made possible is described.
[0016]
Further, Patent Document 2 describes an invention in which the circuit scale is reduced by using the lower bits of PCR to reduce the number of arithmetic registers for generating STC.
In any document, as to how to obtain an STC that satisfies the MPEG2 standard and prevent the occurrence of buffer overflow and underflow when the quality of PCR deteriorates in the course of transmission. It is not described.
[Patent Document 1]
JP 2001-268518 A (pages 5-6, FIG. 1)
[Patent Document 2]
Japanese Patent Laid-Open No. 11-313050 (pages 6-7, FIG. 1)
[0017]
[Problems to be solved by the invention]
As described above, conventionally, when a transmission delay occurs in a TS packet in the process of transmitting an MPEG2 stream signal, a delay also occurs in PCR or SCR, the STC becomes out of synchronization with the transmission side, and the buffer overflows. Or there is a problem that the quality of the video signal and the audio signal is deteriorated because MPEG2 is not correctly decoded due to an underflow.
[0018]
The present invention has been made to cope with the above-described points. By including an effective data amount in an STD (System Tag Decoder) buffer as a loop control signal of a PLL circuit that generates an STC, the signal quality can be reduced. The present invention provides a system clock control apparatus and control method for a stream signal receiver capable of decoding video and audio signals that are not present.
[0019]
[Means for Solving the Problems]
  The system clock control device for a stream receiver according to the present invention comprises a receiving means for receiving a transport stream signal, and a buffer for temporarily storing the received transport stream signal and outputting the received transport stream signal to a decoder for decoding the transport stream signal. Means, numerical information generating means for generating numerical information related to the data amount of the transport stream signal in the buffer means, and an oscillator capable of controlling the oscillation frequency, and a system clock based on the oscillation output of the oscillator System clock generating means, and oscillator control means comprising a feedback loop for controlling the oscillation frequency of the oscillator based on numerical information generated by the numerical information generating means, and the receiving means includes the transport Time base included in the stream Means for extracting information, and the oscillator control means includes a counter that reads the time reference information, counts the output of the oscillator, and outputs a signal for sending the data stored in the buffer to a decoder. It is characterized by.
[0020]
  In addition, the system clock controller of the stream receiver of the present invention includes a receiving means for receiving an MPEG2 transport stream signal, and a decoder for temporarily storing the received transport stream signal and decoding the transport stream signal. From the buffer means to output to the received transport stream signal, the PCR ( Program Clock Reference ) Or SCR ( System Clock Reference ) And DTS ( Decoding Time Stamp ), An oscillation frequency that can be controlled, an oscillator that outputs a system clock for processing the transport stream signal based on the oscillation output, and the PCR or SCR are read at a predetermined period, A counter for counting the oscillation output of the oscillator; decode timing control means for controlling the decode timing by the decoder based on the output of the counter and the DTS; and a transformer stored in the buffer based on the output of the counter Buffer control means for sending a port stream signal to the decoder, numerical information generating means for generating numerical information related to the data amount of the transport stream signal in the buffer means, and the oscillation frequency of the oscillator as the numerical information generating means Information generated in And control means for controlling on the basis, characterized by comprising a.
[0021]
  In addition, the system clock controller of the stream receiver of the present invention includes a receiving means for receiving an MPEG2 transport stream signal, and a decoder for temporarily storing the received transport stream signal and decoding the transport stream signal. From the buffer means to output to the received transport stream signal, the PCR ( Program Clock Reference ) Or SCR ( System Clock Reference ), An oscillation frequency that can be controlled, an oscillator that outputs a system clock for processing the transport stream signal based on the oscillation output, and the PCR or SCR are read at a predetermined period, A counter for counting the oscillation output of the oscillator, and a counter for controlling the oscillator based on the difference between the counter output and the PCR or SCR. 1 Generating the control signal 1 The control signal generating means reads out the transport stream signal stored in the buffer based on the output of the counter, and generates numerical information related to the data amount of the transport stream signal in the buffer means. Second control signal generating means for generating a second control signal for controlling the oscillator based on the numerical information, and the oscillation frequency of the oscillator is controlled by the first control signal and the second control signal. And a control means.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the system clock controller of the stream signal receiver of the present invention will be described in detail. First, the STD (System Target Decoder) portion of the receiver to which the present invention is applied will be described with reference to FIGS. .
FIG. 1 is a circuit block diagram showing an example of an STD of a stream signal receiver. The receiver 100 functions as a TS stream signal receiver, and a digital broadcast signal is input to an input terminal 101 from an antenna (not shown), for example. Or a digital CATV signal is supplied. The digital broadcast signal supplied to the terminal 101 is supplied to the tuner / demodulator 102, where the broadcast signal such as channel selection, demodulation, error correction, etc. is MPEG2-TS signal (hereinafter also referred to simply as TS signal). Processing to convert to is performed.
[0024]
The TS signal from the tuner / demodulator 102 is supplied to the TS demultiplexer / decoder 103, where the video and audio data constituting the program are separated, the video data is supplied to the STD 104, and the audio data is supplied to the STD 105. To be supplied.
Further, the TS demultiplexer / decoder 103 separates the PCR from the TS signal and supplies it to the clock control unit 106. The clock control unit 106 controls the frequency and phase by the input PCR, generates a system clock synchronized with the STC on the transmission side, and supplies the system clock to the video MPEG decoder 107 and the audio MPEG decoder 108.
[0025]
The video MPEG decoder 107 and the audio MPEG decoder 108 perform MPEG2 decoding based on the supplied system clock, output the decoded video data via the frame buffer 109, and output the decoded audio data. Output via the delay buffer 110.
[0026]
FIG. 2 is a circuit block diagram showing another example of the stream signal receiver. The receiver 120 functions as a PS stream signal receiver, and is reproduced from an input terminal 121, for example, from a DVD player (not shown). A signal is supplied. The digital television signal supplied to the input terminal 121 is supplied to the demodulator 122, where the reproduction signal such as demodulation and error correction is converted into an MPEG2-PS signal (hereinafter also referred to simply as a PS signal). The processing for is performed.
[0027]
The PS signal from the demodulator 122 is supplied to the PS decoder 123, where the video and audio data constituting the program are separated, the video data is supplied to an STD (System Target Decoder) 124, and the audio data is supplied to the STD 125. To be supplied.
[0028]
Further, the PS decoder 123 separates the SCR from the PS signal and supplies it to the clock control unit 126. The clock control unit 126 controls the frequency and phase according to the input SCR, generates a system clock synchronized with the STC on the transmission side, and supplies the system clock to the video MPEG decoder 127 and the audio MPEG decoder 128.
[0029]
The video MPEG decoder 127 and the audio MPEG decoder 128 each perform MPEG decoding based on the supplied system clock, output the decoded video data via the frame buffer 129, and output the decoded audio data Output via the delay buffer 130.
[0030]
FIG. 3 is a block diagram showing an embodiment of the system clock controller according to the present invention. In the system clock control device 140 of FIG. 3, based on the technique of performing PLL control of the VCO using PCR as a reference signal, it is further accumulated in a buffer as a temporary storage means provided in the MPEG2 decoder. An effective data amount is detected, and a control signal for controlling the oscillation frequency of the VCO is obtained based on a value obtained by adding the output of a function generator that generates a unique numerical pattern to the data amount.
[0031]
As buffers in the MPEG2 decoder, STD buffers 104 and 124 for temporarily storing video data before decoding are applied as shown in FIGS. The decoder classified as MP @ HL (Main Profile at High Level) in the MPEG2 standard (ISO / IEC 13818-2: 1995 (E) Table 8-14) has VBV (Video Buffering) for video. It is described that a size of 9,781,248 [bit] is required as a Verifier) buffer. It can be assumed that the VBV buffer and the STD buffer for video referred to in the standard are substantially equivalent.
[0032]
The system clock controller 140 in FIG. 3 has a VCO 141 that derives the oscillation output as a system clock. Further, a PCR value is loaded, and a counter 142 that counts the system clock and outputs the STC is provided. The output STC is supplied to the decode timing control unit 143, and the DTS (Decode Time Stamp) timing is set to the STC. Synchronize. As a result, the decode timing is controlled to be synchronized with the STC.
[0033]
In addition, the STD buffer control unit 144 that controls the accumulation and reading of data in the STD buffer is controlled by the output of the decode timing control unit 143 in order to read out the data stored in the STD buffer and lead it to the decoder in accordance with the decode start timing. To do.
[0034]
The STD buffer control unit 144 controls the STD buffer, obtains an effective data amount (buffer remaining amount) accumulated in the STD buffer, and outputs this to the function generation unit 145.
The function generator 145 generates a fixed pattern function corresponding to the remaining buffer capacity output from the STD buffer controller 144, adds this to the remaining buffer capacity, and outputs the result to the LPF / gain controller 146. The LPF / gain controller 146 converts the output of the function generator 145 into a DC voltage for controlling the oscillation frequency of the VCO 141.
[0035]
As shown in FIG. 4, the function generator 145 sets a lower limit threshold L and an upper limit threshold U for the buffer amount of the MPEG2 decoder. If the buffer amount is equal to or less than the lower limit L, the function generation unit 145 sets a negative value. If the value is greater than or equal to the upper limit value U, positive values are generated as fixed patterns.
[0036]
In the process of decoding the MPEG2-TS signal, TS bit stream data is input to the STD buffer at a constant bit rate, and the bit stream data is extracted from the buffer by the DTS synchronized with the STC. Here, since the DTS is described as the count value of the STC counter, the time for decoding actually changes when the system clock frequency of the receiver is changed.
[0037]
On the other hand, since the data to be transmitted is sent according to the system clock on the transmission side, if there is no problem in the transmission path, the bit stream data is input to the receiver at a constant bit rate. When the system clock of the transmitter is constant, the data amount of the STD buffer tends to increase when the system clock frequency of the receiver is lowered, and the data amount of the STD buffer tends to decrease when the system clock frequency of the receiver is raised. It can be easily understood.
[0038]
As described above, the data amount of the STD buffer and the system clock frequency are related to each other, and the information on the data amount of the STD buffer is applied as a control element of the PLL, thereby controlling the frequency of the system clock and the STD buffer. Can prevent overflow or underflow.
[0039]
It should be noted that the system clock feedback control is performed using the data amount of the STD buffer. In the MPEG2 system, it is defined that there are three types of pictures in video bitstream data, which are called I picture, P picture, and B picture, respectively. An I picture that is compressed and encoded only with information in a frame generally has the largest code amount, a P picture that is compressed using a past frame, and a compression using a past and future bidirectional frame. The code amount decreases in the order of B pictures to be performed.
[0040]
Since the video bit stream data is extracted from the STD buffer in units of pictures, the STD buffer amount varies greatly locally. Even for picture types and the same type of picture, the data amount for each picture varies depending on the content of the video. Therefore, in order to use the data capacity of the STD buffer for feedback of the system clock, it is important to eliminate the influence of the instantaneous buffer amount fluctuation, and the fluctuation of the STD buffer amount is averaged under a large time constant. It is necessary to use it for the control of the system clock after taking such measures. Therefore, it is only necessary to perform control such that feedback is performed in units of a certain amount of time. For example, feedback control may be performed on the system clock for an average STD buffer amount for 5 seconds, or feedback control may be performed in units of minutes.
[0041]
FIG. 5 shows the time change of the remaining data amount of the STD buffer when controlled by the system clock controller shown in FIG. 3 and the time change of the remaining data amount of the STD buffer when controlled by the conventional circuit shown in FIG. Show.
In FIG. 5, the vertical axis represents the STD buffer amount [k bit], and the horizontal axis represents time [sec]. It is Xa of the conventional circuit that the STD buffer amount is fixed at 3,000 [k bit] and does not change. Also, what changes from 3,000 [k bit] to over 8,000 [k bit] by 7,000 seconds from the start is due to the system clock control in the apparatus shown in FIG. This is the remaining amount change Ya of the STD buffer. In FIG. 5, it can be read that the STD buffer amount in the conventional circuit is substantially constant and does not change. However, in actuality, in an extremely short time of about 0.1 second from the start, it is zero to 3,000 [k]. bit].
[0042]
In the apparatus of the present invention whose characteristics are displayed in FIG. 5, 30 fields are set as 1 GOP (Group of Pictures) in an MP @ HL image at a transmission rate of 24 Mbps, and decoding is started 8 fields after data reception. . In addition, since the conventional circuit is a model that consumes 0.5 seconds of data at 1 GOP, the STD buffer capacity fluctuates within 1 GOP, but a model that can be regarded as a fixed value having a width when viewed macroscopically. It is said.
[0043]
Further, the change in the STD buffer remaining amount by the apparatus of the present invention shown in FIG. 5 is due to the result of performing the system clock control by applying the function on the step as shown in FIG. In FIG. 6, the vertical axis represents VCO oscillation frequency [MHz] of 27 [MHz] of the standard of 1.0000, and centered on it, taking 0.99990 to 1.00010 with respect to 1.0000, 0.00002, 0.00005 and 0.00010 in the ± direction respectively. In the horizontal axis direction, the data capacity of the STD buffer is 0.4, 0.6, 0.8, 1.1, 1.2, 1.3 as a variable from the reference value of 9,781,248 [bit].
[0044]
As a result, as shown in FIG. 5, it can be understood that when the STD buffer amount is viewed macroscopically, the STD buffer amount gradually increases, but control is possible with a high buffer amount.
In the system clock controller of the present invention shown in FIG. 3, immediately after the start of transmission, the system clock frequency is lowered to delay the decoding start time and gradually increase the amount of data in the buffer. When data in the buffer accumulates to some extent, normal control (feedback based on the buffer amount is set to 0) is performed.
[0045]
At this time, as in the example of function generation shown in FIG. 4, when the data amount of the decoder buffer further increases and exceeds a preset threshold value, control is performed to decrease the system clock frequency. You may do it. 4 shows the function as an example of a linear pattern. However, the function may be a pattern that changes stepwise as shown in FIG. 6 or a curve pattern that monotonously increases, or FIG. As shown, the pattern may have a history characteristic with respect to the change direction. In FIG. 7, L1 and L2 are lower thresholds, and U1 and U2 are upper thresholds.
[0046]
FIG. 8 shows another embodiment of the system clock controller of the present invention. The embodiment of FIG. 8 has a configuration in which the conventional circuit shown in FIG. 13 is added to the embodiment of the present invention shown in FIG.
That is, the system clock controller 150 includes a VCO 151 that outputs a system clock, a counter 152 that loads a PCR, counts the output of the VCO 151, and outputs an STC, and a decode timing control unit 153 that adjusts the decode timing from the STC and the DTS. The STD buffer control unit 154 that controls the reading of data stored in the STD buffer by the output of the decode timing control unit 153 and adjusts the remaining amount of data, and the STD buffer data provided from the STD buffer control unit 154 A function generator 155 that generates a function corresponding to the remaining amount is included, and the configuration thereof is the same as the block of FIG.
[0047]
Further, the system clock controller 150 includes a subtractor 156 that subtracts the PCR and STC to obtain the phase difference between them, an adder 157 that adds the output of the function generator 155 to the output of the subtractor 156, an adder Is provided with an LPF / gain controller 158 that obtains a control signal for controlling the VCO 151 by converting the output of the signal into a DC signal. The VCO 151, the counter 152, the subtractor 156, and the LPF / gain controller 158 have the same configuration as that of the conventional circuit shown in FIG.
[0048]
Based on the effective data amount (buffer remaining amount) accumulated in the buffer which is a temporary storage device in the MPEG2 decoder, the function generator 155 generates a function of a specific numerical pattern shown in FIG. Since the PLL feedback control signal is obtained by adding to the output of the subtractor 156 for obtaining the phase difference between the STC and the PCR, it is possible to start decoding without delaying the decoding start time of the stream so much. .
[0049]
FIG. 9 shows the time change of the effective data amount in the buffer of the MPEG2 decoder in the apparatus shown in FIG. Here again, an STD buffer for temporarily storing data before decoding is used as an MPEG2 decoder buffer. In FIG. 9, the data received by the apparatus of FIG. 8 is HD (High Definition) image data at a constant rate of 24 Mbps, and the data reception amount is equal to the data transmission amount from the MPEG2 decoder in units of 1 GOP. Is assumed.
[0050]
In FIG. 9, 30 fields are set to 1 GOP, and the decoding is started 8 fields after data reception. In FIG. 9, the broken line Xb shows the time change of the effective data amount in the buffer in the conventional circuit, and the solid line Yb shows the time change of the effective data amount in the buffer in the apparatus of the present invention shown in FIG.
[0051]
FIG. 9 shows the result of a model in which the system clock period is increased by about 20% (frequency is reduced to about 5/6) in order to make the effect easy to understand. Therefore, it is appropriate to narrow down the adjustment range of the system clock frequency. In the conventional apparatus, the STD buffer amount varies within one GOP, but the buffer amount is controlled with a certain inherent width as a whole. When the system clock control of the present invention is performed, since the buffer amount control on the receiver side is added as compared with the conventional circuit, the STD buffer amount gradually increases gradually when viewed macroscopically. Thus, the control can be performed with a high buffer amount.
[0052]
Immediately after the start of transmission, the system clock frequency is lowered to delay the decoding start time and gradually increase the amount of data in the buffer. When data in the buffer accumulates to some extent, normal control (feedback based on the buffer amount is set to 0) is performed.
[0053]
As in the example of the function generator having the characteristics shown in FIG. 4, when the data amount of the decoder buffer further increases and exceeds a preset threshold value, control is performed in the direction of decreasing the system clock frequency. You may make it perform.
The function generator 155 in the apparatus shown in FIG. 8 has a linear characteristic as shown in FIG. 4 in the characteristics of the generated function, but is not limited to this, as shown in FIG. A pattern that changes stepwise, a curve pattern that monotonously increases, or a history characteristic with respect to the changing direction as shown in FIG. 7 may be provided.
[0054]
In FIG. 8, it is also possible to select and add only one of the conventional control based on the feedback control of PCR or the feedback control based on the buffer capacity of the MPEG2 decoder. For example, when the transmission quality on the network is poor and the PCR packet data does not satisfy the MPEG2 standard 27 MHz ± 30 ppm and is greatly shifted, the system clock control can be performed using only the feedback control based on the buffer amount of the MPEG2 decoder. It is.
[0055]
Next, still another embodiment of the apparatus of the present invention will be described. In the embodiment of FIG. 10, the receiver 160 has a function generator 165 that generates a function of a fixed pattern corresponding to the remaining data amount of the STD buffer, as compared with the conventional apparatus. An STD timing detection circuit 167 for detecting the STD timing, a gate 166 controlled by the STD timing detection circuit 167, and an adder 164 for adding the output of the gate 166 to the output of the subtractor are added.
[0056]
That is, the VCO 161 that generates the system clock, the PCR loaded with the PCR, the counter 162 that counts the system clock and outputs the STC, the output of the counter 162 is compared with the PCR, the phase difference information is obtained, and the adder 169 A subtractor 163 to be derived and an LPF / gain control unit 168 that obtains the output of the adder 164 as a DC control signal are provided.
[0057]
In the apparatus shown in FIG. 10, when the first STD is detected, the gate 166 is opened, and a function based on the amount of data in the buffer generated by the function generator 165 is added to the adder 164. Operates to add to output.
As a result, the same system clock control as that of the conventional device is performed until the STD is detected and decoding is started, and after the decoding is started, the system clock frequency is controlled based on the amount of data in the buffer. It is. In this apparatus, since the frequency of the system clock is controlled in exactly the same way as in the conventional circuit from the start of TS signal transmission to the first decoding, the decoding start time can be made exactly the same as in the conventional circuit.
[0058]
FIG. 11 shows the time change of the effective data amount in the buffer of the MPEG2 decoder in the apparatus shown in FIG. As shown in FIG. 11, it is clearly shown that a normal control period that is not based on the feedback of the STD buffer amount is set in the initial stage. In FIG. 11, the broken line Xc shows the time change of the effective data amount in the buffer in the conventional circuit, and the solid line Yc shows the time change of the effective data amount in the buffer in the apparatus of the present invention shown in FIG.
[0059]
FIG. 12 is a flowchart for explaining the operation of the apparatus of the present invention shown in FIG. In FIG. 12, the process starts in step S201. In step S202, it is determined whether or not the MPEG decoding process is to be performed. In the case of the MPEG decoding process, the process proceeds to step S203, and the bit stream data is input to the STD buffer.
[0060]
Next, in step S204, it is determined whether or not the input bit stream data is the first TS packet including the PCR value. In the case of the first TS packet including the PCR value, in step S206, the PCR value is loaded into the counter (STC counter) that measures the output of the VCO incorporated in the PLL, and in step S207, the output of the VCO is output by the STC counter. Measure and add to STC counter.
[0061]
If the input bit stream data is not the first TS packet including the PCR value, it is determined whether or not a flag indicating that the PCR is discontinuous is set in step S205. Proceeding to S206, if the flag is set, step S206 is skipped and the process proceeds to step S207.
[0062]
Next, in step S208, it is determined that the value of the STC counter is equal to or greater than the DTS, that is, it is determined that the decoding start timing has been reached. Thus, the bit stream data stored in the STD buffer is read and sent to the subsequent MPEG2 decoder (video decoder and audio decoder). If the value of the STC counter is smaller than the DTS, the process returns to step S203.
[0063]
Next, in step S210, the effective data amount of the STD buffer is obtained, and in step S211, a PLL feedback control signal is obtained based on the obtained effective data amount to control the oscillation frequency of the VCO. Next, in step S212, it is determined whether or not the MPEG decoding process is completed. When it is determined that the MPEG decoding process is not completed, the process returns to step S203. If it is determined in step S202 that it is not an MPEG decoding process, or if it is determined in step S211 that the MPEG decoding process has ended, the process ends in step S213.
[0064]
As described above, according to the present invention, the VCO that is incorporated in the PLL circuit that generates the MPEG2 system clock and outputs the system clock as the oscillation output is incorporated in the MPEG2 decoding processing unit, and the bitstream data is decoded. By detecting the effective data amount (buffer remaining amount) of the buffer temporarily temporarily stored and obtaining the PLL feedback control signal based on the detected effective data amount (buffer remaining amount), the PCR packet is used as a reference for the PLL for generating the system clock. Even when it is difficult to apply, it is possible to accurately control the PLL and obtain a system clock that can decode the bitstream without any problem. In addition, it is possible to prevent overflow and underflow from occurring in the buffer in the decoder.
[0065]
【The invention's effect】
As described above, according to the present invention, even if it is difficult to apply a PCR packet as a reference for a PLL for generating a system clock, the system is based on the effective data amount of a buffer existing in the decoding unit. Since the clock is generated, it is possible to obtain a system clock that can decode the bitstream without any problem.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a main part of an embodiment of a stream receiver in which a system clock controller of the present invention is incorporated.
FIG. 2 is a circuit block diagram showing a main part of another embodiment of a stream receiver in which the system clock controller of the present invention is incorporated.
FIG. 3 is a circuit block diagram showing an embodiment of a system clock control device according to the present invention.
4 is a characteristic diagram for explaining the operation of the main part of the apparatus shown in FIG. 3;
FIG. 5 is a characteristic diagram for explaining the operation of the apparatus shown in FIG. 3;
6 is a characteristic diagram for explaining the operation of the apparatus shown in FIG. 3. FIG.
7 is a characteristic diagram for explaining the operation of the main part of the apparatus shown in FIG. 3. FIG.
FIG. 8 is a circuit block diagram showing another embodiment of the system clock controller according to the present invention.
FIG. 9 is a characteristic diagram for explaining the operation of the apparatus shown in FIG. 8;
FIG. 10 is a circuit block diagram showing still another embodiment of the system clock controller according to the present invention.
11 is a characteristic diagram for explaining the operation of the apparatus shown in FIG.
FIG. 12 is a flowchart for explaining the operation of the apparatus according to the present invention.
FIG. 13 is a circuit block diagram showing a conventional system clock generation circuit.
[Explanation of symbols]
141, 151, 161 ... VCO
142, 152, 162 ... counter
143, 153 ... Decoding timing control unit
144, 154 ... STD buffer control unit
145, 155, 166 ... function generator
146, 158, 165 ... LPF / gain controller
156, 163 ... subtractor
164 ... Adder
167 ... First DTS timing detector
168 ... Gate

Claims (8)

Receiving means for receiving a transport stream signal;
Buffer means for temporarily storing the received transport stream signal and outputting it to a decoder for decoding the transport stream signal;
Numerical information generating means for generating numerical information related to the data amount of the transport stream signal in the buffer means;
A system clock generating means comprising an oscillator capable of controlling the oscillation frequency, and obtaining a system clock based on the oscillation output of the oscillator;
Oscillator control means comprising a feedback loop for controlling the oscillation frequency of the oscillator based on numerical information generated by the numerical information generating means,
The receiving means comprises means for extracting time reference information contained in the transport stream;
Said oscillator control means, said counting the output of said oscillator with time reads the reference information, wherein the to Luz stream received that the data stored in the buffer is intended to include a counter for outputting a signal for feeding to the decoder System clock controller. The transport stream signal is an MPEG2 transport stream signal, the time reference information is PCR (Program Clock Reference) or SCR (System Clock Reference), and the counter output is STC (System Time Clock). The system clock control device for a stream receiver according to claim 1 . Receiving means for receiving an MPEG2 transport stream signal;
And temporarily stores the transport stream signal received before reporting, and buffer means for outputting to a decoder for decoding the trans boat stream signal,
From the transport stream signal received before reporting, and PCR (Program Clock Reference) or SCR (System Clock Reference), means for extracting a DTS (Decoding Time Stamp),
Can be controlled is oscillation frequency, an oscillator for outputting a system clock for processing the transport stream signal based on the oscillation output,
With pre-Symbol PCR or SCR is loaded at a predetermined period, a counter for counting the oscillation output of the oscillator,
A decoding timing control means for controlling the decoding timing of the decoder on the basis of the output of this counter DTS,
Based on the output of the previous SL counter, a buffer control means for feeding a transport stream signal stored in the buffer to the decoder,
And numerical information generating means for generating a numerical value information relating to the data amount of the transport stream signal in the previous SL buffer means,
Control means for controlling on the basis of numerical information generated oscillation frequency before Symbol oscillator by the numerical information generating means,
A system clock control apparatus for a stream receiver, comprising: Receiving means for receiving an MPEG2 transport stream signal;
And temporarily stores the transport stream signal received before reporting, and buffer means for outputting to a decoder for decoding the trans boat stream signal,
From the transport stream signal received before reporting, means for extracting a PCR (Program Clock Reference) or SCR (System Clock Reference),
Can be controlled is oscillation frequency, an oscillator for outputting a system clock for processing the transport stream signal based on the oscillation output,
With pre-Symbol PCR or SCR is loaded at a predetermined period, a counter for counting the oscillation output of the oscillator, the output of this counter the PCR or, compared with SCR, for controlling said oscillator on the basis of the difference First control signal generating means for generating a first control signal;
It reads the transport stream signal stored in the buffer based on the output of the previous SL counter, generates a numerical information associated with the data amount of the transport stream signal in the buffer means, on the basis of this numerical information Second control signal generating means for generating a second control signal for controlling the oscillator;
And control means for controlling the oscillation frequency of the oscillator by the previous SL first control signal and a second control signal,
A system clock control apparatus for a stream receiver, comprising: 5. The stream receiver system according to claim 4 , wherein the system clock control means selectively switches between the first control signal and the second control signal to control the oscillator. Clock control device. 5. The stream receiver according to claim 4 , wherein the system clock control means controls the oscillator only with the first control signal for a predetermined period from the start of decoding of the transport stream signal. System clock controller. The numerical information generating means, any one of claims 1乃optimum 6, characterized in that a function generator for generating a function of fixed pattern associated with the data amount of the transport stream signal in the buffer means A system clock controller for a stream receiver as described in 1. 8. The receiver according to claim 1, further comprising a tuner for selecting a desired program from a digital broadcast signal or a digital CATV signal in order to receive the transport stream signal. A system clock controller for a stream receiver as described in 1 .

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