JP4211385B2 - Semiconductor memory card and management information updating method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory card for storing address management information for a rewritable nonvolatile memory in the nonvolatile memory, and reading and using a necessary part of the address management information in the volatile memory, and the management Information update method.
[0002]
[Prior art]
In a memory card having a rewritable nonvolatile memory, data is written and read by converting a logical address given to access the nonvolatile memory into a physical address. And it has address management information for this address conversion.
[0003]
As described above, a memory card that stores address management information in a non-volatile memory and reads and uses only a necessary portion of the address management information in a volatile memory is disclosed in, for example, Patent Document 1 It has been known.
[0004]
FIG. 4 shows an address map in a nonvolatile memory in a conventional memory card. Nonvolatile memory is generally equivalent to what is called flash memory, and its basic characteristics (such as inability to overwrite or limited number of writes) follow that of typical flash memory. Description of these characteristics is omitted.
[0005]
The nonvolatile memory includes a management area 101 and a data area 102. The data area 102 is an area for storing data (so-called content information such as music data and image data) read / written from / to an external device (host), for example, four areas (data area # 0 to data 1024 for each 1024 blocks). Divided into region # 3). The management area 101 is an area for storing management information such as an address conversion table for determining a physical address corresponding to a logical address of data, and includes an address conversion table (hereinafter referred to as LTPb) 104 and an index of the address conversion table (hereinafter referred to as LTPa). 103). The LTPb 104 includes # 0 to # 3 of the LTPb 104 in order to manage # 0 to # 3 of the data area 102, respectively. The number of entries managed by the LTPb 104 # 0 to LTPb 104 # 3 is equal to the number of blocks. In each data area 102, a logical address (0 to 1023 [block × block size]) is basically assigned to a physical address (0 to 1023). [Block × block size]), each logical block number (corresponding to each word) corresponding to each logical address has a physical block number (corresponding to a physical address) and an allocation flag. The allocation flag is a flag for identifying whether or not data valid for the stored physical block number (physical address) has already been allocated (allocated). The LTPa 103 has a physical block number (corresponding to a physical address) in which LTPb 104 # 0 to LTPb 104 # 3 are stored and an allocation flag. The LTPa 103 and LTPb 104 # 0 to LTPb 104 # 3 exist in an arbitrary block which is an erasure unit. For example, if the inside of the block is from page 1 to page N, one address conversion table using page 1 (for example, 2K bytes). Configure. For example, LTPa 103 is associated with page 1 of the first block of management area 101, LTPb 104 # 0 is associated with page 1 of the next block, and pages other than page 1 of each block may be unused.
[0006]
The write operation of the memory card configured as described above will be described below. In accordance with a logical address given from an external device (host), a data write destination area is determined. For example, when the logical address 0 is designated from the external host, the LTPb 104 # 0 corresponding to the data area 102 # 0 in the nonvolatile memory is read from the nonvolatile memory to the volatile memory based on the LTPa 103. The allocation flag in one word corresponding to the logical block number in the read LTPb 104 # 0 is checked, and if not allocated, the physical block in the data area 102 # 0 corresponding to the physical block number in this one word After erasing (erasing) the data, data is written, the allocation flag in this one word is updated to the allocated state (value 0) in the volatile memory, and then LTPb104 # 0 is written back to the nonvolatile memory. On the other hand, the allocation flag in one word corresponding to the logical block number is checked. If the allocation flag has already been allocated, the physical block numbers corresponding to all areas of the logical block numbers 0 to 1023 are checked, and the physical block numbers that have not been allocated. (For example, 10) is searched for, and data is written to the physical block of the data area 102 # 0 corresponding to the physical block number 10 after the erase process. Also, in the volatile memory, the physical block number 10 is written in the physical block number portion of one word of the logical block number 0, and the physical block in one word of the logical block number in which the physical block number 10 was previously recorded The number part is changed to the physical block number value previously stored in the physical block number part of logical block number 0, and the allocation flag is set to an unallocated state (value 1). Then, LTPb104 # 1 is written back to the nonvolatile memory.
[0007]
[Patent Document 1]
JP 2001-142774 A (paragraphs 0010 to 0012, FIG. 1)
[0008]
[Problems to be solved by the invention]
However, in a memory card equipped with a nonvolatile memory having the above-described conventional configuration, since management of data is performed by providing a management area in the nonvolatile memory, it is required to ensure the reliability of management information. . Therefore, when updating the management information to the non-volatile memory, if a power failure occurs when a write error occurs, the management information may not be updated normally and the reliability of the management information may be impaired. .
[0009]
The present invention solves the above-mentioned conventional problems, and provides a semiconductor memory card and a management information update method that can improve the reliability of management information, in particular, to ensure the reliability of management information. Objective.
[0010]
[Means for Solving the Problems]
In order to achieve this object, a semiconductor memory card and a management information update method according to the present invention have a plurality of address management tables (hereinafter referred to as AT) for converting a logical address given to access a nonvolatile memory into a physical address. ) And address conversion table index information (hereinafter referred to as ATI) group for managing a plurality of ATs (hereinafter referred to as AT groups) are held in a nonvolatile memory, and necessary address management information is appropriately expanded in a volatile memory. This is characterized in that the next AT is written in a write area different from the current AT when the AT is updated when data is updated.
[0011]
As a result, even if an area (for example, a block) in which the next AT is written in the nonvolatile memory becomes defective (bad block) due to the writing of the next AT, the AT information before the update is stored in another area (in the nonvolatile memory). For example, the data in the non-volatile memory can be protected based on the previous AT even if the AT could not be updated normally due to a power shutdown or the like when updating the AT. It is.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
The invention according to claim 1 of the present invention includes a plurality of address management tables which have a nonvolatile memory and convert a logical address given to access the nonvolatile memory into a physical address and the plurality of address management. In a memory card configured to hold an address conversion table index information group for managing a table in the non-volatile memory and appropriately develop necessary address management information in a volatile memory, when updating the address management table generated at the time of data update The semiconductor memory card is characterized in that the next address management table is written in a writing area different from the current address management table. Even if the previous address management table cannot be updated, An effect that it is possible to protect data in the non-volatile memory based on the Le.
[0013]
The invention according to claim 2 of the present invention is the case where the current address management table is the final address management table of the address management table group managed by the current address conversion table index information group in addition to the invention according to claim 1. When the data update occurs, the next address conversion table index information managed by the next address conversion table index information is updated, and then the next address conversion table index information to be updated is written in a writing area different from the current address conversion table index information. As a result, even if the address translation table index information cannot be updated normally due to a power shutdown or the like before the address translation table index information is updated, the final address managed by the previous address translation table index information Management table Based has an effect that it is possible to protect the data in the nonvolatile memory.
[0014]
The invention according to claim 3 of the present invention, in addition to the invention according to claim 1 or 2, manages an address space in which the address management table and the address conversion table index information span a plurality of nonvolatile memories. In this case, when the address management table is updated, the next address management table is written in a writing area of a nonvolatile memory different from the nonvolatile memory in which the current address management table is written. Thus, there is an action of distributing writing to the same nonvolatile memory for updating the address management table.
[0015]
The invention according to claim 4 of the present invention, in addition to the invention according to claim 1 or 2, manages an address space in which the address management table and the address conversion table index information span a plurality of nonvolatile memories. In the case of updating the address translation table index information, the next address translation table index information is written in a write area of a nonvolatile memory different from the nonvolatile memory in which the current address translation table index information is written. This has the effect of distributing writing to the same non-volatile memory for updating the address translation table index.
[0016]
In addition to the invention according to claim 1 or 2, the invention according to claim 5 of the present invention is an address management that is managed by the previous address conversion table index information when the next address conversion table information is updated to the nonvolatile memory. It is characterized by invalidating the block in which the table group is written. This makes it unnecessary to use the address management table that is no longer necessary as a normal data write area, and to use the block used for the address management table group. Has the effect of not concentrating.
[0017]
According to a sixth aspect of the present invention, there are provided a plurality of address management tables for converting a logical address given to access a nonvolatile memory into a physical address and an address conversion for managing the plurality of address management tables. In the management information update method in which the table index information group is held in the nonvolatile memory and necessary address management information is appropriately expanded in the volatile memory, the next address management table is updated when the address management table is updated when data is updated. This is a management information update method characterized by writing to a write area different from the current address management table. This makes it possible to update the address management table normally when the address management table is updated due to a power shutdown or the like. The data in the non-volatile memory is also based on the previous address management table. An effect that can be protected.
[0018]
According to a seventh aspect of the present invention, in addition to the sixth aspect of the present invention, the current address management table is a final address management table of an address management table group managed by the current address conversion table index information group. When the data update occurs, the next address conversion table index information managed by the next address conversion table index information is updated, and then the next address conversion table index information to be updated is written in a writing area different from the current address conversion table index information. As a result, even if the address translation table index information cannot be updated normally due to a power shutdown or the like before the address translation table index information is updated, the final address managed by the previous address translation table index information Management table Based has an effect that it is possible to protect the data in the nonvolatile memory.
[0019]
The invention according to claim 8 of the present invention, in addition to the invention according to claim 6 or 7, manages an address space in which the address management table and the address conversion table index information span a plurality of nonvolatile memories. In this case, when the address management table is updated, the next address management table is written in a writing area of a nonvolatile memory different from the nonvolatile memory in which the current address management table is written. Thus, there is an action of distributing writing to the same nonvolatile memory for updating the address management table.
[0020]
The invention according to claim 9 of the present invention, in addition to the invention according to claim 6 or 7, manages an address space in which the address management table and the address conversion table index information span a plurality of nonvolatile memories. In the case of updating the address translation table index information, the next address translation table index information is written in a write area of a nonvolatile memory different from the nonvolatile memory in which the current address translation table index information is written. This has the effect of distributing writing to the same non-volatile memory for updating the address translation table index.
[0021]
In addition to the invention according to claim 6 or 7, the invention according to claim 10 of the present invention is an address management that is managed by the previous address conversion table index information when the next address conversion table information is updated to the nonvolatile memory. It is characterized by invalidating the block in which the table group is written. This makes it unnecessary to use the address management table that is no longer necessary as a normal data write area, and to use the block used for the address management table group. Has the effect of not concentrating.
[0022]
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.
[0023]
(Embodiment 1)
FIG. 1 is a conceptual diagram showing a configuration of an address management table (AT) and address translation table index information (ATI) in the semiconductor memory card and the management information update method according to the first embodiment of the present invention. It is a conceptual diagram which shows the structure of the semiconductor memory card by embodiment, and the address map of the non-volatile memory in a semiconductor memory card. FIG. 3 is a flowchart showing the management information update method according to this embodiment.
[0024]
In FIG. 1, 1 is an ATI group. Reference numerals 2 and 3 denote AT groups. For convenience, they are referred to as AT group α2 and AT group β3, which are present in addition to those shown in the figure. Reference numeral 10 denotes a block (physical block). The ATI group 1, the AT group α2, the AT group β3,... According to this embodiment are each composed of four blocks 10, each of which has a 4-bank (Bank 0 to Bank 3) configuration. I have to.
[0025]
In FIG. 2, 20 is a non-volatile memory such as a flash memory, 21 is a host interface circuit (host I / F) for transmitting and receiving signals such as data and commands between the semiconductor memory card and the host device, 22 is a control unit that controls the operation of the nonvolatile memory 20 and the semiconductor memory card by a command from the host device, and 23 is a RAM (Random Access Memory) as a volatile memory that temporarily stores data, address management information, and the like. is there. Reference numeral 4 denotes an ATI group area for storing ATI groups, 5 denotes a data area for storing data, and the nonvolatile memory 20 includes an ATI group area 4 and a data area 5. Reference numeral 6 denotes an AT group, and reference numeral 7 denotes a data entry managed by the current AT.
[0026]
The nonvolatile memory 20 described in the present embodiment has a 4-bank configuration (Bank 0 to Bank 3), and each block is limited to a memory in which a page with a data capacity of 2 KB is configured with 2 pages.
[0027]
The ATI group area 4 is an area for storing an ATI group for managing the AT groups in the data area 5 (# 0 to # 3). ATI has a physical block number of each AT group (e.g., corresponding to the physical address of bank 0). If 64 AT groups are managed in each data area with one ATI, 1 word (physical block number) × 4 (number of data areas) × 64 (AT group) = 512B, and as shown in FIG. Eight ATI can be recorded. The head ATI is stored in, for example, the head physical block of the nonvolatile memory 20, and link information to one block per bank is written in the redundant area of the page in which the head ATI is stored, thereby forming an ATI group. Therefore, a maximum of 32 ATIs can be stored.
[0028]
The data area 5 is an area for storing data (so-called content information such as music data and image data) read / written from / from the outside (host) and an AT group. The data area 5 is divided into four areas (data area # 0 to data area # 3) every 1024 blocks / bank, and the AT group is stored in each data area in order to manage each data area. The The data entry 7 managed by the AT is managed with one block / bank and a total of four blocks as one entry. In the redundant area of the lower page of the first block (for example, bank 0) of each entry managed by the AT, link information to one block per bank is written. In each data area, basically, in order to convert a logical address (0 to 1023 [block x block size x number of banks]) into a physical address (0 to 1023 [block x block size x number of banks]) Each logical block number corresponding to a logical address (every word) has a physical block number (for example, corresponding to 9 bits of the physical address of bank 0) and an allocation flag (4 bits) of each bank. Therefore, the data capacity of one AT is 1 word (physical block number) × 1024 (block) = 2048 B, and one AT is stored in one page. The allocation flag is a flag for identifying whether valid data has already been allocated to the physical block number (physical address) of each bank, and is stored in the order of physical block numbers.
[0029]
Next, the write operation according to the present embodiment will be described with reference to FIGS. Note that AT group α2 and AT group β3 in FIG. 1 are AT groups that manage the same data area. In the example shown in FIG. 1, AT group α2 is managed by ATI # 4, and AT group β3 is ATI. This area is managed by # 5. In addition, the update order of AT and ATI is determined in advance so that the next AT and ATI are not written in the same block as the current AT and the current ATI. Further, the process of detecting the latest ATI from the ATI group (S01 in FIG. 3) is performed at the time of initialization, for example, and is not performed for each data write command from the outside (host) to the memory card. 3 is executed by the control unit 22 shown in FIG. 2, and the control unit 22 includes a CPU (Central Processing Unit).
[0030]
First, updating within an AT group managed by one ATI will be described. In accordance with a logical address given from the outside (host), a data write destination area is determined. For example, when the logical address 0 is designated from the external host, the physical block number of the AT group corresponding to the data area # 0 in the nonvolatile memory 20 is obtained from the current ATI, and the volatile memory (RAM 23) is obtained from the nonvolatile memory 20. (S02 in FIG. 3). Within the read current AT group, the current AT (for example, AT # 2) is detected, and the physical block number in one word corresponding to the logical block number is checked (S03). When detecting the current AT, since the AT group including the current AT is erased in advance, the AT group is read normally according to the predetermined AT writing order (# 0 to # 7) shown in FIG. The issued last written AT is set as the current AT. If the physical block number is not registered in one word corresponding to the logical block number, that is, if it is not allocated, the unallocated physical block number of each bank is detected, and the physical block of the corresponding data area # 0 is erased Then, the physical block number of each bank is added to the lower page redundant area of bank 0 and the data is written to the nonvolatile memory 20, and the data corresponds to the physical block number of each bank into which data is written in the volatile memory 23. The allocation flag is updated to the allocated state (value 0) (S04). Thereafter, AT # 3 is written in the nonvolatile memory in accordance with a predetermined writing order shown in FIG. 1 (S05, S07).
[0031]
On the other hand, if the physical block number in one word corresponding to the logical block number is checked and already allocated, the allocated physical block number of each bank from the lower page redundant area of the physical block corresponding to the physical block number. Is read. Furthermore, the physical block number of each bank that has not been allocated is detected in the volatile memory, the physical block of the corresponding data area # 0 in the nonvolatile memory is erased, and the redundant area of the lower page of the physical block in bank 0 is erased. Data is written by adding the physical block number of each bank. Also, in the volatile memory, the physical block number of bank 0 where data was written is written to the physical block number in one word of logical block number 0, and the allocation flag corresponding to the physical block number of each bank used this time has already been allocated The state is updated to the value (value 0), and the allocation flag corresponding to the physical block number of each bank used in the previous logical block number 0 is set to an unallocated state (value 1) (S04). Thereafter, AT # 3 is written in the nonvolatile memory in accordance with a predetermined writing order shown in FIG. 1 (S05, S07).
[0032]
Next, a case where an ATI update occurs will be described. In FIG. 1, if the current AT is the final AT # 7 of the AT group α2 managed by ATI # 4, it is determined in S05 that the current AT is the final AT managed by the current ATI, and the next AT is determined in S06. Reserve a free block to write a group. The unallocated physical block number is detected from the allocation flag of each bank from AT # 7 of AT group α2 which is the current AT in the volatile memory 23, and the physical block in the data area # 0 corresponding to the detected physical block number is detected. The area of the AT group β3 is secured by erasing. The next AT updates the allocation flag corresponding to the physical block number of each bank used to secure the area of the AT group α2 in the volatile memory 23 in addition to the information created in the data write process S04. Further, the allocation flag corresponding to the physical block number of each bank used for securing the area of the AT group β3 is updated to allocate. In S08, the next AT to be updated is written in the AT # 0 area of the AT group β3 in the data area # 0. After that, in S09, the physical block address of each AT of the AT group β3 is written in the area of ATI # 5.
[0033]
When the ATI group 1 is updated, it is necessary to secure a physical block for recording the next ATI group in addition to the process for updating the ATI. The unallocated physical block number is detected from the allocation flag of each bank of AT # 7 in the volatile memory 23, and the target physical block of each bank detected in the nonvolatile memory 20 is erased to thereby determine the area of the next ATI group. Secure. In addition to the next AT information at the time of updating the ATI, the allocation flag corresponding to the physical block number of each bank used to secure the area of the current ATI group in the volatile memory 23 is unallocated, and The allocation flag corresponding to the physical block number of each bank used for securing the area of the next ATI group 1 is updated to allocate. Thereafter, the next AT and the next ATI are written in the nonvolatile memory 20 in the same manner as the ATI update.
[0034]
As described above, when an AT is updated, even if an error occurs during writing of the next AT and the next AT cannot be updated normally by writing the next AT to a block different from the current AT, the memory based on the current AT is stored. Data recorded in the nonvolatile memory 20 in the card can be protected. Further, when an error occurs when updating an AT that requires ATI update, the data recorded in the nonvolatile memory 20 in the memory card can be protected by the current AT based on the current ATI. Furthermore, after the ATI update, the old AT group (for example, the AT group α2 after the ATI update) is used as an area where data can be written, so that the AT group can be prevented from being concentrated in the same area and the reliability of the AT group can be improved.
[0035]
In this embodiment, the case where the memory card is configured by one nonvolatile memory has been described. However, the allocation flag managed by the AT is set to 8 bits even when the memory card is configured by a plurality of nonvolatile memories. If two nonvolatile memories are configured to be managed by one AT, the same processing as in this embodiment is possible. Further, when the AT and ATI are updated, if the processing is performed so that the two nonvolatile memories are alternately written, it is possible to avoid the concentration of writing to the same nonvolatile memory for the AT and ATI update.
[0036]
In the present embodiment, a four-bank nonvolatile memory has been described. However, the same ATI update method can be applied regardless of the bank configuration.
[0037]
Further, in this embodiment, the address management of the memory card has been described as being realized in two layers of ATI and AT. However, when the ATI is further hierarchized, the same ATI update method can be applied. it can. In this case, the frequency of access to the most important ATI can be reduced by storing the ATI on the top floor in the management area and storing data in the other data areas.
[0038]
In the present embodiment, the memory card has been described as an example as shown in FIG. 2, but the present invention is not limited to the memory card. For example, the management information updating method ( A method of updating address management information) may be used. In this case, the host I / F 21 and the control unit 22 may be configured using resources in a device having the same function.
[0039]
【The invention's effect】
As described above, according to the present invention, even when an area (for example, a block) in which the next AT is written in the nonvolatile memory becomes defective (bad block) by writing the next AT, the AT information before update is stored in the nonvolatile memory. Since it can be reserved in another area (for example, block) in the volatile memory, even if the AT could not be updated normally due to a power interruption or the like during the AT update, It is possible to protect the data. Furthermore, even if the ATI cannot be updated normally due to power interruption or the like before the ATI update, the data in the nonvolatile memory can be protected based on the final AT managed by the previous ATI. Furthermore, by disabling the AT group that is no longer required every time the ATI is updated, the reliability of the AT group can be improved because the blocks used for the AT group are not concentrated in the normal data write area. .
[Brief description of the drawings]
FIG. 1 is a conceptual diagram showing an address management method according to an embodiment of the present invention;
FIG. 2 is a diagram showing a configuration and an address map of a memory card according to an embodiment of the present invention.
FIG. 3 is a flowchart for explaining the operation of the address management method according to the embodiment of the present invention;
FIG. 4 is a diagram showing an address map of a conventional memory card
[Explanation of symbols]
1 ATI group
2 AT group α
3 AT group β
4 ATI group area
5 Data area
6 AT area
7 1 data entry range
20 Nonvolatile memory
21 Host I / F
22 Control unit
23 RAM

Claims (8)

A plurality of address management tables that convert a logical address given to access the nonvolatile memory into a physical address, and an address conversion table index information group that manages the plurality of address management tables. In a memory card configured to hold in a non-volatile memory and appropriately develop necessary address management information in a volatile memory,
When updating from the current address management table to the next address management table and updating from the current address conversion table index information to the next address conversion table index information, which occurs when data is updated,
When the current address management table is the final address management table of the address management table group managed by the current address conversion table index information group,
Writing the next address management table in a write area different from the current address management table;
A semiconductor memory card, wherein the next address conversion table index information is written in a write area different from the current address conversion table index information. A plurality of address management tables that convert a logical address given to access the nonvolatile memory into a physical address, and an address conversion table index information group that manages the plurality of address management tables. In a memory card configured to hold in a non-volatile memory and appropriately develop necessary address management information in a volatile memory,
In the case where the address management table and the address conversion table index information manage an address space across a plurality of nonvolatile memories,
When updating from the current address management table to the next address management table and updating from the current address conversion table index information to the next address conversion table index information, which occurs when data is updated,
A semiconductor memory card, wherein the next address management table is written in a write area of a non-volatile memory different from the non-volatile memory in which the current address management table is written. A plurality of address management tables that convert a logical address given to access the nonvolatile memory into a physical address, and an address conversion table index information group that manages the plurality of address management tables. In a memory card configured to hold in a non-volatile memory and appropriately develop necessary address management information in a volatile memory,
In the case where the address management table and the address conversion table index information manage an address space across a plurality of nonvolatile memories,
When updating from the current address management table to the next address management table and updating from the current address conversion table index information to the next address conversion table index information, which occurs when data is updated,
Writing the next address management table in a write area different from the current address management table;
A semiconductor memory card, wherein the next address conversion table index information is written in a write area of a non-volatile memory different from the non-volatile memory in which the current address conversion table index information is written. A plurality of address management tables that convert a logical address given to access the nonvolatile memory into a physical address, and an address conversion table index information group that manages the plurality of address management tables. In a memory card configured to hold in a non-volatile memory and appropriately develop necessary address management information in a volatile memory,
Update from the current address management table to the next address management table that occurs when data is updated, and the next address conversion table index from the current address conversion table index information When updating to information,
Writing the next address management table in a write area different from the current address management table;
A semiconductor memory card, wherein a block in which an address management table group managed by past address conversion table index information is written is invalidated. A plurality of address management tables for converting a given logical address to a physical address for accessing the nonvolatile memory and an address conversion table index information group for managing the plurality of address management tables are held in the nonvolatile memory. In a management information update method for developing appropriate address management information in volatile memory as appropriate,
When updating from the current address management table to the next address management table and updating from the current address conversion table index information to the next address conversion table index information, which occurs when data is updated,
When the current address management table is the final address management table of the address management table group managed by the current address conversion table index information group,
Writing the next address management table in a write area different from the current address management table;
A management information update method, wherein the next address translation table index information is written in a write area different from the current address translation table index information. A plurality of address management tables for converting a given logical address to a physical address for accessing the nonvolatile memory and an address conversion table index information group for managing the plurality of address management tables are held in the nonvolatile memory. In a management information update method for developing appropriate address management information in volatile memory as appropriate,
In the case where the address management table and the address conversion table index information manage an address space across a plurality of nonvolatile memories,
When updating from the current address management table to the next address management table and updating from the current address conversion table index information to the next address conversion table index information, which occurs when data is updated,
A management information update method, wherein the next address management table is written in a write area of a non-volatile memory different from the non-volatile memory in which the current address management table is written. A plurality of address management tables for converting a given logical address to a physical address for accessing the nonvolatile memory and an address conversion table index information group for managing the plurality of address management tables are held in the nonvolatile memory. In a management information update method for developing appropriate address management information in volatile memory as appropriate,
In the case where the address management table and the address conversion table index information manage an address space across a plurality of nonvolatile memories,
When updating from the current address management table to the next address management table and updating from the current address conversion table index information to the next address conversion table index information, which occurs when data is updated,
Writing the next address management table in a write area different from the current address management table;
A management information update method, wherein the next address conversion table index information is written in a write area of a non-volatile memory different from the non-volatile memory in which the current address conversion table index information is written. A plurality of address management tables for converting a given logical address to a physical address for accessing the nonvolatile memory and an address conversion table index information group for managing the plurality of address management tables are held in the nonvolatile memory. In a management information update method for developing appropriate address management information in volatile memory as appropriate,
Update from the current address management table to the next address management table that occurs when data is updated, and the next address conversion table index from the current address conversion table index information When updating to information,
Writing the next address management table in a write area different from the current address management table;
A management information updating method, wherein a block in which an address management table group managed by past address conversion table index information is written is invalidated.

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