JP4198271B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a general semiconductor memory device, and more particularly to a semiconductor memory device that operates in synchronization with a clock.
In recent years, with the increase in CPU speed, semiconductor memory devices such as DRAM (dynamic random access memory) have been required to input / output data signals at a higher signal frequency to increase the data transfer speed. Yes.
[0002]
For example, SDRAM (synchronous dynamic random access memory) and FCRAM (fast cycle random access memory) as semiconductor memory devices that meet this demand realize high-speed operation by operating in synchronization with an external clock signal. is doing.
[0003]
[Prior art]
Hereinafter, as an example of a conventional semiconductor memory device, an operation of an SDRAM will be described.
FIG. 1 shows an example of a circuit configuration around a memory cell of an SDRAM. The circuit of FIG. 1 includes a capacitor 201, NMOS transistors 202 to 212, 223, 224 and PMOS transistors 213, 221, 222. Note that the PMOS transistors 221 and 222 and the NMOS transistors 223 and 224 constitute a sense amplifier 220. Further, 1-bit data is stored in the capacitor 201 which is a memory cell (memory cell).
[0004]
FIG. 2 is a timing chart showing a data read operation of the SDRAM having the circuit around the memory cell shown in FIG. The data read timing control will be described with reference to FIGS.
In the case of data reading, as commands for the SDRAM, a precharge command (PRE) for precharging the bit lines BL and / BL to a predetermined voltage, a / RAS command (R) for row access, and / for column access. CAS commands (C) are sequentially input. The / RAS command selects one row-related memory cell block, that is, a specific word line from the core circuit in the SDRAM. The / CAS command selects a specific column, that is, the sense amplifier 220 from the selected word line. In the core circuit, memory cells 201 are arranged in an array in the row and column directions, and a sense amplifier 220 is provided for each column. Therefore, the sense amplifier 220 captures data of the memory cell corresponding to the selected word line.
[0005]
When the / RAS command is input, the bit line transfer signal BLT0 becomes LOW (at this time, BLT1 is HIGH and the NMOS transistors 203 and 204 are in a conductive state), and the bit lines BL and / BL are sense amplifiers. 220. At the same time, the precharge signal PR is dropped to LOW to release the reset state of the bit line BL.
[0006]
A specific word line is selected by selecting the sub word line selection signal SW and setting it to HIGH. As a result, the NMOS transistor 202 which is a cell gate becomes conductive, and the data of the capacitor 201 is read out to the bit line BL.
Next, in order to drive the sense amplifier 220, the sense amplifier drive signals SA1 and SA2 are activated, and the NMOS transistor 212 and the PMOS transistor 213 are turned on. In this state, the data on the bit lines BL and / BL are read into the sense amplifier 220 via the NMOS transistors 203 and 204. When the sense amplifier 220 is driven, the data on the bit lines BL and / BL are amplified and the amplitude is increased. At this time, the data of all the memory cells corresponding to the selected word line are taken into the sense amplifier 220.
[0007]
Next, in response to the / CAS command, the column line selection signal CL becomes HIGH, and a specific column is selected. The selected NMOS transistors 210 and 211, which are column gates, are turned on, and the amplified data on the bit lines BL and / BL are read to the data buses DB and / DB. In the SDRAM having the above configuration (single bank), when data of the same row address (same word line) is read continuously, different columns are sequentially selected, that is, the data has already been stored. By sequentially setting the column line selection signal corresponding to each stored sense amplifier to HIGH, data of different column addresses can be read sequentially. Therefore, for example, when the burst length BL = 4, as shown in FIG. 2, 4-bit continuous data is read.
[0008]
After that, when a precharge command is input, the precharge signal PR becomes HIGH at an appropriate timing, the NMOS transistors 207, 208, and 209 are turned on, and the bit lines BL and / BL are precharged to a predetermined potential VPR. The As a result, the bit lines BL and / BL can be reset to prepare for the next control signal (R or W).
[0009]
However, if another command input (R), (C), (PRE) is used to read data of different row addresses (different word lines) (that is, in the case of page miss hit), a new word line is created. Therefore, it is necessary to newly read data from each memory cell selected by the bit lines BL and / BL. Further, in the single bank configuration, in order to read new data to the bit lines BL and / BL, it is necessary to precharge the bit lines BL and / BL in advance. For this reason, as shown in FIG. 2, a large time interval, that is, a blank period of 10 clocks, is generated for reading data at different row addresses.
[0010]
Therefore, in order to fill this blank period, a bank interleaving method is employed in an SDRAM having a multi-bank configuration. For example, a command is input so that a plurality of banks are selected and data is sequentially output. That is, as described in the lower part of FIG.
Thereby, the read data of bank 1 is output during the blank period of 10 clocks of the read data of bank 0, and the blank period can be improved to some extent.
[0011]
Other conventional semiconductor memory devices include, for example, FCRAM. Hereinafter, differences from the SDRAM and timing control for reading data from the FCRAM will be described. The circuit configuration around the FCRAM memory cell is the same as the circuit configuration shown in FIG.
As a first difference from the SDRAM, the FCRAM reads data from each sense amplifier 220 in parallel by selecting a plurality of columns at a time. Therefore, it is only necessary to drive each sense amplifier 220 for a fixed period, and the period of the sense amplifier operation is made constant regardless of the burst length BL (for example, the period of the sense amplifier operation of BL = 1 and BL = 4 is The same), and it is possible to execute a raw pipeline operation without any disturbance.
[0012]
Second, the FCRAM automatically performs a reset operation in response to an internal precharge signal (corresponding to (PRE) of SDRAM). This utilizes the fact that the period of the sense amplifier operation is the same, so that precharge is executed at an optimal timing immediately after the data is read from each sense amplifier 220. Therefore, it is possible to realize data reading in a high-speed cycle close to the limit of the operation capability of the sense amplifier 220.
[0013]
Third, in FCRAM, the read cycle of random access is short due to the pipeline operation and the self-precharge. For example, when the burst length BL = 4 as in the SDRAM described above, each sense amplifier The 4-bit parallel data read from the data is converted into serial data, and continuous continuous data reading is realized.
[0014]
FIG. 3 is a timing chart showing the data read operation of the FCRAM having the peripheral circuit of the memory cell shown in FIG. Data read timing control will be described with reference to FIGS. Note that the burst length of read data is assumed to be burst length BL = 4 as in the case of SDRAM.
When an activation command (ACT) is input, the FCRAM internally generates RASZ which is a signal for instructing the sense amplifier 220 to take in the data of each memory cell 201, and further, the word line selection signal MW and SW, bit line transfer signal BLT, and sense amplifier drive signals SA1 and SA2 are generated at appropriate timing. As a result, the data of the memory cell 201 appears on the bit line BL, is taken into the sense amplifier 220, and the amplitude is further amplified within the sense amplifier 220.
[0015]
Further, the FCRAM generates the internal precharge signal PRE after a predetermined time has elapsed since the signal RASZ was received.
Further, in response to the input of the read command (RD), the column line selection signal CL of the column selected by the column address becomes HIGH, and the data of the sense amplifier 220 is read to the data buses DB and / DB. The read data is 4-bit parallel data. This data is converted into serial data and output to the outside as read data DQ.
[0016]
As shown in FIG. 3, the internally generated precharge signal PRE is the same operation as when the precharge signal (PRE) is input from the outside of the SDRAM, and the bit line transfer signal BLT and the word line selection signal MW. And SW are reset, and the bit lines BL and / BL are precharged to a predetermined potential. The timing of the precharge operation by the precharge signal PRE is immediately after data is read from the sense amplifier 220 by the column line selection signal CL.
[0017]
In FCRAM, commands are received in a packet format to shorten the interval between commands. That is, in FIG. 3, an activation command (ACT) and a read command (RD) are input as one packet extending over two cycles.
When the above data read operation is repeatedly executed, the random access read cycle is short in FCRAM. For example, when burst length BL = 4, continuous continuous data read is realized as shown in FIG. is doing. That is, FCRAM does not require the bank interleaving method used in SDRAM.
[0018]
As described above, in the FCRAM, the data reading blank period that occurs in the SDRAM does not occur, and higher-speed data reading is realized.
[0019]
[Problems to be solved by the invention]
As described above, since the FCRAM does not have a blank period generated in the SDRAM when reading data, the data can be read at a higher speed.
Logically, the burst length can be increased by increasing the number of bits of parallel data read simultaneously. However, since the potential difference between a larger number of bit line pairs must be amplified at the same time and then the bit line pairs must be reset, the read operation becomes slow.
[0020]
To speed up the read operation, it is necessary to make the core size as small as possible. However, if the core size is reduced, the number of bits of parallel data that can be read simultaneously decreases. In other words, the conventional technique has a trade-off relationship between the number of bits of parallel data that can be read simultaneously and the speed of data reading, and cannot meet the demand for reading more bits at a higher speed.
[0021]
According to the present invention, a plurality of memory cell blocks can be selectively activated by automatically performing a bank interleaving operation internally, and further, the reading speed of data stored in the memory block can be increased. An object is to provide a semiconductor memory device.
[0022]
[Means for Solving the Problems]
Therefore, in order to solve the above problem, in the invention of claim 1, a semiconductor memory device having a plurality of banks having at least one memory cell block selects a single memory cell block when the burst length is equal to or less than a predetermined value. Activated when the value is longer than the predetermined value. In the bank Memory cell block one of A block activation circuit (equivalent to a RAS generation unit 9, an internal interleave generation circuit 6, a timing controller 10 and a predecoder 11 in an embodiment to be described later) and a specific activation based on an external address signal An address decoder for generating a bank selection signal for selecting a bank (corresponding to an address buffer 3 in an embodiment to be described later), and in the data read operation, the block activation circuit has a burst length equal to or less than a predetermined value. In the case where the single memory cell block is selected and the burst length is longer than a predetermined value, Multiple banks are selected alternately in succession, and one of the memory cell blocks is selected in the selected bank. It is characterized by selecting.
[0023]
According to another aspect of the semiconductor memory device of the present invention, the relationship between the burst length of the data output and the selected memory cell block is defined, and a specific configuration for realizing the relationship is defined.
For example, the conventional FCRAM reads data from each corresponding sense amplifier 220 in parallel by generating a plurality of column line selection signals CL by inputting a single read command (RD). However, in this configuration, when the number of bits of parallel data to be read is 4 bits, for example, the maximum burst length that can be set is BL = 4. That is, the conventional FCRAM can select only a single memory cell block by inputting a read command once.
[0024]
On the other hand, in the semiconductor memory device according to the first aspect, a plurality of memory cell blocks can be selectively activated by inputting a single read command. Therefore, the memory cell block can be selected according to the burst length. Specifically, for example, when the burst length is BL = 32, the semiconductor memory device of the present invention selectively activates eight memory cell blocks by inputting a read command once, and generates 32-bit data in the order of activation. Can be read out.
[0025]
Further, in the invention of claim 2, the semiconductor memory device of claim 1 is the plurality of the plurality of semiconductor memory devices. In the bank Memory cell block one of When the memory cell is activated, the cycle time required for the data reading process is the same as that when the single memory cell block is selected.
According to another aspect of the present invention, there is provided a semiconductor memory device that defines a method for increasing the data reading speed.
[0026]
For example, in the conventional FCRAM, for example, when the burst length is BL = 4, when a read command is input, 4-bit serial data is read. Therefore, in the conventional FCRAM, when this data read operation is executed twice (that is, when a read command is input twice), continuous 8-bit serial data is read. In this case, the cycle time required for the data reading process is twice as long as when reading 4-bit serial data.
[0027]
On the other hand, in the semiconductor memory device according to claim 1, for example, when the burst length is BL = 8, when a read command is input once, two memory cell blocks are automatically selectively activated. Therefore, continuous 8-bit serial data is read at a time. In this case, for example, by doubling the clock frequency or by using DDR (Double Data Rate), the cycle time required for the data reading process is read out with 4-bit serial data at the burst length BL = 4. It can be the same as when. That is, the transfer rate of the semiconductor memory device of the present invention is twice that of the conventional FCRAM.
[0030]
Claims 3 In the invention, the predetermined value of the burst length is the number of bits of parallel data read from the selectively activated memory block according to claim 1. Claim 3 The invention defines an example of a predetermined value of the burst length.
Claims 4 In this invention, the semiconductor memory device according to claim 1 has a parallel / serial conversion circuit (corresponding to parallel-serial conversion circuits 18a and 18b in the embodiments described later) for converting parallel data into serial data. The conversion circuit sequentially takes in a plurality of bits of parallel data output from the plurality of memory cell blocks, outputs serial data based on the burst length information, and if the burst length is longer than a predetermined value, the burst at that time The serial data transmission rate is increased according to the length (corresponding to the parallel-serial conversion circuits 18a and 18b and the DQ controller 17 in the embodiment described later). Claim 4 The described invention defines an example of a configuration for realizing high-speed data reading processing.
[0031]
Further claims 5 The semiconductor memory device described in (2) further includes an address counter (corresponding to an address counter 90 in an embodiment to be described later) in addition to the configuration described in claim 1, and a second burst length set longer than the predetermined value. If it is longer than a predetermined value, a plurality of memory cell blocks are activated repeatedly for a number of times based on the burst length in response to a first address signal given from the outside and a second address signal generated by the address counter based on the first address signal. It is characterized by becoming. By activating a plurality of memory cell blocks repeatedly based on the burst length, data of an arbitrary burst length can be read.
[0032]
Claim 6 The semiconductor memory device according to claim 5 The first address signal and the second address signal select different word lines. By selecting different word lines, data can be read from the same memory block a plurality of times by applying a first address signal from the outside.
Claim 7 The semiconductor memory device according to claim 1 further comprises a burst length information generation circuit (corresponding to a mode register 4 in an embodiment described later) for generating burst length information.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor memory device according to the present invention will be described below with reference to the drawings.
FIG. 4 shows an embodiment of the semiconductor memory device of the present invention. As an example, the FCRAM of the present invention is taken as a specific example.
The FCRAM of the present invention includes a clock buffer 1, a command decoder 2, an address buffer 3, a mode register 4, a clock counter 5, an internal interleave generation circuit 6, a bank 0 circuit 7, a bank 1 circuit 8, a DQ controller 17, and a bank 0. The parallel-serial conversion circuit 18 a, the bank- 1 parallel-serial conversion circuit 18 b, and the data output buffer 19 are included. In the bank 0 circuit 7 and the bank 1 circuit 8, a plurality of memory cell blocks (memory cell blocks 12a, 12b, 12c, 12d) each including memory cells 14 arranged in a matrix, and a RAS generation unit 9, a timing controller 10, a predecoder 11, a row decoder 13, a column decoder 14, a sense amplifier 15, and a sense buffer 16.
[0034]
The FCRAM of the present invention configured as described above automatically activates a plurality of memory cell blocks by automatically performing a bank interleaving operation internally, and further stores data stored in the memory block. Realizes faster reading speed. The memory cell of this embodiment (for example, the illustrated memory cell 20) has, for example, a DRAM type cell structure, and the circuit configuration around the memory cell of this embodiment is the same as that of FIG. The same configuration is used. In this embodiment, for example, a cell matrix (core circuit) in which memory cells are arranged in a matrix is divided into a plurality of bank units (a bank 0 circuit and a bank 1 circuit shown in the figure). The cell matrix divided for each bank forms each block (12a, 12b, 12c, 12d in the figure) in which a plurality of memory cells are arranged in the row and column directions. Each block has a sense amplifier 15 for each column. 1 is illustrated as a two-bank configuration for convenience of explanation, the bank configuration in the FCRAM is not limited to this.
[0035]
The function of each part constituting the FCRAM of the present invention will be briefly described. The clock buffer 1 receives an external clock signal (CLK) and supplies a synchronous clock CLK1 to each part of the FCRAM. The command decoder 2 receives external commands such as a read command (WE: hereinafter referred to as RD), a write command (/ WE), a chip select signal (/ CS), etc., and decodes them for each bank described later. Notify the circuit. Note that / represents a negative logic signal and the others represent positive logic signals. The address buffer 3 receives external memory address signals (A0 to An). The variable n is an integer corresponding to the memory capacity. The mode register 4 includes a register for setting a burst length to be used internally, and generates burst length information based on the burst length from the outside. The clock counter 5 generates a pulse signal at regular timing according to the burst length information. The internal interleave generation circuit 6 selects a bank to be activated based on the burst length information and the pulse signal. The parallel-serial conversion circuits 18a and 18b convert parallel data read from each memory cell block into serial data. The DQ controller 17 controls the parallel-serial conversion circuits 18a and 18b and the data output buffer 19 when reading data.
[0036]
In the bank 0 circuit 7, the RAS generation unit 9 generates a signal brazz for instructing the sense amplifier to read data of each memory cell in the memory cell block. The timing controller 10 generates a signal for activating each block and a signal bsprx signal for automatically precharging the interior after a predetermined time has elapsed since the activation of the memory cell block was started. The predecoder 11 latches and predecodes the supplied address signal, and selects one of a plurality of memory blocks arranged in the bank. The row decoder 13 generates a word line selection signal for selecting a word line corresponding to the address signal. The sense amplifier 15 receives and holds data of all memory cells coupled to the word line selected by the word line selection signal. The column decoder 14 generates a column line selection signal for simultaneously selecting a plurality of bits of data held in the plurality of sense amplifiers. The sense buffer 16 buffers the read parallel data. Note that the configuration and function of the bank 1 circuit 8 are the same as those of the bank 0 circuit 7, and the description thereof is omitted.
[0037]
The FCRAM shown in FIG. 4 starts a data read operation when, for example, a clock signal (CLK), an activation command (ACT), a control signal (RD), and an address signal (A0 to An) are input. . First, a basic data reading operation (for example, when the burst length BL = 4) of the FCRAM of the present invention will be described with reference to FIG.
[0038]
The clock signal (CLK) is always supplied to each component in the FCRAM as an internal global clock signal CLK1 in order to synchronously control the operation of the FCRAM. The activation command (ACT) and the control signal (RD) are decoded by the command decoder 2 and control the RAS generation unit 9 according to the decoding result. Address signals (A0 to An) are supplied to the predecoder 11 via the address buffer 3. In the address buffer 3, address decoding is performed, and the bank selection signal baz is notified to the RAS generation unit 9 of the bank that executes the data read operation. Here, it is assumed that the bank selection signal baz is notified to the bank 0 circuit 7.
[0039]
When an activation command (ACT) is input, the RAS generation unit 9 generates a signal brazz that is an internal RAS signal. The RAS generation unit 9 is for continuously generating a signal brazz when a refresh command is input and executing a refresh operation. When the activation command (ACT) is input, the RAS generation unit 9 generates the signal brazz once. . The generated signal brasz is a signal for instructing the sense amplifier to read data in the memory cell, and is supplied to the timing controller 10.
[0040]
The timing controller 10 generates a block activation signal for activating any block in the bank 0 circuit 7 and supplies the block activation signal to the predecoder 11. At the same time, a sense buffer activation signal sbez for activating the sense amplifier 15 and the sense buffer 16 is generated and supplied to each. Further, when receiving the signal brazz, the timing controller 10 generates a precharge signal bsprx after a predetermined time has elapsed. The internally generated precharge signal bsprx resets the RAS generation unit 9 to perform a precharge operation in the same manner as when a precharge signal is supplied from the outside. This precharge operation by the internally generated precharge signal bsprx is hereinafter referred to as self-precharge.
[0041]
When the predecoder 11 receives the address signal (A0 to An), the predecoder 11 selects one of a plurality of memory cell blocks arranged in the bank 0 circuit 7, for example, the block 12a. Further, when receiving the block activation signal, the predecoder 11 controls the row decoder 13 to generate the word line selection signal swl at an appropriate timing. In the bank 0 circuit 7, the row decoder 13 operates only in the selected memory cell block (block 12a), and all the blocks in the block 12a coupled to the word line selected by the word line selection signal swl are connected. The data of the memory cell is read out and stored in the sense amplifier 15.
[0042]
In addition, the predecoder 11 controls the column decoder 14 to generate the column line selection signal clz at an appropriate timing. The column decoder 14 supplies the column line selection signal clz to a plurality of columns (fixed number of bits), for example, four columns, and reads 4-bit parallel data from the sense amplifiers 15 of these columns, This is supplied to the sense buffer 16. The sense buffer 16 amplifies the read 4-bit parallel data and supplies it to the parallel-serial conversion circuit 18a. The amplified 4-bit parallel data is converted into serial data by the parallel-serial conversion circuit 18 a and read out to the outside through the data output buffer 19.
[0043]
As described above, the FCRAM of the present invention reads a plurality of bits of parallel data from the sense amplifier 15 by selecting a plurality of columns at a time. Therefore, it is only necessary to drive the sense amplifier 15 for a fixed period, and the period of the sense amplifier operation is made constant regardless of the burst length BL (for example, the period of the sense amplifier operation of BL = 1 and BL = 4 is the same). ), Enabling the execution of low-order pipeline operations without disturbance.
[0044]
Further, the FCRAM of the present invention automatically performs a reset operation by the internal precharge signal bsprx. In other words, by utilizing the fact that the period of the sense amplifier operation is the same, the precharge is executed at the optimum timing immediately after the data reading from the sense amplifier 15. Therefore, it is possible to realize data reading in a high-speed cycle close to the limit of the operation capability of the sense amplifier 15.
[0045]
Further, the FCRAM of the present invention has a short random access read cycle due to the pipeline operation and the self-precharge. For example, when the burst length BL = 4 as in the SDRAM described above, By converting 4-bit parallel data read from the amplifier into serial data, continuous continuous data reading can be realized.
[0046]
However, with such a configuration alone, when the number of bits of parallel data selected by the column line selection signal clz and read from the sense amplifier 15 is, for example, 4 bits, the maximum burst length that can be set is BL = 4. . In other words, since only a single memory cell block can be selected by inputting a single read command, the maximum burst length that can be set depends on the number of bits of parallel data read from the sense amplifier 15.
[0047]
Therefore, the FCRAM of the present invention is configured to selectively activate a plurality of memory cell blocks by automatically performing a bank interleaving operation internally in addition to the above basic data reading operation.
FIG. 5 shows a selection of a plurality of memory cell blocks, for example, the bank 0 circuit 7 and the bank 1 circuit 8 shown in FIG. 4 in the RAS generation unit 9 and the internal interleave generation circuit 6 constituting the FCRAM of the present invention. The sequence for activating automatically is shown. Here, the operation of selectively activating the bank 0 circuit 7 and the bank 1 circuit 8 when the burst length BL = 8 will be described with reference to FIGS. As shown in FIGS. 4 and 5, the RAS generation unit 9 is provided for each bank, and selects one of a plurality of memory cell blocks arranged in each bank. The mode register 4 outputs burst length information bl8 indicating that the burst length BL = 8 is set.
[0048]
For example, when a read command (RD) and an address signal (A0 to An) are input, in the FCRAM of the present invention, the internal interleave generation circuit 6 automatically performs a bank interleave operation in accordance with the burst length information bl8. . That is, the bank selection signal baz from the address buffer 3 is invalidated, and a low activation command (low activation command in FIG. 5) is automatically generated by the command generation unit 23 in the internal interleave generation circuit 6 according to the burst length information bl8. Further, the address generator 24 automatically generates a bank address (bank address in FIG. 5) for designating a bank for executing the data read operation, and generates the generated signals, for example, bank 0 This is supplied to the RAS generation unit 9 in the circuit 7 for use. At the same time, the clock counter 5 starts counting in order to generate a pulse signal clkcount for automatically activating other banks.
[0049]
The RAS generation unit 9 in the bank 0 circuit 7 generates a signal bras0z (signal bras0z in FIG. 5), which is a bank 0 RAS signal. The signal bras0z is a signal for instructing the sense amplifier 15 to read the data of the memory cell, and is supplied to the timing controller 10.
The timing controller 10 generates a block activation signal for activating any block in the bank 0 circuit 7 and supplies the block activation signal to the predecoder 11. At the same time, a sense amplifier activation signal for activating the sense amplifier 15 is generated, and then a sense buffer activation signal sbez for activating the sense buffer 16 is generated and supplied to each at a predetermined timing. Further, when receiving the signal brazz, the timing controller 10 generates a precharge signal bsprx after a predetermined time has elapsed. The internally generated precharge signal bsprx resets the RAS generation unit 9 to perform a precharge operation in the same manner as when a precharge signal is supplied from the outside.
[0050]
When the predecoder 11 receives the address signal (A0 to An), the predecoder 11 selects one of a plurality of memory cell blocks arranged in the bank 0 circuit 7, for example, the block 12a. Further, when receiving the block activation signal, the predecoder 11 controls the row decoder 13 to generate the word line selection signal swl at an appropriate timing. In the bank 0 circuit 7, the row decoder 13 operates only in the selected memory cell block (block 12a), and all the blocks in the block 12a coupled to the word line selected by the word line selection signal swl are connected. The data of the memory cell is read out and stored in the sense amplifier 15.
[0051]
In addition, the predecoder 11 controls the column decoder 14 to generate the column line selection signal clz at an appropriate timing. The column decoder 14 supplies the column line selection signal clz to a plurality of columns (the number of bits is fixed), for example, four columns, and reads 4-bit parallel data gdb from the sense amplifier 15 of those columns. , Supplied to the sense buffer 16 in the bank 0 circuit 7.
[0052]
Further, in the FCRAM according to the present invention, the bank interleaving operation automatically executed by the internal interleave generation circuit 6 is continued together with the pulse signal clkcount automatically generated by the clock counter 5.
That is, the command generation unit 23 in the internal interleave generation circuit 6 automatically generates a row activation command (row activation command in FIG. 5), and the address generation unit 24 designates a bank for executing a data read operation. A bank address (bank address in FIG. 5) is automatically generated, and the generated signals are supplied to, for example, the RAS generation unit 9 in the bank 1 circuit 8.
[0053]
The RAS generation unit 9 in the bank 1 circuit 8 generates a signal bras1z (signal bras1z in FIG. 5), which is a bank 1 RAS signal. The signal bras1z is a signal for instructing the sense amplifier 15 to read data in the memory cell, and is supplied to the timing controller 10.
Thereafter, in the bank 1 circuit 8, the same operation as that of the bank 0 circuit 7 is performed, and the column line selection signal clz is supplied to the designated four columns, and the 4-bit sense amplifier 15 of those columns is supplied with 4 bits. The parallel data gdb is read and supplied to the sense buffer 16 in the bank 1 circuit 8.
[0054]
In this state, the FCRAM of the present invention amplifies the 4-bit parallel data read by the sense buffer 16 in each bank and supplies it to the parallel-serial conversion circuits 18a and 18b, respectively. The amplified 4-bit parallel data is converted into serial data by the parallel-serial conversion circuits 18a and 18b, and read out to the outside as serial data continuous in the activation order under the control of the DQ controller 17.
[0055]
As described above, the FCRAM of the present invention can selectively activate a plurality of memory cell blocks by inputting a single read command (RD). Accordingly, the memory cell block can be selected according to the burst length BL. In this embodiment, two memory cell blocks (the memory cell block 12a in the bank 0 circuit 7 and the bank 1 circuit 8) are input by one read command (RD) according to the burst length BL = 8. (2 of the memory cell blocks 12a in the memory cell block 12a) is selectively activated and serial data is read out in the order of activation. For example, when the burst length is BL = 32, as will be described later. The eight memory cell blocks may be selectively activated by inputting one read command (RD), or the two memory cell blocks may be sequentially activated.
[0056]
In the FCRAM of the present invention shown in FIG. 4, the serial data transmission rate of the parallel-serial conversion circuits 18a and 18b is increased according to the burst length BL set in the mode register 4.
For example, when the burst length BL = 8, a clock signal having a frequency twice that of the burst length BL = 4 is input to the parallel-serial conversion circuits 18a and 18b, and the transmission rate at the time of 8-bit burst is set at the time of 4-bit burst. 2 times. Therefore, in the FCRAM of the present invention, the cycle time required for the data read process when the burst length BL = 8 is the same as that when the burst length BL = 4, and the data read operation can be speeded up. Note that the clock signal supplied to the parallel-serial conversion circuits 18a and 18b when the burst length BL = 8 may be double the clock signal CLK (see FIG. 4), or the rising and falling edges of the clock signal CLK. DDR (Double Data Rate) that operates in synchronization with both may be used.
[0057]
The description of the operation of the FCRAM according to the present invention for selectively activating a plurality of memory cell blocks has been completed.
FIG. 6 shows a specific circuit example of the clock counter 5 shown in FIG.
The clock counter 5 uses a four-stage delayed flip-flop (DFF 31, 32, 33, 34) to generate a pulse signal at a regular timing. That is, when a plurality of memory cell blocks are activated, the read data is output to the outside in the activation order by activating the subsequent memory cell block after 4 clocks of the memory cell block to be activated in advance. . The four-stage DFF is adapted to the number of bits of parallel data selected by the column selection signal line and read to the sense buffer 16. For example, in the structure in which 5-bit parallel data is read, the DFF is also 5 It becomes a stage configuration.
[0058]
In the clock counter 5, for example, when the burst length information bl8 is HIGH, the clock signal CLK1 is supplied to each DFF, and the HIGH of the read command (RD) input thereafter rises with a delay of 4 clocks, and pulses at the rising timing. The generation circuit 35 generates a clock count signal clkcount.
[0059]
FIG. 7 shows a specific circuit example of the internal interleave circuit 6 and the RAS generation unit shown in FIG.
The internal interleave circuit 6 includes a command generation unit 23 including a NAND gate 48 and an inverter 49, an address generation unit 24 including delay circuits 41, 42 and 43, inverters 44, 45 and 46, and NAND gates 47 and 48. And have. For example, when the burst length information bl8 is HIGH, the command generation unit 23 sets the internally generated low activation command to HIGH at the rising edge of the clock count signal clkcount, and selects a bank to be selected subsequently when a plurality of banks are selected. Control. The address generator 24 forms RS • F / F (reset • set • flip • flop) at each internal gate, and when the burst length information bl8 is LOW (BL = 4), both internally generated bank addresses To HIGH. Further, when the burst length information bl8 is HIGH (BL = 8), the internally generated bank address for bank 0 is set (LOW), the internally generated bank address for the other bank 1 is reset (HIGH), and the bank 0 Circuit 7 is selected. Thereafter, at the rising edge of the bank 0 RAS signal bras0z, the internally generated bank address for bank 0 is reset (HIGH), the internally generated bank address for the other bank 1 is set (LOW), and the bank 1 circuit 8 is select. The reset signal sttz is normally LOW, and in the initial state, the bank 0 RAS signal bras0z and the bank 1 RAS signal bras1z are LOW.
[0060]
The RAS generation unit 9 in the bank 0 circuit 7 includes a bank 0 row active command generation circuit 21a composed of NAND gates 51, 52 and 53, a NOR gate 71, inverters 72, 75 and 76, a NAND gate 73, 74 includes a bank 0 RAS generation unit 22a and a bank 0 timing controller 10a. When the burst length information bl8 input via the inverter 62 is LOW (BL = 4) and the activation command actpz is HIGH, the bank 0 row activation command generation circuit 21a is HIGH of the bank 0 selection address ba0z. (Output from the address buffer 3) is validated and the bank 0 row activation command LOW is output. When the burst length information bl8 (BL = 8) is HIGH, the bank 0 selection address ba0z is invalidated, and the bank 0 low activation command is output at the rising timing of the activation command actpz. The bank 0 row activation command is LOW if the internally generated bank address is an address for selecting bank 0. The bank 0 RAS generation unit 22a changes the bank 0 RAS signal bras0z from LOW to HIGH in response to the LOW from the bank 0 low activation command generation circuit 21a.
[0061]
The RAS generation unit 9 in the bank 1 circuit 8 includes a bank 1 row active command generation circuit 21b including NAND gates 54 and 55, transistors 56, 57, 58, 59, and 60, a NOR gate 81, and an inverter 82. , 85 and 86, and a bank 1 RAS generation unit 22b composed of NAND gates 83 and 84, and a bank 1 timing controller 10b. When the burst length information bl8 input via the inverter 62 is LOW (BL = 4) and the activation command actpz is HIGH, the bank 1 row activation command generation circuit 21b is HIGH of the bank 1 selection address ba1z. (Output from the address buffer 3) is validated and the bank 1 row activation command LOW is output. When the burst length information bl8 (BL = 8) is HIGH and the count signal clkcount is HIGH, the bank 1 selection address ba1z is invalidated, and the bank 1 row activation command is activated at the rising timing of the activation command actpz. Is output. The bank 1 row activation command is LOW if the internally generated bank address is an address for selecting bank 1. The bank 1 RAS generating unit 22b changes the bank 1 RAS signal bras1z from LOW to HIGH in response to the LOW from the bank 1 low activation command generation circuit 21b and the internally generated low activation command HIGH.
[0062]
FIG. 8 is a timing chart showing the data read operation of the FCRAM of the present invention when the burst length BL = 4. The timing chart will be described in detail according to the circuit examples of FIGS. The burst length BL = 4 is preset in the mode register 4 and the burst length information bl8 is LOW.
For example, the activation command (ACT), the control signal (RD0: read command for the bank 0), and the address signal (A0 to An) are input in a state where the clock signal (CLK) is input at a cycle of 5 ns as shown in the figure. When the command is input, the command actpz becomes HIGH, and the bank 0 RAS generation unit 22a receives the LOW from the bank 0 low activation command generation circuit 21a, and changes the bank 0 RAS signal bras0z from LOW to HIGH. In this case, since the burst length information bl8 is set to LOW in advance, HIGH of the bank 0 selection address ba0z (output from the address buffer 3) becomes valid.
[0063]
The signal bras0z is supplied to the timing controller 10a. In the timing controller 10a, a block activation signal for activating any block in the bank 0 circuit 7 in response to a change of LOW → HIGH of the signal bras0z. Is supplied to the predecoder 11. Further, the timing controller 10a generates the precharge signal bspr0x after a predetermined time has elapsed. The internally generated precharge signal bspr0x resets the RAS generation unit 9 in the bank 0 circuit 7 to perform a precharge operation, similarly to the case where the precharge signal is supplied from the outside.
[0064]
When the predecoder 11 receives an address signal (A0 to An), the predecoder 11 selects one of a plurality of memory cell blocks arranged in the bank 0 circuit 7 and receives a block activation signal. To change the word line selection signal sw10z from LOW to HIGH at an appropriate timing. In the bank 0 circuit 7, the row decoder 13 operates only in the selected memory cell block, and reads the data of all the memory cells coupled to the word line selected by the word line selection signal swl0z to sense amplifiers. 15.
[0065]
Further, the predecoder 11 controls the column decoder 14 to change the column line selection signal cl0z from LOW to HIGH at an appropriate timing. The column decoder 14 supplies the column line selection signal cl0z to the designated four columns, reads 4-bit parallel data gdb0x / z from the sense amplifiers 15 of those columns, and supplies them to the sense buffer 16.
[0066]
In this state, the timing controller 10a further changes the sense buffer activation signal sbe0z for activating the sense buffer 16 from LOW to HIGH, and activates the sense buffer 16. The sense buffer 16 amplifies the read 4-bit parallel data to generate parallel data cdbx / z, and supplies the parallel data cdbx / z to the parallel-serial conversion circuit 18a.
[0067]
The 4-bit parallel data cdbx / z is converted to serial data by the parallel-serial conversion circuit 18 a in synchronization with the clock signal psclk 0 to 3 z from the DQ controller 17 and supplied to the data output buffer 19. Further, the serial data is read out as output data DQ in synchronization with the control signal outp from the DQ controller 17.
[0068]
In the FCRAM of the present invention that performs such a read operation, for example, as shown in the figure, when a read command (R0) is input every 20 ns and the burst length is BL = 4, each read command (R0) is input. The serial data can be read continuously from the memory cell block selected in (1).
FIG. 9 is a timing chart showing the data read operation of the FCRAM of the present invention when the burst length BL = 8. The timing chart will be described in detail according to the circuit examples of FIGS. The burst length BL = 8 is set in the mode register 4 in advance, and the burst length information bl8 is HIGH.
[0069]
For example, in the state where the clock signal (CLK) is input at a cycle of 2.5 ns as shown in the figure, the activation command (ACT), the control signal (RD0: read command for the bank 0), and the address signal (A0 to An ) Is input, the command actpz becomes HIGH, the bank 0 RAS generation unit 22a receives the LOW from the bank 0 low activation command generation circuit 21a, and changes the bank 0 RAS signal bras0z from LOW to HIGH. To do. In this case, since the burst length information bl8 is set to HIGH in advance, the bank 0 selection address ba0z (output from the address buffer 3) is invalidated and the internally generated bank address from the internal interleave 6 is validated instead. To do.
[0070]
In response to HIGH of the command actpz, the clock counter 5 starts counting the clock count signal.
The signal bras0z changed to HIGH is supplied to the timing controller 10a, and the timing controller 10a activates any block in the bank 0 circuit 7 in response to the change of LOW → HIGH of the signal bras0z. A block activation signal is generated and supplied to the predecoder 11. Further, the timing controller 10a generates the precharge signal bspr0x after a predetermined time has elapsed. The internally generated precharge signal bspr0x resets the RAS generation unit 9 in the bank 0 circuit 7 to perform a precharge operation, similarly to the case where the precharge signal is supplied from the outside.
[0071]
When the predecoder 11 receives an address signal (A0 to An), the predecoder 11 selects one of a plurality of memory cell blocks arranged in the bank 0 circuit 7 and receives a block activation signal. To change the word line selection signal sw10z from LOW to HIGH at an appropriate timing. In the bank 0 circuit 7, the row decoder 13 operates only in the selected memory cell block, and reads the data of all the memory cells coupled to the word line selected by the word line selection signal swl0z to sense amplifiers. 15.
[0072]
Further, the predecoder 11 controls the column decoder 14 to change the column line selection signal cl0z from LOW to HIGH at an appropriate timing. The column decoder 14 supplies the column line selection signal cl0z to the designated four columns, reads 4-bit parallel data gdb0x / z from the sense amplifiers 15 of those columns, and supplies them to the sense buffer 16.
[0073]
In this state, the timing controller 10a further changes the sense buffer activation signal sbe0z for activating the sense buffer 16 from LOW to HIGH, and activates the sense buffer 16. The sense buffer 16 amplifies the read 4-bit parallel data to generate parallel data cdbx / z, and supplies the parallel data cdbx / z to the parallel-serial conversion circuit 18a.
[0074]
The 4-bit parallel data cdbx / z is converted to serial data by the parallel-serial conversion circuit 18 a in synchronization with the clock signal psclk 0 to 3 z from the DQ controller 17 and supplied to the data output buffer 19. Further, the serial data is read out as output data DQ in synchronization with the control signal outp from the DQ controller 17.
[0075]
During the execution of the data read operation from the series of bank 0 circuits 7, the bank 1 circuit 8 also executes the data read operations in a pipeline manner.
The clock count signal clkcount output from the clock counter 5 that has started counting outputs a HIGH pulse in synchronization with the rise of the fourth clock after the change of the command actpz from LOW to HIGH.
[0076]
In response to the HIGH pulse, the internal interleave signal generation circuit 6 changes the internally generated low activation command from LOW to HIGH, and the bank 1 low activation command generation circuit 21b receives the HIGH of the internally generated low activation command. Set output to LOW.
The bank 1 RAS generation unit 22b receives LOW from the bank 1 low activation command generation circuit 21b, and changes the bank 1 RAS signal bras1z from LOW to HIGH.
[0077]
This signal bras1z is supplied to the timing controller 10b, and the timing controller 10b activates any block in the bank 1 circuit 8 in response to the change of the signal bras1z from LOW to HIGH. A signal is generated and supplied to the predecoder 11. Further, the timing controller 10b generates a precharge signal bspr1x after a predetermined time has elapsed. The internally generated precharge signal bspr1x resets the RAS generation unit 9 in the bank 1 circuit 8 to perform a precharge operation.
[0078]
When the predecoder 11 receives an address signal (A0 to An), the predecoder 11 selects one of a plurality of memory cell blocks arranged in the bank 1 circuit 8 and further receives a block activation signal. To change the word line selection signal swl1z from LOW to HIGH at an appropriate timing. In the bank 1 circuit 8, the row decoder 13 operates only in the selected memory cell block, and reads the data of all the memory cells coupled to the word line selected by the word line selection signal swl1z to sense amplifiers. 15.
[0079]
Further, the predecoder 11 controls the column decoder 14 to change the column line selection signal cl1z from LOW to HIGH at an appropriate timing. The column decoder 14 supplies the column line selection signal cl1z to the designated four columns, reads the 4-bit parallel data gdb1x / z from the sense amplifiers 15 of these columns, and supplies them to the sense buffer 16.
[0080]
In this state, the timing controller 10b further changes the sense buffer activation signal sbe1z for activating the sense buffer 16 from LOW to HIGH, and activates the sense buffer 16. The sense buffer 16 amplifies the read 4-bit parallel data to generate parallel data cdbx / z, and supplies the parallel data cdbx / z to the parallel-serial conversion circuit 18a.
[0081]
The 4-bit parallel data cdbx / z is converted to serial data by the parallel-serial conversion circuit 18 a in synchronization with the clock signal psclk 0 to 3 z from the DQ controller 17 and supplied to the data output buffer 19. Further, the serial data is read out as output data DQ in synchronization with the control signal outp from the DQ controller 17.
[0082]
The FCRAM of the present invention that performs such a read operation is, for example, a memory cell block that is selected at the rising edge of the command actpz when a read command (R0) is input and the burst length is BL = 8 as shown in the figure. And the memory cell block selected at the rising edge of the clock count signal clkcount are operated in a pipeline manner with a difference of 4 clocks, and serial data can be continuously read from each memory cell block. Further, when the burst length is BL = 8, the clock signal CLK is input at a cycle of 2.5 ns, so that the read data transfer rate is double that when the burst length is BL = 4.
[0083]
FIG. 10 shows a method for setting the burst length BL other than the mode register 4 for registering the burst length BL as described above.
FIG. 10A includes a circuit (corresponding to an inverter here) connected to a power source via a fuse, and selects a burst length (BL = 4 or BL = 8) used in the manufacturing process. That is, as shown in FIG. 10D, the fuse is connected when BL = 4, and the fuse is cut when BL = 8. Thereby, an FCRAM dedicated to the burst length BL = 4 or BL = 8 is obtained. Note that the burst lengths that can be set are not limited to these two types. For example, each burst length includes a circuit (inverter) connected to a power source via a fuse for each of BL = 4, 8, 16, and 32. The burst length may be fixed by selecting the burst length used in the manufacturing process and cutting all the fuses corresponding to other burst lengths.
[0084]
FIG. 10B includes a circuit (inverter) connected to the pad, and selects a burst length (BL = 4 or BL = 8) used in the manufacturing process. That is, as shown in FIG. 10E, when BL = 4, the power source is connected by wire bonding a, and when BL = 8, the ground is connected by wire bonding b. Thereby, an FCRAM dedicated to the burst length BL = 4 or BL = 8 is obtained. Note that the burst lengths that can be set are not limited to these two types. For example, various burst lengths are provided for each of BL = 4, 8, 16, and 32, and a burst length used in the manufacturing process is provided. Alternatively, the burst length may be fixed by supplying power by wire bonding only to a circuit corresponding to the burst length.
[0085]
FIG. 10C includes a circuit (inverter) connected to the switch a and the switch b, and selects a burst length (BL = 4 or BL = 8) used in the manufacturing process. That is, as shown in FIG. 10F, when BL = 4, the switch a is closed, and when BL = 8, the switch b is closed. Thereby, an FCRAM dedicated to the burst length BL = 4 or BL = 8 is obtained. Note that the burst lengths that can be set are not limited to these two types. For example, each burst length includes a circuit (inverter) connected to a power source via a switch for each of BL = 4, 8, 16, and 32. The burst length may be fixed by selecting the burst length used in the manufacturing process and closing only the switch corresponding to the burst length.
[0086]
FIG. 11 is a block diagram showing the configuration of the parallel-serial conversion circuits 18a and 18b shown in FIG. The parallel-serial conversion circuit shown in FIG. 11 receives 4-bit parallel data from the read buffer 28, and between the input-side bus line and the output-side bus line based on the burst length signal and part of the column address information. The data bus switch 440 that changes the connection path of the data bus, the first register 450 and the second register 460 sequentially connected to the output side of the data bus switch 440, and the 4-bit configuration that is output from the second register 460 4 bits → 2 bits conversion circuit 470 for converting the parallel data of 2 bits into parallel data, and the 2 bits of parallel data provided on the output side of the 4 bits → 2 bits conversion circuit 470 are converted into 1 bit serial data. Data output timing switch 480 and latch & level shifter circuit 430 for conversion into To have.
[0087]
Next, a more detailed configuration and operation of each component will be described.
The data bus switch 440 includes switches sw1n, sw2n, sw3n provided corresponding to the four data bus lines d0, d1, d2, and d3, sw24 for connecting the data buses d1 and d3, d0, It comprises a switch sw14 for connecting d3, a switch sw13 for connecting d0 and d2, and a switch sw12 for connecting d0 and d1. These switches are controlled to be turned on / off corresponding to the burst length signal BL and part of the column address signal caa0z and caa1z.
[0088]
FIG. 12 is a table showing the state of each switch when the burst length BL is 1, 2, and 4, respectively. First, when the burst length BL is 4, each data on the data bus lines d0-d3 is directly transmitted to the data bus lines d0′-d3 ′. That is, in this case, the switches sw1n, sw2n, and sw3n are on and the switches sw24, sw14, sw13, and sw12 are off regardless of the values of the column address signals caa0z and caa1z.
[0089]
Next, when the burst length BL is 2, the data transmitted to the data bus lines d0 ′ and d1 ′ is output to the outside. Therefore, in this case, the data set of the data bus lines d0 and d1 is transmitted to the data bus lines d0 ′ and d1 ′, or the data set of the data bus lines d2 and d3 is transmitted to the data bus lines d0 ′ and d1 ′. Which data set is transmitted is determined by the logical value of the column address signal caa0z. That is, when the data set of the data bus lines d0 and d1 is transmitted to the data bus lines d0 ′ and d1 ′, the column address signal caa0z is set to the L level. Then, the switches sw1n, sw2n, and sw3n are turned on, and the switches sw24, sw14, sw13, and sw12 are turned off. On the other hand, when the data set of the data bus lines d2 and d3 is transmitted to the data bus lines d0 ′ and d1 ′, the column address signal caa0z is set to the H level. Then, the switches sw3n, sw24, and sw13 are turned on, and the switches sw1n, sw2n, sw14n, and sw12 are turned off. As a result, data on the data bus line d2 is transmitted to the data bus line d0 ′ via the switch sw13, and data on d3 is transmitted to d1 via the switch sw24. When the burst length BL is 2, the logical value of the column address signal caa1z of another bit is not used for switch selection.
[0090]
On the other hand, when the burst length BL is 1, one of the data on the data bus lines d0, d1, d2, and d3 is selected, and the selected data bit is transmitted to the data bus line d0 ′, and this data is Output to the outside. This data selection is performed based on a combination of logical values of the column address signals caa0z and caa1z. That is, when selecting data on the data bus line d0, both caa0z and caa1z are set to L level. Then, the switches sw1n, sw2n, and sw3n are turned on, and the switches sw24, sw14, sw13, and sw12 are turned off. In this case, the data on the data bus line d0 is transmitted to the data bus line d0 ′. When selecting data on the data bus line d1, caa0z is set to H level and caa1z is set to L level. Then, the switches sw2n, sw3n, and sw12 are turned on, and the switches sw1n, sw24, and sw13 are turned off. In this case, the data on the data bus line d1 is transmitted to the data bus line d0 ′ via the switch sw12. Further, when selecting data on the data bus lines d2 and d3, the switches are turned on / off based on the logic table of FIG.
[0091]
The parallel data d0′-d3 ′ output from the data bus switch 440 is transmitted to the first register 450 and further to the second register 460.
The first register 450 includes four delayed flip-flops DFF401-404, and the data fetch timing of each DFF is controlled by the first control signal po0z. Similarly, the second register 460 includes four delayed flip-flops DFF405-408, and the data fetch timing and latch timing of each DFF are controlled by the second control signal po1z.
[0092]
FIG. 13 shows the operation timing of the first and second registers 450 and 460. In the figure, d [0, 2] corresponds to data on the data bus lines d0 ′ and d2 ′, and d [1, 3] corresponds to data on the data bus lines d1 ′ and d3 ′.
At time t1 in FIG. 13, parallel data appears on the data bus lines d0′-d3 ′. Next, when the first control signal po0z changes from H to L at time t2, the four delayed flip-flops 401-404 constituting the first register 450 latch the data on the data bus lines d0′-d3 ′, respectively. To do. Next, when the second control signal changes from L to H at time t3, the four delayed flip-flops 405 to 408 constituting the second register 460 are latched in the corresponding delayed flip-flops 401 to 404, respectively. Capture data. At time t4, when the second control signal changes from H to L, the four delayed flip-flops 405 to 408 latch the fetched data. After that, when the first control signal changes from L to H, the four delayed flip-flops 401-404 are again in a state of accepting data on the data bus lines d0′-d3 ′. Through the above operation, parallel data on the data bus lines d0′-d3 ′ is sequentially transferred to the first register 450 and the second register 460.
[0093]
The data latched in the second register 460 is then transmitted to the 4-bit → 2-bit conversion circuit 470. Here, 4-bit parallel data is converted into 2-bit parallel data. The 4-bit → 2-bit conversion circuit 470 includes a delayed flip-flop DFF 409-411 and output buffer circuits 420-423. Further, four control clock signals psc1k0z-psc1k3z are supplied to the 4-bit → 2-bit conversion circuit 470, and these control clocks output the output timing of the output buffer circuits 420-423 and the delayed flip-flops DFF409-411. The data latch timing is controlled. Further, the output line of the output buffer circuit 420 and the output line of 422 are commonly connected to the node dd0. This is a wired OR connection. When data is output from the output buffer circuit 420, the output terminal of the output buffer circuit 422 is in a high impedance state. Conversely, when data is output from the output buffer circuit 422, the output terminal of the output buffer circuit 420 is output. Is in a high impedance state. Next, 2-bit data is output from the 4-bit → 2-bit conversion circuit 470 to the nodes dd0 and dd1, and is transmitted to the data output timing switch 480. The data output timing switch 480 includes two switches swdd0 and swdd1, and the ON / OFF is controlled by output control clock signals outp0z and outp1z, respectively. The data output timing switch 480 first transfers one data bit appearing at the node dd0 to the latch & level shifter circuit 430 by closing one switch swdd0 (on), and then closes the other switch swdd1 to set the node dd1. Is transmitted to the latch & level shifter circuit 430. By such an operation, the data output timing switch 480 sequentially transmits the 2-bit data appearing at the nodes dd0 and dd1 to the next latch & level shifter circuit 430 bit by bit. The latch & level shifter circuit 430 latches the input data, converts the level of the input data, and transmits it to the data output buffer 19 in FIG.
[0094]
FIG. 14 shows the operation timing from the 4-bit → 2-bit conversion circuit 470 to the latch & level shifter circuit 430 when the burst length BL is 4. Hereinafter, the operation of these circuits will be described in more detail with reference to FIG.
First, as an initial state, read data is latched in the four DFFs 405 to 408 constituting the second register 460.
[0095]
Then, the four control clock signals psc1k0z-psc1k3z for controlling the operation of the 4-bit → 2-bit conversion circuit 470 sequentially output H pulses in the order of psc1k1z → psc1k2z → psc1k3z → psc1k0z, as shown in FIG. First, when psc1k1z becomes H, the output buffer circuit 420 outputs the data received from the DFF 405 to the node dd0 in response thereto, and at the same time, the DFF 409 latches the data output from the DFF 406. Next, when psc1k2 becomes H, the output buffer circuit 421 responds by outputting the data received from the DFF 409 to the node dd1, and at the same time, the DFF 410 latches the data output from the DFF 407. Such operations are repeated, and new read data are alternately output from the 4-bit → 2-bit conversion circuit 470 to the nodes dd0 and dd1, as can be seen from the waveforms at the nodes dd0 and dd1 in FIG.
[0096]
The DFF 409-411 in the 4-bit → 2-bit conversion circuit 470 allows the next read data set to be latched in the second register 460 during the conversion operation of the 4-bit → 2-bit conversion circuit 470. It is provided to enable data to be output from the data output terminal DQ without any gap.
The two output control clock signals outp0z and outp1z that control the operation of the data output timing switch 480 also alternately output H pulses at the timing shown in FIG. When new data appears at the node dd0, outp0z becomes H after a predetermined time and the switch swdd0 is turned on, whereby the data at the node dd0 is transferred to the latch & level shifter circuit 430. Next, when new data appears at the node dd1, outp1z becomes H after a predetermined time and the switch swdd1 is turned on, whereby the data at the node dd1 is transferred to the latch & level shifter circuit 430. By repeating such an operation, the data of the nodes dd0 and dd1 are alternately and sequentially sent to the latch & level shifter circuit 430, and 2-bit → 1-bit conversion can be performed.
[0097]
The above description of the operation is for the case where the burst length BL is 4. The tables of FIGS. 15A and 15B show the operation states of the four control clock signals psc1k0z-psc1k3z and the two output control clock signals outp0z and outp1z when the burst length is 1, 2, and 4.
When the burst length BL is 4, as described above, the four control clock signals psc1k0z-psc1k3z and the two output control clock signals outp0z and outp1z all perform a clocking operation, and the four DFFs 405 of the second register 460 are used. Convert 4-bit parallel data output from -408 into serial data.
[0098]
On the other hand, when the burst length BL is 2, two control clock signals psc1k1z and psc1k2z and two output control clock signals outp0z and outp1z among the four control clock signals perform a clocking operation. When the burst length BL is 2, as described above, read data is sent only to the nodes d0 ′ and d1 ′, and no read data is sent to the nodes d2 ′ and d3 ′. Therefore, only the control clock signal and the output control clock signal necessary for outputting the read data appearing at the nodes d0 'and d1' to the outside perform the clocking operation.
[0099]
When the burst length BL is 1, only one control clock signal psc1k1z of the four control clock signals and only one outp0z of the two output control clock signals perform the clocking operation. When the burst length BL is 1, as described above, read data is sent only to the node d0 ′, and no read data is sent to the nodes d1 ′ to d3 ′. Therefore, only the control clock signal and the output control clock signal necessary for outputting the read data appearing at the node d0 ′ to the outside perform the clocking operation.
[0100]
In the above embodiment, the 4-bit data output from the second register 460 is first converted into 2-bit data by the 4-bit → 2-bit conversion circuit 470, and then the 2-bit data is converted into the data output timing switch 480 and the latch & level shifter 430. Is converted to 1 bit. That is, parallel / serial conversion is performed in two stages.
[0101]
On the other hand, in the above embodiment, the outputs of the four output buffer circuits 420 to 423 in the 4-bit → 2-bit conversion circuit 470 may be commonly wired-ORed, and the data output timing switch 480 may be constituted by one switch. . In this case, the data output timing switch 480 has only one switch, and the configuration is simplified.
[0102]
On the other hand, when the frequency of the clock signal is increased for high-speed operation, it becomes difficult to generate one output control clock signal outp # z for one switch swdd corresponding to the higher frequency. In such a case, the data output timing switch 480 is composed of two switches as shown in FIG. 11, and these switches are two output control clock signals outp0z having a frequency about half that of the one output control clock signal. , Outp1z may be controlled.
[0103]
FIG. 16A is a configuration example of the delayed flip-flop DDF in FIG. FIG. 16B is a timing chart showing the operation of FIG. 16A.
The delayed flip-flop DFF includes a transfer gate 509 including a PMOS 501 and an NMOS 502, inverters 507 and 508, and a clocked inverter 510 including PMOSs 503 and 504 and NMOSs 505 and 506.
[0104]
When the clock signal clkz corresponding to the control signals po0z, po1z, psc1k0z-psc1k3z in FIG. 11 is H, the input data in is taken into the DFF by turning on the transfer gate 509, while the clocked inverter 510 is Off state. Next, when the clock signal clkz becomes L, the transfer gate 509 is turned off, and the input data in is disconnected from the DFF. At the same time, the clocked inverter 510 is activated, and the inverter 508 and the clocked inverter 510 constitute a latch circuit, and latches the data taken in by the DFF when the clock signal clkz becomes L.
[0105]
FIG. 17A is a configuration example of the output buffers 420-423 in FIG. FIG. 17B is a timing chart showing the operation of FIG. 17A.
The output buffer circuit includes inverters 511 and 512, a NAND circuit 515, a NOR circuit 516, a buffer circuit 519 composed of a PMOS 517 and an NMOS 518, and a latch circuit 520 composed of inverters 513 and 514.
[0106]
When the clock signal clkz corresponding to the control signals psc1k0z-psc1k3z in FIG. 11 becomes H, since the NAND circuit 515 and the NOR circuit 516 function as inverters, output data in phase with the input data appears at the output node out, and this output Data is held in the latch circuit 520. On the other hand, when the clock signal clkz becomes L, both the PMOS 517 and the NMOS 518 are turned off, and the output node is in a high impedance state.
[0107]
FIG. 18 shows a configuration example of the latch & level shifter circuit 403 in FIG. However, a portion 525 composed of the PMOS 547 and the NMOS 548 corresponds to the data output buffer 19.
The latch & level shifter circuit 403 includes a level shift circuit 521 with a latch composed of PMOSs 531 and 532, NMOSs 533 and 534, inverters 543 and 544, a level shift circuit 522 having the same configuration, and an inverter composed of PMOS 535 and NMOS 536. 523 and an inverter 524 composed of a PMOS 541 and an NMOS 542. In the figure, Vccq and Vssq are power lines independent of the power lines Vii and Vss of the internal circuit, and a potential different from, for example, Vii is supplied to Vccq.
[0108]
The output lines dd0 ′ and dd1 ′ (see FIG. 11) of the data output timing switch 480 are commonly connected to the gates of the PMOSs 533 and 539, respectively. For example, when data is supplied from the output line dd0 ′, if the data on the output line dd0 ′ is H, H data is output to the data output terminal DQ, and if the data on the output line dd0 ′ is L, L data is output to the data output terminal DQ.
[0109]
As another modification, the level shift circuit 522 and the inverter 524 may be omitted, and instead, the output of the inverter 523 may be connected to the gates of the PMOS 547 and the NMOS 548 in common. However, when it is necessary to control the data output terminal DQ to the high impedance state, the configuration as shown in FIG. 18 is more suitable.
[0110]
Further, in place of connecting the gate of the NMOS 539 to the output lines dd0 ′ and dd1 ′, another set of switches swdd00 further controlled by the output control clock signals outp0z and outp1z, respectively, in addition to the data output timing switch 480 in FIG. And swdd11 may be provided, and the gate of the NMOS 539 may be connected to the node dd0 via the switch swdd00 and the node dd1 via the switch swdd11.
[0111]
Next, an FCRAM according to another embodiment of the present invention will be described with reference to FIGS.
The embodiment described with reference to FIG. 4 has a burst length of 4 or 8. In contrast, the embodiment shown in FIGS. 19 and 20 is a memory having a burst length of 16 or more. In FIG. 19, the same reference numerals are given to the same components as those shown in the above-mentioned drawings.
[0112]
In the FCRAM shown in FIG. 4, the bank 0 circuit 7 and the bank 1 circuit 8 are automatically activated by one read command and can output 8-bit burst data. On the other hand, in the FCRAM shown in FIG. 19, the bank 0 circuit 7 and the bank 1 circuit 8 are alternately and repeatedly selected to output 16-bit burst data. That is, the bank 0 circuit 7 and the bank 1 circuit 8 are activated in the following order. (1) Bank 0 circuit 7 → (2) Bank 1 circuit 8 → (3) Bank 0 circuit 7 → (4) Bank 1 circuit In this order, the bank 0 circuit 7 is supplied with different addresses in (1) and (3), and the bank 1 circuit 8 is supplied with different addresses in (2) and (4). For this purpose, an address counter 90 is provided in the bank 0 circuit 7 as shown in FIG. Similarly, the bank 1 circuit 8 is provided with the same address counter (not shown) as the address counter 90. The address counter 90 receives an address signal from the address buffer 3 and counts up one predetermined bit of the row address in response to the bank 0 RAS signal bras0z generated internally by the internal interleave generation circuit 6 shown in FIG.
[0113]
As shown in FIG. 20, the address A0 is taken together with the read command RD0 (A), and the bank 0 and the bank 1 are continuously connected to the address A0 by the RAS signals bras0z and bras1z generated by the internal interleave generation circuit 6. Activated. The address counter 90 increments the address A0 by 1 when a predetermined time has elapsed since the generation of the RAS signal bras0z for the bank 0. As a result, an address A1 is generated and output to the predecoder 11. Addresses A0 and A1 select different word lines. The RAS signal bras0z is once deactivated, and the precharge is performed before the read operation of the address A1 is performed by the timing controller 10 shown in FIG.
[0114]
The same operation as that related to bank 0 described above is performed in bank 1. That is, the address counter 90 of the bank 1 circuit 8 increments the address A0 by 1 when a predetermined time elapses after the generation of the RAS signal bras1z for the bank 1. As a result, the address A1 is generated and output to the predecoder 11 of the bank 1 circuit 8. The RAS signal bras1z is once deactivated, and the precharge is performed before the timing controller 10 of the bank 1 circuit 8 performs the read operation of the address A1.
[0115]
Therefore, as shown in FIG. 20, two 4-bit serial data are successively read from bank 0 and bank 1 by address A0, and two 4-bit serial data are successively read by address A1. Respectively. In this way, 16-bit burst data can be read from the data output terminal DQ in response to one read command RD0 (A).
[0116]
The above operation is repeated every time a read command is received.
When the burst length is 32, the address counter 90 provided in each bank performs a count-up operation three times in response to one read command. Thus, every time a read command is received, 32-bit burst data can be read from the data output terminal DQ.
[0117]
In the FCRAM described above, the basic burst length is 4 or 8. When the burst length is 4, parallel data is simply read from one bank. When the burst length is 8, a bank interleave operation is performed. When the burst length exceeds 8, a bank interleave operation and an address count up operation are performed.
[0118]
The present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be modified and changed within the scope of the claims.
[0119]
【The invention's effect】
The conventional FCRAM can select only a single memory cell block by inputting a read command once. Therefore, in this configuration, the number of bits of parallel data read from each sense amplifier is limited, and the maximum burst length that can be set depends on the number of bits.
[0120]
On the other hand, according to the semiconductor memory device of the present invention, a plurality of memory cell blocks can be selectively activated by inputting a read command once. Therefore, the memory cell block can be selected according to the burst length. Specifically, for example, when the burst length is BL = 32, in the semiconductor memory device of the present invention, eight memory cell blocks are selectively activated by inputting a single read command, and 32-bit data is sequentially activated. Can be read out.
[0121]
Further, in the conventional FCRAM, for example, when the burst length is BL = 4, when a read command is input, 4-bit serial data is read. Therefore, in the conventional FCRAM, when this data read operation is executed twice (that is, when the read command is input twice), continuous 8-bit serial data is read, but the cycle time required for the data read processing is reduced. Is twice that when reading 4-bit serial data.
[0122]
In contrast, according to the semiconductor memory device of the present invention, when the burst length is BL = 8, when a read command is input once, two memory cell blocks are automatically selectively activated. Continuous 8-bit serial data is read at a time. At this time, for example, by doubling the clock frequency or by using DDR (Double Data Rate), the cycle time required for the data reading process is read out with 4-bit serial data at the burst length BL = 4. It can be the same as when. That is, the transfer rate of the semiconductor memory device of the present invention can be doubled that of the conventional FCRAM.
[0123]
As described above, according to the present invention, a plurality of memory cell blocks can be selectively activated by automatically performing the bank interleaving operation internally, and the reading speed of data stored in the memory block can be selectively increased. It is possible to provide a semiconductor memory device capable of realizing higher speed.
[Brief description of the drawings]
FIG. 1 is an example of a circuit configuration around a memory cell of an SDRAM.
FIG. 2 is a timing chart showing a data read operation of a conventional SDRAM.
FIG. 3 is a timing chart showing a data read operation of a conventional FCRAM.
FIG. 4 is a diagram showing an embodiment of a semiconductor memory device of the present invention.
FIG. 5 is a sequence diagram of a RAS generation unit and an internal interleave generation circuit.
FIG. 6 is a circuit example of a clock counter.
FIG. 7 is a circuit example of a RAS generation unit and an internal interleave circuit.
FIG. 8 is a timing chart (when burst length BL = 4) showing a data read operation of the semiconductor memory device of the present invention.
FIG. 9 is a timing chart (when burst length BL = 8) showing a data read operation of the semiconductor memory device of the present invention.
FIG. 10 shows a method for setting a burst length BL.
FIG. 11 is a configuration example of a parallel-serial conversion circuit.
12 is a diagram showing the state of each switch shown in FIG. 11 when the burst length is 1, 2, and 4, respectively.
13 is a timing chart showing operation timings of the first and second registers shown in FIG. 11. FIG.
FIG. 14 is a timing chart showing operation timing from a 4-bit → 2-bit conversion circuit to a latch & level shifter circuit when the burst length is 4.
FIG. 15 is a diagram illustrating operation states of four control clock signals and two output control clock signals when the burst length is 1, 2, and 4;
16 is a diagram showing a configuration example of the delayed flip-flop DFF shown in FIG. 11 and its operation.
17 is a diagram showing a configuration example of the output buffer shown in FIG. 11 and its operation.
18 is a circuit diagram showing a configuration example of a latch & level shifter circuit shown in FIG. 11. FIG.
FIG. 19 shows a semiconductor memory device according to another embodiment of the present invention.
20 is a timing chart showing an operation of the semiconductor memory device shown in FIG. 19. FIG.
[Explanation of symbols]
1 clock buffer
2 Command decoder
3 Address buffer
4 Mode register
5 Clock counter
6 Internal interleave generation circuit
7 Bank 0 circuit
8 Bank 1 circuit
9 RAS generation unit
10 Timing controller
11 Predecoder
12a, 12b, 12c, 12d block
13 Row decoder
14 memory cells
15 sense amplifier
16 sense buffers
17 DQ controller
18a, 18b Parasiri conversion circuit
19 Data output buffer
21 Bank-specific row activation command generator
22 Bank RAS generation unit
23 Command generator
24 Address generator
31, 32, 33, 34 DFF
35 Pulse generation circuit
90 address counter

Claims (7)

In a semiconductor memory device including a plurality of banks having at least one memory cell block,
Block activation that selects and activates a single memory cell block when the burst length is less than or equal to a predetermined value, and activates one of the memory cell blocks in a plurality of banks according to the burst length when the burst length is longer than a predetermined value Circuit,
An address decoder that selects a specific bank based on an external address signal;
Have
In the data read operation, the block activation circuit
If the burst length is less than or equal to a predetermined value, select a single memory cell block,
A semiconductor memory device, wherein when a burst length is longer than a predetermined value, a plurality of banks are alternately and continuously selected, and one of the memory cell blocks is selected in the selected bank . The cycle time required for data read processing when one of the memory cell blocks is activated in the plurality of banks is the same as when the single memory cell block is selected. The semiconductor memory device according to Item 1.   2. The semiconductor memory device according to claim 1, wherein the predetermined value of the burst length is a number of bits of parallel data read from a selectively activated memory block. A parallel / serial conversion circuit for converting parallel data into serial data;
The parallel / serial conversion circuit sequentially fetches a plurality of bits of parallel data output from the plurality of memory cell blocks, outputs serial data based on the burst length information, and the burst length is longer than a predetermined value. 2. The semiconductor memory device according to claim 1, wherein said parallel / serial conversion circuit increases a serial data transmission rate in accordance with a burst length at that time. The semiconductor memory device further includes an address counter,
When the set burst length is longer than the second predetermined value which is longer than the predetermined value, the first address signal supplied from the outside and the second address signal generated by the address counter based on the first address signal are generated. 2. The semiconductor memory device according to claim 1, wherein a plurality of memory cell blocks are repeatedly activated based on a burst length.   6. The semiconductor memory device according to claim 5, wherein the first address signal and the second address signal select different word lines.   3. The semiconductor memory device according to claim 1, further comprising a burst length information generation circuit that generates burst length information based on the set burst length.

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