JP4195825B2 - Method for determining both process parameter or design rule and process parameter, method for manufacturing semiconductor integrated circuit device, system for determining both process parameter or design rule and process parameter, and program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for determining both process parameters or design rules and process parameters, a method for manufacturing a semiconductor integrated circuit device, a system for determining both process parameters or design rules and process parameters, and a program.
[0002]
[Prior art]
Recent progress in semiconductor manufacturing technology is very remarkable, and semiconductors with a minimum processing dimension of 0.18 μm are mass-produced. Such miniaturization is realized by dramatic progress in fine pattern formation techniques such as a mask process technique, an optical lithography technique, and an etching technique. When the pattern size is large enough, the planar shape of the LSI pattern to be formed on the wafer is directly drawn as a design pattern, a mask pattern that is faithful to the design pattern is created, and the mask pattern is transferred onto the wafer by the projection optical system. Then, by etching the base, a pattern almost as designed can be formed on the wafer. However, as the pattern becomes finer, it has become difficult to faithfully form the pattern in each process, and a problem has arisen that the final finished dimension does not match the design pattern. In order to solve such a problem, a means for creating a mask pattern different from the design pattern so as to make the final finished dimension equal to the design pattern dimension in consideration of the conversion difference in each process (hereinafter referred to as mask data processing). ) Has become very important.
[0003]
For mask data processing, in addition to MDP (Mask Data Processing) processing that changes a mask pattern using a graphic operation processing, a design rule checker (hereinafter simply referred to as DRC), etc., in recent years, There is OPC (Optical Proximity Correction) processing to correct the optical proximity effect (OPE), etc., and by performing these processing, the mask pattern is appropriately corrected so that the final finished size becomes a desired size. To do. However, in a device such as a logic device that requires a further TAT (Turn Around Time), an increase in processing time required for mask data processing directly increases TAT. On the other hand, if the design rules (hereinafter simply referred to as “DR”) are relaxed in order to reduce the mask data processing load and create a device, the chip size may increase accordingly, leading to a decrease in competitiveness. There is.
[0004]
D. can achieve both TAT improvement and chip size reduction. R. A method for determining the mask data processing load is proposed in Japanese Patent Application No. 2000-199839. The method proposed in Japanese Patent Application No. 2000-199839 is a D.C. R. Based on the above, the design assets of the previous generation are compacted to obtain the design layout that is expected to be used in the next generation, mask data processing and lithography simulation are performed using the design layout, and the evaluation result is D . R. It is a method of feeding back to. In this method, not only the basic pattern of a device as in the prior art but also a layout close to the layout used in an actual device is used. R. Therefore, it is possible to determine in advance the problems that may actually occur. R. Can be presented. However, D. C. presented in this way. R. Even if a design layout is created in this way, the chip size is not necessarily minimized. This is because D.C. corresponding to the pattern in question. R. If the pattern is loosened, the pattern other than that pattern is not problematic. R. As a result, the chip area is unnecessarily increased. Therefore, for example, D.I. R. So that only problem areas can be extracted. R. It is also possible to set this.
[0005]
[Problems to be solved by the invention]
However, individual D.P. R. It is impossible to assign D. R. The complexity of the designer increases the load for the designer to create the design layout. R. C. Difficulties such as complicated verification by the system also occur.
[0006]
D. R. When it becomes difficult to express all the pattern types, there is a possibility that a pattern (hereinafter referred to as a dangerous pattern) that cannot be formed on the wafer with a given predetermined specification may occur in at least some pattern types. In addition, as described above, D.I. R. Is closely related to the chip area. R. If the numerical value is set loosely, the chip area increases. Therefore, the number and type of dangerous patterns, chip area, and D.I. R. By finding the interrelationship of R. It becomes important to set. Furthermore, the number of dangerous patterns and the chip area are as follows. R. It varies not only with settings but also with process parameters. For example, certain D.I. R. Even if the exposure wavelength (λ), lens numerical aperture (NA), illumination shape (σ, ε), mask phase / transmittance, overlay error with other layers, etc. change The number and chip area vary.
[0007]
The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the chip area as much as possible. R. And a method and system for optimally determining at least one of process parameters, and a method of manufacturing a semiconductor integrated circuit device using the method.
[0008]
[Means for Solving the Problems]
The present invention aims to solve the above problems by the following means.
[0009]
That is, according to the present invention,
A system for determining a process parameter for forming a circuit layout of a semiconductor integrated circuit device on a wafer, or both a design rule used when designing the circuit layout and the process parameter, and means for compaction The process parameters using a system comprising chip size information acquisition means, finished shape information acquisition means, comparison means, danger pattern information acquisition means, evaluation means, change means, and definition means, or a method of determining both the said process parameters and the design rule,
A procedure for obtaining a compacted layout by compressing a design layout of a semiconductor integrated circuit device by the compaction means based on prescribed design rule information;
A procedure for obtaining chip size information of the semiconductor integrated circuit device corresponding to the compacted layout by the chip size information obtaining means;
Using the specified process parameters, the procedure for obtaining information on the finished shape on the wafer corresponding to the compacted layout by the finished shape information acquiring means, and the obtained finished shape and the compacted layout A procedure for comparison by a comparison means to obtain a comparison result;
A procedure for extracting a danger pattern that is a pattern in which a predetermined margin cannot be secured from the compacted layout based on the comparison result by the danger pattern information acquisition means, and obtaining danger pattern information that is information related to the danger pattern;
A procedure for determining by the evaluation means whether or not the chip size information and the danger pattern information satisfy respective evaluation conditions;
When at least one of the chip size information and the danger pattern information is determined not to satisfy the evaluation condition, a procedure for changing a process parameter by the changing unit;
When the process parameter is changed, the changed process parameter is defined by the defining means as a new process parameter in the procedure for obtaining the finished shape information, and when the design rule is changed, the changed design rule is changed. A procedure for defining by the defining means as a new design rule in the procedure for obtaining the compacted layout,
A method comprising:
[0010]
In addition, according to the present invention, there is provided a semiconductor integrated circuit comprising the step of transferring a circuit layout of a semiconductor integrated circuit device designed by using the above-described method for determining a process parameter or both a design rule and a process parameter to a wafer. A method of manufacturing a circuit device is provided.
[0011]
Moreover, according to the present invention,
The process parameters for forming the circuit layout of a semiconductor integrated circuit device on a wafer, or, in a system for determining both the design rules used in designing the circuit layout and the process parameters,
Compaction means for obtaining a compacted layout by compressing the design layout of the semiconductor integrated circuit device based on a prescribed design rule;
Chip size information acquisition means for acquiring chip size information of the semiconductor integrated circuit device corresponding to the compacted layout;
Finished shape information acquisition means for obtaining information on the finished shape on the wafer corresponding to the compacted layout using the specified process parameters;
A comparison means for comparing the obtained finished shape with the compacted layout;
Danger pattern information acquisition means for extracting a danger pattern that is a pattern in which a predetermined margin cannot be secured from the compacted layout based on a comparison result by the comparison means, and obtaining danger pattern information that is information related to the danger pattern;
Evaluation means for determining whether the chip size information and the danger pattern information satisfy respective evaluation conditions;
Change means for changing a process parameter when the evaluation means determines that at least one of the chip size information and the danger pattern information does not satisfy the evaluation condition;
When the process parameter is changed, the changed process parameter is defined as a new process parameter to be input to the finished shape information acquisition unit, and when the design rule is changed, the changed design rule is stored in the compaction. There is provided a system comprising defining means for defining as a new design rule to be input to the means.
Furthermore, according to the present invention,
Program for causing a computer to execute a method for determining a process parameter for forming a circuit layout of a semiconductor integrated circuit device on a wafer, or a design rule used when designing the circuit layout and the process parameter in the method,
A procedure for obtaining a compacted layout by compressing the design layout of the semiconductor integrated circuit device based on the prescribed design rule information;
A procedure for obtaining chip size information of a semiconductor integrated circuit device corresponding to the compacted layout;
Using the specified process parameters, a procedure for obtaining information on the finished shape on the wafer corresponding to the compacted layout;
A procedure for obtaining a comparison result by comparing the obtained finished shape and the compacted layout;
A procedure for extracting a danger pattern that is a pattern in which a predetermined margin cannot be secured from the compacted layout based on the comparison result, and obtaining danger pattern information that is information on the danger pattern;
A procedure for determining whether the chip size information and the danger pattern information satisfy respective evaluation conditions;
A procedure for changing a process parameter when it is determined that at least one of the chip size information and the danger pattern information does not satisfy the evaluation condition;
When the process parameter is changed, the changed process parameter is defined as a new process parameter in the procedure for obtaining the finished shape information, and when the design rule is changed, the changed design rule is changed to the covered parameter. There is provided a program comprising a procedure for defining a new design rule in a procedure for obtaining a compaction layout.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
First, the concept which is the premise of the present invention will be described with reference to FIG. (A) of FIG. R. The relationship between the chip area and the number of dangerous patterns with respect to the severity of numerical values shown in FIG. The horizontal axis is D.D. R. This represents the severity of the numerical value of D. R. Is so loose that it reaches the left side of the page. R. Becomes tough. The vertical axis represents the chip area (upper axis) and the number of dangerous patterns (lower axis). For example, D.D. R. When the numerical value is set loosely, the chip size increases, but the number of dangerous patterns can be reduced. On the other hand, as in the area AR2, D.D. R. If the numerical value of is strictly set, the chip size can be reduced, but the number of dangerous patterns increases.
[0013]
As for the chip size and the number of dangerous patterns, predetermined conditions are set according to the required specifications of each device. With regard to the relationship shown in FIG. 1 (a), when the chip size is set to A or less and the number of dangerous patterns is set to B or less, the size of D from the critical lines CLa1 and CLb1 in FIG. . R. You can give a guide as to whether or not to set. By calculating such a relationship using an actual pattern, a mask data processing tool, and a lithography simulation tool, the D.D. R. Can be set appropriately.
[0014]
On the other hand, in FIG. R. The type is constant, and the relationship is shown only when the numerical value becomes stricter or looser. Here, D.I. R. Assuming that the number of types increases, for example, the schematic diagram of FIG. 1B is obtained. As shown in the figure, the slopes of the critical lines CLa2 and CLb2 are D.D. R. It can be seen that as the number of types increases, the lines change like critical lines CLa3 and CLb3, respectively. That is, D.D. R. Increasing the number of R. The same effect can be found as there is less and the numerical value is tightened.
[0015]
This relationship diagram is created by using an actual device pattern, a mask data processing tool, and a lithography simulation tool. R. It was found that setting is possible.
[0016]
Hereinafter, some embodiments of the present invention will be described with reference to the drawings. In the first embodiment, a system (hereinafter referred to as a design rule determination system) and a method (hereinafter referred to as a design rule determination method as appropriate) and a method for determining only a design rule among design rules and process parameters will be described. In the second embodiment, a system (hereinafter referred to as a design rule / process parameter determination system) and a method (hereinafter referred to as a design rule / process parameter determination method as appropriate) for determining at least one of a design rule and a process parameter. explain.
[0017]
(1) First Embodiment FIG. 2 is a block diagram showing a schematic configuration of a design rule determination system according to this embodiment. The design rule determination system 1 shown in the figure includes a compaction tool 8, a design layout data input unit 32, R. Table input unit 34, chip size calculation unit 10, process parameter input unit 36, mask data processing unit 12, shape prediction simulator 14, comparison / evaluation unit 16, risk pattern extraction unit 18, evaluation condition input Part 38, chip size and danger pattern evaluation part 20, R. And a change unit 22.
[0018]
The design layout data input unit 32 is a D.D. of the semiconductor integrated circuit device to be manufactured. R. The existing design layout data (D.R. creation design layout data) for creating the data is input to the compaction tool 8. D. R. The table input unit 34 is a D.D. R. The table is input to the compaction tool 8.
[0019]
The compaction tool 8 receives the input D.D. R. D. Based on the table. R. The creation design layout data is compacted, and layout data assumed in the next generation (hereinafter referred to as compacted layout data) is output to the chip size calculation unit 10 and the comparison / evaluation unit 16.
[0020]
The chip size calculation unit 10 calculates values affecting the chip size (hereinafter referred to as chip size influence value) such as the area of the compacted layout and the shrinkage ratio from the compacted layout data, and the compacted layout data is mask data as it is. This is supplied to the processing unit 12 and the calculated chip size influence value is supplied to the chip size and danger pattern evaluation unit 20 described later.
[0021]
The process parameter input unit 36 inputs process parameters, which are process conditions for manufacturing a target semiconductor integrated circuit device, to the mask data processing unit 12 and the shape prediction simulator 14. These process parameters include parameters such as exposure wavelength, exposure device lens numerical aperture (NA), exposure device illumination shape (σ, ε), mask phase / transmittance, and development / resist process. It is. The mask data processing unit 12 executes mask data processing on the compacted layout data with given process parameters, creates mask pattern data, and supplies the mask pattern data to the shape prediction simulator 14. Mask data processing includes OPC processing for light, proximity effect correction processing for electron beam, and MDP processing.
[0022]
Based on the supplied mask pattern data, the shape prediction simulator 14 executes a lithography simulation with the input process parameters, calculates a planar finished shape on the wafer, and supplies it to the comparison / evaluation unit 16. As the planar finished shape, a mask shape experimentally obtained in an actual process, a resist shape on the wafer, or a shape after processing on the wafer may be used. In this case, it is not necessary to use the shape prediction simulator 14. This also applies to a second embodiment described later.
[0023]
The comparison / evaluation unit 16 compares the finished shape with the compacted layout data, and calculates the difference (error amount) for each edge of each pattern in the design layout. The data is different depending on the magnitude of the difference and the location where the difference occurs, and the data is monitored.
[0024]
Based on the comparison result of the comparison / evaluation unit 16, the dangerous pattern extraction unit 18 extracts the types and number of dangerous patterns for which a predetermined margin cannot be secured on the wafer from the monitored data in this embodiment, and will be described below. The chip size and danger pattern evaluation unit 20 is supplied. When extracting the dangerous pattern, the exposure amount, exposure focus, average finished size and variation of the mask, aberration, overlay error with other layers, and the like are changed to satisfy more actual process conditions.
[0025]
The evaluation condition input unit 38 inputs to the chip size and risk pattern evaluation unit 20 evaluation conditions given in advance for each of the types or number of such risk patterns and the chip size influence value.
[0026]
The dangerous pattern evaluation unit 20 compares the evaluation condition with the chip size and the number of dangerous patterns, and if the comparison result shows that both the chip size and the number of dangerous patterns satisfy the evaluation condition, the set D.D. R. D. which is optimal for a semiconductor integrated circuit device targeted for R. Determine as. On the other hand, when at least one of the chip size and the number of dangerous patterns does not satisfy the evaluation condition, the dangerous pattern evaluation unit 20 outputs the comparison result as D.D. R. Output to the changing unit 22. D. R. In response to this comparison result, the changing unit 22 performs D.D. R. Changed to a new D. R. As D. R. This is supplied to the table input unit 34.
[0027]
The design rule determination system 1 shown in FIG. 1 includes a series of D.D. described in a recipe file stored in a memory (not shown). R. According to the determination procedure, the optimal D.P. R. To decide. Hereinafter, this series of procedures will be described with reference to FIG. 3 as a first embodiment (design rule determination method) of a method for determining at least one of a design rule and a process parameter according to the present invention.
[0028]
FIG. 3 is a flowchart showing a schematic procedure of the design rule determination method of the present embodiment.
[0029]
First, D.D. R. D. Based on the table. R. The design layout data for creation is compacted, and the chip size influence value is also calculated (step S1).
[0030]
Next, the compaction layout data is subjected to mask data processing with given process conditions, specifically, process parameters, and mask pattern data is output (step S2). Mask data processing includes OPC processing for light, proximity effect correction processing for electron beam, and MDP processing.
[0031]
Next, based on the obtained mask pattern data, a lithography simulation is executed with the above process parameters to calculate a finished shape on the wafer. (Step S3). As the finished shape, a mask shape experimentally obtained in an actual process, a resist shape on the wafer, or a shape after processing on the wafer may be used. This also applies to a second embodiment described later.
[0032]
Subsequently, the finished shape and the compacted layout data are compared (step S4). More specifically, the difference (error amount) is calculated for each edge of each pattern in the design layout, and is monitored as different data depending on the magnitude and location of the difference. In step S4, the number and types of dangerous patterns for which a predetermined margin cannot be secured are extracted.
[0033]
Further, the evaluation condition given in advance is compared with the chip size and the number of dangerous patterns (step S5).
[0034]
As a result of the comparison, if both the chip size and the number of dangerous patterns satisfy the evaluation condition (step S6), the set D.D. R. The optimal D. R. (Step S7).
[0035]
On the other hand, if at least one of the chip size and the number of dangerous patterns does not satisfy the evaluation condition (step S6), R. (Step S8), and the above-described steps S1 to S6 are repeated until the evaluation conditions are satisfied for both the chip size and the number of dangerous patterns.
[0036]
According to the present embodiment, since the number and type of dangerous patterns and the chip size are monitored by such a procedure, the optimum D.D. R. Can finally be determined.
[0037]
(2) Second Embodiment FIG. 4 is a block diagram showing a schematic configuration of a design rule / process parameter determination system according to this embodiment. As apparent from comparison with FIG. 2, the design rule / process parameter determination system 2 shown in FIG. 4 further includes a process parameter change unit 24 in addition to the configuration of the design rule determination system 1 described above. That is, the feature of this system 2 is that D.I. R. And at least one of the process parameters is changed to obtain an optimal D.P. R. And the optimum process parameters can be determined simultaneously. The design layout data input to the compaction tool 8 from the design layout data input unit 32 is D.D. R. Data for creating only D. R. And process parameter creation data. The chip size and dangerous pattern evaluation unit 20 is set if both the chip size and the number of dangerous patterns satisfy the evaluation condition as a result of comparing the evaluation conditions given in advance with the chip size and the number of dangerous patterns. D. R. And process parameters to optimize D. R. And output as process parameters. On the other hand, when at least one of the chip size and the number of dangerous patterns does not satisfy the evaluation condition, the dangerous pattern evaluation unit 20 determines whether the D.D. R. And whether or not one or both of the process parameters should be changed and the result is R. One of the change unit 22 and the process parameter change unit 24, or D.I. R. The data is output to both the changing unit 22 and the process parameter changing unit 24. When receiving the determination that the process parameter should be changed (see “NG” in FIG. 4), the process parameter changing unit 24 changes the process parameter and supplies it to the process parameter input unit 36 as a new process parameter. The other configuration of the system 2 shown in FIG. 4 is substantially the same as that of the system 1 shown in FIG.
[0038]
Next, for a series of procedures described in a recipe file (not shown) of the design rule / process parameter determination system 2 shown in FIG. 4, a first method of determining at least one of the design rule and the process parameter according to the present invention. A second embodiment (design rule / process parameter determination method) will be described with reference to FIG.
[0039]
FIG. 5 is a flowchart showing a schematic procedure of the design rule / process parameter determination method of the present embodiment. As is clear from the comparison with FIG. 3, the characteristics of the flow shown in FIG. 5 are in steps S11, S13, S17 and S18, and the other steps are simply 10 in the step numbers shown in FIG. Is substantially the same as Therefore, in the following, the procedure of steps S11, S13, S17 and S18 will be mainly described.
[0040]
That is, first, D.D. R. D. Based on the table. R. The process parameter creation design layout data is compacted, and the chip size influence value is also calculated (step S11).
[0041]
Next, the compaction layout data is mask-processed with the given process parameters (step S12), and based on the obtained mask pattern data, a lithography simulation is executed with the process parameters to obtain a finished shape on the wafer. calculate. (Step S13).
[0042]
Subsequently, the finished shape and the compacted layout data are compared to extract the number and type of dangerous patterns (step S14), and then the evaluation conditions given in advance are compared with the chip size and the number of dangerous patterns. (Step S15).
[0043]
As a result of the comparison, if both the chip size and the number of dangerous patterns satisfy the evaluation conditions (step S16), the set D.D. R. And process parameters to optimize D. R. And it determines as a process parameter (step S17).
[0044]
On the other hand, if at least one of the chip size and the number of dangerous patterns does not satisfy the evaluation condition (step S16), R. At least one of the process parameters is changed (step S18), and the above-described steps S11 to S16 are repeated until the evaluation conditions for both the chip size and the number of dangerous patterns are satisfied.
[0045]
According to this embodiment, the optimal D.P. R. As well as D.D. such that both the chip size and the number of dangerous patterns satisfy the evaluation condition. R. And the optimal combination of process parameters can ultimately be determined.
[0046]
(3) Manufacturing Method of Semiconductor Integrated Circuit Device By manufacturing a semiconductor integrated circuit device using the design rule determining method or the design rule / process parameter determining method described above, a semiconductor integrated circuit device having a smaller chip size can be shortened by TAT. It becomes possible to manufacture with.
[0047]
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and can be applied with various modifications within the technical scope thereof. In the embodiment of the design rule determination method described above, when both the chip size and the number of dangerous patterns satisfy the evaluation conditions (step S6 in FIG. 3 and S16 in FIG. 5), the D.D. R. (Or D.R. and process parameters) to optimize D.R. R. (Or optimal D.R. and process parameters), and if at least one of the chip size and the number of dangerous patterns does not satisfy the evaluation condition, the D.R. R. (Or D.R. and process parameters) are changed, and the design layout data compaction procedure (steps S1 and S11) through the comparison procedure (steps S5 and S15) are performed until both the chip size and the number of dangerous patterns satisfy the evaluation conditions. Although repeated, the present invention is not limited to this. For example, if any one of the chip size and the number of dangerous patterns satisfies the evaluation condition, the set D.D. R. (Or D.R. and process parameters) to optimize D.R. R. (Or optimal D.R. and process parameters) and when both the chip size and the number of dangerous patterns do not satisfy the evaluation conditions, the D.C. R. (Or D.R. and process parameters) may be changed, and the compaction procedure or comparison procedure of the design layout data may be repeated until one of these satisfies the evaluation condition. According to such a procedure, even if there is a dangerous part, the D.D. R. When it is not necessary to uniformly loosen, it is possible to eliminate the waste that the chip size becomes larger than necessary.
[0048]
In addition, a series of procedures in the design rule determination method and the design rule / process parameter determination method described in the above-described embodiment is stored in a recording medium such as a flexible disk or a CD-ROM as a program to be executed by the computer, and is read by the computer. It may be executed. Thereby, the method for determining at least one of the design rule and the process parameter according to the present invention can be realized using a general-purpose computer. The recording medium is not limited to a portable medium such as a magnetic disk or an optical disk, but may be a fixed recording medium such as a hard disk device or a memory. The program may be distributed via a communication line (including wireless communication) such as the Internet. Further, the program may be distributed in a state where the program is encrypted, modulated or compressed, and stored in a recording medium via a wired line such as the Internet or a wireless line.
[0049]
【The invention's effect】
As described above in detail, the present invention has the following effects.
[0050]
That is, according to the method for determining at least one of the design rule and the process parameter according to the present invention, the optimum D.D. R. And process parameters can be set.
[0051]
Further, according to the system for determining at least one of the design rule and the process parameter according to the present invention, the optimum D.D. R. And process parameters can be set.
[0052]
Furthermore, according to the method for manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor integrated circuit device having a smaller chip size can be manufactured with a short TAT.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a premise of the present invention.
FIG. 2 is a block diagram showing a schematic configuration of a first embodiment of a system for determining at least one of a design rule and a process parameter according to the present invention.
FIG. 3 is a flowchart showing a schematic procedure of a first embodiment of a method for determining at least one of a design rule and a process parameter according to the present invention.
FIG. 4 is a block diagram showing a schematic configuration of a second embodiment of a system for determining at least one of a design rule and a process parameter according to the present invention.
FIG. 5 is a flowchart showing a schematic procedure of a second embodiment of a method for determining at least one of a design rule and a process parameter according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Design rule determination system 2 Design rule / process parameter determination system 8 Compaction tool 10 Chip size calculation part 12 Mask data management part 14 Shape prediction simulator 16 Comparison / evaluation part 18 Danger pattern extraction part 20 Chip size and risk pattern evaluation part 22 D . R. Change unit 24 Process parameter change unit 32 Design layout data input unit 34 R. Table input unit 38 Evaluation condition input unit

Claims (16)

A system for determining a process parameter for forming a circuit layout of a semiconductor integrated circuit device on a wafer, or both a design rule used when designing the circuit layout and the process parameter, and means for compaction The process parameters using a system comprising chip size information acquisition means, finished shape information acquisition means, comparison means, danger pattern information acquisition means, evaluation means, change means, and definition means, or a method of determining both the said process parameters and the design rule,
A procedure for obtaining a compacted layout by compressing a design layout of a semiconductor integrated circuit device by the compaction means based on prescribed design rule information;
A procedure for obtaining chip size information of the semiconductor integrated circuit device corresponding to the compacted layout by the chip size information obtaining means;
Using the specified process parameters, the procedure for obtaining information on the finished shape on the wafer corresponding to the compacted layout by the finished shape information acquiring means, and the obtained finished shape and the compacted layout A procedure for comparison by a comparison means to obtain a comparison result;
A procedure for extracting a danger pattern that is a pattern in which a predetermined margin cannot be secured from the compacted layout based on the comparison result by the danger pattern information acquisition means, and obtaining danger pattern information that is information related to the danger pattern;
A procedure for determining by the evaluation means whether or not the chip size information and the danger pattern information satisfy respective evaluation conditions;
When at least one of the chip size information and the danger pattern information is determined not to satisfy the evaluation condition, a procedure for changing a process parameter by the changing unit;
When the process parameter is changed, the changed process parameter is defined by the defining means as a new process parameter in the procedure for obtaining the finished shape information, and when the design rule is changed, the changed design rule is changed. A procedure for defining by the defining means as a new design rule in the procedure for obtaining the compacted layout,
A method comprising:   The procedure from the changing step to the determining step by the changing means is repeated until it is determined that both the chip size information and the danger pattern information satisfy the evaluation condition. Method. The shape information acquisition means includes a simulator,
The method according to claim 1, wherein the information on the finished shape is predicted by simulation by the simulator.   The finished shape information is predicted by the simulator using the compaction layout information converted into photolithographic mask data subjected to optical proximity correction or data converted to electron beam lithography data subjected to proximity effect correction. 4. The method of claim 3, wherein:   3. The finished shape is a mask shape obtained by an experiment, a resist shape obtained by an experiment, or a shape obtained by processing on a wafer obtained by an experiment. The method described in 1.   2. The risk pattern information is calculated by varying at least one of an exposure amount, an exposure focus, an average finished size and variation of a mask, an aberration, and an overlay error with another layer. 6. The method according to any one of 5 to 5.   The process parameter is at least one of an exposure wavelength, a numerical aperture (NA) of a lens of the exposure apparatus, an illumination shape (σ, ε) of the exposure apparatus, a mask phase, a mask transmittance, and a development / resist process parameter. 7. A method according to any one of the preceding claims comprising more than one.   A method for manufacturing a semiconductor integrated circuit device, comprising: transferring a circuit layout of a semiconductor integrated circuit device designed by using the method according to claim 1 to a wafer. The process parameters for forming the circuit layout of a semiconductor integrated circuit device on a wafer, or, in a system for determining both the design rules used in designing the circuit layout and the process parameters,
Compaction means for obtaining a compacted layout by compressing the design layout of the semiconductor integrated circuit device based on a prescribed design rule;
Chip size information acquisition means for acquiring chip size information of the semiconductor integrated circuit device corresponding to the compacted layout;
Finished shape information acquisition means for obtaining information on the finished shape on the wafer corresponding to the compacted layout using the specified process parameters;
A comparison means for comparing the obtained finished shape with the compacted layout;
Danger pattern information acquisition means for extracting a danger pattern that is a pattern in which a predetermined margin cannot be secured from the compacted layout based on a comparison result by the comparison means, and obtaining danger pattern information that is information related to the danger pattern;
Evaluation means for determining whether the chip size information and the danger pattern information satisfy respective evaluation conditions;
Change means for changing a process parameter when the evaluation means determines that at least one of the chip size information and the danger pattern information does not satisfy the evaluation condition;
When the process parameter is changed, the changed process parameter is defined as a new process parameter to be input to the finished shape information acquisition unit, and when the design rule is changed, the changed design rule is stored in the compaction. And a defining means for defining as a new design rule to be input to the means.   The changing unit changes the process parameter or both the design rule and the process parameter until the evaluation unit determines that both the chip size information and the danger pattern information satisfy the evaluation condition. The system according to claim 9.   11. The shape information acquisition unit includes a simulator that predicts information on a finished shape on a wafer corresponding to the compacted layout using the specified process parameter. System.   The simulator predicts the finished shape by using the data of the compacted layout information converted to photolithographic mask data subjected to optical proximity correction or data converted to electron beam lithography data subjected to proximity effect correction. The system of claim 11.   The shape information acquisition means acquires, as the finished shape information, a mask shape obtained by experiment, a resist shape obtained by the experiment, or a shape obtained by processing on the wafer obtained by the experiment. The system according to claim 9 or 10, characterized in that   10. The risk pattern information is calculated by varying at least one of an exposure amount, an exposure focus, a finished average size and variation of a mask, an aberration, and an overlay error with another layer. The system in any one of thru | or 13.   The process parameter is at least one of an exposure wavelength, a numerical aperture (NA) of a lens of the exposure apparatus, an illumination shape (σ, ε) of the exposure apparatus, a mask phase, a mask transmittance, and a development / resist process parameter. 15. A system according to any of claims 9 to 14, comprising one or more. Program for causing a computer to execute a method for determining a process parameter for forming a circuit layout of a semiconductor integrated circuit device on a wafer, or a design rule used when designing the circuit layout and the process parameter in the method,
A procedure for obtaining a compacted layout by compressing the design layout of the semiconductor integrated circuit device based on the prescribed design rule information;
A procedure for obtaining chip size information of a semiconductor integrated circuit device corresponding to the compacted layout;
Using the specified process parameters, a procedure for obtaining information on the finished shape on the wafer corresponding to the compacted layout;
A procedure for obtaining a comparison result by comparing the obtained finished shape and the compacted layout;
A procedure for extracting a danger pattern that is a pattern in which a predetermined margin cannot be secured from the compacted layout based on the comparison result, and obtaining danger pattern information that is information on the danger pattern;
A procedure for determining whether the chip size information and the danger pattern information satisfy respective evaluation conditions;
A procedure for changing a process parameter when it is determined that at least one of the chip size information and the danger pattern information does not satisfy the evaluation condition;
When the process parameter is changed, the changed process parameter is defined as a new process parameter in the procedure for obtaining the finished shape information, and when the design rule is changed, the changed design rule is changed to the covered parameter. A procedure for defining a new design rule in the procedure for obtaining a compaction layout;
A program comprising:

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