JP4186561B2 - Image processing apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus and a method for performing parallel processing by sharing a plurality of processing data.
[0002]
[Prior art]
Combined with improvements in computing speed and enhancement of drawing functions in recent computer systems, research and development of “computer graphics (CG)” technology that creates and processes graphics and images using computer resources is actively conducted. Has been put to practical use.
[0003]
For example, in 3D graphics, optical phenomena when a 3D object is illuminated by a predetermined light source are expressed by a mathematical model, and the object surface is shaded or shaded based on this model. By pasting, a more realistic and three-dimensional two-dimensional high-definition image is generated.
Such computer graphics are increasingly used in CAD / CAM in development fields such as science, engineering and manufacturing, and in various other application fields.
[0004]
Three-dimensional graphics is generally composed of a “geometry subsystem” positioned as a front end and a “raster subsystem” positioned as a back end.
[0005]
The geometry subsystem is a process of performing geometric calculation processing such as the position and orientation of a three-dimensional object displayed on a display screen.
In the geometry subsystem, an object is generally handled as a collection of a large number of polygons, and geometric calculation processing such as “coordinate transformation”, “clipping”, “light source calculation”, and the like is performed for each polygon.
[0006]
On the other hand, the raster subsystem is a process of painting each pixel constituting an object.
The rasterization process is realized by interpolating the image parameters of all the pixels included in the polygon based on the image parameters obtained for each vertex of the polygon, for example.
The image parameters referred to here include color (drawing color) data expressed in a so-called RGB format and the like, a z value indicating a distance in the depth direction, and the like.
Also, in recent high-definition three-dimensional graphics processing, f (fog: fog) for creating a sense of perspective, texture (texture) that gives a sense of materiality and patterns on the surface of an object, and provides reality It is included as one of the parameters.
[0007]
Here, the process of generating the pixels inside the polygon from the vertex information of the polygon is often performed using a linear interpolation method called DDA (Digital Differential Analyzer).
In the DDA process, the inclination of the data in the side direction of the polygon is obtained from the vertex information, the data on the side is calculated using this inclination, and then the inclination in the raster scanning direction (X direction) is calculated. An internal pixel is generated by adding the change amount of the parameter obtained from the above to the parameter value of the scanning start point.
[0008]
By the way, in order to improve the performance of the graphics LSI, it is effective not only to increase the operating frequency of the LSI but also to use a parallel processing technique. The parallel processing methods can be broadly classified as follows.
The first is a parallel processing method by area division, the second is a parallel processing method at a primitive level, and the third is a parallel processing method at a pixel level.
[0009]
The above classification is based on the granularity of parallel processing, the granularity of region division parallel processing is the most, and the granularity of pixel level parallel processing is the finest. The outline of each method is described below.
[0010]
Parallel processing by area division
This is a technique of dividing a screen into a plurality of rectangular areas and performing parallel processing while assigning areas to which each of the plurality of processing units is responsible.
[0011]
Parallel processing at the primitive level
This is a technique in which different primitives (for example, triangles) are given to a plurality of processing units to operate in parallel.
[0012]
Parallel processing at the pixel level
This is the method of parallel processing with the finest granularity.
FIG. 1 is a diagram conceptually illustrating parallel processing at a primitive level based on a parallel processing technique at a pixel level.
As shown in FIG. 1, in the parallel processing method at the pixel level, when rasterizing a triangle, pixels are arranged in a rectangular area unit called a pixel stamp PS made up of pixels arranged in a 2 × 8 matrix. Generated.
In the example of FIG. 1, a total of eight pixel stamps from pixel stamp PS0 to pixel stamp PS7 are generated. A maximum of 16 pixels included in these pixel stamps PS0 to PS7 are processed simultaneously.
This method is more efficient in parallel processing because of its finer granularity than other methods.
[0013]
[Problems to be solved by the invention]
However, in the case of the parallel processing based on the region division described above, in order to efficiently operate each processing unit in parallel, it is necessary to classify objects to be drawn in each region in advance, and the load of scene data analysis is heavy.
In addition, drawing is not started after all the scene data for one frame is prepared, but parallelism is drawn when drawing in so-called immediate mode in which drawing is started immediately when object data is given. I can't.
[0014]
Further, in the case of parallel processing at the primitive level, there is actually a variation in the size of the primitive that constitutes the object, so that there is a difference in the time for processing one primitive for each processing unit. When this difference becomes large, the drawing area of the processing unit is also greatly different, and the locality of data is lost. For example, page misses of the DRAM constituting the memory module frequently occur and the performance deteriorates.
In addition, this method has a problem that the wiring cost is high. Generally, hardware that performs graphics processing performs memory interleaving using a plurality of memory modules in order to widen the memory bandwidth.
At that time, it is necessary to connect all the processing units and all the built-in memory modules.
[0015]
On the other hand, the parallel processing at the pixel level has the advantage that the efficiency of parallel processing is good because the granularity is fine as described above, and the processing including actual filtering is performed according to the procedure shown in FIG. ing.
[0016]
That is, DDA parameters, for example, DDA parameters such as inclinations of various data (Z, texture coordinates, color, etc.) necessary for rasterization are calculated (ST1).
Next, the texture data is read from the memory (ST2), and after the subword rearrangement process is performed in the first processing unit including a plurality of arithmetic units (ST3), the second processing unit includes a plurality of arithmetic units by the crossbar circuit. The processing units are collected (ST4).
Next, texture filtering is performed (ST5). In this case, the second processing unit performs a filtering process such as 4-neighbor interpolation using the read texture data and the (u, v) address using the decimal part obtained at the time of calculation.
Next, pixel-level processing (Per-Pixel Operation), specifically, pixel-based computation is performed using filtered texture data and various data after rasterization (ST5).
Then, the pixel data that passes various tests in the pixel level processing is drawn in the frame buffer and the Z buffer on the plurality of memory modules (ST6).
[0017]
Further, in the image processing apparatus, when a semi-transparent object is synthesized using a plurality of buffers, the z data stored in the z buffer included in the graphics memory and the pixel data supplied as drawing data are used. The corresponding z data is compared, it is determined whether or not it is positioned in front (viewpoint side) based on the image written by the supplied pixel data, and the order is maintained in the depth direction of the z data of each buffer. Synthesize.
[0018]
However, in the conventional image processing apparatus, when the above-described translucent object synthesis (Order Independent Transparency) is performed, when all scene data is flowed and processed in parallel, superposition with an arbitrary number of layers is performed. I can't do it.
Therefore, in the conventional image processing apparatus, there are disadvantages such as an increase in the number of times all scenes are passed and an increase in the load on the upper processing unit, for example, the geometry processing unit.
[0019]
The present invention has been made in view of such circumstances, and an object of the present invention is to perform superposition with an arbitrary number of layers when performing semi-transparent object synthesis, and to reduce the number of times all scene data flows. Therefore, an object of the present invention is to provide an image processing apparatus and method that can reduce the load on the processing unit of the scene data and increase the processing speed.
[0020]
[Means for Solving the Problems]
  To achieve the above object, according to a first aspect of the present invention, pixel data including color data, mixed value data, and depth data is generated based on information about a primitive to be drawn, and the depth direction of a plurality of depth data Is an image processing apparatus that performs a synthesis process of a translucent object,A pixel arithmetic processor for arithmetic processing of the pixel data;A plurality of buffers capable of storing and reading the color data, the mixed value data, and the depth data, and a plurality of sort circuits provided corresponding to the buffers and cascaded from the first stage to the last stage. ,the abovePixel arithmetic processorAnd the above multiple buffersA cache storage unit for storing pixel data for transferring data to and from the pixel arithmetic processor and the buffer;Multiple buffers aboveAnd access the above cache storageAddress generation times for generating addressesRoad andThe sorting circuit in the first stage includes the read depth data value read from the corresponding buffer andOutput from the pixel calculation processor corresponding to the pixel data for drawingCompare with the first supply depth data value,As a result of comparison, in the first case where the first supply depth data value is larger, smaller or equal,The read depth data, color data, and mixed value data are written back to the corresponding buffer, and the supplied first supply depth data value, color data, and mixed value data are supplied to the next-stage sorting circuit, Each sort circuit after the second stage compares the read depth data value read from the corresponding buffer with the second supply depth data value supplied from the previous sort circuit,As a result of the comparison, the second supply depth data value is larger, smaller, or equal to any one of the second values.In this case, the read depth data, color data, and mixed value data are written back to the corresponding buffer and supplied from the previous stage.the aboveThe second supply depth data value, the color data, and the mixed value data are supplied to the next sort circuit, and the read depth data value is compared with the second supply depth data value.As a result, the read depth data value is any one of large, small, or equal to those other than the second case.In case, from the previous stagethe aboveThe second supply depth data value, color data, and mixed value data are written into the corresponding buffer, and the read depth data, color data, and mixed value data are supplied to the next-stage sorting circuit.
[0021]
In the present invention, when the depth data value is not stored in the corresponding buffer, the sorting circuits in the second and subsequent stages receive the second supply depth data value, color data, and mixed value data from the previous stage. Write to the corresponding buffer.
[0022]
Further, according to the present invention, the sort circuits having a plurality of memory banks including a plurality of buffers and provided corresponding to the respective buffers of the same memory bank are not connected to each other and are included in different memory banks. A plurality of sort circuits provided corresponding to the buffers are cascaded in parallel.
[0023]
  According to a second aspect of the present invention, pixel data including color data, mixed value data, and depth data is generated based on information about a primitive to be drawn, and the order of a plurality of depth data in the depth direction is maintained. An image processing apparatus that performs a synthesis process of a translucent object,A pixel arithmetic processor for arithmetic processing of the pixel data;A plurality of buffers capable of storing and reading the color data, mixed value data, and depth data;
  Read depth data values provided corresponding to the plurality of buffers and read from the corresponding buffers;Output from the pixel calculation processor corresponding to the pixel data for drawingA plurality of sorting circuits including a comparing unit for comparing the first supply depth data value;Pixel arithmetic processorAnd the above multiple buffersA cache storage unit for storing pixel data for transferring data to and from the pixel arithmetic processor and the buffer;Multiple buffers aboveAnd access the above cache storageAddress generation times for generating addressesRoad andThe sorting circuits are cascaded from the first stage to the last stage, and the sorting circuits are connected as a result of the comparison by the comparison unit.The first supply depth data value is any one of the first, the first, the second, the depth, or the same as the read depth data value.In this case, the supplied first supply depth data value, color data, and mixed value data are supplied to the next-stage sorting circuit, and the read depth data, color data, and mixed value data are stored in the corresponding buffers. Write back,The first supply depth data value is any one of large, small or equal except in the first case compared to the read depth data value.In this case, the read depth data, color data, and mixed value data are supplied to the sorting circuit in the next stage, and the second supply depth data value, color data, and mixed value data from the previous stage are corresponded to the above. Write to the buffer you want.
[0024]
  In the present invention, the first stagethe aboveThe sort circuitOutput from the pixel calculation processor corresponding to the pixel data for drawingThe first supply depth data value is compared with the read depth data valueresult,The first supply depth data is any one of the second, larger, smaller or equal compared to the read depth data value.In this case, the read depth data, color data, and mixed value data are supplied to the sorting circuit in the next stage, and the supplied first supply depth data value, color data, and mixed value data correspond to the above. Write to buffer.
[0025]
In the present invention, each of the sorting circuits in the second and subsequent stages has the second supply depth data value, color data, and mixed value from the previous stage when the depth data value is not stored in the corresponding buffer. Write data to the corresponding buffer.
[0026]
In the present invention, a plurality of memory banks including a plurality of buffers are arranged in multiple stages, and sort circuits provided corresponding to the buffers of the same memory bank are connected in cascade to each other. The plurality of sort circuits connected in cascade are connected to each buffer of the preceding memory bank, and the output depth data of the last stage among the plurality of sort circuits connected in cascade is stored in the plurality of sort circuits connected in cascade. Supplied.
[0027]
  According to a third aspect of the present invention, there is provided an image processing apparatus in which a plurality of modules share processing data and perform parallel processing, and color data, mixed value data, And a plurality of local modules that generate pixel data including depth data, retain the order of the depth direction of the plurality of depth data, and perform synthesis processing of the translucent object, and the global module includes the plurality of the plurality of local modules. When local modules are connected in parallel and receive a request from the local module, processing data is output to the local module that issued the request according to the request, and the plurality of local modulesA pixel arithmetic processor for arithmetic processing of the pixel data;A plurality of buffers capable of storing and reading the color data, the mixed value data, and the depth data, and a plurality of sort circuits provided corresponding to the buffers and cascaded from the first stage to the last stage. ,the abovePixel arithmetic processorAnd the above multiple buffersA cache storage unit for storing pixel data for transferring data to and from the pixel arithmetic processor and the buffer;
Multiple buffers aboveAnd access the above cache storageAddress generation times for generating addressesRoad andThe sorting circuit in the first stage includes the read depth data value read from the corresponding buffer andOutput from the pixel calculation processor corresponding to the pixel data for drawingCompare with the first supply depth data value,As a result of comparison, in the first case where the first supply depth data value is larger, smaller or equal,The read depth data, color data, and mixed value data are written back to the corresponding buffer, and the supplied first supply depth data value, color data, and mixed value data are supplied to the next-stage sorting circuit, Each sort circuit after the second stage compares the read depth data value read from the corresponding buffer with the second supply depth data value supplied from the previous sort circuit,As a result of the comparison, the second supply depth data value is larger, smaller or equal to one of the second values.In this case, the read depth data, color data, and mixed value data are written back to the corresponding buffer and supplied from the previous stage.the aboveSupplying the second supply depth data value, the color data, and the mixed value data to the sorting circuit in the next stage;The read depth data value is any one of large, small or equal except in the second case.In case, from the previous stagethe aboveThe second supply depth data value, color data, and mixed value data are written into the corresponding buffer, and the read depth data, color data, and mixed value data are supplied to the next-stage sorting circuit.
[0028]
According to a fourth aspect of the present invention, there is provided an image processing apparatus in which a plurality of modules share processing data and perform parallel processing. Color data, mixed value data, And a plurality of local modules that generate pixel data including depth data, hold a sequence in the depth direction of the plurality of depth data, and perform a translucent object combining process, and the global module includes the plurality of the plurality of local modules. When local modules are connected in parallel and receive a request from the local module, processing data is output to the local module that issued the request according to the request, and the plurality of local modulesA pixel arithmetic processor for arithmetic processing of the pixel data;A plurality of buffers capable of storing and reading out the color data, the mixed value data, and the depth data; and a read depth data value provided corresponding to the plurality of buffers and read from the corresponding buffer;Output from the pixel calculation processor corresponding to the pixel data for drawingA plurality of sorting circuits including a comparison unit for comparing with a first supply depth data value;Pixel arithmetic processorAnd the above multiple buffersA cache storage unit for storing pixel data for transferring data to and from the pixel arithmetic processor and the buffer;Multiple buffers aboveAnd access the above cache storageAddress generation times for generating addressesRoad andThe sorting circuits are cascaded from the first stage to the last stage, and the sorting circuits are connected as a result of the comparison by the comparison unit.The first supply depth data value is any one of the first, the first, or the second of the read depth data values greater than, less than, or equal toIn this case, the supplied first supply depth data value, color data, and mixed value data are supplied to the next-stage sorting circuit, and the read depth data, color data, and mixed value data are stored in the corresponding buffers. Write back,The first supply depth data value is any one of large, small, or equal to those other than the first case compared to the read depth data value.In this case, the read depth data, color data, and mixed value data are supplied to the sorting circuit in the next stage, and the second supply depth data value, color data, and mixed value data from the previous stage are corresponded to the above. Write to the buffer you want.
[0029]
According to a fifth aspect of the present invention, pixel data including color data, mixed value data, and depth data is generated based on information about a primitive to be drawn, and the order of a plurality of depth data in the depth direction is maintained. An image processing method for performing synthesis processing of a translucent object, wherein a plurality of sorting circuits corresponding to a plurality of buffers are cascaded from the first stage to the last stage,A cache storage unit is connected to the pixel arithmetic processor for calculating the pixel data and the plurality of buffers to store pixel data for transferring data to the pixel arithmetic processor and the buffer, and an address generation circuit includes the plurality of buffers. And the above cache storage unit,In the first stage sort circuit, the read depth data value read from the corresponding buffer andOutput from the pixel calculation processor corresponding to the pixel data for drawingCompare with the first supply depth data value,
      As a result of comparison, in the first case where the first supply depth data value is larger, smaller or equal,The read depth data, color data, and mixed value data are written back to the corresponding buffer, and the supplied first supply depth data value, color data, and mixed value data are supplied to the next-stage sorting circuit, In each sort circuit in the second and subsequent stages, the read depth data value read from the corresponding buffer is compared with the second supply depth data value supplied from the previous sort circuit,As a result of the comparison, the second supply depth data value is larger, smaller or equal to one of the second values.In this case, the read depth data, color data, and mixed value data are written back to the corresponding buffer, and the second supply depth data value, color data, and mixed value data from the previous stage are converted into the next sort circuit. And compare the read depth data value with the second supply depth data value.As a result, the second supply depth data value is any one of large, small, or equal to those other than the second case.In this case, the second supply depth data, color data, and mixed value data from the previous stage are written in the corresponding buffers, and the read depth data, color data, and mixed value data are supplied to the next-stage sorting circuit. .
[0030]
  According to a sixth aspect of the present invention, pixel data including color data, mixed value data, and depth data is generated based on information about a primitive to be drawn, and the order in the depth direction of the plurality of depth data is maintained. An image processing method for performing synthesis processing of a translucent object, wherein a plurality of sorting circuits corresponding to a plurality of buffers are cascaded from the first stage to the last stage,A cache storage unit is connected to the pixel arithmetic processor for calculating the pixel data and the plurality of buffers to store pixel data for transferring data to the pixel arithmetic processor and the buffer, and an address generation circuit includes the plurality of buffers. And the above cache storage unit,In each sort circuit, the read depth data value read from the corresponding buffer andOutput from the pixel calculation processor corresponding to the pixel data for drawingCompare with the first supply depth data value,
The first supply depth data value is any one of the first, the first, the second, the depth, or the same as the read depth data value.In this case, the supplied first supply depth data value, color data, and mixed value data are supplied to the next sorting circuit, and the read depth data, color data, and mixed value data are stored in the corresponding buffer. Write back toThe first supply depth data value is any one of large, small or equal except in the first case compared to the read depth data value.In this case, the read depth data, color data, and mixed value data are supplied to the next sort circuit, and the second supply depth data value, color data, and mixed value data from the previous stage are supplied to the corresponding buffer. Write to.
[0031]
According to the present invention, for example, depth data, color data, and mixed value data stored in each buffer are read out to a corresponding sort circuit.
  The first-stage sorting circuit is supplied with the first supply depth data value, color data, and mixed value data corresponding to the pixel data supplied for drawing. In the first sort circuit, the read depth data value read from the corresponding buffer is compared with the first supplied depth data value corresponding to the pixel data supplied for drawing.
  And as a result of comparison,The first supply depth data value is larger, smaller or equal to the read depth data value.In this case, the read depth data, color data, and mixed value data are written back to the corresponding buffer, and the supplied first supply depth data value, color data, and mixed value data are input to the next-stage sorting circuit. Supplied.
  In each sort circuit in the second and subsequent stages, the read depth data value read from the corresponding buffer is compared with the second supply depth data value supplied from the previous sort circuit.
  And as a result of comparison,The first supply depth data value is larger, smaller or equal compared to the read depth data value.In this case, the read depth data, color data, and mixed value data are written back to the corresponding buffers, and the second supply depth data value, color data, and mixed value data from the previous stage are supplied to the next-stage sorting circuit. Is done.
  on the other hand,Any one of the first supply depth data value is larger, smaller or equal than in the second case compared to the read depth data valueIn this case, the second supply depth data value, color data, and mixed value data from the previous stage are written in the corresponding buffers, and the read depth data, color data, and mixed value data are supplied to the next sort circuit. Is done.
[0032]
Further, according to the present invention, for example, depth data, color data, and mixed value data stored in each buffer are read out to a corresponding sort circuit.
  Each sort circuit is supplied with the first supply depth data value, color data, and mixed value data corresponding to the pixel data supplied for drawing.
In each sort circuit, the read depth data value read from the corresponding buffer is compared with the first supply depth data value corresponding to the pixel data supplied for drawing.
  And as a result of comparison,The first supply depth data value is either one of the first, the first, or the second depth data value greater than, less than or equal to the read depth data value.In this case, the supplied first supply depth data value, color data, and mixed value data are supplied to the sorting circuit in the next stage, and the read depth data, color data, and mixed value data are written in the corresponding buffers. Returned.
  on the other hand,The first supply depth data value is any one of large, small or equal except in the first case compared to the read depth data value.In this case, the read depth data, color data, and mixed value data are supplied to the next-stage sorting circuit, and the second supplied depth data value, color data, and mixed value data from the previous stage are written in the corresponding buffers. It is.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 is a block diagram showing an embodiment of the image processing apparatus according to the present invention.
[0034]
As shown in FIG. 3, the image processing apparatus 10 according to the present embodiment includes a stream data controller (SDC) 11, a global module 12, and a plurality of local modules 13-0 to 13-3.
[0035]
In the image processing apparatus 10, the SDC 11 and the global module 12 exchange data, and a plurality of m, or four local modules 13-0 to 13-3 in this embodiment are connected in parallel to one global module 12. Are connected to each other, and the plurality of local modules 13-0 to 13-3 share processing data and process them in parallel.
With respect to the texture read system, memory access to other local modules is required, but instead of taking the form of a global access bus, access is performed via one global module 12 having a function as a router.
The global module 12 has a global cache, and each of the local modules 13-0 to 13-3 has a local cache.
That is, the image processing apparatus 10 has two levels of caches, for example, a global cache shared by four local modules 13-0 to 13-3 and a local cache locally owned by each local module.
[0036]
The configuration and function of each component will be described below in order with reference to the drawings.
[0037]
The SDC 11 is responsible for data exchange with the CPU and external memory, and data exchange with the global module 12, computation for vertex data, and rasterization in the processing units of the local modules 13-0 to 13-3. Processes such as parameter generation necessary for
[0038]
Specific processing contents in the SDC 11 are as follows. Moreover, the processing procedure of SDC11 is shown in FIG.
[0039]
First, when data is input (ST1), the SDC 11 performs a Per-Vertex operation (ST2).
In this process, when vertex data of three-dimensional coordinates, normal vectors, and texture coordinates is input, computation is performed on the vertex data. Typical calculations include coordinate conversion calculation processing that performs deformation of an object, projection onto a screen, lighting calculation processing, and clipping calculation processing.
The processing performed here corresponds to execution of a so-called Vertex Shader.
[0040]
Next, a DDA (Digital Differential Analyzer) parameter is calculated (ST3).
In this process, DDA parameters such as inclinations of various data (Z, texture coordinates, color, etc.) necessary for rasterization are calculated.
[0041]
Next, the calculated DDA parameter is broadcast to all the local modules 13-0 to 13-3 via the global module 12 (ST4).
In this process, the broadcast parameters are transferred to the local modules 13-0 to 13-3 via the global module 12 using a channel different from the cache fill. However, it does not affect the contents of the global cache.
[0042]
The global module 12 has a router function and a global cache 121 shared by all local modules.
The global module 12 broadcasts the DDA parameters by the SDC 11 to all the local modules 13-0 to 13-3 connected in parallel.
[0043]
Further, for example, when receiving a local cache fill LCF request from a certain local module, the global module 12 checks a global cache entry (ST11) as shown in FIG. (ST12), the requested block data is read (ST13), the read data is sent to the local module that sent the request (ST14), and if there is no entry (ST12), the block data is retained. A global cache fill (GCF) request is sent to the target local module (ST15), and then the global cache is updated with the block data sent. While (ST16, ST17), reads out the block data (ST13), the read data is sent to the local module that sent the request for the local cache fill LDF the (ST14).
[0044]
The local module 13-0 is a processing unit 131-0, for example, a memory module 132-0 made of DRAM, a local cache 133-0 unique to the module, and a global interface (GAIF) that controls an interface with the global module 12. ) 134-0.
[0045]
Similarly, the local module 13-1 is a processing unit 131-1, for example, a memory module 132-1 made of DRAM, a module-specific local cache 133-1, and a global interface (GAIF) 134 that controls an interface with the global module 12. -1.
The local module 13-2 includes a processing unit 131-2, for example, a memory module 132-2 including a DRAM, a module-specific local cache 133-2, and a global interface (GAIF) 134-2 that controls an interface with the global module 12. Have.
The local module 13-3 includes a processing unit 131-3, for example, a memory module 132-3 made of DRAM, a local cache 133-3 specific to the module, and a global interface (GAIF) 134-3 that controls an interface with the global module 12. Have.
[0046]
In each of the local modules 13-0 to 13-3, the memory modules 132-0 to 132-3 are interleaved in units of a predetermined size, for example, a 4 × 4 rectangular area, and the memory module 132-0 and the processing unit 131 are interleaved. −0, the memory module 132-1 and the processing unit 131-1, the memory module 132-2 and the processing unit 131-2, and the memory module 132-3 and the processing unit 131-3 have a one-to-one correspondence area. In the drawing system, memory access to other local modules does not occur.
On the other hand, the local modules 13-0 to 13-3 require memory access to other local modules with respect to the texture read system. In this case, the local modules 13-0 to 13-3 perform access via the global module 12.
[0047]
The processing units 131-0 to 131-3 of the local modules 13-0 to 13-3 are streaming processors that perform so-called streaming data processing, which is characteristic of image processing and graphics processing, at high throughput.
[0048]
The processing units 131-0 to 131-3 of the local modules 13-0 to 13-3 perform, for example, the following graphics processing and image processing, respectively.
[0049]
First, the outline of the graphics processing of the processing units 131-0 to 131-3 will be described with reference to the flowcharts of FIGS.
[0050]
When the broadcast parameter data is input (ST21), the processing unit 131 (-0 to -3) determines whether or not the triangle is the area that it is in charge of (ST22). First, rasterization is performed (ST23).
That is, when the broadcast parameter is received, it is determined whether or not the triangle belongs to an area that the user is in charge of, for example, an area interleaved in a rectangular area unit of 4 × 4 pixels. Rasterize various data (Z, texture coordinates, color, etc.). In this case, the generation unit is 2 × 2 pixels in one cycle per local module.
[0051]
Next, perspective collection of texture coordinates (Perspective Correction) is performed (ST24). Further, this processing stage includes calculation of a mipmap (MipMap) level by LOD (Level of Detail) calculation, and (u, v) address calculation for texture access.
[0052]
Next, the texture is read (ST25).
In this case, as shown in FIG. 7, the processing units 131-0 to 131-3 of the local modules 13-0 to 13-3 first store the local caches 133-0 to 133-3 in the texture read. The entry is checked (ST31). If there is an entry (ST32), necessary texture data is read (ST33).
If the required texture data is not in the local cache 133-0 to 133-3, each processing unit 131-0 to 131-3 transmits to the global module 12 through the global interface 134-0 to 134-3. In response, a local cache fill request is sent (ST34).
Then, the global module 12 returns the requested block to the local module that sent the request. If not, as described above (explained in association with FIG. 5), the global module 12 responds to the local module that holds the block. Send a global cache fill request. After that, the block data is filled in the global cache, and the data is sent to the local module that sent the request.
When the requested block data is sent from the global module 12, the corresponding local module updates the local cache (ST35, ST36), and the processing unit reads the block data (ST33).
Here, it is assumed that a maximum of four textures are simultaneously processed, and the number of texture data to be read is 16 texels per pixel.
[0053]
  Next, texture filtering is performed (ST26).
  In this case, the processing unit131-0 to 131-3Performs a filtering process such as 4-neighbor interpolation using the read texture data and the decimal part obtained when calculating the (u, v) address.
[0054]
Next, pixel level processing (Per-Pixel Operation) is performed (ST27).
In this processing, calculation in units of pixels is performed using the texture data after filtering and the various data after rasterization. The processing performed here corresponds to a so-called Pixel Shader such as lighting at the pixel level (Per-Pixel Lighting). In addition, the following processing is included.
That is, the processes of alpha test, scissoring, Z buffer test, stencil test, alpha blending, logical operation, and dithering.
[0055]
Then, the pixel data that passes various tests in the pixel level processing is written into the memory modules 132-0 to 132-3, for example, the frame buffer and the Z buffer on the built-in DRAM memory (ST28: MemoryWrite).
[0056]
Next, an outline of image processing of the processing units 131-0 to 131-3 will be described in association with the flowchart of FIG.
[0057]
Prior to executing image processing, image data is loaded into the memory module 132 (-0 to -3).
Then, in the processing unit 131 (-0 to -3), a command and data necessary for generating a read (source) address and a write (destination) address necessary for image processing are input (ST41). .
Then, in the processing unit 131 (-0 to -3), a source address and a destination address are generated (ST42).
Next, the source image is read from the memory module 132 (-0 to -3) or supplied from the global module 12 (ST43), and predetermined image processing such as template matching is performed (ST44).
Then, a predetermined calculation process is performed as necessary (ST45), and the result is written in the area designated by the destination address of the memory module 132 (-0 to -3) (ST46).
[0058]
The local caches 133-0 to 133-3 of the local modules 13-0 to 13-3 store drawing data and texture data necessary for the processing of the processing units 131-0 to 131-3, and the processing unit 131-0. ˜131-3, and exchange of data (writing and reading) with the memory modules 132-0 to 132-3.
[0059]
FIG. 9 is a block diagram illustrating a configuration example of the local caches 133-0 to 133-3 of the local modules 13-0 to 13-3.
[0060]
As shown in FIG. 9, the local cache 133 includes a read only cache (RO $) 1331, a read / write cache (RW $) 1332, a reorder buffer (RB) 1333, and a memory controller (MC) 1334.
[0061]
The read-only cache 1331 is a read-only cache for reading a source image for arithmetic processing, and is used for storing, for example, texture data.
The read / write cache 1332 is a cache for executing an operation that requires both reading and writing, for example, read modification write (Read Modify Write) in graphics processing, for example, for storing drawing data. Used.
[0062]
The reorder buffer 1333 is a so-called queuing buffer. If there is no data required for the local cache, the order of data sent to the global module 12 may differ when a local cache fill request is issued. The order of the data is adjusted so that the order is returned to the processing units 131-0 to 131-3 in the requested order.
[0063]
FIG. 10 is a block diagram illustrating a configuration example of the texture system of the memory controller 1334.
As shown in FIG. 10, the memory controller 1334 arbitrates local cache fill requests output from the cache controllers 13340 to 13343 corresponding to the four caches CSH0 to CSH3, and the global controllers 134 { An arbiter 13344 that outputs to −0 to 3} and a memory interface 13345 that receives a global cache fill request input via the global interface 134 {−0 to 3} and controls data transfer.
[0064]
In addition, the cache controllers 13340 to 13343 are used to perform two-neighbor interpolation on data corresponding to the four pixels PX0 to PX3, respectively, and two-dimensional addresses COuv00 to COuv03, COuv10 to COuv13, COuv20 to COuv23, The conflict checker CC10 that checks and distributes address conflicts in response to the COuv30 to COuv33, checks the addresses distributed by the conflict checker CC10, and determines whether or not the data indicated by the addresses exists in the read-only cache 1331. It has a tag circuit TAG10 and a queue register QR10.
The tag circuit TAG10 has four tag memories BX10 to BX13 corresponding to addressing related to bank interleaving described later, and is stored in a read-only cache 1331.
The address distributed by the conflict checker CC10 holding the address tag of the block data is compared with the address tag, and a flag indicating whether or not they match and the address are set in the queue register QR10. The address is sent to the arbiter 13344.
The arbiter 13344 receives the address sent from the cache controllers 13340 to 13343, performs arbitration work, selects an address according to the number of requests that can be sent simultaneously via the global interface (GAIF) 134, and generates a local cache fill request. The data is output to the global interface (GAIF) 134.
When data is sent from the global cache 12 in response to a local cache fill request sent via the global interface (GAIF) 134, it is set in the reorder buffer 1333.
The cache controllers 13340 to 13343 check the flag at the head of the queue register QRL0. If the flag indicating that they match is set, the read-only cache 1331 is based on the address at the head of the queue register QRL0. Are read out and provided to the processing unit 131. On the other hand, if the flag indicating that they match is not set, the corresponding data is read from the reorder buffer 1333 when it is set in the reorder buffer 1333, and is read with the block data based on the address of the queue register QRL0. The only cache 1331 is updated and output to the processing unit 131.
[0065]
Next, the memory capacity of the DRAM as a memory module, the local cache, and the global cache will be described.
As a matter of course, the relationship of the memory capacity is DRAM> global cache> local cache, but the ratio depends on the application.
The cache block size corresponds to the data size read from the lower layer memory at the time of cache fill.
As a characteristic of the DRAM, the performance is deteriorated during random access, but continuous access of data belonging to the same row (ROW) is fast.
[0066]
In terms of performance, it is preferable that the global cache performs the continuous access in terms of reading data from the DRAM.
Therefore, a large cache block size is set.
For example, the size of the cache block of the global cache can be set to the block size of one line of the DRAM macro.
[0067]
On the other hand, in the case of a local cache, if the block size is increased, the percentage of unused data increases even if it is put in the cache, and the lower layer is a global cache and there is no need for continuous access instead of DRAM. Set the block size small.
As the block size of the local cache, a value close to the size of the rectangular area of the memory interleave is appropriate. In the present embodiment, the block size is 4 × 4 pixels, that is, 512 bits.
[0068]
Next, texture compression will be described.
Since a plurality of pieces of texture data are required for processing one pixel, the texture read bandwidth often becomes a bottleneck. In order to reduce this, a method of compressing the texture is often employed.
There are various compression methods, but in the case of a method that can compress / decompress in units of a small rectangular area such as 4 × 4 pixels, the compressed data is placed in the global cache, and decompressed in the local cache. It is preferable to put later data.
[0069]
Next, a specific configuration example of the processing units 131-0 to 131-3 of the local modules 13-0 to 13-3 will be described.
[0070]
FIG. 11 is a block diagram illustrating a specific configuration example of the processing unit of the local module according to the present embodiment.
[0071]
  The processing unit 131 (-0 to -3) of the local module 13 (-0 to -3) includes a rasterizer (RSTR) 1311 and a core 1312 as shown in FIG.
  Among these components, the arithmetic processing that the core 1312 realizes this architectureIn the departmentThe core 1312 is supplied with various data for graphics processing and image processing such as addresses and coordinates by the rasterizer 1311.
[0072]
In the case of graphics processing, the rasterizer 1311 receives the parameter data broadcast from the global module 12 and determines, for example, whether or not the triangle is an area for which it is in charge. Rasterization is performed based on the input triangle vertex data, and the generated pixel data is supplied to the core 1312.
Pixel data generated by the rasterizer 1311 includes window coordinates (X, Y, Z), primary colors (Primary Color: PC) (Rp, Gp, Bp, Ap), secondary colors (Secondary Color: SC) (Rs, Various data such as Gs, Bs, As), Fog coefficient (f), texture coordinates, normal vector, line-of-sight vector, light vector ((V1x, V1y, V1z), (V2x, V2y, V2z)) are included.
The data supply line from the rasterizer 1311 to the core 1312 includes, for example, a window coordinate (X, Y, Z) supply line, other primary colors (Rp, Gp, Bp, Ap), and secondary colors (Rs, Gs). , Bs, As), Fog coefficient (f), texture coordinates (V1x, V1y, V1z), and (V2x, V2y, V2z) supply lines are formed by different wirings.
[0073]
In the case of image processing, the rasterizer 1311 outputs a source address and an image processing result for reading out image data from the memory module 132 (-0 to -3) output from a host device (not shown) via the global module 12, for example. The command and data necessary for generating the destination address for writing the data, for example, the width and height data (Ws, Hs) of the search rectangular area, the block size data (Wbk, Hbk) are input, and based on the input data, A source address (X1s, Y1s) and / or (X2s, Y2s) is generated, and a destination address (Xd, Yd) is generated and supplied to the core 1312.
As the data supply line from the rasterizer 1311 to the core 1312 at the time of image processing, for example, the supply line of the window coordinates (X, Y, Z) at the time of graphics processing is shared for the destination address (Xd, Yd), and the source For addresses (X1s, Y1s) and (X2s, Y2s), supply lines such as texture coordinates (V1x, V1y, V1z) and (V2x, V2y, V2z) are shared.
[0074]
The core 1312 is an arithmetic processing unit that implements this architecture. The core 1312 is supplied with various data by the rasterizer 1311.
The core 1312 includes the following functional units that perform arithmetic processing on stream data.
That is, the core 1312 includes a graphics unit (GRU) 13121 as a first functional unit, a pixel engine (PXE) 13122 as a third functional unit, and a pixel as a second functional unit. An arithmetic processor (Pixel 0peration Processor: POP) group 13123 is included.
The core 1312 corresponds to various algorithms by switching the connection between these functional units according to, for example, a data flow graph (DFG).
Further, the core 1312 includes a register unit (RGU) 13124 and a crossbar circuit (Interconnection X-Bar: IXB) 13125.
[0075]
The graphics unit (GRU) 13121 is a functional unit in which a hardware that is clearly advantageous in terms of cost performance to which dedicated hardware is added when executing graphics processing is implemented.
The graphics unit 13121 implements functions such as perspective correction, MIPMAP level calculation, and the like as those related to graphics processing.
[0076]
The graphics unit 13121 is supplied by the crossbar circuit 13125, the texture coordinates (V1x, V1y, V1z) supplied by the rasterizer 1311 via the register unit (RGU) 13124, and / or supplied by the rasterizer 1311 or the pixel engine (PXE) 13122. Texture coordinate (V2x, V2y, V2z) data is input, and based on the input data, perspective collection, mipmap (MIPMAP) level calculation by LOD (LevelofDetail) calculation, cube map (Cube Map) surface selection and Normalized texel coordinates (s, t) are calculated, for example, graphics data (s1, t1, l including normalized texel coordinates (s, t) and LOD data (lod). d1) and / or (s2, t2, lod2) is output to the pixel operation processor (POP) group 13123.
Note that the output graphics data (s1, t1, lod1) and (s2, t2, lod2) of the graphics unit 13121 are shown through the crossbar circuit 13125 and the register unit (RGU) 13124 or as shown by broken lines in FIG. In addition, it is directly supplied to the pixel operation processor (POP) group 13123 by another wiring.
[0077]
A pixel engine (PXE) 13122 as a third functional unit is a functional unit that performs stream data processing, and has a plurality of arithmetic units therein.
The pixel engine 13122 has a high degree of freedom in connection between arithmetic units as compared with the pixel arithmetic processor (POP) group 13123, and has abundant arithmetic unit functions.
[0078]
The pixel engine (PXE) 13122 sets the information related to the drawing target and the calculation result in the pixel calculation processor (POP) group 13123 in the desired FIFO register of the register unit (RGU) 13124 by the crossbar circuit 13125, for example, It is supplied directly through the register unit (RGU) 13124 without going through the bar circuit 13125.
The data input to the pixel engine (PXE) 13122 includes, for example, information on the surface to be drawn (surface direction, color, reflectance, pattern (texture), etc.), information on light hitting the surface (incident direction, intensity) Etc.), past calculation results (intermediate values of calculations), etc. are common.
[0079]
The pixel engine (PXE) 13122 has a plurality of arithmetic units, and is an arithmetic unit capable of reconfiguring an arithmetic path by external control, for example, between internal arithmetic units so as to realize a desired arithmetic operation. Establish electrical connection and input data via the register unit (RGU) 13124 to the data path of a series of arithmetic units formed from the arithmetic units and the electrical connection network (interconnect). And output the calculation result.
[0080]
That is, the pixel engine 13122 has, for example, a plurality of reconfigurable data paths, and arithmetic units (adders, multipliers, multipliers / adders, etc.) are connected by an electrical connection network. To constitute an arithmetic circuit.
The pixel engine 13122 can continuously input data to the arithmetic circuit thus reconfigured and perform arithmetic operations, for example, using a binary tree-like DFG (data flow graph). It is possible to configure an arithmetic circuit using a connection network that can realize the expressed arithmetic efficiently and with a small circuit scale.
[0081]
FIG. 12 is a diagram illustrating a configuration example of the pixel engine (PXE) 13122 and a connection example with the register unit (RGU) 13124 and the crossbar circuit 13125.
[0082]
As shown in FIG. 12, the pixel engine (PXE) 13122 has a plurality of (16 in the example of FIG. 12) arithmetic units OP1 to OP8 and OP11 to OP18 based on a 2- or 3-input MAC (Multiple and Accumulator). And one or more (four in the example of FIG. 12) lookup tables LUT1, LUT2, LUT11, and LUT12.
[0083]
As shown in FIG. 12, the two inputs of the arithmetic units OP1 to OP8 and OP11 to OP18 in the pixel engine (PXE) 13122 are the FIFO (First-IN First-Out) register FREG of the register unit (RGU) 13124. Is directly connected.
Similarly, one input of the lookup tables LUT1, LUT2, LUT11, and LUT12 is directly connected to the FIFO register FREG of the register unit (RGU) 13124.
The outputs of the arithmetic units OP1 to OP8 and OP11 to OP18 and the lookup tables LUT1, LUT2, LUT11, and LUT12 are connected to a crossbar circuit 13125.
[0084]
Further, in the example of FIG. 12, the output of the arithmetic unit OP1 is connected to the two inputs of the arithmetic units OP3 and OP4 and the one input of the three-input arithmetic unit OP2. Similarly, the output of the computing unit OP2 is connected to the 2-input of the computing unit OP4 and the 1-input of the 3-input computing unit OP3, respectively. The output of the arithmetic unit OP3 is connected to one input of the three-input arithmetic unit OP4.
The output of the arithmetic unit OP5 is connected to the two inputs of the arithmetic units OP7 and OP8 and the one input of the three-input arithmetic unit OP6. Similarly, the output of the calculator OP6 is connected to the two inputs of the calculator OP8 and the one input of the three-input calculator OP7. The output of the arithmetic unit OP7 is connected to one input of the three-input arithmetic unit OP8.
Further, the output of the arithmetic unit OP11 is connected to the two inputs of the arithmetic units OP13 and OP14 and the one input of the three-input arithmetic unit OP12. Similarly, the output of the calculator OP12 is connected to the two inputs of the calculator OP14 and the one input of the three-input calculator OP13, respectively. The output of the arithmetic unit OP13 is connected to one input of the three-input arithmetic unit OP14.
The output of the calculator OP15 is connected to the two inputs of the calculators OP17 and OP18 and the one input of the three-input calculator OP16. Similarly, the output of the arithmetic unit OP16 is connected to the two inputs of the arithmetic unit OP18 and the one input of the three-input arithmetic unit OP17. The output of the computing unit OP17 is connected to one input of the 3-input computing unit OP18.
[0085]
As described above, in the pixel engine (PXE) 13122 of FIG. 12, the output of the computing unit OP1 is connected to the computing units OP2, OP3, and OP4 through the forwarding path, and the computing units OP2, OP3, and OP4 are connected to the computing unit. The output of OP1 can be referenced as a source operand.
The output of the computing unit OP2 is connected to the computing units OP3 and OP4 through a forwarding path, and the computing units OP3 and OP4 can refer to the output of the computing unit OP2 as a source operand.
The output of the computing unit OP3 is connected to the computing unit OP4 through a forwarding path, and the computing unit OP4 can refer to the output of the computing unit OP3 as a source operand.
The output of the arithmetic unit OP5 is connected to the arithmetic units OP6, OP7, and OP8 by a forwarding path, and the outputs of the arithmetic units OP6, OP7, OP8, and the arithmetic unit OP5 can be referred to as source operands.
The output of the arithmetic unit OP6 is connected to the arithmetic units OP7 and OP8 through a forwarding path, and the arithmetic units OP7 and OP8 can refer to the output of the arithmetic unit OP6 as a source operand.
The output of the computing unit OP7 is connected to the computing unit OP8 through a forwarding path, and the computing unit OP8 can refer to the output of the computing unit OP7 as a source operand.
Similarly, the output of the computing unit OP11 is connected to the computing units OP12, OP13, and OP14 through a forwarding path, and the computing units OP12, OP13, and OP14 can refer to the output of the computing unit OP11 as a source operand.
The output of the computing unit OP12 is connected to the computing units OP13 and OP14 through a forwarding path, and the computing units OP13 and OP14 can refer to the output of the computing unit OP12 as a source operand.
The output of the computing unit OP13 is connected to the computing unit OP14 through a forwarding path, and the computing unit OP14 can refer to the output of the computing unit OP13 as a source operand.
The output of the computing unit OP15 is connected to the computing units OP16, OP17, OP18 through a forwarding path, and the outputs of the computing units OP16, OP17, OP18, and the computing unit OP15 can be referred to as source operands.
The output of the computing unit OP16 is connected to the computing units OP17 and OP18 through a forwarding path, and the computing units OP17 and OP18 can refer to the output of the computing unit OP16 as a source operand.
The output of the computing unit OP17 is connected to the computing unit OP18 through a forwarding path, and the computing unit OP18 can refer to the output of the computing unit OP17 as a source operand.
The lookup tables LUT1, LUT2, LUT11, and LUT12 are, for example, RAM-LUTs that can be arbitrarily defined. Up to L (L: the number of tables that can be referred to simultaneously) can be referenced in one context. The lookup tables LUT1, LUT2, LUT11, and LUT12 hold elementary functions such as sin / cos.
[0086]
  In the above configuration, regarding the number of connections between the pixel engine (PXE) 13122 and the register unit (RGU) 13124, the crossbar circuit (IXB) The number of connections CN1 to 13125 is as follows.
[0087]
[Expression 1]
CN1 = (number of arithmetic units + number of LUTs that can be referred simultaneously) × 1
[0088]
The number of connections CN2 from the register unit (RGU) 13124 to the pixel engine (PXE) 13122 is as follows.
[0089]
[Expression 2]
CN2 = number of arithmetic units × 2 + number of LUTs that can be referred to simultaneously × 1
[0090]
The pixel engine (PXE) 13122 having the above configuration is set to a desired FIFO register of the register unit (RGU) 13124 via the crossbar circuit 13125 and is directly input from the FIFO register, for example, at the time of graphics processing. Operation result data (TR1, TG1, TB1, TA1) and (TR2, TG2, TB2, TA2) in the pixel operation processor (POP) group 13123, and a desired FIFO register of the register unit (RGU) 13124 are set by the rasterizer 1311. Based on the primary color (PC), secondary color (SC), and Fog coefficient (F) directly input from the FIFO register, an operation such as a pixel shader is performed. , Color data (FR1, FG1, FB1) and mixing value (a blend value: FA1) Request.
The pixel engine (PXE) 13122 transfers this data (FR1, FG1, FB1, FA1) in a predetermined POP of the pixel arithmetic processor (POP) group 13123 or via the crossbar circuit 13125 and the register unit (RGU) 13124. It transfers to the light unit WU provided separately.
[0091]
The pixel operation processor (POP) group 13123 includes a plurality of POPs, which are functional units that perform highly parallel operation processing utilizing the memory bandwidth, and in this embodiment, for example, four POP0 to POP3 as shown in FIG. Have.
Each POP has a plurality of arithmetic units called POPE (Pixel Operation Processing Elements) arranged in parallel. It also has an address generation function for the memory.
Since the pixel operation processor (POP) group 13123 and the cache are connected with a wide bandwidth and have a built-in address generation function for memory access, stream data that maximizes the computing capability of the computing unit. Can be supplied.
[0092]
The pixel operation processor (POP) group 13123 performs, for example, the following processing at the time of graphics processing.
For example, based on the values of (s1, t1, lod1) and (s2, t2, lod2) directly supplied from the graphics unit (GRU) 13121, (u, v) address calculation for texture access is performed. , (U, v) coordinates of four neighbors for performing four-neighbor filtering based on the address data (ui, vi, lodi), that is, (u0, v0), (u1, v1), (u2, v2), (U3, v3) is calculated and supplied to the memory controller MC, and desired texel data is read from the memory module 132 to each POPE through, for example, the read-only cache RO $.
The pixel operation processor (POP) group 13123 calculates a texture filter coefficient K based on data (uf, vf, lodf) for coefficient generation and supplies the texture filter coefficient K to each POPE.
In each POP of the pixel arithmetic processor (POP) group 13123, color data (TR, TG, TB) and a mixed value (blend value: TA) are obtained, and (TR, TG, TB, TA) is obtained as a crossbar circuit 13125. Then, the data is transferred to the pixel engine (PXE) 13122 via the register unit (RGU) 13124.
[0093]
On the other hand, the pixel operation processor (POP) group 13123 performs, for example, the following processing during image processing.
The pixel operation processor (POP) group 13123 is generated by, for example, the rasterizer 1311 and set in the register unit (RGU) 13124, and is supplied directly without passing through the crossbar circuit 13125 through the graphics unit (GRU) 13121. Based on the read source addresses (X1s, Y1s) and (X2s, Y2s), for example, the image data stored in the memory module 132 is read and read via the read-only cache RO $ and / or the read-write cache RW $. A predetermined calculation process is performed on the data, and the calculation result is transferred to the write unit WU via the crossbar circuit 13125 and the register unit (RGU) 13124.
[0094]
A more specific configuration of the POP having the above-described function will be described in detail later.
[0095]
A register unit (RGU) 13124 is a FIFO-structured register file that stores stream data processed by each functional unit in the core 1312.
In addition, when the DFG must be divided into a plurality of sub-DFGs (Sub-DFGs) and executed due to hardware resources, it also functions as an intermediate value storage buffer between the sub-DFGs.
As shown in FIG. 12, the output of the FIFO register FREG in the register unit (RGU) 13124, the pixel engine (PXE) 13122 which is a functional unit, and the input ports of the respective arithmetic units of the pixel arithmetic processor (POP) group 13123 are One-to-one correspondence.
[0096]
The crossbar circuit 13125 realizes this connection switching so that the core 1312 can cope with various algorithms by changing the connection between the functional units according to the DFG.
As described above, the output of the FIFO register FREG in the register unit (RGU) 13124 and the input port of the functional unit are fixed and correspond one-to-one, but the output port of the functional unit and the FIFO in the register unit (RGU) 13124 The input of the register FREG is switched by the crossbar circuit 13125.
[0097]
FIG. 14 is a diagram illustrating a connection form between a POP (pixel arithmetic processor) and a memory and a configuration example of the POP.
The example of FIG. 14 is a case where each POP (0 to 3) has four arithmetic units POPE0 to POPE3 arranged in parallel.
[0098]
In this embodiment, the image data is stored in the memory module 132 (-0 to -3) of the local module 13 (-0 to -3), but the local module 13 (-0 to -3) , POP (0 to 3) and the memory module 132 are divided local caches D133 (-0 to -3), respectively.
In such a configuration, when pixel-level parallel processing is performed in POP0 to POP3, there are the following two methods for accessing image data.
The first is a method in which image data stored in the memory module 132 is directly read to perform calculation.
The second method is a method in which a part of the image data stored in the memory module 132 required for the operation is stored in the local cache 133 and the operation is performed by reading the data in the local cache 133.
[0099]
In the present embodiment, the above-described second method is employed.
In the local cache 133, read-only caches RO $ 0 to RO $ 3 and read / write caches RW $ 0 to RW $ 3 are arranged corresponding to POPE0 to POPE3 of POP (0 to 3), respectively.
[0100]
The local cache 133 includes selectors SEL1 to SEL12 and sort circuits SRT0 to SRT3.
The selectors SEL1 to SEL4 select either read data of 32-bit width from the corresponding read line ports p (0) to p (3) of the memory module 132 or read data from other ports, and read / write The data is output to the caches RW $ 0 to RW $ 3 and the selectors SEL9 to SEL12.
The selector SEL5 selects any one of the depth data, the color (RGB) data, and the mixed value (α) data relating to the pixel output from the POP POPE0 or the sort circuit SRT1 to the read / write cache RW $ 0. Supply. The selector SEL5 supplies the read depth data value read from the read / write port p (0) to the read / write cache RW $ 0 to the sort circuit SRT0.
The selector SEL6 selects any one of the calculation result of the POP POPE1 or the depth data, color (RGB) data, and mixed value (α) data related to the pixels output from the sort circuit SRT2 to the read / write cache RW $ 1. Supply. The selector SEL6 supplies the read depth data value read from the read / write port p (1) to the read / write cache RW $ 1 to the sort circuit SRT1.
The selector SEL7 selects any of depth data, color (RGB) data, and mixed value (α) data related to the pixel output from the POP POPE2 or the sort circuit SRT3, and stores it in the read / write cache RW $ 2. Supply. The selector SEL7 supplies the read depth data value read from the read / write port p (2) to the read / write cache RW $ 2 to the sort circuit SRT2.
The selector SEL8 selects either the calculation result of POP POPE3 or the depth data, the color (RGB) data, and the mixed value (α) data related to the pixels output from the sort circuit SRT4 to the read / write cache RW $ 3. Supply. The selector SEL8 supplies the read depth data value read from the read / write port p (3) to the read / write cache RW $ 3 to the sort circuit SRT3.
The selector SEL9 selects either the data from the selector SEL1 or the data transferred by the global module 12 and supplies it to the read-only cache RO $ 0.
The selector SEL10 selects either the data from the selector SEL2 or the data transferred by the global module 12 and supplies the selected data to the read-only cache RO $ 1.
The selector SEL11 selects either the data from the selector SEL3 or the data transferred by the global module 12 and supplies the selected data to the read-only cache RO $ 2.
The selector SEL12 selects either the data from the selector SEL4 or the data transferred by the global module 12 and supplies the selected data to the read-only cache RO $ 3.
[0101]
Each POP (0 to 3) has a write unit WU, a filter function unit FFU, an output selection circuit OSLC, and an address generator AG in addition to four arithmetic units POPE0 to POPE3 arranged in parallel.
[0102]
The light unit WU supplies, for example, the first supply depth data value for drawing via the register unit (RGU) 13124 to each of the sort circuits SRT0 to SRT3 in the translucent object synthesis mode.
In the example of FIG. 14, an example in which the light unit WU is provided in each POP is shown. However, for example, as shown in FIG. The supply depth data value may be supplied to each of the sort circuits SRT0 to SRT3 and SRT4 to SRT7 of the plurality of divided memory modules D133 arranged in parallel.
[0103]
The memory module 132 is divided into a plurality of buffers BUF0 to BUF3 (in FIG. 15, BUF0 to BUF7).
In each of the buffers BUF0 to BUF3, data relating to an image is stored. In this data, for example, depth data whose value varies depending on the depth and depth position used also in the semi-transparent object synthesis mode, and corresponding to this Color (RGB) data and mixed value (α) data to be stored are stored.
Hereinafter, color (RGB) data and mixed value (α) data are indicated as RGBα data.
[0104]
The sort circuits SRT0 to SRT3 (in FIG. 15, SRT0 to SRT7, based on the configuration in FIG. 14 below) each port p (0) of the plurality of buffers BUF0 to BUF3 (BUF0 to BUF7 in FIG. 15) of the memory module 132. To p (3) (in FIG. 15, p (0) to p (7)).
The sort circuits SRT0 to SRT3 are cascaded from the first stage SRT0 to the final stage SRT3, and read / write caches RW $ 0 to RW $ 3 (RW $ 0 to RW $ 7 in FIG. 15) from the corresponding buffers BUF0 to BUF3. A comparison unit that compares the read depth data value read out in step S1 with the first supplied depth data value ZDRW corresponding to the pixel data supplied together with the RGBα data from the light unit WU for rendering.
When the first supply depth data is larger than (or smaller than) the read depth data as a result of comparison by the comparison unit, the sort circuits SRT0 to SRT3 receive the supplied first supply depth data and RGBα data in the next stage. The depth data and RGBα data read out supplied to the sort circuit are written back to the corresponding buffers BUF0 to BUF3.
On the other hand, when the first supply depth data is smaller than (or larger than) the read depth data as a result of the comparison by the comparison unit, the sort circuits SRT0 to SRT3 use the read depth data and RGBα data as the next sort circuit. And the second supply depth data and RGBα data from the previous stage are written into the corresponding buffers BUF0 to BUF3.
[0105]
Further, when the first supply depth data is smaller (or larger) than the read depth data, the first-stage sort circuit SRT0 supplies the read depth data and RGBα data to the next-stage sort circuit SRT1 for supply. The first supplied depth data and RGBα data are written to the corresponding buffer BUF0 via the read / write cache RW $ 0.
In addition, when the depth data value is not stored in the corresponding buffers BUF1 to BUF3, the sorting circuits SRT1 to SRT3 in the second and subsequent stages correspond to the second supply depth data value ZNBR and the RGBα data from the previous stage. Are written in the buffers BUF1 to BUF3.
[0106]
FIG. 16 is a block diagram illustrating a specific configuration example of the sort circuit according to the present embodiment.
As shown in FIG. 16, the sort circuit SRT (0 to 3) includes a comparison unit (CMP) 301, a supply data selection unit (SDSEL) 302, and a write data selection unit (WDSEL) 303.
[0107]
The comparison unit 301 corresponds to the read depth data value ZRD read from the corresponding buffer BUF (0 to 3) to the read / write cache RW $ (0 to 3) and the pixel data supplied from the light unit WU for drawing. The first supply depth data value ZDRW is compared, and if the comparison result of the comparison unit shows that the first supply depth data value ZDRW is larger than the read depth data value ZRD (ZDRW> ZRD), the low level (logic 0) is output to the supply data selection unit 302 and the write data selection unit 303.
On the other hand, when the comparison result of the comparison unit indicates that the first supply depth data value ZDRW is smaller than the read depth data value ZRD (when (ZDRW <ZRD), the control signal CTL 301 at the high level (logic 1). Are output to the supply data selection unit 302 and the write data selection unit 303.
[0108]
The supply data selection unit 302 supplies the read depth data value ZRD and RGBα data read from the corresponding buffer BUF (0 to 3) to the read / write cache RW $ (0 to 3) and the write unit WU for drawing. When the first supply depth data value ZDRW and RGBα data corresponding to the processed pixel data are input and the low-level control signal CTL301 is received from the comparison unit 301, the first supply depth data value ZDRW and RGBα data are selected. When the high-level control signal CTL 301 is received, the read depth data value ZRD and RGBα data are selected and the next-stage sort circuit SRT (1-3) is supplied to the next-stage sort circuit SRT (1-3). ).
[0109]
The write data selection unit 303 reads the read depth data value ZRD and RGBα data read from the corresponding buffer BUF (0 to 3) into the read / write cache RW $ (0 to 3) and the preceding sort circuit SRT (0 to 0). 2), when the second supply depth data value ZNBR (first sort circuit SRT0 is supplied with the first supply depth data value ZDRW) and RGBα data, and receives the low-level control signal CTL301 from the comparison unit 301, When the read depth data value ZRD and RGBα data are selected and written back to the corresponding buffers BUF0 to BUF3, and the high level control signal CTL301 is received, the second supply depth data ZNBR (or the first supply) from the previous stage is received. Depth data value ZDRW) and RGBα data corresponding buffer BUF0 Write to BUF3.
[0110]
FIG. 17 is a diagram for explaining the operation in the semi-transparent object composition mode using the sort circuit.
In this example, Z = 25 and RGBα data depth data are stored in the buffer BUF0, Z = 32 depth data and RGBα data are stored in the buffer BUF1, and Z = 40 depth data and RGBα data are stored in the buffer BUF2. These are read out by the sort circuits SRT0 to SRT2.
[0111]
First, in cycle 1, the first supply depth data value ZDRW and RGBα data of Z = 29 are supplied from the light unit WU to each sort circuit SRT0 to SRT3 for drawing.
In the first-stage sort circuit SRT0, the comparison result of the comparison unit 301 is that the first supply depth data value ZDRW (= 29) is larger than the read depth data ZRD (= 25). Is output to the supply data selection unit 302 and the write data selection unit 303.
As a result, in the supply data selection unit 302, the first supply depth data value ZDRW (= 29) and RGBα data are selected and supplied to the next-stage sort circuit SRT1.
In parallel with this, the write data selection unit 303 selects the read depth data value ZRD (= 25) and RGBα data and writes them back to the corresponding buffer BUF0.
[0112]
In the second-stage sort circuit SRT1, since the comparison result of the comparison unit 301 is that the first supply depth data value ZDRW (= 29) is smaller than the read depth data ZRD (= 32), the high-level control is performed. A signal CTL 301 is output to the supply data selection unit 302 and the write data selection unit 303.
As a result, in the supply data selection unit 302, the read depth data ZRD (= 32) and the RGBα data are selected and supplied to the next-stage sort circuit SRT2.
In parallel with this, the write data selection unit 303 selects the second supply depth data ZNBR (= 29) and the RGBα data from the previous stage and writes them in the corresponding buffer BUF1.
[0113]
  In the third-stage sort circuit SRT2, since the comparison result of the comparison unit 301 is that the first supply depth data value ZDRW (= 29) is smaller than the read depth data ZRD (= 40), a high level control is performed. A signal CTL 301 is output to the supply data selection unit 302 and the write data selection unit 303.
  As a result, the supply data selection unit 302 selects the read depth data ZRD (= 40) and the RGBα data, and the next sort circuit SRT.3To be supplied.
  In parallel with this, the write data selection unit 303 selects the second supply depth data ZNBR (= 32) and RGBα data from the previous stage and writes them to the corresponding buffer BUF2.
[0114]
In the fourth-stage sort circuit SRT3, since the comparison by the comparison unit 301 does not include the read depth data ZRD, a high-level control signal CTL301 is output to the supply data selection unit 302 and the write data selection unit 303.
As a result, the supply data selection unit 302 selects the read depth data ZRD (= 40) and RGBα data, but does not supply the next stage.
In parallel with this, the write data selection unit 303 selects the second supply depth data ZNBR (= 40) and RGBα data from the previous stage and writes them to the corresponding buffer BUF3.
[0115]
As described above, in the image processing apparatus 10, the synthesis (Order Independent Transparency) of a plurality (four in the case of FIG. 14) of semi-transparent objects can be easily realized in hardware.
Then, it is possible to perform superposition with an arbitrary number of layers, and to reduce the number of times that all scene data flows. As a result, the load on the processing unit for scene data can be reduced, and the processing speed can be increased.
[0116]
For example, as shown in FIG. 18, a plurality of memory banks BNK including a plurality of buffers are arranged in multiple stages (four stages of 0 to 3 in FIG. 18), and provided corresponding to each buffer of the same memory bank. The sort circuits SRT0 to SRT3, SRT4 to SRT7, SRT8 to SRT11, SRT12 to SRT15 are cascade-connected to each other, and are provided corresponding to the respective buffers of the memory banks BNK0 to BNK3. SRT3, SRT4 to SRT7, SRT8 to SRT11, SRT12 to SRT15 are provided corresponding to the respective buffers of the preceding memory banks BNK0 to BNK3, and the final stages SRT3, SRT7, It is configured to supply output depth data of SRT11 and SRT15. The vertical four-stage, four horizontal stages by complex, it is possible to synthesize the 16 layers.
[0117]
The filter function unit FFU supplies the operation parameters set in the FIFO register in the register RGU unit (RGU) 13124 to each POPE0 to POPE3, specifically, the filter coefficient K to each POPE0 to POPE3.
[0118]
POPE0 receives the 32-bit width data read from the read-only cache RO $ 0 or the read / write cache RW $ 0 and the operation parameter by the filter function unit FFU, performs a predetermined operation (for example, addition), and performs an operation result. Is output to POPE1 in the next stage. POPE0 has an 8-bit × 4 output line OTL0 for outputting the predetermined calculation result to the output selection circuit OSLC.
POPE0 is set in the register unit (RGU) 13124, receives the 8-bit × 4 32-bit data transferred through the crossbar circuit 13125, performs a predetermined operation, and performs the operation on the divided local cache D133 ( 0) to the read / write cache RW $ 0 via the selector SEL5.
[0119]
POPE1 receives a 32-bit width data read from read-only cache RO $ 1 or read-write cache RW $ 1 and an operation parameter by filter function unit FFU, and performs a predetermined operation (for example, addition), and the operation result And the operation result are added by POPE0 and output to POPE2 in the next stage. The POPE1 has an 8-bit × 4 output line OTL1 for outputting the predetermined calculation result to the output selection circuit OSLC.
The POPE 1 is set in the register unit (RGU) 13124, receives the 8-bit × 4 32-bit data transferred through the crossbar circuit 13125, performs a predetermined operation, and performs the operation on the divided local cache D133 ( 0) to the read / write cache RW $ 1 via the selector SEL6.
[0120]
POPE2 receives the 32-bit width data read from the read-only cache RO $ 2 or the read-write cache RW $ 2 and the operation parameter by the filter function unit FFU, and performs a predetermined operation (for example, addition). And POPE1 add the calculation results and output the result to POPE3 in the next stage. Further, POPE2 has an 8-bit × 4 output line OTL2 for outputting the predetermined calculation result to the output selection circuit OSLC.
The POPE2 is set in the register unit (RGU) 13124, receives the 8-bit × 4 32-bit data transferred through the crossbar circuit 13146, performs a predetermined operation, and performs the operation on the divided local cache D133 ( 0) to the read / write cache RW $ 2 via the selector SEL7.
[0121]
POPE3 receives the 32-bit width data read from the read-only cache RO $ 3 or the read / write cache RW $ 3 and the operation parameter by the filter function unit FFU and performs a predetermined operation (for example, addition), and the operation result And the operation result are added by POPE2, and this operation result (total in one POP) is output to the output selection circuit OSLC via the 8-bit × 4 output line OTL3.
The POPE 3 is set in the register unit (RGU) 13124, receives the 8-bit × 4 32-bit data transferred through the crossbar circuit 13125, performs a predetermined operation, and performs the operation on the divided local cache D133 ( 0) to the read / write cache RW $ 3 via the selector SEL8.
[0122]
FIG. 19 is a circuit diagram showing a specific configuration example of POPE (0 to 3) according to the present embodiment.
As shown in FIG. 19, this POPE has multiplexers (MUX) 401 to 405, an adder / subtracter (addsub) 406, a multiplier (mul) 407, an adder / subtractor (addsub) 408, and an integration register 409.
[0123]
The multiplexer 401 stores data read from the register unit (RGU) 13124, operation parameters by the filter function unit FFU, read-only cache RO $ (0-3), or read-write cache RW $ (0-3). One of them is selected and supplied to the adder / subtracter 406.
[0124]
The multiplexer 402 selects one of the data read from the register unit (RGU) 13124, the read-only cache RO $ (0-3), or the data read from the read-write cache RW $ (0-3). To the adder / subtractor 406.
[0125]
The multiplexer 403 stores the data read from the register unit (RGU) 13124, the calculation parameter by the filter function unit FFU, the read-only cache RO $ (0-3), or the read-write cache RW $ (0-3). One of them is selected and supplied to the multiplier 407.
[0126]
The multiplexer 404 selects either the calculation result of the previous stage POPE (0 to 2) or the output data of the integration register 409 and supplies it to the adder / subtractor 408.
[0127]
The multiplexer 405 stores the data read from the register unit (RGU) 13124, the calculation parameter by the filter function unit FFU, the read-only cache RO $ (0 to 3), or the data read from the read / write cache RW $ (0 to 3). One of them is selected and supplied to the adder / subtractor 408.
[0128]
  The adder / subtracter 406 adds (subtracts) the selection data of the multiplexer 401 and the selection data of the multiplexer 402 and outputs the result to the multiplier 407.
The multiplier 407 multiplies the output data of the adder / subtracter 406 and the selection data of the multiplexer 403 and outputs the result to the adder / subtractor 408.
  The adder / subtracter 408 adds (subtracts) the output data from the multiplier 407, the selection data of the multiplexer 404, and the selection data of the multiplexer 405, and outputs the result to the integration register 409.
  Then, the data held in the integration register 409 is converted into the operation result of each POPE.FruitThen, it is output to the output selection circuit OSLC and the next stage POPE (1 to 3).
[0129]
The output selection circuit OSLC has a function of selecting any of the operation data transferred from the output lines OTL0 to OTL3 of the POPE0 to P0PE3 and outputting the selected operation data to the crossbar circuit 13125.
In the present embodiment, the output selection circuit OSLC is configured to select the operation data transferred through the output line OTL3 of POPE3 that outputs the total in one POP and output it to the crossbar circuit 13125.
The calculation data output to the crossbar circuit 13125 is set in the register unit 13124, and the setting data is directly supplied to a predetermined calculator of the pixel engine 13122 without passing through the crossbar circuit 13125.
[0130]
As shown in FIG. 20, the address generator AG performs data transfer from the memory module 132 simultaneously in one column (for four POPs) and reads each of the divided local caches D133 (0) to D133 (3). Since the access to the only cache RO $ 0 to RO $ 3 or the read / write cache RW $ 0 to RW $ 3 is performed independently, each read only cache RO $ 0 to RO $ 3 or the read / write cache RW $. The cache addresses CADR0 to CADR3 for reading the element data read in parallel from the ports p (0) to p (3) of the memory module 132 to the corresponding POPE0 to POPE3 at 0 to RW $ 3, respectively. Generate and supply.
For example, the operation result OPR0 of POPE0 is supplied to POPE1 at the timing when the operation of POPE1 ends, and the operation result of POPE1 (the result of adding the operation result OPR0 of POPE0) OPR1 ends the operation of POPE2. The read-only caches RO $ 0 to RO $ 0 are supplied to the POPE2 at the timing of the operation, and the operation result of the POPE2 (the result of adding the operation result OPR1 of the POPE1) OPR2 is supplied to the POPE3 at the timing when the operation of the POPE3 is completed. Cache addresses CADR0 to CADR3 are supplied to RO $ 3 or read / write caches RW $ 0 to RW $ 3 with a predetermined timing shift.
For example, when the number of element data supplied to each of POPE0 to POPE3 is the same and the element data is sequentially added to each of POPE0 to POPE3, the address supply is performed by sequentially shifting the address supply timing by one address.
As a result, computation without mistakes can be performed efficiently. That is, in the core 1312 according to the present embodiment, the calculation efficiency is improved.
[0131]
  Next, the memory dataInBased on the calculation processing performed by the pixel arithmetic processor group 13123 and further performed by the pixel engine 13122, the operation will be described with reference to FIGS.
  Here, as shown in FIG. 22A, an example will be described in which calculation is performed on 16 × 16 element data of 16 × 16 columns.
[0132]
Step ST51
First, in step ST51, one row (for four POPs) is simultaneously transferred from the memory module (eDRAM) 132 to the read-only caches RO $ 0 to RO $ 3 of the local cache 133.
Next, as shown in FIGS. 23 (A), (C), (E), and (G), the address generator AG sequentially shifts the addresses one by one to POPE0 to POPE3 in one POP. Thus, the cache addresses CADR0 to CADR3 are supplied.
As a result, the 16 element data are sequentially read into the POPE0 to POPE3 of the POP0 to POP3.
[0133]
For example, the cache addresses CADR00 to CADR0F are sequentially given to the read-only cache RO $ 0 of the divided local cache D133 (0), and in response to this, the data 00 to 0F for one column is read to POPE0 of POP0.
Similarly, the cache addresses CADR10 to CADR1F are sequentially given to the read-only cache RO $ 1 of the divided local cache D133 (0), and in response to this, the data 10 to 1F for one column is read to POPE1 of POP0.
The cache addresses CADR20 to CADR2F are sequentially given to the read-only cache RO $ 2 of the divided local cache D133 (0), and in response to this, the data 20 to 2F for one column is read to POPE2 of POP0.
Cache addresses CADR30 to CADR3F are sequentially given to the read-only cache RO $ 3 of the divided local cache D133 (0), and in response to this, data 30 to 3F for one column is read to POPE3 of POP0.
[0134]
Cache addresses CADR40 to CADR4F are sequentially given to the read-only cache RO $ 0 of the divided local cache D133 (1), and in response to this, the data 40 to 4F for one column is read to POPE0 of POP1.
Similarly, the cache addresses CADR50 to CADR5F are sequentially given to the read-only cache RO $ 1 of the divided local cache D133 (1), and in response to this, the data 50 to 5F for one column is read to the POPE1 of the POP1.
Cache addresses CADR60 to CADR6F are sequentially given to the read-only cache RO $ 2 of the divided local cache D133 (1), and in response to this, the data 60 to 6F for one column is read to POPE2 of POP1.
Cache addresses CADR70 to CADR7F are sequentially given to the read-only cache RO $ 3 of the divided local cache D133 (1), and in response to this, the data 70 to 7F for one column is read to POPE3 of POP1.
[0135]
Cache addresses CADR80 to CADR8F are sequentially given to the read-only cache RO $ 0 of the divided local cache D133 (2), and in response to this, the data 80 to 8F for one column is read to POPE0 of POP2.
Similarly, the cache addresses CADR90 to CADR9F are sequentially given to the read-only cache RO $ 1 of the divided local cache D133 (2), and in response to this, the data 90 to 9F for one column is read to the POPE1 of the POP2.
Cache addresses CADRA0 to CADRAF are sequentially given to the read-only cache RO $ 2 of the divided local cache D133 (2), and in response to this, the data A0 to AF for one column is read to POPE2 of POP2.
Cache addresses CADRB0 to CADRBF are sequentially given to the read-only cache RO $ 3 of the divided local cache D133 (2), and in response to this, the data B0 to BF for one column is read to POPE3 of POP2.
[0136]
Cache addresses CADRC0 to CADRCF are sequentially given to read-only cache RO $ 0 of divided local cache D133 (3), and in response to this, data C0 to CF for one column is read to POPE0 of POP3.
Similarly, the cache addresses CADRD0 to CADRDF are sequentially given to the read-only cache RO $ 1 of the divided local cache D133 (3), and in response to this, the data D0 to DF for one column is read to POPE1 of POP3.
Cache addresses CADRE0 to CADREF are sequentially given to the read-only cache RO $ 2 of the divided local cache D133 (3), and in response to this, the data E0 to EF for one column is read to POPE2 of POP3.
Cache addresses CADRF0 to CADRFF are sequentially given to the read-only cache RO $ 3 of the divided local cache D133 (3), and in response to this, the data F0 to FF for one column is read to POPE3 of POP3.
[0137]
Step ST52
In step ST52, one element (16 pieces) is added to each POPE0 to POPE3 of each POP (0 to 3).
Specifically, in POPE0 of POP0, as shown in FIG. 23B, data 00 to 0F are sequentially added, and the operation result OPR0 is output to POPE1.
In POPE1 of POP0, data 10 to 1F are sequentially added as shown in FIG.
In POPE2 of POP0, data 20 to 2F are sequentially added as shown in FIG.
In POPE3 of POP0, as shown in FIG. 23 (H), data 30 to 3F are sequentially added.
The same applies to the other POP1 to POP3.
[0138]
Step ST53
In step ST53, the calculation results of POPE0 to POPE3 of each POP (0 to 3) are added to obtain an addition result of 16 × 4 elements.
Specifically, as shown in FIGS. 23B and 23D, the operation result OPR0 of POPE0 of POP0 is output to POPE1.
In POPE1 of POP0, as shown in FIGS. 23D and 23F, the operation result OPR0 of POPE0 of POP0 is added to its own operation result, and the operation result OPR1 is output to POPE2.
In POPE2 of POP0, as shown in FIGS. 23F and 23H, the operation result OPR1 of POPE1 of POP0 is added to its own operation result, and the operation result OPR2 is output to POPE3.
Then, in POPE3 of POP0, as shown in FIG. 23H, the calculation result OPR2 of POPE2 of POP0 is added to its own calculation result, and the calculation result OPR3 is output to the output selection circuit OSLC.
The same applies to the other POP1 to POP3.
[0139]
Step ST54
In step ST54, the total calculation result OPR3 is transferred from the output selection circuit OSLC of each POP0 to POP3 to the register unit (RGU) 13124 via the crossbar circuit 13125.
For example, as shown in FIG. 24, the total operation result OPR3 of POPE3 of POP0 is stored in the FIFO register FREG1 of the register unit (RGU) 13124 via the crossbar circuit 13125.
The total operation result OPR3 of POPE3 of POP1 is stored in the FIFO register FREG2 of the register unit (RGU) 13124 via the crossbar circuit 13125.
The total operation result OPR3 of POPE3 of POP2 is stored in the FIFO register FREG3 of the register unit (RGU) 13124 via the crossbar circuit 13125.
The total operation result OPR3 of POPE3 of POP3 is stored in the FIFO register FREG4 of the register unit (RGU) 13124 via the crossbar circuit 13125.
[0140]
Step ST55
In step ST55, the total operation results of POP0 and POP1 set in the FIFO registers FREG1 and FREG2 of the register unit (RGU) 13124 are added by the first adder ADD1 of the pixel engine (PXE) 13122. Is stored in the FIFO register FREG5 of the register unit (RGU) 13124 via the crossbar circuit 13125.
The total operation result of POP2 and POP3 set in the FIFO registers FREG3 and FREG4 of the register unit (RGU) 13124 is added by the second adder ADD2 of the pixel engine (PXE) 13122, and this operation result is crossbar. The data is stored in the FIFO register FREG6 of the register unit (RGU) 13124 via the circuit 13125.
Then, the operation results of the first and second adders ADD1 and ADD2 set in the FIFO registers FREG5 and FREG6 of the register unit (RGU) 13124 are added by the third adder ADD3 of the pixel engine (PXE) 13122. The
[0141]
Step ST56
In step ST56, as shown in FIG. 23 (P), the addition result of the third adder ADD3 of the pixel engine (PXE) 13122 is output as a series of calculation results.
[0142]
FIG. 25 is a diagram showing an operation outline including a core pixel engine (PXE) 13122, a pixel operation processor (POP) group 13123, a register unit (RGU) 13124, and a memory portion in the processing unit according to the present embodiment.
[0143]
In FIG. 25, the broken line indicates the flow of address data, the alternate long and short dash line indicates the flow of read data, and the solid line indicates the flow of write data.
In the register unit (RGU) 13124, FREGA1 and FREGA2 indicate FIFO registers used for the address system, FREGR indicates a FIFO register used for read data, and FREGW indicates a FIFO register used for write data.
[0144]
In the example of FIG. 25, for example, source (read) address data generated by the rasterizer 1311 is set in the FIFO registers FREGA1 and FREGA2 of the register unit (RGU) 13124 via the crossbar circuit 13125.
The address data set in the FIFO register FREGA1 is directly supplied to the address generator AG1 of the pixel operation processor (POP) 13123 without going through the crossbar circuit 13125, for example. The address generator AG1 generates an address of data to be read, and based on this, desired data read from the memory module 132 to the read-only cache 1331 is supplied to each calculator (POPE) of the pixel calculation processor (POP) 13123. Is done.
[0145]
An operation result of each operation unit (POPE) of the pixel operation processor (POP) 13123 is set in the FIFO register FREGR of the register unit (RGU) 13124 via the crossbar circuit 13125.
The data set in the FIFO register FREGR is directly supplied to each arithmetic unit OP of the pixel engine (PXE) 13122 without passing through the crossbar circuit 13125.
Then, the calculation result of each calculator OP of the pixel engine (PXE) 13122 is set in the FIFO register FREGW of the register unit (RGU) 13124 via the crossbar circuit 13125.
The data set in the FIFO register FREGW is supplied to each arithmetic unit (POPE) of the pixel arithmetic processor (POP) 13123.
[0146]
Also, the destination (write) address data generated by the rasterizer 1311 is set in the FIFO register FREGA2 of the register unit (RGU) 13124 via the crossbar circuit 13125.
The address data set in the FIFO register FREGA2 is directly supplied to the address generator AG2 of the pixel arithmetic processor (POP) 13123 without passing through the crossbar circuit 13125. An address of data to be written is generated in the address generator AG2, and based on this, the calculation result of each calculator (POPE) of the pixel calculation processor (POP) 13123 is written in the read / write cache 1332 and further written in the memory module 132. .
[0147]
In the example of FIG. 25, it is described that the read / write cache 1332 performs only writing, but reading is performed by the same operation as that of the read-only cache 1331 described above.
[0148]
Next, specific operations in the case of graphics processing and image processing in the processing unit 131 (-0 to -3) having the above configuration will be described with reference to the drawings.
[0149]
First, graphics processing in the case of no dependent texture will be described with reference to FIGS.
[0150]
In this case, the rasterizer 1311 receives the parameter data broadcast from the global module 12 and determines, for example, whether or not the triangle is an area for which it is in charge. Is generated and supplied to the core 1312.
Specifically, in the rasterizer 1311, window coordinates (X, Y, Z), primary color (PC; Rp, Gp, Bp, Ap), secondary color (SC; Rs, Gs, Bs, As), Fog coefficient ( f) Various pixel data of texture coordinates and various vectors (V1x, V1y, V1z) and (V2x, V2y, V2z) are generated.
[0151]
Then, the generated window coordinates (X, Y, Z) are directly stored in the pixel arithmetic processor (POP) group 13123 or separately through a specific FIFO register of the register unit (RGU) 13124. Supplied to unit WU.
In addition, the two sets of generated texture coordinate data and various vectors (V1x, V1y, V1z), (V2x, V2y, V2z) are transmitted through the FIFO unit of the crossbar circuit 13125 and register unit (RGU) 13124 to the graphics unit ( GRU) 12121.
Further, the generated primary color (PC), secondary color (SC), and fog coefficient (F) are supplied to the pixel engine (PXE) 13122 through the FIFO register of the crossbar circuit 13125 and the register unit (RGU) 13124.
[0152]
  The graphics unit (GRU) 13121 is based on the supplied texture coordinate data and various vectors (V1x, V1y, V1z) and (V2x, V2y, V2z), and a mipmap based on perspective collection and LOD (Levelof Detail) calculation. (MIPMAP) level calculation, cube map (CubeMap) face selection and normalizationpixelA calculation process of coordinates (s, t) is performed.
Then, two sets of data (s1, t1, lod1), (s2, t2, lod2) generated by the graphics unit (GRU) 13121 including, for example, normalized texel coordinates (s, t) and LOD data (lod) ) Is supplied directly to the pixel operation processor (POP) group 13123 via individual wiring without passing through the crossbar circuit 13125, for example.
[0153]
In the pixel arithmetic processor (POP) group 13123, as shown in FIG. 27, (s1, t1, lod1), (s2, t2, lod2) directly supplied from the graphics unit (GRU) 13121 in the filter function unit FFU. )), (U, v) address calculation for texture access is performed, address data (ui, vi, lodi) is supplied to the address generator AG, and data (uf, vf, lodf) is supplied to the coefficient generation unit COF.
[0154]
The address generator AG receives the address data (ui, vi, lodi), and (u, v) coordinates of four neighbors for performing four-neighbor filtering, that is, (u0, v0), (u1, v1). , (U2, v2), (u3, v3) are calculated and supplied to the memory controller MC.
Accordingly, desired texel data is read from the memory module 132 to each POPE of the pixel operation processor (POP) group 13123 through, for example, the read-only cache RO $.
The coefficient generator COF receives the data (uf, vf, lodf), calculates the texture filter coefficient K (0-3), and supplies it to each corresponding POPE of the pixel operation processor (POP) group 13123. .
In each POP of the pixel arithmetic processor (POP) group 13123, color data (TR, TG, TB) and a mixed value (blend value: TA) are obtained, and two sets of data (TR1, TG1, TB1, TA1) are obtained. And (TR2, TG2, TB2, TA2) are transferred through the crossbar circuit 13125 and set in a predetermined FIFO register of the register unit (RGU) 13124, and this setting data is directly passed through the crossbar circuit 13125. Supplied to a pixel engine (PXE) 13122.
[0155]
In the pixel engine (PXE) 13122, data (TR1, TG1, TB1, TA1) and (TR2, TG2, TB2, TA2) by the pixel arithmetic processor (POP) group 13123, and primary color (PC) and secondary by the rasterizer 1311 are used. Based on the color (SC) and the Fog coefficient (F), for example, Pixel Shader is calculated to obtain color data (FR1, FG1, FB1) and a mixed value (blend value: FA1), and this data (FR1, FG1, FB1, FA1) are transferred through the crossbar circuit 13125 and set in a predetermined FIFO register of the register unit (RGU) 13124, and this setting data is directly passed through the pixel operation processor (not via the crossbar circuit 13125). POP) Group 1 123 is supplied to a predetermined POP within or separately provided light unit WU of.
[0156]
In the light unit WU, based on the window coordinates (X, Y, Z) by the rasterizer 1311, for example, the destination color data (RGB), the mixed value data (A), and the depth data (from the memory module 132 through the read / write cache RW $) Z) is read out.
In the write unit WU, data (FR1, FG1, FB1, FA1) by the pixel engine (PXE) 13122, and read destination color data (RGB) and mixed value data (A) from the memory module 132 through the read / write cache RW $. ) And depth data (Z), operations necessary for pixel writing of graphics processing such as α blending, various tests, and logical operations are performed, and the operation result is written back to the read / write cache RW $.
[0157]
Next, the graphics processing when there is a dependent texture will be described with reference to FIGS.
[0158]
In this case, in the rasterizer 1311, window coordinates (X, Y, Z), primary color (PC; Rp, Gp, Bp, Ap), secondary color (SC; Rs, Gs, Bs, As), Fog coefficient (f) Various pixel data of texture coordinates (V1x, V1y, V1z) are generated.
[0159]
Then, the generated window coordinates (X, Y, Z) are supplied directly to the pixel operation processor (POP) group 13124 through a specific FIFO register of the register unit (RGU) 13124.
Further, the generated texture coordinates (V1x, V1y, V1z) are supplied to the graphics unit (GRU) 12121 through the FIFO register of the crossbar circuit 13125 and the register unit (RGU) 13124.
Further, the generated primary color (PC), secondary color (SC), and fog coefficient (F) are supplied to the pixel engine (PXE) 13122 through the FIFO register of the crossbar circuit 13125 and the register unit (RGU) 13124.
[0160]
In the graphics unit (GRU) 13121, based on the supplied texture coordinate (V1x, V1y, V1z) data, perspective collection, calculation of mipmap (MIPMAP) level by LOD calculation, surface selection of cube map (CubeMap), A calculation process of normalized texel coordinates (s, t) is performed.
A set of data (s1, t1, lod1) including, for example, normalized texel coordinates (s, t) and LOD data (lod) generated by the graphics unit (GRU) 13121 is, for example, the crossbar circuit 13125. Without being passed, the pixel operation processor (POP) group 13123 is directly supplied.
[0161]
In the pixel arithmetic processor (POP) group 13123, as shown in FIG. 27, based on the value of (s1, t1, lod1) directly supplied from the graphics unit (GRU) 13121 in the filter function unit FFU, (U, v) address calculation for access is performed, address data (ui, vi, lodi) is supplied to the address generator AG, and data (uf, vf, lodf) is used as a coefficient generator for coefficient calculation. Supplied to the COF.
[0162]
The address generator AG receives the address data (ui, vi, lodi), and (u, v) coordinates of four neighbors for performing four-neighbor filtering, that is, (u0, v0), (u1, v1). , (U2, v2), (u3, v3) are calculated and supplied to the memory controller MC.
Accordingly, desired texel data is read from the memory module 132 to each POPE of the pixel operation processor (POP) group 13123 through, for example, the read-only cache RO $.
The coefficient generator COF receives the data (uf, vf, lodf), calculates the texture filter coefficient K (0-3), and supplies it to each POPE of the pixel operation processor (POP) group 13123.
In each POP of the pixel arithmetic processor (POP) group 13123, color data (TR, TG, TB) and a mixed value (blend value: TA) are obtained, and the data (TR1, TG1, TB1, TA1) are crossed. The bar circuit 13125 is transferred and set in a predetermined FIFO register of the register unit (RGU) 13124, and the setting data is directly supplied to the pixel engine (PXE) 13122 without passing through the crossbar circuit 13125.
[0163]
In the pixel engine (PXE) 13122, data (TR1, TG1, TB1, TA1) by the pixel arithmetic processor (POP) group 13123, primary color (PC), secondary color (SC), and fog coefficient (F) by the rasterizer 1311 are used. For example, Pixel Shader calculation is performed to generate texture coordinates (V2x, V2y, V2z), which are supplied to the graphics unit (GRU) 13121 via the crossbar circuit 13125 and the register unit (RGU) 13124. The
[0164]
In the graphics unit (GRU) 13121, based on the supplied texture coordinate (V2x, V2y, V2z) data, perspective collection, calculation of mipmap (MIPMAP) level by LOD calculation, surface selection of cube map (CubeMap), A calculation process of normalized texel coordinates (s, t) is performed.
Then, data (s2, t2, lod2) including, for example, normalized texel coordinates (s, t) and LOD data (lod) generated by the graphics unit (GRU) 13121 does not pass through the crossbar circuit 13125, for example. Directly supplied to a pixel operation processor (POP) group 13123.
[0165]
In the pixel arithmetic processor (POP) group 13123, as shown in FIG. 27, based on the value of (s2, t2, lod2) directly supplied from the graphics unit (GRU) 13121 in the filter function unit FFU, (U, v) address calculation for access is performed, address data (ui, vi, lodi) is supplied to the address generator AG, and data (uf, vf, lodf) is used as a coefficient generator for coefficient calculation. Supplied to the COF.
[0166]
The address generator AG receives the address data (ui, vi, lodi), and (u, v) coordinates of four neighbors for performing four-neighbor filtering, that is, (u0, v0), (u1, v1). , (U2, v2), (u3, v3) are calculated and supplied to the memory controller MC.
Accordingly, desired texel data is read from the memory module 132 to each POPE of the pixel operation processor (POP) group 13123 through, for example, the read-only cache RO $.
The coefficient generator COF receives the data (uf, vf, lodf), calculates the texture filter coefficient K (0-3), and supplies it to each POPE of the pixel operation processor (POP) group 13123.
In each POP of the pixel arithmetic processor (POP) group 13123, color data (TR, TG, TB) and a mixed value (blend value: TA) are obtained, and the data (TR2, TG2, TB2, TA2) are crossed. The bar circuit 13125 is transferred and set in a predetermined FIFO register of the register unit (RGU) 13124, and the setting data is directly supplied to the pixel engine (PXE) 13122 without passing through the crossbar circuit 13125.
[0167]
In the pixel engine (PXE) 13122, data (TR2, TG2, TB2, TA2) by the pixel arithmetic processor (POP) group 13123, and primary color (PC), secondary color (SC), and fog coefficient (F) by the rasterizer 1311. Based on the above, predetermined filtering calculation processing such as 4-neighbor interpolation is performed to obtain color data (FR1, FG1, FB1) and a mixed value (blend value: FA1), and this data (FR1, FG1, FB1, FA1). ) Is transferred through the crossbar circuit 13125 and set in a predetermined FIFO register of the register unit (RGU) 13124, and this setting data is directly passed through the pixel arithmetic processor (POP) group 13123 without passing through the crossbar circuit 13125. Within a given POP or separately It is provided by supplying to the light unit WU.
[0168]
In the light unit WU, based on the window coordinates (X, Y, Z) by the rasterizer 1311, for example, the destination color data (RGB), the mixed value data (A), and the depth data (from the memory module 132 through the read / write cache RW $) Z) is read out.
In the write unit WU, data (FR1, FG1, FB1, FA1) by the pixel engine (PXE) 13122, and read destination color data (RGB) and mixed value data (A) from the memory module 132 through the read / write cache RW $. ) And depth data (Z), operations necessary for pixel writing of graphics processing such as α blending, various tests, and logical operations are performed, and the operation result is written back to the read / write cache RW $.
[0169]
Next, image processing will be described.
[0170]
First, an operation when performing SAD (Summed Absolute Difference) processing as shown in FIG. 29 will be described with reference to FIG.
[0171]
In the SAD processing, for each block (X1s, Y1s) of the original image ORIM as shown in FIG. 29A, the search rectangular area SRGN of the reference image RFIM as shown in FIG. While shifting, the SAD (absolute value difference) in the corresponding block BLK is obtained.
Among them, the position (X2s, y2s) and SAD value of the block where SAD is minimum are stored in (Xd, Yd) as shown in FIG.
(X1s, Y1s) is set as a context in a register in the POP from an upper position (not shown).
[0172]
In this case, the source address and image processing result for reading the reference image data from the memory module 132 (−0 to −3) output from the host device (not shown) via the global module 12, for example, to the rasterizer 1311. Commands and data necessary for generating a destination address for writing, for example, width, height (Ws, Hs) data and block size (Wbk, Hbk) data of the search rectangular area SRGN are input.
The rasterizer 1311 generates a source address (X2s, Y2s) of the reference image RFIM stored in the memory module 132 based on the input data, and a destination address for storing the processing result in the memory module 132 ( Xd, Yd) is generated.
[0173]
The generated destination address (Xd, Yd) is shared through the supply line of the window coordinates (X, Y, Z) at the time of graphics processing, and directly through a specific FIFO register of the register unit (RGU) 13124. This is supplied to the light unit WU of the pixel operation processor (POP) group 13124.
Further, the source address (X2s, Y2s) of the generated reference image RFIM is supplied to the graphics unit (GRU) 12121 through the FIFO register of the crossbar circuit 13125 and the register unit (RGU) 13124.
The source address (X2s, Y2s) passes through the graphics unit (GRU) 12121 and is supplied directly to the pixel operation processor (POP) group 13123 without passing through the crossbar circuit 13125, for example.
[0174]
  In the pixel operation processor (POP) group 13123, the memory module 132 is connected to the memory module 132 via, for example, the read-only cache RO $ and the read / write cache RW $ based on the supplied source addresses (X1s, Y1s) and (X2s, Y2s). Each data of the stored original image ORIM and reference image RFIM is read out.
Here, the coordinates of the original image ORIM arecontextIs set in the register. As the coordinates of the reference image RFIM, for example, the coordinates of the sub-blocks handled by each of the four POPs are given.
  Then, the pixel arithmetic processor (POP) group 13123 shifts the search rectangular area SRGN of the reference image RFIM by one pixel from one block (X1s, Y1s) of the original image ORIM, while shifting the SAD in the corresponding sub-block BLK. (Absolute value difference) is obtained from time to time.
  Then, the position (X2s, y2s) of each sub-block and each SAD value are transferred through the crossbar circuit 13125 and set in a predetermined FIFO register of the register unit (RGU) 13124, and this setting data is stored in the crossbar circuit 13125. Without being routed to the pixel engine (PXE) 13122.
[0175]
  Pixel engine (PXE)13122Then, the SAD of the entire block is aggregated, and the position (X2s, y2s) of the block and the SAD value are transferred to the crossbar circuit 13125 and set in a predetermined FIFO register of the register unit (RGU) 13124. It is directly transferred to the light unit WU without going through the crossbar circuit 13125.
[0176]
In the light unit WU, the block position (X2s, y2s) and the SAD value by the pixel engine (PXE) 13122 are stored in the destination address (Xd, Yd) by the rasterizer 1311.
In this case, for example, the SAD value read from the memory module 132 to the read / write cache RW $ and the SAD value by the pixel engine (PXE) 13122 using a function (Z comparison) for performing hidden surface removal (Hidden Surface Removal), for example. Are compared.
As a result of the comparison, when the SAD value by the pixel engine (PXE) 13122 is smaller than the stored value, the block position (X2s, y2s) by the pixel engine (PXE) 13122 and the SAD value are represented by the destination address (Xd , Yd) is written (updated) via the read / write cache RW $.
[0177]
Next, the operation when performing the convolution filter process as shown in FIG. 31 will be described with reference to FIG.
[0178]
In the convolution filter process, for each pixel (X1s, Y1s) of the target image OBIM as shown in FIG. 31 (A), the peripheral pixels of the filter kernel size are read out, and the result obtained by multiplying by the filter coefficient is added. The result is stored in the destination address (Xd, Yd) as shown in FIG.
The storage address of the filter kernel coefficient is set in a register in the POP as a context.
[0179]
In this case, for example, a source address and an image for reading image data (pixel data) from the memory module 132 (−0 to −3) output from the host device (not shown) via the global module 12 to the rasterizer 1311. Commands and data necessary for generating a destination address for writing a processing result, for example, filter kernel size data (Wk, Hk) are input.
The rasterizer 1311 generates the source address (X1s, Y1s) of the target image OBIM stored in the memory module 132 based on the input data, and the destination address for storing the processing result in the memory module 132 ( Xd, Yd) is generated.
[0180]
The generated destination address (Xd, Yd) is shared through the supply line of the window coordinates (X, Y, Z) at the time of graphics processing, and directly through a specific FIFO register of the register unit (RGU) 13124. This is supplied to the light unit WU of the pixel operation processor (POP) group 13124.
Further, the source address (X1s, Y1s) of the generated target image OBIM is supplied to the graphics unit (GRU) 12121 through the FIFO register of the crossbar circuit 13125 and the register unit (RGU) 13124.
The source address (X1s, Y1s) passes through the graphics unit (GRU) 12121 and is supplied directly to the pixel operation processor (POP) group 13123 without passing through the crossbar circuit 13125, for example.
[0181]
  In the pixel operation processor (POP) group 13123, based on the supplied source address (X1s, Y1s), for example, peripheral pixels having a kernel size enabled in the memory module 132 are read via the read-only cache RO $. .
In a pixel operation processor (POP) group 13123, a predetermined filter coefficient is multiplied with the read data.ThisFurther, these are added together, and the resulting data (R, G, B, A) including color data (R, G, B) and mixed value data (A) are crossbar circuit 13125, register unit (RGU). ) 13124 to the light unit WU.
[0182]
In the write unit WU, data from the pixel operation processor (POP) group 13123 is stored in the destination address (Xd, Yd) via the read / write cache RW $.
[0183]
Finally, the operation of the system configuration in FIG. 3 will be described.
Here, texture processing will be described.
[0184]
First, when the vertex data of three-dimensional coordinates, normal vectors, and texture coordinates is input in the SDC 11, an operation is performed on the vertex data.
Next, various parameters necessary for rasterization are calculated.
In the SDC 11, the calculated parameters are broadcast to all the local modules 13-0 to 13-3 via the global module 12.
In this processing, the broadcast parameters are transferred to the local modules 13-0 to 13-3 via the global module 12 using a channel different from a cache fill described later. However, it does not affect the contents of the global cache.
[0185]
In each of the local modules 13-0 to 13-3, the following processing is performed in the processing units 131-0 to 131-3.
That is, when the processing unit 131 (−0 to 3) receives the broadcast parameter, whether or not the triangle belongs to an area that the triangle is in charge of, for example, a 4 × 4 pixel rectangular area unit. Is judged. As a result, if it belongs, various data (Z, texture coordinates, color, etc.) are rasterized.
Next, calculation of a mipmap (MIPMAP) level by LOD (Level of Detail) calculation and (u, v) address calculation for texture access are performed.
[0186]
Next, the texture is read out.
In this case, the processing units 131-0 to 131-3 of the local modules 13-0 to 13-3 first check the entries in the local caches 133-0 to 133-3 at the time of texture reading.
As a result, if there is an entry, necessary texture data is read out.
If the required texture data is not in the local cache 133-0 to 133-3, the processing units 131-0 to 131-3 are connected to the global module 12 through the global interfaces 134-0 to 134-3. Request for local cache fill.
[0187]
In the global module 12, when it is determined that the requested block data is in any of the global caches 121-0 to 121-3, it is read from any of the corresponding global caches 121-0 to 121-3. Sent back to the local module that sent the request through the given channel.
[0188]
On the other hand, if it is determined that the requested block data is not in any of the global caches 121-0 to 121-3, the global cache fill is sent to the local module holding the block from any of the desired channels. A request is sent.
In the local module receiving the global cache fill request, the corresponding block data is read from the memory and sent to the global module 12 through the global interface.
Thereafter, in the global module 12, the block data is filled in a desired global cache, and data is transmitted from a desired channel to the local module that has sent the request.
[0189]
When the requested block data is sent from the global module 12, the local cache is updated in the corresponding local module, and the block data is read out by the processing unit.
[0190]
Next, in the local modules 13-0 to 13-3, filtering processing such as 4-neighbor interpolation is performed on the read texture data and the (u, v) address using the decimal part obtained at the time of calculation.
Next, a pixel unit operation is performed using the texture data after filtering and the various data after rasterization.
Then, the pixel data that passes various tests in the pixel level processing is written in the memory modules 132-0 to 132-3, for example, the frame buffer and the Z buffer on the built-in DRAM memory.
[0191]
As described above, according to the present embodiment, the plurality of buffers BUF0 to BUF3 of the memory module 132 are provided corresponding to each other, cascaded from the first stage SRT0 to the last stage SRT3, and the corresponding buffers BUF0 to BUF3. The read depth data values read from the read / write caches RW $ 0 to RW $ 3 are compared with the first supply depth data value ZDRW corresponding to the pixel data supplied from the write unit WU for rendering. If the first supply depth data is larger than (or smaller than) the read depth data as a result of the comparison of the units, the first supply depth data and the RGBα data are supplied to the sorting circuit at the next stage, and the read depth data The RGBα data is written back to the corresponding buffers BUF0 to BUF3, and the first data is supplied. When the feed depth data is smaller (or larger) than the read depth data, the read depth data and RGBα data are supplied to the next-stage sorting circuit, and the second supply depth data and RGBα data from the previous stage correspond to each other. Since the sort circuits SRT0 to SRT3 for writing in the buffers BUF0 to BUF3 are provided, the synthesis of a plurality of (for example, four) layers of translucent objects (Order Independent Transparency) can be easily realized in hardware.
Then, it is possible to perform superposition with an arbitrary number of layers, and to reduce the number of times that all scene data flows. As a result, there is an advantage that the load on the processing unit of the scene data can be reduced and the processing speed can be increased.
[0192]
In the above-described embodiment, the sort circuit is provided corresponding to each buffer of the memory module, and these are connected in cascade. However, the present invention is not limited to this.
For example, as shown in FIGS. 33A and 33B, the sort circuits SRT10 to SRT17 are arranged in the buffers BUF10 to BUF17 of the memory module, respectively, and the sort function is provided to the memory module 132A itself only in the translucent object synthesis mode. It is also possible to synthesize a translucent object using a plurality of buffers.
[0193]
In this case, in the memory module 132A, RGB α / Z data flows in a so-called bucket relay from the input side toward the buffer BUF17 from the buffer BUF10.
Then, the depth data Z is compared between the existing data and the data that has flowed at each stage, and as a result of the comparison, it is selected whether to flow as it is or to store the flowed data in the buffer and flow the existing data .
By repeating this, data is always stored while keeping the order in the depth direction.
[0194]
FIG. 33B is a diagram showing a configuration example of the sort circuits SRT10 to SRT17 in this case.
The sort circuits SRT (10 to 17) are cascaded from the first stage to the last stage.
[0195]
The sort circuit SRT (10 to 17) includes a comparison unit (CMP) 401 and a data selection unit (DSEL) 402 as shown in FIG.
[0196]
The comparison unit 401 reads the read depth data value ZRD read from the corresponding buffer BUF (10 to 17) and the second supply depth data value ZPRV from the previous stage (pixels supplied from the light unit WU for drawing at the first stage). The first supply depth data value ZDRW) corresponding to the data is compared, and, as a result of comparison by the comparison unit, the second or first supply depth data value ZPRV (ZDRW) is larger than the read depth data value ZRD (ZPRV) When (ZDRW)> ZRD), a low level (logic 0) control signal CTL 401 is output to the data selection unit 402.
On the other hand, if the comparison unit 401 determines that the second or first supply depth data value ZPRV (ZDRW) is smaller than the read depth data value ZRD ((ZPRV (ZDRW) <ZRD)), A level (logic 1) control signal CTL 301 is output to the data selection unit 402.
[0197]
  The data selection unit 402 reads the read depth data value ZRD and RGBα data read from the corresponding buffer BUF (10 to 17) and the second supply depth data value ZPRV from the previous stage (in the first stage, the light unit WU for drawing). When the first supply depth data value ZDRW) and RGBα data corresponding to the pixel data supplied from is input and the low-level control signal CTL 401 is received from the comparison unit 401, the second supply depth data value ZPRV (or The first supply depth data value ZDRW) and RGBα data are selected and supplied to the next sort circuit SRT (11-17), and the read depth data value ZRD and RGBα data are written back to the corresponding buffers BUF10 to BUF17.
  on the other hand,SupplyWhen the data selection unit 302 receives the high-level control signal CTL 401, the data selection unit 302 selects the read depth data value ZRD and the RGBα data, and supplies the read depth data value ZRD and RGBα data to the next-stage sorting circuits SRT (11 to 17). (Or the first supply depth data value ZDRW) and RGBα data are written into the corresponding buffers BUF10 to BUF17.
[0198]
FIG. 34 is a diagram for explaining the operation of the memory module having the sort function of FIG. 33 in the translucent object synthesis mode.
In this example, Z = 15 and RGBα data depth data are stored in the buffer BUF10, Z = 25 and RGBα data depth data are stored in the buffer BUF11, and Z = 32 and RGBα data depth data are stored in the buffer BUF12. It is assumed that Z = 40 and depth data of RGBα data are stored in the buffer BUF13, and these are read out to the respective sort circuits SRT10 to SRT13.
[0199]
First, in cycle 1, the first supply depth data value ZDRW and RGBα data of Z = 29 are supplied from the light unit WU to each sort circuit SRT10 for drawing.
In the first-stage sort circuit SRT10, the comparison result of the comparison unit 401 indicates that the first supply depth data value ZDRW (= 29) is larger than the read depth data ZRD (= 15). Is output to the data selection unit 402.
As a result, in the data selection unit 402, the first supply depth data value ZDRW (= 29) and RGBα data are selected and supplied to the next-stage sort circuit SRT11.
In parallel with this, the data selection unit 402 selects the read depth data value ZRD (= 15) and RGBα data and writes them back to the corresponding buffer BUF10.
[0200]
In the second-stage sort circuit SRT11, the comparison result of the comparison unit 401 indicates that the first supply depth data value ZDRW (= 29) is larger than the read depth data ZRD (= 32). A signal CTL 401 is output to the data selection unit 402.
As a result, in the data selection unit 402, the second supply depth data value ZPRV (= 29) and RGBα data are selected and supplied to the next-stage sort circuit SRT12.
In parallel with this, the data selection unit 402 selects the read depth data value ZRD (= 25) and RGBα data and writes them back to the corresponding buffer BUF11.
[0201]
In the third-stage sort circuit SRT12, the comparison result of the comparison unit 401 indicates that the third supply depth data value ZPRV (= 29) is smaller than the read depth data ZRD (= 32). A signal CTL 401 is output to the data selection unit 402.
As a result, in the data selection unit 402, the read depth data ZRD (= 32) and RGBα data are selected and supplied to the next-stage sort circuit SRT13.
In parallel with this, the data selection unit 403 selects the second supply depth data ZPRV (= 29) and RGBα data from the previous stage, and writes them in the corresponding buffer BUF12.
[0202]
In the fourth-stage sort circuit SRT13, the comparison result of the comparison unit 401 indicates that the second supply depth data value ZPRV (= 32) is smaller than the read depth data ZRD (= 40). A signal CTL 401 is output to the data selection unit 402.
As a result, in the data selection unit 402, the read depth data ZRD (= 40) and the RGBα data are selected and supplied to the next-stage sort circuit SRT14.
In parallel with this, in the data selection unit 403, the second supply depth data ZPRV (= 32) and RGBα data from the previous stage are selected and written into the corresponding buffer BUF13.
[0203]
In the fifth-stage sort circuit SRT14, since the comparison by the comparison unit 401 does not include the read depth data ZRD, a high-level control signal CTL401 is output to the data selection unit 402.
As a result, the data selection unit 402 selects read depth data ZRD (= 40) and RGBα data, but does not supply them to the next stage.
In parallel with this, the data selection unit 403 selects the second supply depth data ZPRV (= 40) and RGBα data from the previous stage and writes them in the corresponding buffer BUF14.
[0204]
In this way, in the circuit of FIG. 33, as shown in FIG. 35, the synthesis (Order Independent Transparency) of a plurality (8 in the case of FIG. 33) of translucent objects can be easily realized in hardware.
Then, it is possible to perform superposition with an arbitrary number of layers, and to reduce the number of times that all scene data flows. As a result, the load on the processing unit for scene data can be reduced, and the processing speed can be increased.
[0205]
For example, as shown in FIG. 36, a plurality of memory banks BNK10, BNK11,... Including a plurality of buffers are arranged, and sort circuits SRT10 to SRT13, SRT14 provided corresponding to the respective buffers of the same memory bank. To SRT17 are connected to each other, and a plurality of sort circuits provided corresponding to buffers included in different memory banks, in the example of FIG. 33, sort circuits SRT10 and SRT14, SRT11 and SRT15, SRT12 and SRT16 and SRT13 And SRT 17 can be connected in cascade to perform a translucent object combining operation.
[0206]
In addition, according to the present embodiment, a plurality of POP0 to POP3 that are functional units that perform highly parallel arithmetic processing utilizing the memory bandwidth are provided, and each POP has arithmetic units POPE0 to POPE3 arranged in parallel. Each of the POPE0 to POPE3 receives a 32-bit width data read from the cache and an operation parameter by the filter function unit FFU, performs a predetermined operation (for example, addition), and outputs the operation result to the next-stage POPE Then, the next-stage POPE adds the previous-stage calculation result to its own calculation result, and outputs the calculation result to the next-stage POPE. In the final-stage POPE3, the sum of the calculation results of all POPE0 to POPE3 is obtained. Each POP selects only the calculation result of one POPE3 from the calculation outputs of a plurality of POPEs and outputs it to the crossbar circuit 13125. The pixel operation processor (POP) group 13123 having an output selection circuit OSLC since provided that, Hakare the size of the crossbar circuit, it is possible to increase the speed of processing.
[0207]
In the present embodiment, the configuration example in which only one core 1312 as an arithmetic processing unit is provided has been described. For example, as illustrated in FIG. 37, a plurality of cores 1312-1 are provided for one rasterizer 1311. It is also possible to employ a configuration in which ˜1312-1 are provided in parallel.
Even in this case, the DFG executed in each core is the same.
In addition, as a unit of parallelization in a configuration in which a plurality of cores are provided, for example, a small rectangular area (stamp) unit in the case of graphics processing, and a block unit in the case of image processing. In this case, there is an advantage that parallel processing with fine granularity can be realized.
[0208]
In this embodiment, the pixel operation processor (POP) group 13123 and the cache are connected with a wide bandwidth and have an address generation function for memory access. Stream data can be supplied as much as possible.
[0209]
Further, in the present embodiment, arithmetic units are arranged at high density in the form of matching the output data width in the vicinity of the memory, and the regularity of the processing data is used, so that a large amount of arithmetic operations can be performed with a minimum number of arithmetic units. Moreover, it can be realized with a simple configuration, and as a result, there is an advantage that the cost can be reduced.
[0210]
According to the present embodiment, the SDC 11 and the global module 12 exchange data, and a plurality of (four in the present embodiment) local modules 13-0 to 13-3 are transmitted to one global module 12. Are connected in parallel, the processing data is shared and processed in parallel by the plurality of local modules 13-0 to 13-3, the global module 12 has a global cache, and each of the local modules 13-0 to 13-3 Since each of the local caches has two layers, a global cache shared by the four local modules 13-0 to 13-3 and a local cache that each local module has locally, as a hierarchy of caches, a plurality of processes are performed. Duplicate access is reduced when devices process and share processing data in parallel Yellow, cross-bar is not required a lot of number of wires. As a result, there is an advantage that an image processing apparatus that can be easily designed and can reduce wiring cost and wiring delay can be realized.
[0211]
Further, according to the present embodiment, as shown in FIG. 3, the arrangement relationship between the global module 12 and each of the local modules 13-0 to 13-3 is the local module 13-0 around the global module 12. Since 13-3 is arranged in the vicinity of its periphery, the distance between each corresponding channel block and the local module can be kept uniform, the wiring regions can be arranged in order, and the average wiring length can be shortened. Therefore, there are advantages that the wiring delay and the wiring cost can be reduced and the processing speed can be improved.
[0212]
In this embodiment, the case where the texture data is on the built-in DRAM is described as an example. However, as another case, only the color data and the z data are placed in the built-in DRAM, and the texture data is stored in the external memory. It is also possible to be placed in In this case, if a miss occurs in the global cache, a cache fill request is issued to the external DRAM.
[0213]
In the above description, the configuration shown in FIG. 3, that is, an image processing apparatus in which a plurality of (four in this embodiment) local modules 13-0 to 13-3 are connected in parallel to one global module 12. 10 is an example specialized for parallel processing, but the configuration of FIG. 3 is a single cluster CLST, for example, as shown in FIG. 37, four clusters CLST0 to CLST3 are arranged in a matrix. It is also possible to configure so that data is exchanged between the global modules 12-0 to 12-3 of the clusters CLST0 to CLST3.
In the example of FIG. 37, the global module 12-0 of the cluster CLST0 and the global module 12-1 of the cluster CLST1 are connected, the global module 12-1 of the cluster CLST1 and the global module 12-3 of the cluster CLST3 are connected, The global module 12-3 of the cluster CLST3 and the global module 12-2 of the cluster CLST2 are connected, and the global module 12-2 of the cluster CLST2 and the global module 12-0 of the cluster CLST0 are connected.
That is, the global modules 12-0 to 12-3 of the plurality of clusters CLST0 to CLST3 are connected in a ring shape.
In the case of the configuration in FIG. 37, it is possible to configure so that parameters are broadcast from one SDC to the global modules 12-0 to 12-3 of CLST0 to CLST3.
[0214]
By adopting such a configuration, more accurate image processing can be realized, and the wiring between each cluster is simply connected in a single system as bidirectional, so the load between each cluster can be kept uniform. The wiring areas can be arranged in an orderly manner, and the average wiring length can be shortened. Therefore, wiring delay and wiring cost can be reduced, and the processing speed can be improved.
[0215]
【The invention's effect】
As described above, according to the present invention, synthesis of a plurality of layers of translucent objects (Order Independent Transparency) can be easily realized in hardware.
Then, it is possible to perform superposition with an arbitrary number of layers, and to reduce the number of times that all scene data flows. As a result, the load on the processing unit for scene data can be reduced, and the processing speed can be increased.
[Brief description of the drawings]
FIG. 1 is a diagram conceptually showing parallel processing at a primitive level based on a parallel processing technique at a pixel level.
FIG. 2 is a diagram for explaining a processing procedure including texture filtering in a general image processing apparatus.
FIG. 3 is a block configuration diagram showing an embodiment of an image processing apparatus according to the present invention.
FIG. 4 is a flowchart for explaining main processing of a stream data controller (SDC) according to the present embodiment.
FIG. 5 is a flowchart for explaining functions of the global module according to the present embodiment;
FIG. 6 is a diagram for explaining graphics processing of a processing unit in the local module according to the present embodiment.
FIG. 7 is a flowchart for explaining the operation of the local module at the time of texture reading according to the present embodiment.
FIG. 8 is a diagram for explaining image processing of a processing unit in the local module according to the present embodiment.
FIG. 9 is a block diagram showing a configuration example of a local cache in the local module according to the present embodiment.
FIG. 10 is a block diagram illustrating a configuration example of a memory controller of a local cache according to the present embodiment.
FIG. 11 is a block diagram illustrating a specific configuration example of a processing unit of a local module according to the present embodiment.
FIG. 12 is a diagram illustrating a configuration example of a pixel engine according to the present embodiment, and a connection example with a register unit (RGU) and a crossbar circuit.
FIG. 13 is a diagram illustrating a configuration example of a pixel operation processor (POP) group according to the present embodiment.
FIG. 14 is a diagram showing a connection form between a POP (pixel arithmetic processor) and a memory and a configuration example of a POP according to the present embodiment.
FIG. 15 is a diagram showing a connection form between a POP (pixel arithmetic processor) and a memory and another configuration example of the POP according to the present embodiment;
FIG. 16 is a block diagram illustrating a specific configuration example of a sort circuit according to the present embodiment.
FIG. 17 is a diagram for explaining an operation in a semi-transparent object synthesis mode using a sort circuit.
FIG. 18 is a diagram illustrating a circuit example in which 16 layers can be combined by combining 4 vertical stages and 4 horizontal stages using the sort circuit according to the present embodiment;
FIG. 19 is a circuit diagram showing a specific configuration example of POPE according to the present embodiment.
FIG. 20 is a diagram showing a form of reading data from the memory to the cache and a form of reading data from the cache to each POPE according to the present embodiment;
FIG. 21 is a flowchart for explaining an operation in the case where arithmetic processing is performed by a pixel arithmetic processor group based on data in a memory according to the present embodiment, and further arithmetic is performed by a pixel engine.
FIG. 22 is a diagram for explaining an operation in a case where a calculation process is performed by a pixel calculation processor group based on data in a memory according to the present embodiment and a calculation is further performed by a pixel engine.
FIG. 23 is a timing chart for explaining an operation in the case where arithmetic processing is performed by a pixel arithmetic processor group based on data in a memory according to the present embodiment, and further arithmetic is performed by a pixel engine.
FIG. 24 is a block diagram for explaining an operation in the case where arithmetic processing is performed by the pixel arithmetic processor group based on the data in the memory according to the present embodiment, and further arithmetic is performed by the pixel engine.
FIG. 25 is a diagram showing an outline of an operation including a core pixel engine (PXE), a pixel operation processor (POP), a register unit (RGU), and a memory part in the processing unit according to the present embodiment.
FIG. 26 is a diagram for explaining graphics processing when there is no dependent texture in the processing unit according to the present embodiment;
FIG. 27 is a diagram for explaining a specific operation of a pixel processing processor (POP) group for graphics processing in the processing unit according to the present embodiment;
FIG. 28 is a diagram for explaining graphics processing when there is a dependent texture in the processing unit according to the present embodiment;
FIG. 29 is a diagram for explaining SAD (summed absolute difference) processing;
FIG. 30 is a diagram for explaining SAD processing in the processing unit according to the embodiment;
FIG. 31 is a diagram for explaining a convolution filter process;
FIG. 32 is a diagram for explaining convolution filter processing in the processing unit according to the embodiment.
FIG. 33 is a diagram showing a configuration example of a memory module having a sorting function according to the present embodiment and capable of realizing a semi-transparent object synthesis mode operation.
34 is a diagram for explaining the operation of the memory module having the sort function of FIG. 30 in the translucent object synthesis mode.
FIG. 35 is a diagram for explaining the effect of the translucent object synthesis mode of the memory module having the sort function of FIG. 30;
FIG. 36 is a diagram showing another configuration example of the memory module that has the sort function according to the present embodiment and can realize the translucent object synthesis mode operation;
FIG. 37 is a diagram showing another configuration example (an example in which a plurality of cores are provided) in the processing unit according to the embodiment.
FIG. 38 is a block diagram showing another embodiment of the image processing apparatus according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10,10A ... Image processing apparatus, 11 ... Stream data controller (SDC), 12-0 to 12-3 ... Global module, 121-0 to 121-3 ... Global cache, 13-0 to 13-3 ... Local module, 131-0 to 131-3 ... processing unit, 132-0 to 132-3 ... memory module, 133-0 to 133-3 ... local cache, 134-0 to 134-3 ... global interface (GAIF), CLST0 to CLST3 ... Cluster, 1311 ... Rasterizer, 1312, 1312-1 to 1312-n ... Core, 13121 ... Graphics unit (GRU), 13122 ... Pixel engine (PXE), 13123 ... Pixel arithmetic processor (POP) group, 13124 ... Register unit (RGU), 3125 ... Crossbar circuit (IXB), POPE0-3 ... arithmetic unit, OSLC ... output selection circuit, SRT0-SRT8 ... sort circuit, BUF0-BUF7 ... buffer, 301 ... comparison unit, 302 ... supply data selection unit, 303 ... write Data selection unit 401... Comparison unit 402 402 Data selection unit.

Claims (16)

An image that generates pixel data including color data, mixed value data, and depth data based on information about a primitive to be drawn, and maintains the order of the depth direction of the plurality of depth data to perform a semitransparent object composition process A processing device comprising:
A pixel arithmetic processor for arithmetically processing the pixel data ;
A plurality of buffers capable of storing and reading the color data, mixed value data, and depth data;
A plurality of sorting circuits provided corresponding to the buffers, cascaded from the first stage toward the last stage,
A cache storage unit, connected to the pixel arithmetic processor and the plurality of buffers , for storing pixel data for transferring data to the pixel arithmetic processor and the buffer;
Anda address generation circuitry for generating an address for accessing said plurality of buffers and the cache storage unit,
The sort circuit in the first stage compares the read depth data value read from the corresponding buffer with the first supply depth data value output from the pixel arithmetic processor corresponding to the pixel data for drawing , and compares As a result, in the first case where the first supply depth data value is larger, smaller or equal , the read depth data, color data, and mixed value data are stored in the corresponding buffer. And supplying the supplied first supply depth data value, color data, and mixed value data to the sorting circuit in the next stage,
Each sort circuit in the second and subsequent stages compares the read depth data value read from the corresponding buffer with the second supply depth data value supplied from the previous sort circuit . In the second case of any one of the two supply depth data values being larger, smaller or equal , the read depth data, color data, and mixed value data are written back to the corresponding buffer. , supplied from the previous stage was the second feed depth data values, the color data, and the blended value data is supplied to the next stage of the sorting circuit, and comparing the read depth data value and the second supply depth data value result, towards the read depth data value is other than the case of the second large, if Komata is equal to or of any of 1, the second feed depth data values from the previous stage, the color data And mixtures value data written to the corresponding buffer, the read depth data, color data, and mixtures value data image processing apparatus to be supplied to the next stage of the sorting circuit. When the depth data value is not stored in the corresponding buffer, the sorting circuits in the second and subsequent stages correspond to the second supply depth data value, color data, and mixed value data from the previous stage, respectively. The image processing apparatus according to claim 1, wherein the image processing apparatus writes in a buffer. A plurality of memory banks including the plurality of buffers;
Sort circuits provided corresponding to each buffer of the same memory bank are in a non-connected state,
The image processing apparatus according to claim 1, wherein a plurality of sort circuits provided corresponding to buffers included in different memory banks are cascade-connected in parallel. An image that generates pixel data including color data, mixed value data, and depth data based on information about a primitive to be drawn, and maintains the order of the depth direction of the plurality of depth data to perform a semitransparent object composition process A processing device comprising:
A pixel arithmetic processor for arithmetically processing the pixel data ;
A plurality of buffers capable of storing and reading the color data, mixed value data, and depth data;
It provided corresponding to said plurality of buffers and a corresponding first feed depth data values are output from the pixel operation processor corresponding to the pixel data for drawing the read depth data value read from the buffer A plurality of sort circuits including a comparison unit to be compared;
A cache storage unit, connected to the pixel arithmetic processor and the plurality of buffers , for storing pixel data for transferring data to the pixel arithmetic processor and the buffer;
Anda address generation circuitry for generating an address for accessing said plurality of buffers and the cache storage unit,
Each sort circuit is cascaded from the first stage to the last stage, and as a result of the comparison by the comparison unit, each sort circuit has the first supply depth data value larger than the read depth data value. In the first case of any one of small and equal , the supplied first supply depth data value, color data, and mixed value data are supplied to the sorting circuit in the next stage and read out. Data, color data, and mixed value data are written back to the corresponding buffers, and the first supply depth data value is compared with the read depth data value in the case of large, small, or equal to those other than the first case. If any one of, the read depth data, color data, and the mixed value data is supplied to the next stage sorting circuit, the second supply depth data values from the previous stage, the color data, Oyo The mixture value data image processing apparatus for writing to the corresponding buffer. The first stage of the sorting circuit, as a result of the first feed depth data value output from the pixel operation processor corresponding to the pixel data for drawing is compared with the read depth data value, the first supply depth data is read In the second case of any one of large, small or equal compared to the depth data value , the read depth data, color data, and mixed value data are supplied to the next sort circuit, The image processing apparatus according to claim 4, wherein the supplied first supply depth data value, color data, and mixed value data are written in the corresponding buffer. If the depth data value is not stored in the corresponding buffer, the sorting circuits in the second and subsequent stages receive the second supply depth data value, color data, and mixed value data from the previous stage in the corresponding buffer. The image processing apparatus according to claim 4. A plurality of memory banks including the plurality of buffers are arranged in multiple stages,
Sort circuits provided corresponding to the respective buffers of the same memory bank are connected in cascade,
The plurality of sort circuits provided corresponding to each buffer of each memory bank and connected in cascade are provided among the plurality of sort circuits connected corresponding to each buffer of the preceding memory bank and connected in cascade. The image processing apparatus according to claim 4, wherein output depth data of the last stage is supplied. An image processing apparatus in which a plurality of modules share processing data and perform parallel processing,
A global module,
A plurality of pixel data including color data, mixed value data, and depth data are generated based on information about primitives to be drawn, and a plurality of depth data is retained in the depth direction to perform a translucent object combining process. Including local modules,
The above global module
When the multiple local modules are connected in parallel and receive a request from the local module, the processing data is output to the local module that issued the request according to the request,
The multiple local modules are
A pixel arithmetic processor for arithmetically processing the pixel data ;
A plurality of buffers capable of storing and reading the color data, mixed value data, and depth data;
A plurality of sorting circuits provided corresponding to the buffers, cascaded from the first stage toward the last stage,
A cache storage unit, connected to the pixel arithmetic processor and the plurality of buffers , for storing pixel data for transferring data to the pixel arithmetic processor and the buffer;
Anda address generation circuitry for generating an address for accessing said plurality of buffers and the cache storage unit,
The sort circuit in the first stage compares the read depth data value read from the corresponding buffer with the first supply depth data value output from the pixel arithmetic processor corresponding to the pixel data for drawing , and compares As a result, in the first case where the first supply depth data value is larger, smaller or equal , the read depth data, color data and mixed value data are stored in the corresponding buffer. And supplying the supplied first supply depth data value, color data, and mixed value data to the sorting circuit in the next stage,
Each sort circuit in the second and subsequent stages compares the read depth data value read from the corresponding buffer with the second supply depth data value supplied from the previous sort circuit . In the second case where one of the two supplied depth data values is larger, smaller or equal , the read depth data, color data, and mixed value data are written back to the corresponding buffer. , supplied from the previous stage was the second feed depth data values, the color data, and the blended value data is supplied to the next stage of the sorting circuit, large towards the read depth data value is other than the case of the second, small or in the case of equal to or of any of 1 writes the second feed depth data values from the previous stage, the color data, and the mixed value data in the buffer to the corresponding read depth data , Color data, and the mixed value data image processing apparatus to be supplied to the next stage of the sorting circuit. An image processing apparatus in which a plurality of modules share processing data and perform parallel processing,
A global module,
A plurality of pixel data including color data, mixed value data, and depth data are generated based on information about primitives to be drawn, and a plurality of depth data is retained in the depth direction to perform a translucent object combining process. Including local modules,
The above global module
When the multiple local modules are connected in parallel and receive a request from the local module, the processing data is output to the local module that issued the request according to the request,
The multiple local modules are
A pixel arithmetic processor for arithmetically processing the pixel data ;
A plurality of buffers capable of storing and reading the color data, mixed value data, and depth data;
A read depth data value provided corresponding to the plurality of buffers and read from the corresponding buffer is compared with a first supply depth data value output from the pixel arithmetic processor corresponding to the pixel data for drawing. A plurality of sorting circuits including a comparing unit to perform,
A cache storage unit, connected to the pixel arithmetic processor and the plurality of buffers , for storing pixel data for transferring data to the pixel arithmetic processor and the buffer;
Anda address generation circuitry for generating an address for accessing said plurality of buffers and the cache storage unit,
Each sort circuit is cascade-connected from the first stage to the last stage. As a result of comparison by the comparison unit, each sort circuit has a first supply depth data value larger than the read depth data value. In the first case of any one of small and equal , the supplied first supply depth data value, color data, and mixed value data are supplied to the sorting circuit in the next stage and read out. Depth data, color data, and mixed value data are written back to the corresponding buffer, and whether the first supply depth data value is larger, smaller, or equal to the read depth data value other than the first case If any one of the inner is the read depth data, color data, and the mixed value data is supplied to the next stage sorting circuit, the second supply depth data values from the previous stage, the color data And mixtures value data image processing apparatus for writing to the corresponding buffer. An image that generates pixel data including color data, mixed value data, and depth data based on information about a primitive to be drawn, and maintains the order of the depth direction of the plurality of depth data to perform a semitransparent object composition process A processing method,
A plurality of sort circuits corresponding to a plurality of buffers are cascaded from the first stage to the last stage,
A cache storage unit is connected to a pixel operation processor that calculates the pixel data and the plurality of buffers, and stores pixel data for transferring data to the pixel operation processor and the buffer,
The address generation circuit accesses the plurality of buffers and the cache storage unit,
In the first sort circuit above,
Comparing the read depth data value read from the corresponding buffer with the first supply depth data value output from the pixel arithmetic processor corresponding to the pixel data for rendering ;
As a result of comparison, in the first case where the first supply depth data value is larger, smaller or equal , the read depth data, color data, and mixed value data correspond to the above Write back to the buffer and supply the supplied first supply depth data value, color data, and mixed value data to the next-stage sorting circuit,
In each sort circuit after the second stage,
Comparing the read depth data value read from the corresponding buffer with the second supplied depth data value supplied from the preceding sort circuit;
As a result of the comparison, if the second supply depth data value is larger, smaller, or equal to the second case, the read depth data, color data, and mixed value data correspond to the above The second supply depth data value, color data, and mixed value data from the previous stage are supplied to the next stage sort circuit,
As a result of comparing the read depth data value with the second supply depth data value , one of the second supply depth data value is larger, smaller, or equal to those other than the second case. In this case, the second supply depth data, color data, and mixed value data from the previous stage are written in the corresponding buffers, and the read depth data, color data, and mixed value data are supplied to the next sort circuit. Image processing method. In each sort circuit after the second stage, when the depth data value is not stored in the corresponding buffer, the second supply depth data value, color data, and mixed value data from the previous stage are stored in the corresponding buffer. The image processing method according to claim 10. A plurality of memory banks including the plurality of buffers are arranged in multiple stages,
Sort circuits corresponding to each buffer of the same memory bank are disconnected from each other.
The image processing method according to claim 10, wherein a plurality of sort circuits corresponding to buffers included in different memory banks are cascade-connected in parallel. An image that generates pixel data including color data, mixed value data, and depth data based on information about a primitive to be drawn, and maintains the order of the depth direction of the plurality of depth data to perform a semitransparent object composition process A processing method,
A plurality of sort circuits corresponding to a plurality of buffers are cascaded from the first stage to the last stage,
A cache storage unit is connected to a pixel operation processor that calculates the pixel data and the plurality of buffers, and stores pixel data for transferring data to the pixel operation processor and the buffer,
The address generation circuit accesses the plurality of buffers and the cache storage unit,
In each sort circuit above,
Comparing the read depth data value read from the corresponding buffer with the first supply depth data value output from the pixel arithmetic processor corresponding to the pixel data for rendering ;
In the first case where the first supply depth data value is larger, smaller or equal to the read depth data value , the supplied first supply depth data value, color data , And the mixed value data are supplied to the sorting circuit in the next stage, and the read depth data, color data, and mixed value data are written back to the corresponding buffer,
If the first supply depth data value is any one of large, small, or equal to other than the first case compared to the read depth data value , the read depth data, color data, and An image processing method for supplying mixed value data to a sorting circuit at the next stage and writing the second supply depth data value, color data, and mixed value data from the previous stage into the corresponding buffer. In the first-stage sorting circuit, the first supply depth data value is compared with the read depth data value, and the first supply depth data value is large, small, or equal to the read depth data value. In the second case of any one of the above, the read depth data, color data, and mixed value data are supplied to the next-stage sort circuit, and the first supply depth data value, color data, and The image processing method according to claim 13, wherein the mixed value data is written to the corresponding buffer. In each sort circuit after the second stage, when the depth data value is not stored in the corresponding buffer, the second supply depth data value, color data, and mixed value data from the previous stage are stored in the corresponding buffer. The image processing method according to claim 13. A plurality of memory banks including a plurality of buffers are arranged in multiple stages,
Sort circuits provided corresponding to each buffer of the same memory bank are connected in cascade,
14. The output depth data of the last stage of the plurality of sort circuits connected in cascade corresponding to the preceding memory bank is supplied to the plurality of sort circuits connected in cascade corresponding to each of the memory banks. Image processing method.

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