JP4167415B2 - Synchronization processing apparatus and synchronization processing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital broadcast signal transmission system that handles a multiplex signal in which a digital video signal and a digital audio signal, which are transmitted from outside and have a transmission block structure of a predetermined data length unit, are handled. In particular, the digital audio signal is extracted from the multiplexed signal. The present invention also relates to a synchronization processing apparatus and a synchronization processing method for synchronizing this digital audio signal with a clock signal handled by a digital broadcast signal transmission system.
[0002]
[Prior art]
In broadcasting stations of digital broadcasting systems, in addition to SDI (Serial Digital Interface) signals in which material data (video data and audio data) of digital broadcasting programs handled in the station is multiplexed, SDI signals outside the station are also handled. .
[0003]
FIG. 6 is a block diagram showing a configuration of a signal processing apparatus that processes an SDI signal from outside the broadcasting station.
[0004]
An SDI signal coming from outside the station is first input to the audio signal extraction unit 11 and the clock generation unit 12. Of these, the clock generator 12 generates a clock signal synchronized with the input SDI signal. The audio signal extraction unit 11 extracts a digital audio signal multiplexed on the SDI signal at an extraction timing synchronized with the clock signal generated by the clock generation unit 12. The extracted digital audio signal is converted into an analog audio signal by a D / A converter (D / A) 13 at a timing synchronized with the clock signal generated by the clock generator 12, and is then converted into an A / D converter. 14 is input.
[0005]
The A / D converter 14 converts the analog audio signal into a digital audio signal according to the clock signal synchronized with the in-station synchronization signal generated from the clock generator 15. Thereafter, the digital audio signal is remultiplexed by the audio signal multiplexing unit 16 into an SDI signal synchronized with the synchronization signal in the station.
[0006]
On the other hand, the SDI signal from outside the station is input to the video signal extraction unit 17 to extract a digital video signal. This digital video signal is written into the video signal combining unit 18 at a write timing synchronized with the clock signal generated from the clock generator 12 and read out at a read timing synchronized with the clock signal generated from the clock generator 15. Thus, it is converted into a digital video signal synchronized with the clock signal in the station, and is output to the audio signal multiplexing unit 16 as an SDI signal.
[0007]
[Problems to be solved by the invention]
By the way, in the signal processing device, in order to synchronize the digital audio signal outside the station with the clock of the own station, the digital audio signal outside the station is once converted into an analog audio signal, and then the clock of the own station (internal). Since it is converted into a digital audio signal synchronized with the signal, the quality of the digital audio signal is degraded.
[0008]
Accordingly, an object of the present invention is to provide a synchronization processing device and a synchronization processing method capable of processing a digital material signal coming from the outside in synchronization with an internal clock signal without causing quality deterioration. It is in.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a synchronization processing apparatus according to the present invention is configured as follows.
(1) Digital broadcasting that handles a multiplexed signal that comes from the outside and multiplexes a first digital material signal such as a digital video signal and a second digital material signal such as a digital audio signal having a transmission block structure of a predetermined data length unit. A clock signal that is applied to a signal transmission system, extracts a second digital material signal from the multiplexed signal, synchronizes the second digital material signal with a clock signal handled by the digital broadcast signal transmission system, and handles the digital broadcast signal transmission system A synchronization processor for re-multiplexing the first digital material signal synchronized with
The storage means for storing the second digital material signal extracted from the multiplexed signal and the read timing generated from the coupling information and clock signal of the first digital material signal provided separately are stored in the storage means. Read control means for reading out the second digital material signal, and resampling processing means for resampling the second digital material signal read from the storage means by the read control means at a frequency rate synchronized with the clock signal. It is what I did.
[0010]
According to the configuration of (1) above, the digital audio signal extracted from the multiplexed signal from the outside is taken in and stored in the storage means. The digital audio signal stored in the storage means is read out at the read timing generated from the combined information of the clock signal of the digital broadcast signal transmission system and the first digital material signal, and thereafter the frequency synchronized with the clock signal. It will be resampled at the rate.
[0011]
Therefore, in order to synchronize an external digital audio signal with an internal clock signal, an A / D converter that converts the digital audio signal into an analog audio signal, or a digital audio that synchronizes this analog audio signal with the internal clock signal. There is no need to prepare a D / A converter to convert the signal, and digital audio signals from the outside can be processed in synchronization with the internal clock signal by digital processing by the storage means, sampling processing means and readout control means. Therefore, a relatively small and inexpensive device can be provided without causing quality deterioration or discontinuity in the digital audio signal and without using the A / D converter and the D / A converter.
[0012]
(2) The reading control means of (1) described above, when the digital video signal is lost, the digital audio stored in the storage means at a reading timing less than a reference clock number synchronized with the transmission block of the clock signal. A function for reading a signal is provided.
[0013]
According to the configuration of (2), when the external digital video signal has a lower frequency than the digital video signal in the own system, video loss occurs in the digital video signal in the own system at regular intervals. Since the same video as before missing is inserted for complementation, the digital audio signal stored in the storage means can be read out at a predetermined number of times less than the reference clock number synchronized with the clock signal transmission block. , The missing part of the video is offset. Therefore, if the number of clocks of the clock signal is controlled so as to compensate for the lack, it is possible to synchronously reproduce a digital audio signal that does not feel uncomfortable even if the digital video signal is missing.
[0014]
(3) The reading control means of (1) described above, when the digital video signal is skipped, the digital audio signal stored in the storage means at a predetermined number of times more than the number of clocks synchronized with the clock signal transmission block. Is provided with a function of reading out.
[0015]
According to the configuration of (3), when the external digital video signal has a higher frequency than the digital video signal in the own system, the video outside the station cannot be used for the digital video signal in the own system at regular intervals. Since the interval will occur, the digital audio signal stored in the storage means is read out at a read timing that is a predetermined number greater than the reference clock number synchronized with the clock signal transmission block, so that the skipped portion of the video is canceled out. ing. Therefore, if the number of clocks of the clock signal is controlled so as to compensate for the skip, a digital audio signal that does not feel uncomfortable can be synchronously reproduced even if the digital video signal handled internally is skipped.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0017]
FIG. 1 is a block diagram showing an embodiment of a synchronization processing apparatus according to the present invention.
[0018]
As shown in the figure, the synchronization processing device includes an audio signal extraction unit 21, a clock generation unit 22, a FIFO (First In First Out) memory (FIFO) 23, a read control unit 24, and a clock generation unit 25. A sampling rate converter 26, an audio signal multiplexing unit 27, a video signal extraction unit 28, and a video signal coupling unit 29.
[0019]
An SDI signal arriving from outside the station is first input to the audio signal extraction unit 21 and the clock generation unit 22. Of these, the clock generator 22 generates a clock signal synchronized with the input SDI signal. The audio signal extraction unit 21 extracts a digital audio signal multiplexed on the SDI signal at an extraction timing synchronized with the clock signal generated by the clock generation unit 22. The extracted digital audio signal is written into the FIFO memory 23 at a timing synchronized with the clock signal generated by the clock generator 22.
[0020]
The digital audio signal written in the FIFO memory 23 is read by the read control unit 24 at a read timing generated by the internal (intra-station) clock signal generated by the clock generation unit 25 and the video combination information provided separately. And input to the sampling rate converter 26. The internal clock signal is generated by the clock generator 25 from the synchronization signal in the station.
[0021]
The sampling rate converter 26 performs a resampling process on the digital audio signal read from the FIFO memory 23 at a frequency rate synchronized with the internal clock signal generated by the clock generator 25.
[0022]
Thereafter, the digital audio signal sampled by the sampling rate converter 26 is remultiplexed by the audio signal multiplexing unit 27 into an SDI signal synchronized with the synchronization signal in the station.
[0023]
On the other hand, the SDI signal from outside the station is input to the video signal extraction unit 28 to extract a digital video signal. This digital video signal is written to the video signal combining unit 29 at a write timing synchronized with the clock signal generated from the clock generation unit 22, and read at a read timing synchronized with the clock signal generated from the clock generation unit 25. As a result, it is converted into a digital video signal synchronized with the clock signal in the station, and is output to the audio signal multiplexing unit 27 as an SDI signal.
[0024]
Next, the operation of the above configuration will be described.
First, in order to synchronize the external digital audio signal with the internal clock signal, the audio signal extraction unit 21 extracts the digital audio signal from the external SDI signal, and the clock is synchronized with the SDI signal generated by the clock generation unit 22. The extracted digital audio signal is written into the FIFO memory 23 in accordance with the signal.
[0025]
The digital audio signal written in the FIFO memory 23 is read by the read control unit 24 at the read timing generated from the clock signal in the station and the video combination information, and is written in the sampling rate converter 26 with the same clock as the read timing.
[0026]
The sampling rate converter 26 performs a resampling process on the digital audio signal read from the FIFO memory 23 at a frequency rate synchronized with the internal clock signal generated by the clock generator 25.
[0027]
Here, if the frequency of the synchronization signal outside the station is lower than the frequency of the synchronization signal inside the station, the digital video signal inside the station will be lost in units of frames or fields at regular intervals, so the same as before being lost The video is inserted and complemented. FIG. 2 shows a state of the reading process of the reading control unit 24 in this case.
[0028]
In FIG. 2, N, N + 1... Indicate the frame of the digital video signal, and R indicates the reference clock number (reference frequency) synchronized with the frame of the clock signal by the read control unit 24.
[0029]
Here, the reading control unit 24 reads the digital audio signal from the FIFO memory 23 with a clock having a frequency lower than the reference frequency (with a longer period) in order to cancel out the missing portion of the video, and with the same clock as this. Write to the sampling rate converter 26. Then, the clock for reading the digital audio signal from the FIFO memory 23 and the clock for writing to the sampling rate converter 26 return to the reference frequency at a certain fixed time (when the audio complement is completed).
[0030]
For example, if the reference clock number of the digital audio signal synchronized with the video unit frame is R, the number of clocks for reading the digital audio signal from the FIFO memory 23 per video unit frame when it is notified that the video is missing. Is set to R-α, the missing portion of the video is complemented over the R / α frame period. Α is a value that can be arbitrarily set so as to complement the missing portion.
[0031]
On the other hand, when the frequency of the sync signal outside the station is higher than the frequency of the sync signal inside the station, the digital video signal inside the station has a section (jumping) where the video outside the station cannot be used in units of frames or fields at regular intervals. appear. The state of the reading process of the reading control unit 24 in this case is shown in FIG.
[0032]
Here, the reading control unit 24 reads the digital audio signal from the FIFO memory 23 with a clock having a frequency higher than the reference frequency (with a shorter period) in order to cancel out the interlaced portion of the video, and with the same clock as this. Write to the sampling rate converter 26. Then, the clock for reading the digital audio signal from the FIFO memory 23 and the clock for writing to the sampling rate converter 26 return to the reference frequency at a certain fixed time (when the audio complement is completed).
[0033]
For example, if the reference clock number of the digital audio signal synchronized with the video unit frame is R, the number of clocks for reading the digital audio signal from the FIFO memory 23 per video unit frame when it is notified that the video jump has occurred. Is set to R + α, the interlaced portion of the video is complemented over the R / α frame period.
[0034]
As a result, it is possible to realize synchronized reproduction of audio although it takes a certain period of time to complete audio complementation.
[0035]
As described above, in the above embodiment, instead of the A / D converter and the D / A converter, the FIFO memory 23, the read control unit 24, and the sampling rate converter 26 are provided, and the audio signal is extracted from the SDI signal from outside the station. The digital audio signal extracted by the unit 21 is written in the FIFO memory 23. The read control unit 24 reads the digital audio signal written in the FIFO memory 23 at the read timing generated from the in-station clock signal generated by the clock generation unit 25 and the video combination information, and the sampling rate converter 26 The digital audio signal read from the FIFO memory 23 is resampled at a frequency rate synchronized with the in-station clock signal generated by the clock generator 25.
[0036]
Therefore, in order to synchronize the digital audio signal from outside the station with the clock signal inside the station, it is not necessary to prepare an A / D converter or a D / A converter as in the prior art, and the FIFO memory 23, the read control unit 24, and Digital processing by the sampling rate converter 26 enables processing of a digital audio signal from outside the station in synchronization with an internal clock signal, so that the digital audio signal does not cause quality deterioration or discontinuity, and A Since a / D converter and a D / A converter are not used, a relatively small and inexpensive apparatus can be provided.
[0037]
Further, in the above-described embodiment, when the reading control unit 24 is notified of the occurrence of a missing digital video signal from the outside, the FIFO memory 23 has a predetermined timing less than the reference clock number synchronized with the video frame of the clock signal. Since the stored digital audio signal is read out, the number of clocks of the clock signal is reduced by a predetermined number, and control is performed so as to compensate for the missing video image. Digital audio signals without any sense of incongruity can be played back synchronously.
[0038]
Further, in the above-described embodiment, when the reading control unit 24 is notified of the occurrence of the jump of the digital video signal from the outside, the FIFO memory is read at a predetermined number of times higher than the reference clock number synchronized with the video frame of the clock signal. Since the digital audio signal stored in the digital video signal is read out, the digital video signal can be skipped simply by increasing the number of clocks of the clock signal by a predetermined number and controlling to complement the video jump. Even if it occurs, a digital audio signal that does not feel uncomfortable can be synchronously reproduced.
[0039]
In the above-described embodiment, the hardware configuration has been described. However, as illustrated in FIG. 4, the hardware configuration may be realized.
[0040]
In other words, reference numeral 100 denotes a synchronous processing device, to which a FIFO memory 200 is connected. The processing by the audio signal extraction unit 21, the clock generation unit 22, the read control unit 24, the clock generation unit 25, the sampling rate converter 26, and the audio signal multiplexing unit 27 is realized by software processing of the synchronization processing device 100. .
[0041]
First, when the control processing shown in FIG. 5 is started, the synchronization processing device 100 extracts a digital audio signal from an SDI signal coming from outside the station (step ST5a), and writes the extracted digital audio signal in the FIFO memory 200 ( Step ST5b).
[0042]
Subsequently, the synchronization processing apparatus 100 determines whether or not a video loss has occurred from the outside (step ST5c).
[0043]
If no video loss has occurred, synchronization processing apparatus 100 determines whether or not a video skip has occurred from the outside (step ST5d).
[0044]
Here, if video skipping has not occurred, the synchronization processing device 100 reads out the digital audio signal from the FIFO memory 200 at the reference clock number R synchronized with the video frame of the internal clock signal (step ST5e), and further the internal processing. The digital audio signal is resampled at a frequency rate synchronized with the clock signal (step ST5f), and the process ends.
[0045]
On the other hand, if a video loss occurs, the synchronization processing apparatus 100 reads the digital audio signal from the FIFO memory 200 with the number of clocks smaller by α than the reference clock number R synchronized with the video frame of the internal clock signal (step ST5g). Then, the process proceeds to step ST5f.
[0046]
If video skipping occurs, the synchronization processing device 100 reads out the digital audio signal from the FIFO memory 200 with a clock number that is α more than the reference clock number R synchronized with the video frame of the internal clock signal (step ST5h). Then, the process proceeds to step ST5f.
[0047]
As described above, the present invention can also be implemented by the other embodiments described above. In particular, since each process can be realized by software, the configuration is simplified, which can contribute to downsizing.
[0048]
In addition, the configuration of the synchronization processing device, the type of signal to be handled, the control procedure for synchronizing the digital audio signal with the clock signal in the station, and the contents thereof can be variously modified and implemented without departing from the scope of the present invention.
[0049]
【The invention's effect】
As described above in detail, according to the present invention, a synchronization processing apparatus and a synchronization processing method capable of processing a digital material signal coming from the outside in synchronization with an internal clock signal without causing quality degradation. Can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a synchronization processing apparatus according to the present invention.
FIG. 2 is a timing chart for explaining a processing operation when an image is missing in the embodiment.
FIG. 3 is a timing chart for explaining a processing operation at the time of image skipping in the embodiment.
FIG. 4 is a block diagram showing a configuration of a synchronization processing device according to another embodiment of the present invention.
FIG. 5 is a flowchart for explaining a processing operation in the other embodiment;
FIG. 6 is a block diagram showing the configuration of a signal processing apparatus that has been conventionally considered.
[Explanation of symbols]
11, 21 ... voice signal extraction unit,
12, 15, 22, 25 ... clock generator,
13 ... D / A converter (D / A),
14 ... A / D converter (A / D),
23, 200 ... FIFO memory,
24. Read control unit,
26: Sampling rate converter,
27. Audio signal multiplexing unit,
100: Synchronous processing device.

Claims (8)

The present invention is applied to a digital broadcast signal transmission system that handles a multiplex signal that comes from the outside and multiplexes a first digital material signal and a second digital material signal having a transmission block structure of a predetermined data length unit. And the second digital material signal is synchronized with the clock signal handled by the digital broadcast signal transmission system, and the first digital material signal synchronized with the clock signal handled by the digital broadcast signal transmission system is extracted. A re-multiplexing synchronization processing device comprising:
Storage means for storing the second digital material signal extracted from the multiplexed signal;
Read control means for reading out the second digital material signal stored in the storage means at the read timing generated from the combined information of the first digital material signal and the clock signal provided separately;
Re-sampling processing means for resampling the second digital material signal read from the storage means by the read control means at a frequency rate synchronized with the clock signal;
The reading control means is configured to store the first digital material signal stored in the storage means at a predetermined timing less than a reference clock number synchronized with the transmission block of the clock signal when a loss occurs in the first digital material signal. A synchronization processing apparatus comprising a function of reading two digital material signals . The present invention is applied to a digital broadcast signal transmission system that handles a multiplex signal that comes from the outside and multiplexes a first digital material signal and a second digital material signal having a transmission block structure of a predetermined data length unit. And the second digital material signal is synchronized with the clock signal handled by the digital broadcast signal transmission system, and the first digital material signal synchronized with the clock signal handled by the digital broadcast signal transmission system is extracted. A re-multiplexing synchronization processing device comprising:
Storage means for storing the second digital material signal extracted from the multiplexed signal;
Read control means for reading out the second digital material signal stored in the storage means at the read timing generated from the combined information of the first digital material signal and the clock signal provided separately;
Re-sampling processing means for resampling the second digital material signal read from the storage means by the read control means at a frequency rate synchronized with the clock signal;
The read control means is configured to store the first digital material signal stored in the storage means at a read timing greater than a reference clock number synchronized with the transmission block of the clock signal when a jump occurs in the first digital material signal. A synchronization processing apparatus comprising a function of reading two digital material signals . This is applied to a digital broadcast signal transmission system that handles a multiplexed signal in which a digital video signal and a digital audio signal having a transmission block structure of a predetermined data length unit are received from outside, and the digital audio signal is extracted from the multiplexed signal. A synchronization processor that synchronizes a digital audio signal with a clock signal handled by the digital broadcast signal transmission system and re-multiplexes the digital audio signal with a digital video signal synchronized with the clock signal handled by the digital broadcast signal transmission system;
Storage means for storing the digital audio signal extracted from the multiplexed signal;
Read control means for reading out the digital audio signal stored in the storage means at the read timing generated from the combined information of the digital video signal and the clock signal provided separately;
Re-sampling processing means for resampling the digital audio signal read from the storage means by the read control means at a frequency rate synchronized with the clock signal;
The read control means reads the digital audio signal stored in the storage means at a read timing less than a reference clock number synchronized with the transmission block of the clock signal when a loss occurs in the digital video signal. A synchronization processing apparatus comprising a reading function . This is applied to a digital broadcast signal transmission system that handles a multiplexed signal in which a digital video signal and a digital audio signal having a transmission block structure of a predetermined data length unit are received from outside, and the digital audio signal is extracted from the multiplexed signal A synchronization processor that synchronizes a digital audio signal with a clock signal handled by the digital broadcast signal transmission system and re-multiplexes the digital audio signal with a digital video signal synchronized with the clock signal handled by the digital broadcast signal transmission system;
Storage means for storing the digital audio signal extracted from the multiplexed signal;
Read control means for reading out the digital audio signal stored in the storage means at read timing generated from the combined information of the digital video signal and the clock signal provided separately;
Resampling processing means for resampling the digital audio signal read from the storage means by the read control means at a frequency rate synchronized with the clock signal;
The reading control means, when a jump occurs in the digital video signal, reads the digital audio signal stored in the storage means at a reading timing that is a predetermined number more than a reference clock number synchronized with the transmission block of the clock signal. A synchronization processing apparatus comprising a reading function. The present invention is applied to a digital broadcast signal transmission system that handles a multiplex signal that comes from the outside and multiplexes a first digital material signal and a second digital material signal having a transmission block structure of a predetermined data length unit. And the second digital material signal is synchronized with the clock signal handled by the digital broadcast signal transmission system, and the first digital material signal synchronized with the clock signal handled by the digital broadcast signal transmission system is extracted. Re-multiplexing synchronous processing method,
A first step of storing the second digital material signal extracted from the multiplexed signal in a memory;
A second step of reading out the second digital material signal stored in the memory at a read timing generated from the coupling information of the first digital material signal and the clock signal provided separately;
A third step of resampling the second digital material signal read from the memory by the second step at a frequency rate synchronized with the clock signal;
In the second process, when a loss occurs in the first digital material signal, the clock signal stored in the storage unit is read at a predetermined number of times less than a reference clock number synchronized with the transmission block of the clock signal. A synchronization processing method characterized by reading a second digital material signal . The present invention is applied to a digital broadcast signal transmission system that handles a multiplex signal that comes from the outside and multiplexes a first digital material signal and a second digital material signal having a transmission block structure of a predetermined data length unit. And the second digital material signal is synchronized with the clock signal handled by the digital broadcast signal transmission system, and the first digital material signal synchronized with the clock signal handled by the digital broadcast signal transmission system is extracted. Re-multiplexing synchronous processing method,
A first step of storing the second digital material signal extracted from the multiplexed signal in a memory;
A second step of reading out the second digital material signal stored in the memory at a read timing generated from the coupling information of the first digital material signal and the clock signal provided separately;
A third step of resampling the second digital material signal read from the memory by the second step at a frequency rate synchronized with the clock signal;
The second process, when the jump to the first digital materials signal is generated, at a predetermined numerous read timing from the reference number of clocks in synchronization with the transmission blocks of the clock signal, stored in said storage means A synchronization processing method, wherein the second digital material signal is read . This is applied to a digital broadcast signal transmission system that handles a multiplexed signal in which a digital video signal and a digital audio signal having a transmission block structure of a predetermined data length unit are received from outside, and the digital audio signal is extracted from the multiplexed signal. A synchronization processing method for synchronizing a digital audio signal with a clock signal handled by the digital broadcast signal transmission system and remultiplexing the digital audio signal into a digital video signal synchronized with the clock signal handled by the digital broadcast signal transmission system,
A first step of storing the digital audio signal extracted from the multiplexed signal in a memory;
A second step of reading the digital audio signal stored in the memory at a read timing generated from the combined information of the digital video signal and the clock signal provided separately;
A third step of resampling the digital audio signal read from the memory by the second step at a frequency rate synchronized with the clock signal;
In the second process, when the digital video signal is missing, the digital audio signal stored in the storage means is read at a predetermined number of times less than a reference clock number synchronized with the transmission block of the clock signal. A synchronous processing method characterized by reading out. This is applied to a digital broadcast signal transmission system that handles a multiplexed signal in which a digital video signal and a digital audio signal having a transmission block structure of a predetermined data length unit are received from outside, and the digital audio signal is extracted from the multiplexed signal A synchronization processing method for synchronizing a digital audio signal with a clock signal handled by the digital broadcast signal transmission system and remultiplexing the digital audio signal into a digital video signal synchronized with the clock signal handled by the digital broadcast signal transmission system,
A first step of storing the digital audio signal extracted from the multiplexed signal in a memory;
A second step of reading the digital audio signal stored in the memory at a read timing generated from the combined information of the digital video signal and the clock signal provided separately;
A third step of resampling the digital audio signal read from the memory by the second step at a frequency rate synchronized with the clock signal;
In the second step, the digital audio signal stored in the storage means is read out at a predetermined number of times higher than a reference clock number synchronized with the transmission block of the clock signal when a jump occurs in the digital video signal. A synchronous processing method characterized by reading out.

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