JP4162947B2 - Semiconductor device and electronic apparatus using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having an image sensor function. In particular, the present invention relates to a structure of a pixel portion of the semiconductor device.
[0002]
[Prior art]
A semiconductor device having an image sensor function is provided with a photoelectric conversion element and one or a plurality of transistors for controlling the photoelectric conversion element. As the photoelectric conversion element, a PN type photodiode is often used. In addition, there are a PIN photodiode, an avalanche diode, an npn buried diode, a Schottky diode, a phototransistor, an X-ray photoconductor, an infrared sensor, and the like.
[0003]
Semiconductor devices having an image sensor function are roughly classified into a CCD type and a CMOS type. CMOS type semiconductor devices are classified as passive types without an amplification circuit and active types with an amplification circuit. Since the amplification circuit has a function of amplifying the image signal of the subject read by the photoelectric conversion element, it is not easily affected by noise. Therefore, an active CMOS semiconductor device on which an amplification circuit is mounted is employed in many electronic devices.
[0004]
FIG. 4 is a schematic view of a semiconductor device provided with a photoelectric conversion element. The semiconductor device in FIG. 4 includes a pixel portion 104, a source signal line driver circuit 101, a gate signal line driver circuit 102, and a reset signal line driver circuit 103 arranged around the pixel portion 104. The source signal line drive circuit 101 includes a bias circuit 101a, a sample hold circuit 101b, a signal output line drive circuit 101c, and a final output amplification circuit 101d. The pixel portion 104 includes (x × y) pixels 100 provided in a matrix (x and y are natural numbers).
[0005]
FIG. 11A shows a circuit diagram of the pixel 100 provided in the i-th column and the j-th row (i and j are natural numbers). The pixel 100 includes any one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), one of gate signal lines (G1 to Gy), and a reset signal line ( R1 to Ry) are arranged in a region surrounded by any one of them. The pixel 100 includes an n-channel switching transistor 1120, an n-channel amplification transistor 1130, a p-channel reset transistor 1140, and a photoelectric conversion element 1110. The p-channel side terminal of the photoelectric conversion element 1110 is connected to the power supply reference line 1210.
[0006]
Note that when describing the circuit operation, the operation of the transistor may be described. When the transistor is turned on, the absolute value of the gate-source voltage of the transistor is the absolute value of the threshold voltage of the transistor. This corresponds to the case where the source region and the drain region of the transistor are brought into conduction through the channel formation region. On the other hand, when the transistor is turned off, the absolute value of the gate-source voltage of the transistor is lower than the absolute value of the threshold voltage of the transistor, and the source region and the drain region of the transistor are in a non-conductive state. Equivalent to.
[0007]
The photoelectric conversion element 1110 included in the pixel 100 changes its potential when irradiated with light reflected from the subject. More specifically, the potential of the n-channel side terminal of the photoelectric conversion element 1110 changes. In this state, when the gate signal line (Gj) is selected, the switching transistor 1120 connected to the gate signal line (Gj) is turned on. Then, the potential of the n-channel side terminal of the photoelectric conversion element 1110 is read as a signal. The signal output to the signal output line (Sj) is supplied to the source signal line driver circuit 101.
[0008]
Note that the accumulation time corresponds to a period from when a photoelectric conversion element provided in a pixel is initialized to when a signal is output from the pixel. Further, it is a time for irradiating light to the light receiving portion of the photoelectric conversion element and accumulating signals, and corresponds to a time called exposure time.
[0009]
The amplitude of the signal input to the n-channel transistor is V V for both the signal input from the reset signal line and the signal input from the gate signal line. _dd (Hi, H level) -V _ss (Lo, L level). The amplitude of the signal input to the p-channel transistor is V V for both the signal input from the reset signal line and the signal input from the gate signal line. _ss (Hi, H level) -V _dd (Lo, L level). As an initial state, the potentials of the source signal line (Si), the gate signal line (Gj), the reset signal line (Rj), and the power supply reference line 1210 are all V. _ss And the potential of the power supply line (VBi) is V _dd And
[0010]
Next, a connection relation and operation of the p-channel reset transistor 1140 in FIG. 11A are briefly described. The source region of the reset transistor 1140 is connected to the power supply line (VBi), and the drain region is connected to the n-channel side terminal of the photoelectric conversion element 1110. The gate electrode of the reset transistor 1140 is connected to the reset signal line (Rj).
[0011]
Further, in the pixel 100 in FIG. 11A, the p-channel side terminal of the photoelectric conversion element 1110 is connected to the power supply line 1210, and the n-channel side terminal is connected to the source region of the reset transistor 1140.
[0012]
When the reset signal line (Rj) in the j-th row is selected, the gate electrode of the p-channel type reset transistor 1140 has V _ss (Hi) signal is input. Then, the gate-source voltage V _gs Becomes less than or equal to zero, and the reset transistor 1140 is turned on. At this time, the potential of the source region of the reset transistor 1140 connected to the power supply line (VBi) is V _dd It is. Then, the potential V between both terminals of the photoelectric conversion element 1110 _pd Is the potential V of the power supply line (VBi) _dd And the same potential (V _pd = V _dd )
[0013]
Next, the relationship between the intensity of light applied to the photoelectric conversion element 1110 and the potential of the photoelectric conversion element 1110 will be described with reference to FIG. In FIG. 11B, the solid line indicates the potential V of the photoelectric conversion element 1110 when dark light is irradiated. _pd The dotted line indicates the potential V of the photoelectric conversion element 1110 when bright light is irradiated. _pd The broken line indicates the potential of the reset signal line Rj.
[0014]
The photoelectric conversion element 1110 accumulates charges generated by the irradiated light during the accumulation time. Therefore, if the accumulation time is different, even if light having the same light intensity is irradiated, the total amount of charges generated by the light is different, and thus the signal value is also different. As shown in FIG. 11B, when bright light is irradiated to the photoelectric conversion element 1110, the saturation state is reached in a short accumulation time. On the other hand, when the photoelectric conversion element 1110 is irradiated with dark light, the storage time is long, but eventually reaches saturation. That is, the signal read from the photoelectric conversion element 1110 is determined by the product of the intensity of the irradiated light and the accumulation time. Note that saturation is a state in which the potential of the n-channel terminal of the photoelectric conversion element 1110 becomes low and the potential reaches the potential of the power supply reference line 1210 and is not changed when very bright light is irradiated. Equivalent to.
[0015]
In the pixel 100 illustrated in FIG. 11, the reset transistor 1140 is a p-channel type, and the potential difference V between both electrodes of the photoelectric conversion element 1110. _pd Is the potential V supplied from the power supply line (VBi). _dd Thus, it is possible to obtain a sufficient signal amplitude. In other words, the potential of the n-channel side terminal of the photoelectric conversion element 1110 does not cause amplitude attenuation, and V _dd The potential can be raised sufficiently.
[0016]
Next, the case where all the transistors included in the pixel 100 are n-channel transistors is described with reference to FIG. Note that the threshold voltage of the n-channel reset transistor 1140 is V _thN Is written. The operation of the n-channel reset transistor 1140 in FIG. 12A will be briefly described. When the reset signal line (Rj) in the j-th row is selected, the gate electrode of the n-channel type reset transistor 1140 has V _dd (Hi) signal is input. The potential of the drain region of the reset transistor 1140 connected to the power supply line (VBi) is V _dd It becomes.
[0017]
The reset transistor 1140 is turned on when the absolute value of the gate-source voltage (Vgs) exceeds the absolute value of the threshold voltage (VthN), and the absolute value of the gate-source voltage (Vgs). Becomes lower than the absolute value of the threshold voltage (VthN).
[0018]
That is, the gate-source voltage V of the reset transistor 1140 _gs Is V _thN Is larger than the reset transistor 1140, the reset transistor 1140 is turned on. Conversely, V _gs Is V _thN If it becomes smaller than that, the reset transistor 1140 is turned off, and the voltage supplied from the power supply line (VBi) does not reach the n-channel terminal of the photoelectric conversion element 1110. That is, the potential difference V between both electrodes of the photoelectric conversion element 1110 _pd Is the potential V of the power supply line (VBi) _dd To threshold voltage V of reset transistor 1140 _thN Minus (V _dd -V _thN ) No more than that.
[0019]
Next, the relationship between the intensity of light applied to the photoelectric conversion element 1110 and the potential of the photoelectric conversion element 1110 will be described with reference to FIG. As described above, the potential difference V between both terminals of the photoelectric conversion element 1110 _pd Is the potential V of the power supply line (VBi) _dd To threshold voltage V _thN Minus (V _dd -V _thN ) No more than that. Therefore, threshold voltage V _thN As the value increases, the amplitude attenuation increases, so that the potential difference V between both terminals of the photoelectric conversion element 1110 _pd Cannot obtain a sufficient signal amplitude. That is, the threshold voltage V _thN As the value increases, the potential of the n-channel terminal of the photoelectric conversion element 1110 cannot be sufficiently increased. As a result, the change in potential of the photoelectric conversion element 1110 becomes weak, and the signal output from the pixel 100 is not so different. If it does so, it will become difficult to read the information on a subject clearly.
[0020]
Next, the case where all the transistors included in the pixel 100 are p-channel transistors is described with reference to FIG. The threshold voltage of the p-channel type reset transistor 1140 is V _thP Is written. In the pixel 100 in FIG. 14A, the n-channel side terminal of the photoelectric conversion element 1110 is connected to the power supply line 1210, and the p-channel side terminal is connected to the source region of the reset transistor 1140.
[0021]
In FIG. 14A, V is applied to the reset transistor 1140. _ss When the (Hi) signal is input, the reset transistor is turned on. At this time, the potential of the drain region of the reset transistor 1140 is V _ss The potential of the source region is the potential V of the power supply line (VBi). _ss And the threshold voltage (V _ss + | V _thP |) Then, the potential V between both terminals of the photoelectric conversion element 1110 _pd Is the potential V of the power supply line (VBi) _dd To the potential V of the power supply line (VBi) _ss And the threshold voltage (V _ss + | V _thP |) No more. That is, the potential of the photoelectric conversion element 1110 is V _dd -(V _ss + | V _thP |) No more.
[0022]
In summary, the pixel illustrated in FIGS. 11A, 12A, and 14A includes three transistors, a switching transistor 1120, an amplifying transistor 1130, and a resetting transistor 1140, and a photoelectric conversion element. 1110 and the three pixels have the same configuration. However, in FIGS. 11A and 14A, the reset transistor 1140 is a p-channel type and in FIG. 12A is an n-channel type, and their conductivity types are different.
[0023]
As described above, in the pixel illustrated in FIG. 11A, the reset transistor 1140 is a p-channel transistor, and the potential difference V between both electrodes of the photoelectric conversion element 1110 _pd Is the power supply potential V _dd Can be raised enough. On the other hand, in the pixel illustrated in FIG. 12A, the reset transistor 1140 is an n-channel type, and the potential V between both terminals of the photoelectric conversion element 1110. _pd Amplitude decay occurs and the power supply potential V _dd To threshold voltage V _thN Greater than or equal to (V _dd -V _thN ) Does not. In the pixel illustrated in FIG. 14A, the reset transistor 1140 is a p-channel transistor, and the potential between both terminals of the photoelectric conversion element is attenuated by amplitude. _dd -(V _ss + | V _thP |) No more.
[0024]
[Problems to be solved by the invention]
By the way, in a semiconductor device in which a semiconductor element such as a transistor is manufactured over an insulating surface or a semiconductor substrate, a complicated point of the manufacturing process leads to a decrease in yield and an increase in cost. Therefore, simplification of the process as much as possible is a main issue for yield increase and cost reduction. Therefore, the present inventor has devised that the pixel portion and the peripheral drive circuits (source signal line drive circuit, gate signal line drive circuit, and the like) are configured by transistors of a single polarity (the same conductivity type).
[0025]
By the way, in the pixel 100 illustrated in FIG. 12A, all transistors are n-channel transistors, and are configured with a single polarity transistor. Similarly, in the pixel 100 illustrated in FIG. 14A, all the transistors are p-channel transistors and are formed of a single polarity transistor. However, amplitude attenuation has occurred in both pixels, and sufficient signal amplitude cannot be obtained.
[0026]
In addition, the pixel 100 illustrated in FIG. 11A includes a potential difference V between both electrodes of the photoelectric conversion element 1110. _pd The power supply potential V _dd It is possible to obtain a sufficient signal amplitude. However, since the pixel 100 includes transistors of different conductivity types, the manufacturing process is complicated.
[0027]
From the above, if the pixel unit and the drive circuit unit are configured with a single polarity transistor in the conventional pixel configuration, the process reduction is realized, but a sufficient signal amplitude cannot be obtained.
[0028]
The present invention has been made in view of the above problems, and provides a semiconductor device that realizes an increase in yield and cost by reducing the number of steps by forming a pixel with a single polarity (same conductivity type) transistor. The task is to do. Another object of the present invention is to provide a semiconductor device in which a photoelectric conversion element can obtain a sufficient signal amplitude.
[0029]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a semiconductor device in which each pixel is provided with an electric circuit (bootstrap circuit) that generates a potential higher than a voltage given by capacitive coupling. In addition, the present invention provides a semiconductor device capable of obtaining a sufficient signal amplitude by setting the potential between both terminals of the photoelectric conversion element to the same value as the power supply potential by using the electric circuit. Furthermore, the present invention provides a semiconductor device in which a pixel is configured by a single polarity transistor, thereby reducing the number of steps and realizing an increase in yield and a reduction in cost.
[0030]
A pixel provided in the semiconductor device of the present invention will be briefly described with reference to FIG. In FIG. 14B, the pixel 100 includes a switching element, an amplifying element, a resetting element, and a bootstrap circuit. A semiconductor element such as a transistor is used as the element. The bootstrap circuit is composed of a semiconductor element, a capacitor element, and the like, and has a function of generating a potential higher than a voltage given by capacitive coupling. In the present invention, the amplitude attenuation is generated in the potential between the two terminals of the photoelectric conversion element by the threshold voltage of the resetting element. So that a sufficient signal amplitude can be obtained.
[0031]
FIG. 1A illustrates a detailed structure of the pixel illustrated in FIG. A pixel 100 illustrated in FIG. 1A includes a photoelectric conversion element 111, a switching transistor 112, an amplification transistor 113, a reset transistor 114, a boot transistor 115, a capacitor 116, and a discharge transistor 117. Note that in FIG. 1A, all transistors provided in the pixel 100 are n-channel transistors.
[0032]
As shown in FIG. 1A, the gate electrode of the boot transistor 115 is connected to the power supply line (VBi), and one of the source region and the drain region of the boot transistor 115 is the reset signal line (Rj). And the other is connected to the gate electrode of the resetting transistor 114. One of the source region and the drain region of the reset transistor is connected to a power supply line (VBi).
[0033]
One terminal of the capacitor 116 is connected to one of the source region and the drain region of the boot transistor 115 and the gate electrode of the reset transistor 114, and the other terminal is the other of the source region and the drain region of the reset transistor. It is connected to the.
[0034]
Note that in the pixel 100 illustrated in FIG. 12, the potential supplied from the power supply line (VBi) to the photoelectric conversion element 111 through the reset transistor 114 did not exceed (Vdd−VthN). However, the pixel 100 shown in FIG. 1 includes a boot transistor 115 and a capacitor 116 to which a bootstrap circuit is applied. In brief, the bootstrap method is a method of creating a potential higher than a given voltage by using capacitive coupling. In other words, the pixel 100 of the present invention has a pixel configuration to which the bootstrap method is applied, and thus the potential applied to the photoelectric conversion element 111 can be returned to a normal amplitude by using capacitive coupling. In other words, in the pixel 100 of the present invention, the potential applied to the photoelectric conversion element 111 through the reset transistor 114 can be the same potential (Vdd) as the power supply line (VBi).
[0035]
The present invention having the above-described structure can provide a semiconductor device in which the number of steps is reduced by forming a pixel with transistors having the same polarity (same conductivity type), thereby increasing yield and reducing cost. In addition, the present invention can provide a semiconductor device in which the photoelectric conversion element can obtain a sufficient signal amplitude. Thereby, it is possible to improve the reading accuracy of the subject by the photoelectric conversion element.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment)
An embodiment of the present invention will be described with reference to FIGS.
[0037]
FIG. 4 shows a schematic diagram of the semiconductor device. The semiconductor device illustrated in FIG. 4 includes a pixel portion 104, a source signal line driver circuit 101 and a gate signal line driver circuit 102 which are arranged around the pixel portion 104. Note that although one source signal line driver circuit 101 and one gate signal line driver circuit 102 are provided in this embodiment mode, the present invention is not limited to this. Depending on the configuration of the pixel 100, the number of driver circuits such as the gate signal line driver circuit 102 and the reset signal line driver circuit 103 can be arbitrarily set. 4 includes a bias circuit 101a, a sample hold circuit 101b, a signal output line drive circuit 101c, and a final output amplification circuit 101d. However, the present invention is not limited to this. . In addition to the above, the source signal line driver circuit 101 may be provided with an analog / digital signal conversion circuit, a noise reduction circuit, or the like.
[0038]
The pixel portion 104 has a plurality of pixels 100 arranged in a matrix. More specifically, the pixel unit 104 includes x columns (vertical) × y rows (horizontal) (100, x and y are natural numbers) of pixels 100.
[0039]
A structure of the pixel 100 provided in the i-th column and the j-th row in the pixel portion 104 is described with reference to FIG. The pixel 100 includes a signal output line (S ₁ ~ S _x ) And the power supply line (VB) ₁ ~ VB _x ) And a gate signal line (G ₁ ~ G _y ) And the reset signal line (R ₁ ~ R _y ) And a discharge signal line (H ₁ ~ H _y ) Are arranged in a region surrounded by any one of the above. In addition, the pixel 100 includes a switching transistor 112, an amplification transistor 113, a reset transistor 114, a boot transistor 115, a capacitor 116, a discharge transistor 117, and a photoelectric conversion element 111. . The boot transistor 115, the capacitor 116, and the discharge transistor 117 correspond to a bootstrap circuit.
[0040]
The photoelectric conversion element 111 includes an n-channel side terminal, a p-channel side terminal, and a photoelectric conversion layer provided between the n-channel side terminal and the p-channel side terminal. One of the p-channel side terminal and the n-channel side terminal is connected to the power supply reference line 121, and the other is connected to the gate electrode of the amplifying transistor 113.
[0041]
The gate electrode of the switching transistor 112 is a gate signal line (G _j )It is connected to the. One of the source region and the drain region of the switching transistor 112 is connected to the source region of the amplifying transistor 113, and the other is connected to the signal output line (S _i )It is connected to the. The switching transistor 112 is a transistor that functions as a switching element when a signal from the photoelectric conversion element 111 is output to the source signal line driver circuit 101.
[0042]
The drain region of the amplifying transistor 113 is a power supply line (VB _i )It is connected to the. The source region of the amplifying transistor 113 is connected to the source region or the drain region of the switching transistor 112. The amplifying transistor 113 forms a source follower circuit with a biasing transistor (not shown) provided in a peripheral circuit of the pixel portion 104. Therefore, the polarity of the amplifying transistor 113 and the biasing transistor is preferably the same.
[0043]
The gate electrode of the reset transistor 114 is connected to the reset signal line (R _j )It is connected to the. One of the source region and the drain region of the reset transistor 114 is a power supply line (VB _i And the other is connected to the gate electrodes of the photoelectric conversion element 111 and the amplifying transistor 113. The reset transistor 114 is a transistor that functions as a switching element for initializing (resetting) the photoelectric conversion element 111.
[0044]
The gate electrode of the boot transistor 115 is a power supply line (VB _i )It is connected to the. One of the source region and the drain region of the boot transistor 115 is a reset signal line (R _j And the other is connected to the gate electrode of the resetting transistor 114 and one terminal of the capacitor 116.
[0045]
The gate electrode of the discharge transistor 117 is connected to the discharge signal line (H _j )It is connected to the. One of the source region and the drain region of the discharging transistor 117 is connected to one terminal of the photoelectric conversion element 111, and the other is connected to the power supply reference line 118.
[0046]
Next, operation of the pixel 100 illustrated in FIG. 1A will be described with reference to FIGS. 1B, 2, and 3. The description of the operation of the pixel 100 will be divided into an initialization operation and a reset operation. The initialization operation corresponds to an operation for sufficiently reducing the potential of the n-channel terminal of the photoelectric conversion element 111. More specifically, the potential of the n-channel side terminal of the photoelectric conversion element 111 is set to the potential V of the power supply reference line. _ss This corresponds to an operation of reducing the potential difference between both electrodes of the photoelectric conversion element 111 to zero. The reset operation corresponds to an operation for sufficiently raising the potential of the n-channel terminal of the photoelectric conversion element 111. More specifically, the potential of the n-channel side terminal of the photoelectric conversion element 111 is set to the potential V of the power supply line. _dd The potential difference between both electrodes of the photoelectric conversion element 111 is V _dd It corresponds to the same operation. 1B shows the pixel 100 when the initialization operation is performed, and FIGS. 2A and 2B show the pixel 100 when the reset operation is performed. FIG. 3 shows the relationship between the potential of the photoelectric conversion element 111, the potential of the gate electrode of the resetting transistor 114, and time. Note that FIG. 1B to FIG. 2B are time-series, and the horizontal axis of FIG. 3 indicates time, so that FIG. 2 and FIG. 3 should correspond to each other. Here, all the transistors constituting the pixel 100 are n-channel transistors, and the threshold voltage is V _thN Is written.
[0047]
First, the initialization operation of the pixel 100 will be described with reference to FIG. In FIG. 1B, when the discharge signal line (Hj) in the j-th row is selected, the signal (V) is supplied to the discharge transistor 115 connected to the discharge signal line (Hj). _dd (Hi)) is input to turn on. Then, the potential of the n-channel side terminal of the photoelectric conversion element 111 is the potential V of the power supply reference line 118. _ss The potential difference between both electrodes of the photoelectric conversion element 111 can be made zero. As shown in FIG. 3, the potential of the power supply line 121 is V _ss Is set to
[0048]
Next, the reset operation of the pixel 100 will be described with reference to FIGS. Here, the potential of the gate electrode of the boot transistor 115 connected to the power supply line (VBi) is V _dd And it is on. At this time, a region connected to the reset signal line (Rj) of the boot transistor 115 is a drain region, and the other region is a source region.
[0049]
The boot transistor 115 has a gate-source voltage V _gs Is the threshold voltage V _thN If it is larger than V, it turns on and V _gs Is V _thN When it becomes smaller than that, the boot transistor 114 is turned off. That is, the potential difference between the source region of the boot transistor 115 and the gate electrode of the reset transistor 114 is the potential V of the power supply line (VBi). _dd To threshold voltage V _thN Minus (V _dd -V _thN ) No more than that.
[0050]
In this state, when the reset signal line (Rj) in the j-th row is selected, a signal is input to the gate electrode of the reset transistor 114, and the reset transistor 114 is turned on. Note that the signal input to the reset transistor 114 is V _dd Although the signal should be (Hi), the potential of the source region of the boot transistor 115 is (V _dd -V _thN ) It will not be the above value. Therefore, in practice, the gate electrode of the reset transistor 114 has V _dd Not (Hi) potential signal, (V _dd -V _thN ) The following potential signals are input.
[0051]
Here, the relationship between the potential of the gate electrode of the resetting transistor 114 and time will be described with reference to FIG. As can be seen from FIG. 3, the signal (V _dd When (Hi)) is input, the potential of the gate electrode of the reset transistor 114 gradually increases. Along with this, the potential at the n-channel side terminal of the photoelectric conversion element 111 gradually increases. The potential of the gate electrode of the resetting transistor 114 is (V _dd -V _thN ) To the value of V) of the boot transistor 115 _gs Is the threshold voltage V _thN It becomes the same value as and turns off. At the same time, the potential of the source region of the boot transistor 115 is (V _dd -V _thN ) And the gate electrode of the resetting transistor 114 is once in a floating state.
[0052]
In this state, the potential of the gate electrode of the reset transistor 114 and the potential of the source region of the boot transistor 115 are raised by capacitive coupling by a bootstrap method. As shown in FIG. 3, even after the boot transistor 115 is turned off, conversion The potential of the element 111 continues to rise. This is because the potential of the gate electrode of the resetting transistor 114 is gradually increased due to the amplitude compensation of capacitive coupling.
[0053]
As the potential of the gate electrode of the resetting transistor 114 increases, the potential of the n-channel side terminal of the photoelectric conversion element 111 also increases little by little, and the maximum signal amplitude between both terminals of the photoelectric conversion element 111 is V _dd It becomes.
[0054]
Next, when the reset transistor 114 is turned off and the accumulation period is started, the potential of the n-channel side terminal of the photoelectric conversion element 111 gradually increases with the intensity of light irradiated on the photoelectric conversion element 111. Going down. When a certain period of time has passed and the accumulation period ends, the j-th gate signal line (Gj) is selected. When the gate signal line (Gj) is selected, the switching transistor 112 is turned on. Then, the signal of the pixel 100 is output to the signal output line (Si) through the amplification transistor 113 and the switching transistor 112. Then, when the signal of the pixel 100 is output to the signal output line (Si), one frame period ends. Then, the next frame period is started and the above operation is repeated.
[0055]
The present invention having the above-described structure can provide a semiconductor device in which the number of steps is reduced by forming a pixel with transistors having the same polarity (same conductivity type), thereby increasing yield and reducing cost. In addition, the present invention can provide a semiconductor device in which the photoelectric conversion element can obtain a sufficient signal amplitude.
[0056]
【Example】
(Example 1)
In this embodiment, the case where the present invention is applied to a semiconductor device in which a light emitting element and a photoelectric conversion element are provided in one pixel will be described with reference to FIGS.
[0057]
A schematic view of the semiconductor device of the present invention is shown in FIG. The semiconductor device in FIG. 7 includes a pixel portion 130 and a plurality of driver circuits arranged around the pixel portion 130. The pixel unit 130 is roughly divided into a light emitting element unit and a sensor unit, and the plurality of driving circuits include a source signal line driving circuit 131, a gate signal line driving circuit 132, a reset signal line driving circuit 133, and a sensor that control the light emitting element unit. A sensor source signal line driving circuit 134, a sensor gate signal line driving circuit 135, a sensor reset signal line driving circuit 136, and a sensor discharge signal line driving circuit 137.
[0058]
Note that the present invention is not limited to the above configuration, and an output switching circuit or the like is provided to share the gate signal line driving circuit 132 and the sensor gate signal line driving circuit 135, or the reset signal line driving circuit 133 and the sensor reset signal. The line driving circuit 136 may be shared.
[0059]
The pixel portion 104 has a plurality of pixels 100 arranged in a matrix. More specifically, the pixel unit 104 has x columns (vertical) × y rows (horizontal) pixels 100.
[0060]
FIG. 8 illustrates a configuration of the pixel 100 provided in the i-th column and the j-th row in the pixel unit 104. The pixel 100 is roughly divided into a light emitting element portion and a sensor portion. The light emitting element section includes any one of source signal lines (S1 to Sx), one of power supply reference lines (V1 to Vx), one of gate signal lines (EG1 to EGy), and a reset signal line. They are arranged in a region surrounded by any one of (ER1 to ERy). The light-emitting element portion includes a selection transistor 126, a reset transistor 127, a capacitor 128, a drive transistor 129, and a light-emitting element 125. One terminal of the light emitting element 125 is connected to the power supply line 153 (V _dd )It is connected to the.
[0061]
The sensor unit includes any one of signal output lines (SS1 to SSx), one of power supply reference lines (VB1 to VBx), one of gate signal lines (SG1 to SGy), and a reset signal line ( SR1 to SRy) and any one of the discharge signal lines (H1 to Hy) are arranged in a region. The sensor portion also includes a switching transistor 142, an amplification transistor 143, a reset transistor 144, a boot transistor 145, a capacitor 146, a discharge transistor 147, and a photoelectric conversion element 141. One terminal of the photoelectric conversion element is connected to the power supply line 151 (V _dd ) And one of the source region and the drain region of the discharge transistor 147 is connected to the power supply line 148 (V _dd )It is connected to the.
[0062]
In this embodiment, all transistors included in the pixel 100 illustrated in FIG. 8 are p-channel transistors. The amplitude of the signal input to the transistor is V _ss (Hi) -V _dd (Lo). Further, as an initial state, the potentials of the source signal line (S), the gate signal line (EG), the reset signal line (ER), and the power supply reference line (V) are V _ss And The potentials of the signal output line (SS), the gate signal line (G), the sensor reset signal line (R), and the power supply line (VB) are V _ss And The potentials of the power supply line 153, the power supply line 151, and the power supply line 148 are V. _dd And
[0063]
Next, a light-emitting element 125 provided in the light-emitting element portion, and a connection structure of a plurality of transistors and capacitors that control the light-emitting element 125 are described.
[0064]
The light emitting element 125 includes an anode and a cathode, and an organic compound layer provided between the anode and the cathode. In the case where the anode is connected to the source region or the drain region of the driving transistor 129, the anode serves as a pixel electrode and the cathode serves as a counter electrode. Conversely, when the cathode is connected to the source region or the drain region of the driving transistor 129, the cathode serves as a pixel electrode and the anode serves as a counter electrode. In this embodiment, since the driving transistor 129 is a p-channel type, the anode of the light emitting element 125 is connected to the source region or the drain region of the driving transistor, and the cathode of the light emitting element 125 is the power supply line 1. 5 3 (V _dd ).
[0065]
Note that the light-emitting element has a structure in which an organic compound layer is sandwiched between a pair of electrodes (an anode and a cathode). The organic compound layer can be manufactured using a known light-emitting material. In addition, the organic compound layer has two structures, a single layer structure and a laminated structure, and either structure may be used in the present invention. Note that luminescence in the organic compound layer includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Can be applied to a light-emitting device using either light emission.
[0066]
The gate electrode of the selection transistor 126 is connected to the gate signal line (EGj). One of the source region and the drain region of the selection transistor 126 is connected to the source signal line (Si), and the other is connected to the gate electrode of the driving transistor 126. The selection transistor 126 is a transistor that functions as a switching element when writing a signal to the light-emitting element portion.
[0067]
One of a source region and a drain region of the driving transistor 129 is connected to the power supply reference line (Vi), and the other is connected to the light emitting element 125. The capacitor 128 is provided connected to the gate electrode of the driving transistor 129 and the power supply reference line (Vi). The driving transistor 129 is a transistor that functions as an element (current control element) for controlling a current supplied to the light emitting element 125.
[0068]
One of the source region and the drain region of the light emitting reset transistor 127 is connected to the power supply reference line (Vi), and the other is connected to the gate electrode of the driving transistor 129. The gate electrode of the reset transistor 127 is connected to the reset signal line (ERj). The reset transistor 127 is a transistor that functions as an element for erasing (resetting) a signal written in the light emitting element portion of the pixel 100.
[0069]
Next, a connection structure of the photoelectric conversion element 141 and a plurality of transistors and capacitors that control the photoelectric conversion element 141 will be described.
[0070]
The photoelectric conversion element 141 includes an n-channel terminal and a p-channel terminal, and a photoelectric conversion layer provided between the n-channel terminal and the p-channel terminal. One of the p-channel side terminal and the n-channel side terminal is connected to the power supply line 151 (Vdd), and the other is connected to the gate electrode of the amplifying transistor 143.
[0071]
The gate electrode of the switching transistor 142 is connected to the gate signal line (Gj). One of the source region and the drain region of the switching transistor 142 is connected to the source region of the amplifying transistor 143, and the other is connected to the signal output line (SSi). The switching transistor 142 is a transistor that functions as a switching element when outputting a signal from the photoelectric conversion element 141.
[0072]
The drain region of the amplifying transistor 143 is connected to the power supply reference line (VBi). The source region of the amplifying transistor 143 is connected to the source region or the drain region of the switching transistor 142. The amplifying transistor 143 forms a source follower circuit with a biasing transistor (not shown) provided in the sensor source signal line driving circuit 134. Therefore, the polarity of the amplifying transistor 143 and the biasing transistor is preferably the same.
[0073]
The gate electrode of the reset transistor 144 is connected to the sensor reset signal line (Rj) via the boot transistor 145. One of the source region and the drain region of the reset transistor 144 is connected to the power supply reference line (VBi), and the other is connected to the gate electrodes of the photoelectric conversion element 141 and the amplification transistor 143. The reset transistor 144 is a transistor that functions as an element (switching element) for initializing (resetting) the photoelectric conversion element 141.
[0074]
The gate electrode of the boot transistor 145 is connected to the power supply reference line (VBi). One of the source region and the drain region of the boot transistor 145 is connected to the reset signal line (Rj), and the other is connected to the gate electrode of the reset transistor 144.
[0075]
The gate electrode of the discharge transistor 147 is connected to the discharge signal line (Hj). One of the source region and the drain region of the discharging transistor 147 is connected to one terminal of the photoelectric conversion element 141 and the gate electrode of the amplifying transistor, and the other is connected to the power supply line 151 (Vdd).
[0076]
The boot transistor 145, the capacitor 146, and the discharge transistor 147 correspond to a bootstrap circuit.
[0077]
The semiconductor device in this embodiment shown in FIGS. 7 and 8 includes a reading function for reading an object using both the light emitting element portion and the sensor portion, and a display function for displaying an image using only the light emitting element portion. Has one function. Briefly describing the two functions, the former reading function is such that the light emitted from the light emitting element 125 is irradiated onto the subject, and the light reflected from the subject is photoelectrically converted by the photoelectric conversion element 141 provided in the sensor unit. To do. In this way, the subject information is read, and the information is stored as an image signal in a storage medium such as a memory provided in the semiconductor device. The latter display function displays an image using the image signal of the subject read by the photoelectric conversion element 141.
[0078]
The configuration of elements included in the sensor portion of the pixel 100 illustrated in FIG. 8 and the connection relationship thereof are the same as those of the pixel 100 illustrated in FIG. 1 described in the above embodiment. However, in the pixel 100 illustrated in FIG. 1, all transistors are n-channel transistors, and in the pixel 100 illustrated in FIG. 8, all transistors are p-channel transistors. Therefore, the potentials of the power supply line and the power supply line are different between the two pixels. Further, since the operation of the pixel 100 shown in FIG. 8 conforms to the above-described embodiment mode, detailed description of the operation is omitted in this embodiment.
[0079]
The present invention having the above-described structure can provide a semiconductor device in which the number of steps is reduced by forming a pixel with transistors having the same polarity (same conductivity type), thereby increasing yield and reducing cost. In addition, the present invention can provide a semiconductor device in which the photoelectric conversion element can obtain a sufficient signal amplitude.
[0080]
(Example 2)
In this embodiment, a method for manufacturing a pixel portion in which a photoelectric conversion element and a transistor are provided over the same insulating surface and a driver circuit around the pixel portion with a single polarity transistor will be described with reference to FIGS. To do.
[0081]
First, as shown in FIG. 5A, a silicon oxide film and a silicon nitride film are formed on a substrate 5001 made of barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass. A base film 5002 made of an insulating film such as a film or a silicon oxynitride film is formed. Although not shown in particular, the base film 5002 is made of, for example, SiH by plasma CVD. _Four , NH _Three , N ₂ A silicon oxynitride film made of O is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm) and similarly SiH _Four , N ₂ A silicon oxynitride silicon film formed from O is laminated to a thickness of 50 to 200 nm (preferably 100 to 150 nm).
[0082]
Subsequently, the island-shaped semiconductor layers 5003 to 5005 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. The island-shaped semiconductor layers 5003 to 5005 are formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no particular limitation on the material of the crystalline semiconductor layer, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.
[0083]
In order to fabricate a crystalline semiconductor film by laser crystallization, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO _Four Use a laser. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The crystallization conditions are such that when an excimer laser is used, the pulse oscillation frequency is 30 Hz and the laser energy density is 100 to 400 mJ / cm. ² (Typically 200-300mJ / cm ² ). When a YAG laser is used, the second harmonic is used, the pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is 300 to 600 mJ / cm. ² (Typically 350-500mJ / cm ² ) Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the overlapping rate (overlap rate) of the linear laser at this time is 80 to 98%.
[0084]
Subsequently, a gate insulating film 5006 is formed to cover the island-shaped semiconductor layers 5003 to 5005. The gate insulating film 5006 is formed using an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 120 nm is formed. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when silicon oxide is used, TEOS (Tetraethyl Orthosilicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0085]
Then, a first conductive film 5007 and a second conductive film 5008 for forming a gate electrode are stacked over the gate insulating film 5006. In this embodiment, the first conductive layer 5007 is formed of tantalum (Ta) to a thickness of 50 to 100 nm, and the second conductive layer 5009 is formed of tungsten (W) to a thickness of 100 to 300 nm (FIG. 5 (A)).
[0086]
The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for the gate electrode. In order to form an α-phase Ta film, tantalum nitride (TaN) having a crystal structure close to the α phase of Ta is formed on a Ta base with a thickness of about 10 to 50 nm. It can be easily obtained.
[0087]
When forming a W film, it is formed by sputtering using W as a target. In addition, tungsten hexafluoride (WF ₆ It is also possible to form it by a thermal CVD method using). In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Accordingly, when the W film is formed by sputtering, a W target having a purity of 99.9999% is used, and the W film is formed with sufficient consideration so that impurities are not mixed in from the gas phase during film formation. 9-20 μΩcm can be realized.
[0088]
Note that in this embodiment, the first conductive film 5007 is Ta and the second conductive film 5008 is W, but there is no particular limitation, and any element selected from Ta, W, Mo, Al, and Cu Alternatively, an alloy material or a compound material containing the above element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As an example of another combination other than the present embodiment, a combination in which the first conductive film is TaN, the second conductive film is W, the first conductive film is TaN, and the second conductive film is Al. It is desirable to use a combination of TaN for the first conductive film and Cu for the second conductive film.
[0089]
Next, a resist mask 5009 is formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, ICP (Inductively coupled plasma) etching is used, and CF is used as an etching gas. _Four And Cl ₂ And 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma. An RF power of 100 [W] is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ When W is mixed, the W film and the Ta film are etched to the same extent.
[0090]
Under the above etching conditions, the end portions of the first conductive film and the second conductive film are tapered due to a suitable mask shape by the resist and the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the overetching process. Thus, the first shape conductive layers 5010 to 5013 including the first conductive layers 5010a to 5013a and the second conductive layers 5010b to 5013b are formed by the first etching treatment. At this time, regions that are not covered with the first shape conductive layers 5010 to 5013 in the gate insulating film 5006 are etched and thinned by about 20 to 50 nm (FIG. 5B).
[0091]
Then, a first doping process is performed, and an impurity element imparting N-type conductivity is added (FIG. 5B). The doping process may be performed by an ion doping method or an ion implantation method. The condition for the ion doping method is that the dose is 1 × 10. ¹³ ~ 5x10 ¹⁴ atoms / cm ² The acceleration voltage is 60-100 keV. As the impurity element imparting N-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but P is used. In this case, the conductive layers 5010 to 5013 serve as a mask for the impurity element imparting N-type, and the first impurity regions 5014 to 5016 are formed in a self-aligning manner. The first impurity regions 5014 to 5016 include 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three An impurity element imparting N-type is added in a concentration range of.
[0092]
Next, a second etching process is performed (FIG. 5C). In the second etching process, an ICP etching method is used, and an etching gas is CF. _Four And Cl ₂ And O ₂ And RF power of 500 [W] is supplied to the coil-type electrode at a pressure of 1 Pa to generate plasma. Further, RF power of 50 [W] is also applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the second conductive layer W is anisotropically etched, and the first conductive layer Ta is anisotropically etched to form the second shape conductive layers 5017 to 5020 (first Conductive layers 5017a to 5020a and second conductive layers 5017b to 5020b) are formed. At this time, regions that are not covered with the second shape conductive layers 5017 to 5020 in the gate insulating film 5006 are further etched and thinned by about 20 to 50 nm.
[0093]
CF of W film and Ta film _Four And Cl ₂ The etching reaction by the mixed gas can be estimated from the generated radical or ion species and the vapor pressure of the reaction product. Comparing the vapor pressure of fluoride and chloride of W and Ta, WF, which is fluoride of W ₆ Vapor pressure is extremely high and other WCl _Five , TaF _Five , TaCl _Five About the same. Therefore, CF _Four And Cl ₂ With this mixed gas, both the W film and the Ta film are etched. However, an appropriate amount of O is added to this mixed gas. ₂ When CF is added _Four And O ₂ Reacts to CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, even if Ta increases, the etching rate increases relatively little. Further, since Ta is more easily oxidized than W, O ₂ When Ta is added, the surface of Ta is oxidized. Since Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film decreases. Therefore, it becomes possible to make a difference in the etching rate between the W film and the Ta film.
[0094]
Then, a second doping process is performed (FIG. 5D). In this case, doping is performed with an impurity element that imparts N-type as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is 70 to 120 keV and 1 × 10 ¹³ atoms / cm ² A new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. 5B. Doping is performed by using the second conductive layers 5017b to 5020b as masks against the impurity elements and adding the impurity elements to the lower regions of the first conductive layers 5017a to 5020a. Thus, second impurity regions 5021 to 5023 overlapping with the first conductive layer are formed.
[0095]
Subsequently, a third etching process is performed (FIG. 6A). In the third etching process, Cl is used as an etching gas. ₂ And using an ICP etching apparatus. In this example, Cl ₂ The gas flow rate ratio was set to 60 sccm, RF power of 350 [W] was applied to the coil-type electrode at a pressure of 1 Pa, plasma was generated, and etching was performed for 70 seconds. RF power was also applied to the substrate side (sample stage), and a substantially negative self-bias voltage was applied. By this treatment, the first conductive layer recedes to form third shape conductive layers 5024 to 5027 (first conductive layers 5024a to 5027a and second conductive layers 5024b to 5027b), and second impurities The regions 5021 to 5023 serve as second impurity regions 5028a to 5030a that overlap with the first conductive layer and third impurity regions 5028b to 5030b that do not overlap with the first conductive layer.
[0096]
Through the above steps, impurity regions are formed in each island-shaped semiconductor layer. The third shape conductive layers 5024 to 5026 overlapping with the island-shaped semiconductor layers function as gate electrodes of the transistors. The third shape conductive layer 5027 functions as a source signal line.
[0097]
Subsequently, for the purpose of controlling the conductivity type, a step of activating the impurity element added to each island-shaped semiconductor layer is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method and a rapid thermal annealing method (RTA method) can be applied. The thermal annealing method is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the temperature is 4 at 500 [° C.]. Heat treatment for hours. However, when the wiring material used for 5024 to 5027 is vulnerable to heat, it is desirable to perform thermal activation after forming an interlayer insulating film (mainly composed of silicon) in order to protect the wiring and the like.
[0098]
Further, a heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another method of thermal hydrogenation, plasma hydrogenation using hydrogen excited by plasma may be used.
[0099]
Next, as shown in FIG. 6B, a first interlayer insulating film 5031 is formed of a silicon oxynitride film with a thickness of 100 to 200 nm. After a second interlayer insulating film 5032 made of an organic insulating material is formed thereon, contact holes are opened in the first interlayer insulating film 5031, the second interlayer insulating film 5032, and the gate insulating film 5006. A film made of a wiring material is formed, and the wirings 5033 to 5037 and the connection electrode 5038 are formed by patterning.
[0100]
As the second interlayer insulating film 5032, a film made of an organic resin such as polyimide, polyamide, acrylic, or BCB (benzocyclobutene) is used. In particular, since the second interlayer insulating film 5032 has a strong meaning of flattening, acrylic having excellent flatness is desirable. In this embodiment, the acrylic film is formed with a thickness that can sufficiently flatten the step formed by the transistor. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).
[0101]
The contact holes are formed by dry etching or wet etching using N-type impurity regions 5014 to 5016, source signal lines 5027, gate signal lines (not shown), current supply lines (not shown), and gate electrodes 5024 to 5024. 5026 is formed.
[0102]
The wirings 5033 to 5038 are formed by patterning a three-layer stacked film continuously formed by sputtering using a Ti film of 100 nm, an Al film containing Ti of 300 nm, a Ti film of 150 nm, and a sputtering method. Of course, the present invention is not limited to this, and other conductive materials may be used.
[0103]
Next, as shown in FIG. 6C, an insulating film is formed to a thickness of about 1 to 3 μm using an organic material such as acrylic, and a third interlayer insulating film 5040 is formed.
[0104]
Then, as the wirings 5041 and 5042, a three-layer laminated film in which a Ti film is formed by 100 nm, an Al film containing Ti by 300 nm, and a Ti film by 150 nm is formed by sputtering is patterned into a desired shape. Of course, the present invention is not limited to this, and other conductive materials may be used. Note that the wirings 5041 and 5042 are connected to a source region or a drain region of a transistor provided in the pixel 100.
[0105]
Subsequently, a metal film is formed with a thickness of 100 to 500 nm so as to be in contact with the wiring 5041. The metal film is formed using a known conductive material such as an ITO film. Next, a first microcrystalline semiconductor film is formed at a thickness of 25 to 80 nm by a known method so as to be in contact with the metal film.
[0106]
Next, an impurity element imparting p-type conductivity is added to the first microcrystalline semiconductor film using a known method. Then, the metal film and the first microcrystalline semiconductor film are simultaneously patterned into a desired shape so as to overlap with the wiring 5041, thereby forming the metal layer 5043 and the microcrystalline semiconductor layer (p-type semiconductor layer) 5044 at the same time. To do.
[0107]
Note that as a method for adding an impurity element imparting p-type conductivity, a doping gas containing an impurity element imparting p-type conductivity may be mixed when forming the first microcrystalline semiconductor film. Alternatively, after the metal film and the first microcrystalline semiconductor film are first patterned, an impurity element imparting p-type conductivity may be added only to the microcrystalline semiconductor layer 5044.
[0108]
Next, an amorphous semiconductor film is formed to a thickness of 10 to 200 nm so as to overlap with the microcrystalline semiconductor layer (p-type semiconductor layer) 5044. Next, a second microcrystalline semiconductor film is formed to a thickness of 25 to 80 nm on the amorphous semiconductor film. Any known material may be used for the amorphous semiconductor film and the second microcrystalline semiconductor film, and a manufacturing method thereof is not particularly limited.
[0109]
Next, an impurity element imparting n-type conductivity is added to the second microcrystalline semiconductor film using a known method. Then, the amorphous semiconductor film and the second microcrystalline semiconductor film are simultaneously patterned so as to have a desired shape so as to overlap with the p-type semiconductor layer 5044, so that an amorphous semiconductor layer (photoelectric conversion layer) is obtained. 5045 and a microcrystalline semiconductor layer (n-type semiconductor layer) 5046 are formed at the same time.
[0110]
Note that the impurity element imparting n-type is added by mixing a doping gas containing an impurity element imparting n-type when the microcrystalline semiconductor film is formed, A method in which an impurity element imparting n-type conductivity is added only to the microcrystalline semiconductor layer 5046 after patterning of the crystalline semiconductor film may be used.
[0111]
A stacked body of the p-type semiconductor layer 5044, the photoelectric conversion layer 5045, and the n-type semiconductor layer 5046 corresponds to the photoelectric conversion element 111. Subsequently, a metal film is formed with a thickness of 20 to 100 nm using a conductive material so as to cover the n-type semiconductor layer 5046 and the wiring 5042. Then, the metal film is patterned so as to have a desired shape, and a metal layer 5047 is formed so that the microcrystalline semiconductor layer 5046 of the photoelectric conversion element 111 and the wiring 5042 are electrically connected.
[0112]
Next, a fourth interlayer insulating film 5048 made of an organic resin film is formed. The fourth interlayer insulating film 5048 has a function of planarizing the surface in addition to insulating the wiring material. Although any known material can be used as the material, in this embodiment, an acrylic resin is used as the material, and an organic resin film having a thickness of 50 to 300 nm μm is formed.
[0113]
Further, according to the steps shown in this embodiment, the number of photomasks necessary for the production of the active matrix substrate is four (an island semiconductor layer pattern, a first wiring pattern (a gate wiring, an island source wiring, a capacitor wiring). ), A contact hole pattern, and a second wiring pattern (including connection electrodes). As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.
[0114]
This embodiment can be freely combined with the embodiment mode and Embodiment 1.
[0115]
(Example 3)
In this embodiment, a method for manufacturing a pixel portion provided with a photoelectric conversion element, a light emitting element, and a transistor over the same insulating surface, and a driver circuit around the pixel portion with a unipolar transistor is illustrated in FIGS. Will be described. In this embodiment, a p-channel transistor is used.
[0116]
In the above-described second embodiment, a manufacturing method in which the pixel portion and the peripheral driving circuit are formed using only n-channel transistors is shown. Note that in an n-channel transistor, an impurity region called an overlap region is provided in a region overlapping with a gate electrode in order to suppress hot carrier deterioration and the like. On the other hand, a p-channel transistor is less affected by hot carrier deterioration, so that it is not particularly necessary to provide an overlap region and can be manufactured by a simpler process.
[0117]
First, as illustrated in FIG. 9A, a base film 6002 is formed over an insulating substrate 6001 such as glass, and then island-shaped semiconductor layers 6003 to 6005, a gate insulating film 6006, and conductive layers 6007 and 6008 are formed. . Here, the conductive layers 6007 and 6008 have a laminated structure, but may be a single layer. Since this process is in accordance with the above-described second embodiment, detailed description thereof is omitted.
[0118]
Next, as shown in FIG. 9B, a resist mask 6009 is formed, and a first etching process is performed. In Example 2, anisotropic etching was performed using the selection ratio depending on the material of the conductive layer having a laminated structure. However, in this case, it is not necessary to provide a region to be an overlap region. Just do it. At this time, in the gate insulating film 6006, a region which is thinned by about 20 nm to 50 nm is formed by etching.
[0119]
Subsequently, a first doping process for adding an impurity element imparting P-type to the island-shaped semiconductor layer is performed. Using the conductive layers 6010 to 6012 as masks against the impurity elements, impurity regions are formed in a self-aligning manner. As an impurity element imparting P-type, boron (B) or the like is typical. Here, diborane (B ₂ H ₆ ), And the impurity concentration in the semiconductor layer is 2 × 10 ²⁰ ~ 2x10 ^{twenty one} atoms / cm ^Three To be.
[0120]
When the resist mask is removed, the first interlayer insulating film 6022 is formed using a film made of an organic resin such as polyimide, polyamide, acrylic, or BCB (benzocyclobutene). Since the first interlayer insulating film 6022 has a strong meaning of planarization, acrylic having excellent planarity is desirable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the steps formed by the transistors. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).
[0121]
Next, contact holes are formed so as to reach the p-type impurity regions 6014 to 6016 by using a dry etching method or a wet etching method.
[0122]
Further, as the wirings 6018 to 6021, 6023, and 6024, a three-layer laminated film continuously formed by a sputtering method with a Ti film of 100 nm, a Ti-containing Al film of 300 nm, and a Ti film of 150 nm is formed and patterned into a desired shape . Subsequently, a second interlayer insulating film 6025 is formed with a silicon oxynitride film with a thickness of 100 to 200 nm so as to cover the wirings 6018 to 6021, 6023, and 6024 and the first interlayer insulating film 6022.
[0123]
Then, the wirings 6041 and 6042 are formed by patterning a three-layer film continuously formed by sputtering using a Ti film of 100 nm, an Al film containing Ti of 300 nm, a Ti film of 150 nm, and a sputtering method. Of course, the present invention is not limited to this, and other conductive materials may be used.
[0124]
Subsequently, a metal film is formed with a thickness of 100 to 500 nm so as to be in contact with the wiring 6041. The metal film is formed using a known conductive material such as an ITO film. Next, a first microcrystalline semiconductor film is formed to have a thickness of 25 to 80 nm by a known method so as to be in contact with the metal film.
[0125]
Next, an impurity element imparting p-type conductivity is added to the first microcrystalline semiconductor film using a known method. Then, the metal film and the first microcrystalline semiconductor film are simultaneously patterned so as to have a desired shape so as to overlap with the wiring 6041, so that a metal layer 6043 and a microcrystalline semiconductor layer (p-type semiconductor layer) 6044 are formed. Are formed at the same time.
[0126]
Note that the impurity element imparting p-type is added by a method in which a doping gas containing an impurity element imparting p-type is mixed when the first microcrystalline semiconductor film is formed, It is preferable to use a method in which an impurity element imparting p-type conductivity is added only to the microcrystalline semiconductor layer 6044 after patterning of one microcrystalline semiconductor film is performed first.
[0127]
Next, an amorphous semiconductor film is formed to a thickness of 10 to 200 nm so as to overlap with the microcrystalline semiconductor layer (p-type semiconductor layer) 6044. Next, a second microcrystalline semiconductor film is formed to a thickness of 25 to 80 nm on the amorphous semiconductor film. A manufacturing method of the amorphous semiconductor film and the second microcrystalline semiconductor film is not particularly limited, and any known material may be used.
[0128]
Next, an impurity element imparting n-type conductivity is added to the second microcrystalline semiconductor film using a known method. Then, the amorphous semiconductor film and the second microcrystalline semiconductor film are simultaneously patterned so as to have a desired shape so as to overlap with the p-type semiconductor layer 6043, so that an amorphous semiconductor layer (photoelectric conversion layer) is formed. 6045 and a microcrystalline semiconductor layer (n-type semiconductor layer) 6046 are formed at the same time.
[0129]
Note that the addition of the impurity element imparting n-type is performed by mixing a doping gas containing an impurity element imparting n-type when the microcrystalline semiconductor film is formed, or the amorphous semiconductor film A method in which an impurity element imparting n-type conductivity is added only to the microcrystalline semiconductor layer 5046 after patterning of the microcrystalline semiconductor film is preferably used.
[0130]
A stacked body of the p-type semiconductor layer 6044, the photoelectric conversion layer 6045, and the n-type semiconductor layer 6046 corresponds to the photoelectric conversion element 111. Subsequently, a metal film is formed with a thickness of 20 to 100 nm using a conductive material so as to cover the second interlayer insulating film 6025, the n-type semiconductor layer 6046, and the wiring 6042. Then, the metal film is patterned so as to have a desired shape, and a metal layer 6047 is formed so that the microcrystalline semiconductor layer 6046 and the wiring 6042 of the photoelectric conversion element 111 are electrically connected.
[0131]
Next, a third interlayer insulating film 6048 made of an organic resin film is formed. The third interlayer insulating film 6048 has a function of planarizing the surface in addition to insulating the wiring material. Although any known material can be used as the material, in this embodiment, an acrylic resin is used as the material, and an organic resin film having a thickness of 50 to 300 nm μm is formed.
[0132]
Subsequently, an opening is formed in the second interlayer insulating film 6025 and the third interlayer insulating film 6048 so that the source wiring or the drain wiring of the driving transistor is exposed. When the opening is formed, a tapered sidewall can be easily obtained by using a wet etching method. If the side wall of the opening is not sufficiently gentle, it should be noted that deterioration or disconnection of the organic compound layer due to the step becomes a significant problem. When the opening is formed, a pixel electrode (transparent electrode) 6049 is formed, and then an organic compound layer 6050 is formed using a vacuum evaporation method. Then, a cathode 6051 made of MgAg is formed so as to cover the organic compound layer 6050. The film thickness of the pixel electrode 6049 and the cathode 6051 is 80 to 120 nm, and the organic compound layer 6050 is 80 to 200 nm (typically 100 to 120 nm).
[0133]
In this step, the organic compound layer 6050 and the cathode 6051 are sequentially formed for the pixel corresponding to red, the pixel corresponding to green, and the pixel corresponding to blue. However, since the organic compound layer 6050 has poor resistance to a solution, it must be formed individually for each color without using a photolithography technique. Therefore, it is desirable to conceal other than desired pixels with a metal mask or the like and selectively form only necessary portions.
[0134]
Here, a method of forming three types of light emitting elements corresponding to RGB is used, but a method of combining a white light emitting element and a color filter, a blue or blue green light emitting element, and a phosphor (fluorescent color). A method in combination with a conversion layer (CCM) may be used. Note that a known material can be used for the organic compound layer 6050, and it is preferable to use an organic material as the known material in consideration of a driving voltage.
[0135]
Next, a protective film 6052 made of a silicon nitride film is formed to a thickness of 50 to 300 nm. The protective film 6052 serves to protect the organic compound layer 6050 from moisture and the like.
[0136]
Actually, when the state shown in FIG. 10B is completed, a protective film (laminate film, UV curable film, etc.) or a translucent sealing with high air tightness and low outgassing so as not to be exposed to the outside air. It is preferable to enclose with a material. At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the light emitting element is improved.
[0137]
Moreover, if the airtightness is increased by processing such as packaging, a connector (FPC) for connecting a terminal routed from an element or circuit formed on the substrate and an external signal terminal is attached. Complete.
[0138]
According to the structure of this embodiment, light emitted from the light emitting element is emitted to the substrate 6001 side where the transistor is formed. The light emitted from the light emitting element is applied to the subject, and the light reflected from the subject is applied to the photoelectric conversion element.
[0139]
Note that light emitted from the light-emitting element may be emitted in the direction of the substrate 6001 or in the direction opposite to the substrate 6001. The former is called bottom emission, and the latter is called top emission. In the case of bottom emission, the pixel electrode 6049 corresponds to the anode and the counter electrode 6051 corresponds to the cathode. In the case of top emission, the pixel electrode 6049 corresponds to the cathode and the counter electrode 6051 corresponds to the anode. In this embodiment, only the case of bottom emission in which light is emitted in the direction of the substrate 6001 is illustrated, but the present invention is not limited to this. Upper surface emission in which light is emitted in a direction opposite to the substrate 6001 may be performed. In the case of top emission, almost all light emitted from the light emitting element can be extracted outside without depending on the aperture ratio of the pixel. Therefore, this is effective when a large number of circuit elements are arranged in the pixel.
[0140]
The present invention having the above-described structure can provide a semiconductor device in which the number of steps is reduced by forming a pixel with transistors having the same polarity (same conductivity type), thereby increasing yield and reducing cost. In addition, the present invention can provide a semiconductor device in which the photoelectric conversion element can obtain a sufficient signal amplitude.
[0141]
This embodiment can be freely combined with the embodiment mode and Embodiments 1 and 2.
[0142]
Example 4
An embodiment of an electronic device using the semiconductor device of the present invention will be described with reference to FIG.
[0143]
FIG. 13A illustrates a hand scanner using a line sensor. An optical system 1002 such as a rod lens array is provided above the CCD type (CMOS type) image sensor 1001. The optical system 1002 is used so that an image on the subject 1004 is displayed on the image sensor 1001. A light source 1003 such as an LED or a fluorescent lamp is provided at a position where light can be emitted to the subject 1004. A glass 1005 is provided below the subject 1004.
[0144]
Light emitted from the light source 1003 enters the subject 1004 through the glass 1005. Light reflected by the subject 1004 enters the optical system 1002 through the glass 1005. The light that has entered the optical system 1002 enters the image sensor 1001, where it is photoelectrically converted. The semiconductor device of the present invention can be used for the image sensor 1001.
[0145]
In FIG. 13B, reference numeral 1801 denotes a substrate, 1802 denotes a pixel portion, 1803 denotes a touch panel, and 1804 denotes a touch pen. The touch panel 1803 has a light-transmitting property, can transmit light emitted from the pixel portion 1802 and light incident on the pixel portion 1802, and can read an image on a subject through the touch panel 1803. Even when an image is displayed on the pixel portion 1802, the image on the pixel portion 1802 can be viewed through the touch panel 1803.
[0146]
When the touch pen 1804 touches the touch panel 1803, information on a position of a portion where the touch pen 1804 and the touch panel 1803 are in contact with each other can be taken into the semiconductor device as an electric signal. In the touch panel 1803 and the touch pen 1804 used in this embodiment, information on the position of the part where the touch pen 1803 is translucent and the touch pen 1804 and the touch panel 1803 are in contact is taken into the semiconductor device as an electrical signal. Any known one can be used. The semiconductor device of the present invention can be used for the pixel portion 1802.
[0147]
FIG. 13C illustrates a portable hand scanner different from that in FIG. 13B, which includes a main body 1901, a pixel portion 1902, an upper cover 1903, an external connection port 1904, and an operation switch 1905. FIG. 13D is a view in which the upper cover 1903 of the same portable hand scanner as FIG. 13C is closed.
[0148]
13C and 13D, the image signal read by the pixel portion 1902 is sent from the external connection port 1904 to an electronic device connected to the outside of the portable hand scanner, and the image is corrected by the personal computer. It is also possible to perform composition, editing, and the like. The semiconductor device of the present invention can be used for the pixel portion 1902.
[0149]
Further, examples of the electronic device using the semiconductor device of the present invention include a video camera, a digital still camera, a notebook personal computer, a portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like).
[0150]
FIG. 13E shows a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2104, an external connection port 2105, a shutter 2106, and the like. The semiconductor device of the present invention can be used for the display portion 2102.
[0151]
FIG. 13F illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The semiconductor device of the present invention can be used for the display portion 2302.
[0152]
FIG. 13G illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The semiconductor device of the present invention can be used for the display portion 2703.
[0153]
As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.
[0154]
【The invention's effect】
The present invention can provide a semiconductor device in which the number of steps is reduced by forming a pixel with transistors having the same polarity (same conductivity type), thereby increasing yield and reducing cost.
[0155]
In addition, by applying the bootstrap method, the present invention can provide a semiconductor device in which a photoelectric conversion element can obtain a sufficient signal amplitude. Thereby, the improvement of the reading accuracy of the subject by the photoelectric conversion element can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a pixel of a semiconductor device.
FIG. 2 is a circuit diagram of a pixel of a semiconductor device.
FIG. 3 is a graph showing the relationship between the potential of a photoelectric conversion element and time.
FIG. 4 is a schematic diagram of a semiconductor device.
FIGS. 5A to 5D are diagrams illustrating a manufacturing process of a semiconductor device. FIGS.
6A and 6B illustrate a manufacturing process of a semiconductor device.
FIG. 7 is a schematic diagram of a semiconductor device.
FIG. 8 is a circuit diagram of a pixel of a semiconductor device.
FIG. 9 illustrates a manufacturing process of a semiconductor device.
10A to 10E illustrate a manufacturing process of a semiconductor device.
FIG. 11 is a circuit diagram of a pixel of a semiconductor device.
FIG. 12 is a circuit diagram of a pixel of a semiconductor device.
FIG. 13 illustrates an example of an electronic device to which the present invention is applied.
FIG. 14 is a diagram of a semiconductor device.

Claims (10)

A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a photoelectric conversion element;
A gate of the first transistor is connected to one of a source and a drain of the third transistor;
One of the source and drain of the first transistor, the gate of the third transistor, and one of the source and drain of the fourth transistor are connected to a first wiring,
The other of the source and the drain of the first transistor is connected to one of the source and the drain of the second transistor, at least one terminal of the photoelectric conversion element, and the gate of the fourth transistor.
A gate of the second transistor is connected to a second wiring;
The other of the source and the drain of the second transistor is connected to a third wiring,
The other of the source and the drain of the third transistor is connected to a fourth wiring;
The other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the fifth transistor;
A gate of the fifth transistor is connected to a fifth wiring;
The other of the source and the drain of the fifth transistor is connected to a sixth wiring;
The semiconductor device is characterized in that the capacitor is provided between the gate of the first transistor and the other of the source and drain of the first transistor. A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a photoelectric conversion element;
A gate of the first transistor is connected to one of a source and a drain of the third transistor and a first terminal of the capacitor;
One of the source and drain of the first transistor, the gate of the third transistor, and one of the source and drain of the fourth transistor are connected to a first wiring,
The other of the source and drain of the first transistor is one of the source and drain of the second transistor, at least one terminal of the photoelectric conversion element, the gate of the fourth transistor, and the capacitance element. Connected to the second terminal,
A gate of the second transistor is connected to a second wiring;
The other of the source and the drain of the second transistor is connected to a third wiring,
The other of the source and the drain of the third transistor is connected to a fourth wiring;
The other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the fifth transistor;
A gate of the fifth transistor is connected to a fifth wiring;
The other of the source and the drain of the fifth transistor is connected to a sixth wiring. A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a photoelectric conversion element;
A gate of the first transistor is connected to one of a source and a drain of the third transistor;
One of the source and drain of the first transistor, the gate of the third transistor, and one of the source and drain of the fourth transistor are connected to a first wiring,
The other of the source and the drain of the first transistor is connected to one of the source and the drain of the second transistor, at least one terminal of the photoelectric conversion element, and the gate of the fourth transistor.
A gate of the second transistor is connected to a second wiring;
The other of the source and the drain of the second transistor is connected to a third wiring,
The other of the source and the drain of the third transistor is connected to a fourth wiring;
The other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the fifth transistor;
A gate of the fifth transistor is connected to a fifth wiring;
The other of the source and the drain of the fifth transistor is connected to a sixth wiring;
The capacitive element is provided between the gate of the first transistor and the other of the source and drain of the first transistor;
Each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor has the same conductivity type. A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a photoelectric conversion element;
A gate of the first transistor is connected to one of a source and a drain of the third transistor and a first terminal of the capacitor;
One of the source and drain of the first transistor, the gate of the third transistor, and one of the source and drain of the fourth transistor are connected to a first wiring,
The other of the source and drain of the first transistor is one of the source and drain of the second transistor, at least one terminal of the photoelectric conversion element, the gate of the fourth transistor, and the capacitance element. Connected to the second terminal,
A gate of the second transistor is connected to a second wiring;
The other of the source and the drain of the second transistor is connected to a third wiring,
The other of the source and the drain of the third transistor is connected to a fourth wiring;
The other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the fifth transistor;
A gate of the fifth transistor is connected to a fifth wiring;
The other of the source and the drain of the fifth transistor is connected to a sixth wiring;
Each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor has the same conductivity type. A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, a photoelectric conversion element, and a light-emitting element;
A gate of the first transistor is connected to one of a source and a drain of the third transistor;
One of the source and drain of the first transistor, the gate of the third transistor, and one of the source and drain of the fourth transistor are connected to a first wiring,
The other of the source and the drain of the first transistor is connected to one of the source and the drain of the second transistor, at least one terminal of the photoelectric conversion element, and the gate of the fourth transistor.
A gate of the second transistor is connected to a second wiring;
The other of the source and the drain of the second transistor is connected to a third wiring,
The other of the source and the drain of the third transistor is connected to a fourth wiring;
The other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the fifth transistor;
A gate of the fifth transistor is connected to a fifth wiring;
The other of the source and the drain of the fifth transistor is connected to a sixth wiring;
The capacitive element is provided between the gate of the first transistor and the other of the source and drain of the first transistor;
The light emitted from the light emitting element irradiates the subject, and the light reflected from the subject A semiconductor device, wherein the photoelectric conversion element is irradiated. A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, a photoelectric conversion element, and a light-emitting element;
A gate of the first transistor is connected to one of a source and a drain of the third transistor and a first terminal of the capacitor;
One of the source and drain of the first transistor, the gate of the third transistor, and one of the source and drain of the fourth transistor are connected to a first wiring,
The other of the source and drain of the first transistor is one of the source and drain of the second transistor, at least one terminal of the photoelectric conversion element, the gate of the fourth transistor, and the capacitance element. Connected to the second terminal,
A gate of the second transistor is connected to a second wiring;
The other of the source and the drain of the second transistor is connected to a third wiring,
The other of the source and the drain of the third transistor is connected to a fourth wiring;
The other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the fifth transistor;
A gate of the fifth transistor is connected to a fifth wiring;
The other of the source and the drain of the fifth transistor is connected to a sixth wiring;
The semiconductor device is characterized in that light emitted from the light emitting element is irradiated on a subject, and light reflected on the subject is irradiated on the photoelectric conversion element. A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, a photoelectric conversion element, and a light-emitting element;
A gate of the first transistor is connected to one of a source and a drain of the third transistor;
One of the source and drain of the first transistor, the gate of the third transistor, and one of the source and drain of the fourth transistor are connected to a first wiring,
The other of the source and the drain of the first transistor is connected to one of the source and the drain of the second transistor, at least one terminal of the photoelectric conversion element, and the gate of the fourth transistor.
A gate of the second transistor is connected to a second wiring;
The other of the source and the drain of the second transistor is connected to a third wiring,
The other of the source and the drain of the third transistor is connected to a fourth wiring;
The other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the fifth transistor;
A gate of the fifth transistor is connected to a fifth wiring;
The other of the source and the drain of the fifth transistor is connected to a sixth wiring;
The capacitive element is provided between the gate of the first transistor and the other of the source and drain of the first transistor;
The light emitted from the light emitting element is applied to the subject, the light reflected from the subject is applied to the photoelectric conversion element,
Each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor has the same conductivity type. A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, a photoelectric conversion element, and a light-emitting element;
A gate of the first transistor is connected to one of a source and a drain of the third transistor and a first terminal of the capacitor;
One of the source and drain of the first transistor and the gate of the third transistor; And one of a source and a drain of the fourth transistor is connected to the first wiring,
The other of the source and drain of the first transistor is one of the source and drain of the second transistor, at least one terminal of the photoelectric conversion element, the gate of the fourth transistor, and the capacitance element. Connected to the second terminal,
A gate of the second transistor is connected to a second wiring;
The other of the source and the drain of the second transistor is connected to a third wiring,
The other of the source and the drain of the third transistor is connected to a fourth wiring;
The other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the fifth transistor;
A gate of the fifth transistor is connected to a fifth wiring;
The other of the source and the drain of the fifth transistor is connected to a sixth wiring;
The light emitted from the light emitting element is applied to the subject, the light reflected from the subject is applied to the photoelectric conversion element,
Each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor has the same conductivity type. An electronic apparatus using the semiconductor device according to claim 1. The electronic apparatus according to claim 9, wherein the electronic apparatus is a scanner, a touch panel, a video camera, a digital still camera, a computer, or a portable information terminal.

Images