JP4145988B2 - Analog buffer and display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit configuration such as an analog buffer for driving a capacitive load, and is directed to, for example, a circuit used for a signal line driving circuit for supplying pixel data to a display element.
[0002]
[Prior art]
The liquid crystal display device includes a pixel array portion in which signal lines and scanning lines are arranged vertically and horizontally, a signal line driving circuit that drives the signal lines, and a scanning line driving circuit that drives the scanning lines.
[0003]
An analog buffer for amplifying pixel data is provided at the output stage of the signal line driver circuit, and pixel data amplified by the analog buffer is supplied to each signal line. Since the signal line is a capacitive load, when a signal voltage is supplied to each signal line, the voltage is held in the capacity of each signal line.
[0004]
Recently, in order to reduce the cost and size of the liquid crystal display device, a technique for integrally forming the pixel array portion and the drive circuit on the same transparent insulating substrate has been studied. In this case, since the transistors constituting the pixel array portion and the driving circuit are formed in the same manufacturing process, the manufacturing process can be simplified.
[0005]
[Problems to be solved by the invention]
However, a transistor formed over a substrate does not necessarily have uniform electrical characteristics, and in particular, the threshold voltage of the transistor varies greatly. Since the analog buffer in the signal line driver circuit described above is configured using transistors, when the threshold voltage of the transistor fluctuates, the operating point voltage of the analog buffer itself also fluctuates. An analog buffer is provided for each signal line in the signal line driver circuit, so if the operating point voltage of the analog buffer fluctuates, even if the same pixel data is input, it is displayed with different brightness depending on the display position on the screen. As a result, the uniformity of the image quality in the liquid crystal panel is impaired.
[0006]
The present invention has been made in view of these points, and an object of the present invention is to provide an analog buffer and a display device in which output is not affected by variations in threshold voltage of transistors. .
[0007]
[Means for Solving the Problems]
In order to solve the above-described problem, the invention according to claim 1 is an analog buffer that supplies a voltage according to an input voltage to a capacitive load, according to a difference voltage between the input voltage and a voltage supplied to the capacitive load. Connected between a first capacitor for accumulating the stored charge, a positive phase amplifier having a predetermined operating point voltage and outputting an input signal in phase, and one end of the first capacitor and an input terminal of the positive phase amplifier And the second capacitor in accordance with the operating point voltage in a state where the first capacitor is discharged so that the input voltage of the positive phase amplifier is substantially equal to the operating point voltage. A charge is accumulated, and then a charge corresponding to the differential voltage is accumulated in the first capacitor, and an input voltage of the positive phase amplifier is added to the voltage across the first capacitor and the operating point voltage is added. Approximately equal to Comprising a voltage control circuit that, the.
[0008]
The invention of claim 2 comprises a display element, a signal line for supplying pixel data to the display element, and a signal line driving circuit for driving the signal line, and the signal line driven by the signal line driving circuit is In a display device that is a capacitive load, a first capacitor that accumulates electric charge according to a voltage difference between input pixel data and a signal line voltage, and has a predetermined operating point voltage and outputs an input signal in phase. The positive phase amplifier, the second capacitor connected between one end of the first capacitor and the input terminal of the positive phase amplifier, and the input voltage of the positive phase amplifier are substantially equal to the operating point voltage. In the state where the first capacitor is discharged, the electric charge corresponding to the operating point voltage is accumulated in the second capacitor, and then the electric charge corresponding to the differential voltage is accumulated in the first capacitor, Input of the positive phase amplifier Comprising a voltage control circuit for substantially equal pressure to the first voltage plus the operating point voltage in the voltage across the capacitor, the.
[0009]
The invention of claim 1 will be described with reference to FIG. 4, for example. The “first capacitor” is the capacitor C1, the “positive phase amplifier” is the positive phase amplifier 22, and the “second capacitor” is the capacitor C2. The “voltage control circuit” corresponds to the switches SW1 to SW7 and the PMOS transistor Q1, respectively.
[0010]
The invention of claim 2 will be described with reference to FIGS. 1 to 4, for example. “Display element” corresponds to TFT 1 in FIG. 1, and “Signal line drive circuit” corresponds to signal line drive circuit 3 in FIG. To do.
[0011]
The invention of claim 3 will be described with reference to FIG. 4, for example. The “first switching means” is the switch SW1, the “second switching means” is the switch SW2, and the “third switching means” is the switch. In SW3, "fourth switching means" is in switch SW4, "fifth switching means" is in switch SW5, "sixth switching means" is in switch SW6, and "seventh switching means" is in switch SW7. , “Switching elements” correspond to the PMOS transistor Q1, respectively.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a display device according to the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a display device according to the present invention. The display device of FIG. 1 includes a pixel array section 2 having a pixel display TFT 1 disposed in the vicinity of intersections of signal lines S1 to Sn and scanning lines G1 to Gn arranged vertically and horizontally, and signal lines S1 to Sn. A signal line driving circuit 3 for driving and a scanning line driving circuit 4 for driving the scanning lines G1 to Gn are provided.
[0013]
FIG. 2 is a block diagram showing a detailed configuration in the signal line driving circuit 3. 2 includes a shift register 11 that outputs a pulse for driving each signal line, a first analog switch 12 connected to each output terminal of the shift register 11, and a first analog The first latch circuit 13 that latches the data that has passed through the switch 12, the second analog switch 14 that is connected to each output terminal of the first latch circuit 13, and the pixel data that is latched by the first latch circuit 13 Are latched together for one horizontal line, and an analog buffer 16 for amplifying the data latched by the second latch circuit 15 is provided. The output of each analog buffer 16 is supplied to the corresponding signal line.
[0014]
By providing the second latch circuit 15, it is possible to drive each signal line with a margin within one horizontal line display period.
[0015]
FIG. 3 is a block diagram showing the internal configuration of the analog buffer 16. As illustrated, the analog buffer 16 is configured using a comparator 21. The pixel data output from the second latch circuit 15 in FIG. 2 is input to one input terminal (in +) of the comparator 21, and a signal line that is a capacitive load is input to the other input terminal (in−). Is input.
[0016]
Thus, the comparator 21 compares the pixel data with the signal line voltage and outputs a voltage corresponding to the difference voltage. As a result, an analog voltage corresponding to the pixel data is supplied to each signal line.
[0017]
FIG. 4 is a circuit diagram showing the internal configuration of the comparator 21. As shown in FIG. 4, the comparator 21 includes a positive phase amplifier 22 including two inverter stages, capacitors C1 and C2, switches SW1 to SW7, and a PMOS transistor Q1. The positive phase amplifier 22 and the switches SW1 to SW7 are configured using NMOS transistors or PMOS transistors.
[0018]
One end of each of the switches SW1 and SW4 and the capacitor C2 is connected to one end of the capacitor C1. One end of each of the switches SW2 and SW3 is connected to the other end of the capacitor C1. The pixel data output from the second latch circuit 15 shown in FIG. 2 is input to the other end of the switch SW1, and the output terminal out of the comparator 21, that is, a signal line is connected to the other end of the switch SW2. . One end of each of the switches SW5 and SW7 and the input terminal of the positive phase amplifier 22 are connected to the other end of the capacitor C2, and the other ends of the switches SW3, SW4 and SW7 are grounded. The output terminal of the positive phase amplifier 22 is connected to one end of the switch SW6 and the gate terminal of the PMOS transistor Q1, the source terminal is connected to the power supply terminal VDD, and the drain terminal is connected to the other end of the switch SW5. The
[0019]
FIG. 5 is a diagram showing the switching timing of the switches SW1 to SW7 shown in FIG. 4, and “ON” is displayed when the switch is on, and “OFF” is displayed when the switch is off. FIG. 5 shows the waveforms of the input terminal (in +, in−), the output terminal out, and (1) to (4) in FIG. Hereinafter, the operation of the comparator 21 of FIG. 4 will be described with reference to FIG.
[0020]
At time t1, the switches SW3, SW4 and SW7 are turned on, and the other switches are turned off. Thereby, all the electric charges accumulated in the capacitors C1 and C2 are discharged.
[0021]
Next, at time t2, the switches SW3 to SW5 are turned on, and the other switches are turned off. Thereby, the PMOS transistor Q1 is turned on / off according to the output of the positive phase amplifier 22.
[0022]
For example, when the output of the positive phase amplifier 22 becomes less than a predetermined level, the PMOS transistor Q1 is turned on, a current flows from the power supply terminal VDD through the source and drain of the PMOS transistor Q1 toward the capacitor C2, and the capacitor C2 is charged. The As the capacitor C2 is charged, the input voltage of the positive phase amplifier 22 gradually increases.
[0023]
Eventually, when the input voltage of the positive phase amplifier 22 exceeds its operating point voltage, the output of the positive phase amplifier 22 becomes high level, and the PMOS transistor Q1 is turned off. As a result, the input voltage of the positive phase amplifier 22 becomes the operating point voltage of the positive phase amplifier 22. This voltage is a voltage approximately halfway between the high level voltage and the low level voltage of the positive phase amplifier 22.
[0024]
Next, at time t3, the switches SW1 and SW2 are turned on, and the other switches are turned off. As a result, the voltage across the capacitor C1 becomes the difference voltage between the pixel data voltage output from the second latch circuit 15 shown in FIG. 2 and the signal line voltage.
[0025]
Next, at time t4, the switches SW3 and SW6 are turned on. At this time, since the charge corresponding to the operating point voltage of the positive phase amplifier 22 is accumulated in the capacitor C2, the input voltage of the positive phase amplifier 22 is the difference voltage between the pixel data voltage and the signal line voltage, A voltage obtained by adding the operating point voltage of the positive phase amplifier 22 is obtained. That is, the input voltage of the positive phase amplifier 22 is a voltage that changes according to the pixel data and the signal line voltage with reference to the operating point voltage of the positive phase amplifier 22.
[0026]
FIG. 6 is a display timing chart of the liquid crystal display device of FIG. 1, and shows the switching timing of the switches SW1 to SW7 within the display period of one horizontal line. As shown in the figure, during the display period of one horizontal line, first, switching at times t1 and t2 shown in FIG. 5 is performed, and thereafter, switching at times t3 and t4 is alternately repeated.
[0027]
Each time one horizontal line is displayed, the switch at times t1 and t2 may be switched. Alternatively, the switch at times t1 and t2 may be switched only once for the first time after power-on.
[0028]
As described above, the analog buffer 16 in FIG. 3 charges the capacitor according to the operating point voltage of the positive phase amplifier 22 before inputting the pixel data, and then sets the difference voltage between the pixel data and the signal line voltage. Since the voltage obtained by adding the operating point voltage of the positive phase amplifier 22 is supplied to each signal line, the luminance of the display panel does not vary even if the operating point voltage of the positive phase amplifier 22 fluctuates.
[0029]
Although FIG. 4 shows an example in which the positive phase amplifier 22 is configured by two stages of inverters, the configuration of the positive phase amplifier 22 is not limited to that illustrated. For example, the positive phase amplifier 22 may be configured with four or more stages of inverters and one or more stages of positive phase buffers.
[0030]
FIG. 4 shows an example using the PMOS transistor Q1, but an NMOS transistor may be used. In this case, the connection between the power supply terminal VDD and the ground terminal may be reversed from that in FIG.
[0031]
【The invention's effect】
As described above in detail, according to the present invention, the input voltage of the positive phase amplifier is set to the operating point voltage of the positive phase amplifier in advance before the input voltage is supplied to the analog buffer. The output is not affected by variations in the operating point voltage of the positive phase amplifier.
[0032]
Therefore, when the present invention is applied to signal line driving of a display device, luminance unevenness due to variations in operating point voltages in the positive phase amplifier does not occur.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a display device according to the present invention.
FIG. 2 is a block diagram showing a detailed configuration in a signal line driver circuit.
FIG. 3 is a block diagram showing an internal configuration of an analog buffer.
FIG. 4 is a circuit diagram showing an internal configuration of a comparator.
FIG. 5 is a diagram showing the switching timing of the switch shown in FIG. 4;
6 is a display timing chart of the liquid crystal display device of FIG. 1. FIG.
[Explanation of symbols]
1 TFT
2 pixel array unit 3 signal line drive circuit 4 scanning line drive circuit 11 shift register 12 first analog switch 13 first latch circuit 14 second analog switch 15 second latch circuit 16 analog buffer 21 comparator 22 positive phase Amplifier SW1 to SW7 Switch Q1 PMOS transistor

Claims (3)

In an analog buffer that supplies a voltage according to the input voltage to the capacitive load,
A first capacitor for accumulating charge according to a voltage difference between an input voltage and a voltage supplied to the capacitive load;
A positive-phase amplifier having a predetermined operating point voltage and outputting an input signal in phase;
A second capacitor connected between one end of the first capacitor and an input terminal of the positive phase amplifier;
In the state where the first capacitor is discharged so that the input voltage of the positive phase amplifier becomes substantially equal to the operating point voltage, electric charge corresponding to the operating point voltage is accumulated in the second capacitor, and then A voltage control circuit that accumulates electric charge according to the differential voltage in a first capacitor, and makes an input voltage of the positive phase amplifier substantially equal to a voltage obtained by adding the operating point voltage to a voltage across the first capacitor; An analog buffer comprising: A display element;
A signal line for supplying pixel data to the display element;
A signal line driving circuit for driving the signal line,
In the display device in which the signal line driven by the signal line driving circuit is a capacitive load,
A first capacitor for accumulating charges according to a voltage difference between the input pixel data and the voltage of the signal line;
A positive-phase amplifier having a predetermined operating point voltage and outputting an input signal in phase;
A second capacitor connected between one end of the first capacitor and an input terminal of the positive phase amplifier;
In the state where the first capacitor is discharged so that the input voltage of the positive phase amplifier becomes substantially equal to the operating point voltage, electric charge corresponding to the operating point voltage is accumulated in the second capacitor, and then A voltage control circuit that accumulates electric charge according to the differential voltage in a first capacitor, and makes an input voltage of the positive phase amplifier substantially equal to a voltage obtained by adding the operating point voltage to a voltage across the first capacitor; A display device comprising: The voltage control circuit includes:
First switching means in which pixel data is input to one end and one end of the first capacitor is connected to the other end;
A second switching means having a signal line connected to one end and the other end of the first capacitor connected to the other end;
Third switching means connected between the other end of the first capacitor and a ground terminal;
Fourth switching means connected between one end of the first capacitor and a ground terminal;
When the output voltage of the positive phase amplifier increases, control is performed such that the input voltage of the positive phase amplifier decreases, and when the output voltage of the positive phase amplifier decreases, the input voltage of the positive phase amplifier increases. A switching element for controlling,
Fifth switching means connected between the output terminal of the switching element and the input terminal of the positive phase amplifier;
Sixth switching means connected between the output terminal of the positive phase amplifier and the signal line;
A seventh switching means connected between the input terminal and the ground terminal of the positive phase amplifier,
When the first time comes, the third and fourth switching means are turned on and the other switching means are turned off so that the accumulated charges of the first and second capacitors are all discharged.
At a second time after the first time, the third and fifth switching means are turned on so that the input voltage of the positive phase amplifier becomes substantially equal to the operating point voltage, and other switching means. Turn off
At the third time after the second time, the first and second switching means are applied so that a difference voltage between the pixel data and the voltage of the signal line is applied to both ends of the first capacitor. To turn off other switching means,
At a fourth time after the third time, the input voltage of the positive phase amplifier becomes the voltage obtained by adding the operating point voltage to the voltage across the first capacitor. Turn on other switching means and turn off other switching means,
3. The display according to claim 2, wherein after the fourth time, the operation at the third time and the fourth time is alternately repeated until at least one signal line is driven once. apparatus.

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