JP4143889B2 - Video signal processing apparatus and method, and program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a video signal processing apparatus and method, and a program, and more particularly to a video signal processing apparatus and method, and a program that can more reliably transmit data between video devices.
[0002]
[Prior art]
Video for production, monitoring, FA (Factory Automation), etc. is mainly point-to-point transmission and requires high-quality video, so it may be uncompressed or low-compressed, and further widened. Many.
[0003]
The SDI (Serial Digital Interface) of HDTV signals that are currently used as an interface between the video equipment is standardized as SMPTE (The Society of Motion Picture and Television Engineers) 292M or BTA S-004. Has been. In this method, video data is allocated to a TS (time slot) in the original analog video section, audio or other data is packetized, and placed in a video H / V (horizontal / vertical) blanking period.
[0004]
[Problems to be solved by the invention]
However, since the SDI uses a scramble method for channel coding (channel coding), there is no increase in transmission rate, but when a specific signal such as a pathological pattern is used, the output is 0 or 1 continuously. As a result, clock reproduction becomes severe and transmission distance must be shortened, or a code error occurs.
[0005]
The present invention has been made in view of such a situation, and makes it possible to more reliably transmit data between video devices even over a long distance.
[0006]
[Means for Solving the Problems]
  The video signal processing device of the present invention allocates a video signal, an audio signal, and a data signal to predetermined bits in a time slot that is an integer multiple of 8 bits, and an audio signal and a data signal to the surplus bits. Multiplexing means for multiplexing the synthesized signal composed of the data channels, and one or more specific data that are time slots output from the multiplexing means and located in the blanking period of the video signal 8B / 10B code synchronization code is assigned to a time slot with no signal in the channel, encoding means for converting the composite signal into 8B / 10B code, and transmission means for transmitting 8B / 10B code are provided, and multiplexed. Means8B / 10B The other party of the code isControl the phase of 8B / 10B codeSometimes referred toThe Genlock control signal is further multiplexed with the synthesized signal.
[0007]
  8B / 10B SignThe synchronization code can be a comma code.
[0008]
  Sent from the other partyReceiving means for receiving the 8B / 10B code, decoding means for detecting the synchronization code from the 8B / 10B code, and decoding the 8B / 10B code into the synthesized signal based on the detected synchronization code, and synthesis Signal, video signal, audio signal,And data signalsAnd a disassembling means for disassembling.
[0009]
The frame of the video channel has the same cycle as the line cycle of the video signal, the data channel has a multi-frame configuration, and the multi frame can have the same cycle as the line cycle of the video signal.
[0010]
  The multiplexing means arranges a multiframe synchronization code in an arbitrary subchannel of the subchannels constituting the data channel, and the encoding means predetermines a time slot other than the subchannel in which the multiframe synchronization code is arranged. ThingsIn 8B / 10B SignSynchronization codeAssignCan be.
[0011]
  As a synchronization code for the data channel,8B / 10B SignCan be used.
[0012]
The multiplexing means may arrange the frame synchronization code within the blanking period of the video channel.
[0013]
  As the synchronization code of the video channel,8B / 10B SignCan be used.
[0015]
  The video signal processing method of the present invention allocates a video signal, an audio signal, and a data signal to a predetermined bit in a time slot that is an integer multiple of 8 bits, and an audio signal and a data signal to the surplus bits. A multiplexing step that multiplexes into a composite signal composed of a plurality of data channels, and a time slot that is output from the processing of the multiplexing step, and one or more specific ones located in the blanking period of the video signal Allocating a synchronization code of 8B / 10B code to a time slot in which the data channel is no signal, an encoding step for converting the synthesized signal into an 8B / 10B code, and a transmission step for transmitting the 8B / 10B code, In the multiplexing step,8B / 10B The other party of the code isControl the phase of 8B / 10B codeSometimes referred toThe Genlock control signal is further multiplexed with the synthesized signal.
[0016]
  The program of the present invention includes a video channel in which a video signal, an audio signal, and a data signal are allocated to a predetermined bit in a time slot that is an integer multiple of 8 bits, and a data channel in which the audio signal and the data signal are allocated to the surplus bits. A multiplexing step that multiplexes the resultant signal into a composite signal, and one or more specific data channels that are time slots output by the processing of the multiplexing step and are located in the blanking period of the video signal Assigns an 8B / 10B code synchronization code to a time slot in which no signal is present, and executes a process including an encoding step for converting the synthesized signal into an 8B / 10B code and a transmission step for transmitting the 8B / 10B code. In the multiplexing step,8B / 10B The other party of the code isControl the phase of 8B / 10B codeSometimes referred toThe Genlock control signal is further multiplexed with the synthesized signal.
[0017]
  In the video signal processing apparatus and method and the program according to the present invention, the video signal, the audio signal, and the data signal are assigned to a predetermined bit in a time slot that is an integral multiple of 8 bits, and the surplus bits are audio. One or more specific data channels, which are the time slots multiplexed and output in a composite signal composed of a data channel to which a signal and a data signal are allocated, and located in a blanking period of the video signal A synchronous code of 8B / 10B code is assigned to a time slot in which no signal is present, and the combined signal is converted into an 8B / 10B code, and an 8B / 10B code is transmitted. Also,8B / 10B The other party of the code isControl the phase of 8B / 10B codeSometimes referred toGenlock control signals are further multiplexed into the composite signal.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a configuration example of a camera control system to which the present invention is applied.
[0019]
The camera control system includes a camera head 1 and a CCU (camera control unit) 2. Usually, the camera head 1 is arranged in a studio or the like where video is shot, and the CCU 2 controls the entire camera head 1 and is arranged in a separate room (control room) that can be remotely controlled. Yes.
[0020]
The camera head 1 and the CCU 2 are connected by a cable such as G-bit (Gigabit) Ether or Fiber Channel using an optical fiber. For transmission over this cable, a G-bit Ether or Fiber Channel physical layer is used, and a TS (time slot) allocation frame configuration is used instead of a packet in order to increase transmission efficiency (details are shown in FIG. 5). To be described later).
[0021]
As shown in FIG. 1, the signals transmitted from the camera head 1 to the CCU 2 include, for example, video signals, audio signals, camera control data, metadata, external control data, and intercom signals captured by the camera head 1. There is.
[0022]
For example, when the camera head 1 uses an ND filter or the like, the camera control data includes a signal for notifying the CCU 2 side of this, and the external control data indicates the camera head 1 such as pan and tilt. Includes external signals that tilt or move in a horizontal direction. The metadata is additional information data of a captured video signal, and includes, for example, a shooting date, position information by GPS (Global Positioning System), a title, and copyright information. The income signal includes an income signal for making a call between the operator of the camera head 1 and the operator of the CCU 2.
[0023]
The signals transmitted from the CCU 2 to the camera head 1 include, for example, a return video signal, a return audio signal, camera control data, a Genlock control signal, external control data, and an income signal.
[0024]
The return video signal and the return audio signal are signals that are being broadcast (output) at that time, such as video captured by other camera heads (not shown) or playback signals played back by a VTR (not shown) or the like. It is. As a result, the cameraman who operates the camera head 1 can check the video captured by another camera head or the VTR and the video broadcast at that time. Further, the camera control data transmitted from the CCU 2 to the camera head 1 is a signal for controlling, for example, adjustment of brightness and the like at the time of shooting by the camera on the CCU 2 side. The Genlock control signal is a control signal for synchronizing signals in the camera control system (broadcast station). This Genlock control signal is received by the CCU 2 from another reference device not shown.
[0025]
Each of the camera head 1 and the CCU 2 inputs / outputs external control data and an income signal to / from an external device. Further, the CCU 2 transmits a video signal, an audio signal, and metadata captured by the camera head 1 to another video device (not shown), and receives a return video signal and an audio signal from the other video device. At this time, the audio signal and the metadata are multiplexed on the data channel.
[0026]
FIG. 2 is a block diagram illustrating a configuration example of the camera head 1 of FIG.
[0027]
The imaging display unit 11 includes an imaging unit 21, a display unit 22, a control unit 23, and the like. The video signal photographed by the photographing unit 21 is supplied and displayed on the display unit 22. Thereby, the cameraman can perform a predetermined operation while viewing the video displayed on the display unit 22. The control unit 23 generates various signals (such as audio signals or control data) other than video signals as data signals.
[0028]
The 10-bit G, B, and R color signals of the video imaged by the imaging unit 21 are output to the multiplexer 12 (there may be Y, Pb, and Pr depending on the video signal). A data signal from the control unit 23 is also output to the multiplexer 12. The multiplexer 12 multiplexes the G, B, and R color signals and data signals into a 16-bit synthesized signal composed of a 15-bit video signal and a 1-bit data signal, and outputs the multiplexed signal to the encoding unit 13.
[0029]
The encoding unit 13 performs 8B / 10B conversion (channel coding) on the 16-bit composite signal. At this time, the encoding unit 13 inserts a comma code representing an 8-bit break once into one line of the video.
[0030]
The synthesized signal output from the encoding unit 13 is converted from a parallel signal to a serial signal by a P / S (Parallel / Serial) conversion unit 14 and converted from an electric signal by an E / O (Electrical-Optical) conversion unit 15. It is converted into an optical signal and transmitted to the CCU 2 via an optical fiber cable.
[0031]
In FIG. 2, an optical fiber cable is used. However, a coaxial cable may be used instead of the optical fiber cable. If the distance is short, LVDS (Low Voltage Differential Signal) is used after serial conversion. ) Or the like (with a stranded wire).
[0032]
An O / E converter (Optical-Electrical) 16 converts a video signal received from the CCU 2 via an optical fiber cable from an optical signal to an electrical signal, and outputs it to an S / P (Serial / Parallel) converter 17. To do. The S / P converter 17 converts the input signal from a serial signal to a parallel signal and outputs the parallel signal to the decoder 18.
[0033]
The decoding unit 18 detects a comma code from the input signal, and performs 8B / 10B inverse conversion (channel decoding) based on the comma code. At the same time, the decoding unit 18 also decodes the Genlock control signal encoded in the CCU 2 (described later with reference to FIG. 4). The demultiplexer 19 decomposes the input signal into 10-bit G, B, and R color signals, data signals, and Genlock control signals, and supplies them to the imaging display unit 11. Further, the demultiplexer 19 reproduces the instruction pulse from the Genlock control signal.
[0034]
FIG. 3 shows parameters in each part of FIG. 2 corresponding to the imaging method of the photographing display unit 11. In the upper row, when the video signal output by the photographing display unit 11 is a video signal of 1440 × 1080 / 59.94i GBR 3: 3: 3 each 10 bits encoded, the middle row shows 1920 × 1080 / 60i GBR 4: 4: 4 In the case of each 10-bit encoded video signal, and the lower part, each parameter in the case of a 1920 × 1080 / 59.94i YPbPr 4: 2: 2 12-bit encoded video signal is shown. First, the video signal of 10 bits encoding of each 1440 × 1080 / 59.94i GBR 3: 3: 3 in the upper stage will be described.
[0035]
The video sampling frequency fs of the video signal (10-bit G, B, and R color signals) output from the imaging display unit 11 or output from the demultiplexer 19 is 55.631868 MHz. The amount of video data is 1.112637 Gbps.
[0036]
The parallel data rate fp of the next composite signal (video signal 15 bits and data signal 1 bit) output from the multiplexer 12 or output from the decoding unit 18 is 111.263736 Mbps, and the total amount of data at this time Is 1.780220 Gbps.
[0037]
Furthermore, the parallel channel coding rate fcc of the video signal output from the encoding unit 13 or output from the S / P conversion unit 17 is 139.079670 Mbps and output from the P / S conversion unit 14. Alternatively, the serial transmission rate ft of the video signal output from the O / E converter 16 is 2.225275 Gbps.
[0038]
Similarly, in the case of a video signal of 10 bits encoded at 1920 × 1080 / 60i GBR 4: 4: 4 in the middle stage, the video sampling frequency fs is 74.25 MHz, and the total video data amount at this time is 2.2275 Gbps. is there. The parallel data rate fp is 148.5 Mbps, the total data amount at this time is 2.376 Gbps, the parallel channel coding rate fcc is 185.625 Mbps, and the serial transmission rate ft is 2.97 Gbps. .
[0039]
Further, similarly, in the case of a video signal of 12 bits encoding each of 1920 × 1080 / 59.94i YPbPr 4: 2: 2 in the lower stage, the video sampling frequency fs is 74.25 MHz, and the total video data amount at this time is 1.782Gbps. The parallel data rate fp is 148.5 Mbps, the total data amount at this time is 2.376 Gbps, the parallel channel coding rate fcc is 185.625 Mbps, and the serial transmission rate ft is 2.97 Gbps. .
[0040]
Next, FIG. 4 is a block diagram showing a configuration example of the CCU 2 of FIG. The multiplexer 52, encoding unit 53, P / S conversion unit 54, E / O conversion unit 55, O / E conversion unit 56, S / P conversion unit 57, decoding unit 58, and demultiplexer 59 are respectively shown in FIG. Multiplexer 12, encoding unit 13, P / S conversion unit 14, E / O conversion unit 15, O / E conversion unit 16, S / P conversion unit 17, decoding unit 18, and demultiplexer 19, basically The same function is executed, and the description thereof will be repeated and will be omitted.
[0041]
The decoding unit 58 detects a comma code from the combined signal, performs 8B / 10B inverse transform (channel decoding) based on the comma code, and outputs the result to the demultiplexer 59. The demultiplexer 59 decomposes the combined signal into 10-bit G, B, and R color signals and data signals, and supplies them to the process control unit 60.
[0042]
The CPU 61 obtains a phase difference between the camera head 1 and the CCU 2 based on a preset reference signal of the camera control system, and controls the Genlock generator 62 so that the frame phase of the video signal to be transmitted is in phase. Generate a Genlock control signal. This Genlock control signal is controlled to advance the phase corresponding to the transmission delay between the camera head 1 and the CCU 2, the system delay in the camera head 1, and the CCU 2, and finally the phase at the output end is specified. Phase relationship (for example, the same phase). Further, the CPU 61 determines whether or not there is a margin in the transmission line based on the video signal from the camera head 1 supplied from the process control unit 60, and instructs the method for transmitting the Genlock control signal.
[0043]
The process control unit 60 outputs the 10-bit G, B, and R color signals and data signals to be transmitted to the CPU 61 and the multiplexer 52.
[0044]
The multiplexer 52 multiplexes the G, B, and R color signals, the data signal, and the Genlock control signal generated by the Genlock generator 62 into a 16-bit composite signal composed of a 15-bit video signal and a 1-bit data signal. And output to the encoding unit 53.
[0045]
5 and 8 to 12 show configuration examples of transmission frames of HDTV defined by SMPTE 274M or several video schemes equivalent thereto. These frame configurations can be similarly configured for other video formats such as SMPTE 274M, 296M, and super 1920 × 1080.
[0046]
First, with reference to FIG. 5, an example of a frame configuration of a 10-bit encoded video signal with an active area of 1440 × 1080, 59.94i, and GBR 3: 3: 3 will be described.
[0047]
In this case (1440 × 1080, 60i (60 / 1.001i)), as shown in FIG. 6A, the horizontal total number of samples / line is 1650, and the horizontal standard active pixel number / line is 1440. The number of pixels / line at the time of horizontal narrowing ranking is 1468. The total number of lines is 1125 / frame, and one frame is composed of two fields, a first field (field 1) 563 and a second field (field 2) 562. The standard number of active lines is 1080 / frame, each field is composed of 540 / field, the number of active lines at the time of narrowing ranking is 1082 / frame, and each field is 541 / field. The sampling frequency (equivalent to Y) is 55.6875 (55.6875 / 1.001) MHz. The number of pixels at the time of narrowing ranking is an example.
[0048]
In general, in a video camera, a slight margin is added outside the active area (effective pixel) of the video signal in order to be useful for video signal processing. In the camera control system, horizontal blanking (hereinafter, H (Horizontal) blanking) period and vertical blanking (hereinafter referred to as V (Vertical) blanking) period, the narrowing blanking period (narrow BLK) video signal. Handle.
[0049]
FIG. 5A shows the standard blanking and narrowing ranking of such a video signal during the V blanking period, and the upper numbers indicate line numbers. As shown in FIG. 6A, the total number of lines in one frame is 1125 / frame, and one frame is composed of two fields, a first field (field 1) 563 and a second field (field 2) 562. Therefore, F in FIG. 5A is a field identification code according to SMPTE 274M and 292M, and the value is “0” in the first field (# 1) (line number 1 to line number 563 (563 lines)). In the second field (# 2) (line number 564 to line number 1125 (562 lines)), the value is “1”.
[0050]
V is a V blanking identification code according to SMPTE 274M, 292M, a value “1” indicates a standard blanking period, and a value “0” is not a standard blanking period. , Indicating a standard active line (video). Therefore, line numbers 1124 to 20 (22 lines) are standard blanking periods (BLK) with a value of “1”, and line numbers 21 to 560 (540 lines) are standard active with a value of “0”. Line numbers 56 1 to 583 (23 lines) are standard blanking periods (BLK) of value “1”, and line numbers 584 to 1123 (540 lines) are values “ 0 "standard active line.
[0051]
Furthermore, the narrowing ranking period includes line numbers 1124 to 19 (21 lines) and line numbers 561 to 582 (22 lines, and other periods (line numbers 20 to 560 (541 lines)). ) And line numbers 583 to 1123 (541 lines)) are active lines (nbvideo) at the time of narrowing ranking.
[0052]
On the other hand, FIG. 5B shows a multiplexed frame of video and data signals in the case of narrowing ranking near H blanking.
[0053]
The upper G, B, and R are 10-bit encoded digital GBR signals output from the imaging display unit 11 in FIG. 2, respectively, and the middle # 0 to # 1649 (1650 samples) are samples of one line. Numbers are shown (total number of horizontal samples / line in FIG. 6A). At this time, the H narrowing ranking period is 182 samples (pixels), and the standard blanking period is 210 pixels. The lower part shows a 16-bit parallel data sequence of a multiplexed frame (transmission frame) of the composite signal output from the multiplexer 12 of FIG.
[0054]
In the multiplexer 12, each 10 bits of GBR is allocated to two TS (time slots) of the upper 15 bits (b0 to b14) of 16 bits parallel data. Since one sample (pixel) is composed of two TSs, each TS is set as a TS of φ1 and φ2, respectively. Therefore, the upper 10 bits (b0 to b9) are assigned G data to the φ1 TS, and the upper 5 bits of the 10 bit B data are assigned to the next 5 bits (b10 to b14). Is assigned the R data in the upper 10 bits, and the lower 5 bits of the 10 bits of B data are assigned to the next 5 bits. The lowest 16th bit (b15) is used for data. Hereinafter, the upper 15 bits (b0 to b14) of the 16-bit parallel data (synthesized signal) are referred to as a video channel, and the lowermost 16th bit (b15) is referred to as a data channel.
[0055]
This 16-bit parallel data video transmission frame has the same cycle as one line of the GBR video signal. Then, “SAV (Start of Active Video)” is provided as a frame synchronization code. SAV is a TS in the narrowing ranking period, and 10 bits are allocated from the MSB (Most Significant Bit) of four TSs immediately before the start TS of the video signal. It has the same purpose as SMPTE 292M's SAV (or EAV (End of Active Video)), but it is simplified and 3FFh (all 10 bits are "1"), 000h ( 10 bits all “0”), 3FFh (10 bits all “1”) are assigned as synchronization codes, and the fourth TS includes F (field identification code) and V (V blanking identification code) in FIG. Information is allocated.
[0056]
The 3FFh, 000h, and 3FFh codes (10 bits) used as the synchronization code are codes that cannot appear in the video data (prohibition code) in order to prevent a part of the video data from being erroneously detected as the synchronization code. . As the video data, a range from 001h to 3FEh is used. In FIG. 5B, “Res” represents Reserve, and a signal is assigned as necessary.
[0057]
Further, the video data in the H blanking period and the V blanking period is fixed to a specific code, for example, 040h (black level of the video signal). It is possible to insert other data signals or the like into this portion as necessary.
[0058]
The lowest 16th bit (b15) of the 16-bit parallel data is a data channel for various signals (audio signal and data signal) other than the video signal. The data channel has a multi-frame configuration, and a necessary number of subchannels (tributaries) are provided. The multi-frame cycle is the same cycle as one line of the GBR video signal, like the video transmission frame. For example, in the example of FIG. 5B, since one multiframe is composed of 3300 (= 1650 × 2) TSs, the number of subchannels is the number of TSs of one multiframe (in this case, 3300 TS). Any number may be used as long as it is a divisor. For example, if the number of subchannels is 20, the parallel data rate fp is 111.263736 Mbps (FIG. 3), so the data rate per subchannel is about 5.6 Mbps. Since the control data is asynchronous, it can be transmitted as a packet, but even if it is sampled and transmitted at 5.6 MHz, a sufficient capacity can be secured.
[0059]
When the number of subchannels is 20, TSs with subchannel numbers (Subch No.) of 0 to 19 are sequentially arranged in the data channel as shown in FIG. One of the subchannels (for example, Subch No. 0 which is the first channel) is assigned for multi-frame synchronization. The number of bits per multi-frame of the subchannel is 3300/20 = 165, and the synchronization code (Multi Frame Sync pattern) is a fixed pattern of an appropriate length, for example, 20 bits length, and is “10111111101000000010” (The remaining 145 bits become free bits). Then, the start position of the multiframe is set to a specific phase of the video channel, for example, the first TS of the SAV.
[0060]
Further, when 8B / 10B conversion (channel coding) is performed in the encoding unit 13 of FIG. 2, in order to be able to detect a break when 10B is reversely converted to 8B on the receiving side, generally “K28. A specific 10-bit code “Comma Code” called “5” is inserted.
[0061]
In order to establish 8B / 10B conversion and inverse conversion as a transmission line, there is a method of transmitting K28.5 only at the start of transmission and not transmitting after establishment, but in the present invention, in consideration of bit errors, K28.5 is transmitted even after synchronization.
[0062]
In the TS into which K28.5 is inserted, the original data is replaced with K28.5, and therefore, it is necessary to place meaningless data in that portion of the original data. Therefore, for example, K28.5 is also inserted at a period of one line of the video, and the phase thereof is multiplexed within the H blanking (or H narrowing ranking) period of the video as shown in FIG. It is not a Multi Frame Sync pattern of a multi-frame synchronization channel (first subchannel) in the data channel, that is, a TS without a significant signal (no signal).
[0063]
Therefore, in FIG. 5B and FIG. 7, K28.5 is assigned to one TS or a plurality of TSs among 18 TSs # 1638φ1, # 1628φ1, # 1618φ1,. For example, when K28.5 is assigned to # 1638φ1, since the comma code is 16 bits, the 16 bits of the video channel and data channel of # 1638φ1 are replaced with K28.5. Further, comma code synchronization (multi-frame synchronization) is performed only on the data channel.
[0064]
As described above, in the frame configuration of the present invention, since the video channel, the data channel, and the comma code (K28.5) have the same period, multi-frame synchronization of the video channel or the data channel is achieved at K28.5. It is also possible.
[0065]
FIG. 8 shows a frame configuration example of a video signal with an active area of 1920 × 1080, 60i (59.94i), and GBR 4: 4: 4 each 10 bits encoded. FIG. 8A shows standard blanking and narrowing ranking in the V blanking period, and FIG. 8B shows multiple frames of video and data signals in the case of narrowing ranking in the vicinity of H blanking.
[0066]
In this case (1920 × 1080, 60i (60 / 1.001i)), as shown in FIG. 6B, the horizontal total number of samples / line is 2200, and the horizontal standard active pixel number / line is 1920. The number of active pixels / line at the time of horizontal narrowing ranking is 1956. The total number of lines is 1125 / frame, and one frame is composed of two fields, a first field (field1) 563 and a second field (field2) 562, and the standard active line number is 1080 / frame. Each field consists of 540 / field. The number of active lines at the time of narrowing ranking is 1086 / frame, and in each field is 543 / field. The sampling frequency (equivalent to Y) is 74.25 (74.25 / 1.001) MHz. At this time, the H narrowing ranking period is 244 (= 2200-1956) pixels, and the standard blanking period is 280 (= 2200-1920) pixels. The number of pixels at the time of narrowing ranking is an example.
[0067]
The frame configuration in FIG. 8 is the same as the frame configuration in FIG. 5 described above except that the total number of samples and the number of pixels in one line are different, so the description will be repeated. Omitted.
[0068]
FIG. 9 shows an example of a frame configuration of a video signal with an active area of 1920 × 1080, 60i (59.94i), and YPbPr 4: 4: 4 each 10 bits encoded. FIG. 9 shows multiplexed frames of video and data signals in the case of narrowing ranking in the vicinity of H blanking, where GBR in FIG. 8B is YPbPr, and the Y blanking period of Y, Pb, and Pr. Since the other configurations are the same as the frame configuration of FIG. 5B or FIG. 8B described above except that the values of are set to 040h, 200h, and 200h, the description thereof will be repeated. Omitted.
[0069]
FIG. 10 shows an example of a frame configuration of a video signal with an active area of 1920 × 1080, 60i (59.94i), and GBR 4: 4: 4 12-bit encoding.
[0070]
In this case, a 12-bit encoded digital GBR video signal (12 bits × 3 (GBR)) of 74.25 MHz samples is sequentially assigned to the upper 12 bits (b0 to b11) of three TSs of 148.5 Mbps 16-bit parallel data. The lower 3 bits (b12 to b14) are Res (Reserve). The value of the H blanking period of GBR is 100h in all cases.
[0071]
As SAV synchronization codes, FFFh, 000h, and FFFh (12 bits each), which are codes (prohibition codes) that cannot appear in the video signal, are used to prevent erroneous detection. In order to make the synchronization detection circuit common to the case of 10 bits encoding, the synchronization code may be upper 10 bits and may be 3FFh, 000h, 3FFh (10 bits). In that case, the prohibition codes are FFFh to FFBh and 000h to 003h (12 bits).
[0072]
Since the other configuration of the frame configuration in FIG. 10 is the same as the frame configuration in FIG. 5B described above, the description thereof will be omitted and will be omitted.
[0073]
Further, FIG. 11 shows that the active area is 1920 × 1080, 60i (59.94i), YPbPr 4: 2: 2
FIG. 12 shows an example of the frame configuration of each 10-bit encoded video signal, and FIG. 12 shows an example of the frame configuration of each 12-bit encoded video signal with an active area of 1920 × 1080, 60i (59.94i), YPbPr 4: 2: 2. . # 0 to # 2199 in the middle row indicate Y sample numbers.
[0074]
In the case of the 10-bit encoded video signal of FIG. 11, the 10-bit encoded video signal (10 bits × 2 (YPb / Pr)) of 74.25 MHz sample is the upper 10 bits of two TSs of 148.5 Mbps 16-bit parallel data. Allocated sequentially to (b0 to b9). The lower 5 bits (b10 to b14) are reserved. The values of the H blanking periods of Y, Pb, and Pr are 040h, 200h, and 200h, respectively.
[0075]
In the case of the 12-bit encoded video signal of FIG. 12, the 12-bit encoded video signal of 74.25 MHz sample (12 bits × 2 (YPb / Pr)) is the upper 12 bits of two TSs of 148.5 Mbps 16-bit parallel data. Allocated sequentially to (b0 to b11). The lower 3 bits (b12 to b14) are reserved. The values of the Y blanking period of Y, Pb, and Pr are 100h, 800h, and 800h, respectively.
[0076]
Other configurations of the frame configurations of FIGS. 11 and 12 are the same as those of the above-described frame configuration of FIG. 5B or FIG.
[0077]
Next, the video signal transmission processing of the camera head 1 will be described with reference to the flowchart of FIG. In the following, it is assumed that video signal processing of 1440 × 1080 / 59.94i GBR 3: 3: 3 each 10 bits encoding is performed.
[0078]
In step S <b> 1, the photographing display unit 11 supplies the multiplexer 12 with the GBR video signal (10 bits × 3) photographed by the photographing unit 21 and the data signal generated by the control unit 23.
[0079]
In step S <b> 2, the multiplexer 12 multiplexes the supplied video signal and data signal into a 16-bit video signal, and supplies the multiplexed video signal (synthesized signal) to the encoding unit 13.
[0080]
In step S3, the encoding unit 13 replaces a predetermined TS of the video signal with K28.5 (comma code), performs 8B / 10B conversion (channel coding), and sends the video signal to the P / S conversion unit 14. Supply.
[0081]
In step S <b> 4, the P / S conversion unit 14 converts the video signal of 16-bit parallel data into serial data and supplies it to the E / O conversion unit 15.
[0082]
In step S5, the E / O conversion unit 15 converts the supplied video signal into an optical signal, and transmits the optical signal to the CCU 2 via the optical fiber cable.
[0083]
Corresponding to the transmission processing of the camera head 1, the CCU 2 performs reception processing of the transmitted video signal. The reception processing of CCU2 will be described with reference to the flowchart of FIG.
[0084]
In step S <b> 21, the O / E conversion unit 56 receives the video signal transmitted from the camera head 1 via the optical fiber cable, converts it into an electrical signal, and supplies it to the S / P conversion unit 57.
[0085]
In step S <b> 22, the S / P converter 57 converts the serial data video signal into parallel data and outputs the parallel data to the decoder 58.
[0086]
In step S23, the decoding unit 58 detects the comma code replaced by the process of step S3 in FIG. 13, converts the 10B video signal back to 8B based on the comma code, and supplies it to the demultiplexer 59. .
[0087]
In step S <b> 24, the demultiplexer 59 decomposes the supplied video signal into RGB color signals and other data signals, and supplies them to the process control unit 60.
[0088]
As described above, transmission / reception of the video signal between the camera head 1 and the CCU 2 is reversely converted to 8B / 10B by inserting a comma code and detecting the comma code on the receiving side on the transmitting side for 8B / 10B conversion. be able to. As a result, video signals can be transmitted and received between the camera head 1 and the CCU 2 by using a physical layer of 8B / 10B channel coding of G-bit Ether or Fiber Channel.
[0089]
With the development of the Internet in recent years, infrastructure such as G-bit (Gigabit) Ether or Fiber Channel has been established, and it has become a level applicable to wideband video signals. Therefore, in the present invention, these infrastructures can be used instead of SDI. These use 8B / 10B channel coding and have a 25% increase in transmission rate, but do not generate the pathological pattern that is a drawback of SDI.
[0090]
Furthermore, since a system using G-bit (Gigabit) Ether or Fiber Channel is more popular than SDI, it can be constructed at low cost.
[0091]
Next, video signal transmission processing of the CCU 2 will be described based on the flowchart of FIG. This process is basically the same process as the camera head 1, but when transmitting a video signal, the CCU 2 generates a Genlock control signal for phase matching as a unique control between the CCU 2 and the camera head 1. .
[0092]
In step S41, the process control unit 60 transmits a video signal (video captured by another camera head, return video signal that is a reproduction signal reproduced by a VTR, etc.), audio signal, and data to be transmitted to the camera head 1 The signal is supplied to the multiplexer 52, and the video signal received from the camera head 1 is supplied to the CPU 61 in step S42.
[0093]
In step S43, the CPU 61 obtains a phase difference between the camera head 1 and the CCU 2 based on a preset reference signal of the camera control system.
[0094]
In step S44, the CPU 61 controls the Genlock generator 62 so that the frame phase of the video signal from the CCU 2 has a specific phase relationship (for example, in-phase) based on the phase difference obtained in step S43. A Genlock control signal is generated and supplied to the multiplexer 52. This Genlock control signal is controlled to advance the phase corresponding to the transmission delay between the camera head 1 and the CCU 2, the system delay in the camera head 1, and the CCU 2, and finally the phase at the output end is specified. Phase relationship (for example, in-phase).
[0095]
In step S <b> 45, the CPU 61 determines whether there is a margin in the transmission line between the camera head 1 and the CCU 2 based on the video signal received from the camera head 1. For example, it is determined whether 2 bits or more of an 8B / 10B 16-bit transmission frame can be used for a data signal. If it is determined in step S45 that there is a margin in the transmission line, in step S46, the multiplexer 52 uses 2 bits of the 8B / 10B 16-bit transmission frame for the data signal, and controls the Genlock control signal in 1 bit of the data signal. Assign pulses. In this case, for example, by using 1 bit of 16 bits of the video signal as a Genlock control signal, the phase on the camera head 1 side can be controlled with an accuracy of fp.
[0096]
In step S45, if it is determined that there is no room in the transmission line, for example, if there is only one data channel as in the frame configuration of the present invention, the data subchannel has an accuracy of, for example, fp / 20. In step S47, the demultiplexer 52 encodes (time stamps) the phase difference (Genlock control signal) from the multi-frame synchronization phase of the data channel using a specific subchannel (for example, the 19th channel), and The head 1 is instructed.
[0097]
The number of bits of the phase difference (Genlock control signal) in this case is 11 bits when the accuracy of the phase difference is the precision of the pixel sampling fs and the total number of samples per line is 1650 (for example, FIG. 5). When the total number of samples per line is 2200 (for example, FIG. 8), it is represented by 12 bits, and when the number of lines is 1125, it is represented by 11 bits. This Genlock control signal is transmitted every frame. Further, instead of coding the number of lines with 11 bits, a flag may be set only for a transmission frame instructed with 1 bit.
[0098]
In step S <b> 48, the encoding unit 53 performs 8B / 10B conversion on the video signal supplied from the multiplexer 52 and supplies the converted video signal to the P / S conversion unit 54.
[0099]
In step S49, the P / S converter 54 serially converts the 8B / 10B converted video signal. In step S50, the E / O converter 55 converts the serially converted video signal into an optical signal. It transmits to the camera head 1 via an optical fiber cable.
[0100]
Corresponding to the transmission processing of the CCU 2, the camera head 1 performs reception processing of the transmitted video signal. The reception process of the camera head 1 will be described with reference to the flowchart of FIG.
[0101]
In step S <b> 61, the O / E converter 16 converts the video signal received from the CCU 2 via the optical fiber cable from an optical signal to an electrical signal, and outputs the electrical signal to the S / P converter 17. In step S <b> 62, the S / P conversion unit 17 converts the serial data video signal into parallel data and outputs the parallel data to the decoding unit 18.
[0102]
In step S63, the decoding unit 18 detects a comma code from the video signal, and performs inverse 8B / 10B conversion (channel decoding) based on the comma code. At this time, the decoding unit 18 also performs 8B / 10B inverse conversion processing on the encoded Genlock control signal in step S43 of FIG.
[0103]
In step S64, the demultiplexer 19 decomposes the video signal into 10-bit G, B, and R color signals, data signals, and Genlock control signals, and reproduces the instruction pulse from the Genlock control signals. The demultiplexer 19 supplies all of them to the imaging display unit 11.
[0104]
As described above, the Genlock control signal encoded by the CCU 2 is inversely converted (decoded) by 8B / 10B on the camera head 1 side, and the instruction pulse is reproduced, so that the phase difference between the camera head 1 and the CCU 2 is obtained. Can be reduced (phase-synchronized).
[0105]
As described above, many high-speed devices are used by using the physical layer of 8B / 10B channel coding (conversion) of G-bit Ether or Fiber Channel, which is standardized and expected to be widely used. can do. Also, the 8B / 10B channel coding can avoid the SDI (scrambled NRZI) pathology pattern problem of video. Furthermore, the present invention can be applied to 2k × 4k pixel class images such as Beond HD and D-cinema.
[0106]
In addition, by making the data channel independent of the video channel, control data such as synchronization codes can be handled easily. For example, the video channel can be synchronized only by the data channel without taking the frame synchronization of the video channel, and the data channel is not affected even if the video channel is out of synchronization. Further, since the assembly or disassembly of the packet is not necessary, the circuit load is reduced, or the asynchronous control data can be transmitted by multipoint sampling.
[0107]
Furthermore, the frame configuration in which the H blanking of the video and the vacant TS (time slot) of the data channel are arranged in phase allows the 8B / 10B comma code to be replaced periodically without converting the speed of the video signal. The line reliability is improved.
[0108]
The series of processes described above can be executed by hardware, but can also be executed by software. In this case, for example, multiplexers 12 and 52, encoding units 13 and 53, P / S conversion units 14 and 54, E / O conversion units 15 and 55, O / E conversion units 16 and 56, and S / P conversion unit 17. , 57, decoding units 18, 58, and demultiplexers 19, 59 are constituted by a video signal processing device 70.
[0109]
In FIG. 17, a CPU (Central Processing Unit) 71 performs various processes according to a program stored in a ROM (Read Only Memory) 72 or a program loaded from a storage unit 78 to a RAM (Random Access Memory) 73. Execute. The RAM 73 also appropriately stores data necessary for the CPU 71 to execute various processes.
[0110]
The CPU 71, ROM 72, and RAM 73 are connected to each other via a bus 74. An input / output interface 75 is also connected to the bus 74.
[0111]
The input / output interface 75 includes an input unit 76 including a keyboard and a mouse, a display including a CRT (Cathode Ray Tube) and an LCD (Liquid Crystal Display), an output unit 77 including a speaker, and a hard disk. A communication unit 79 including a storage unit 78, a modem, a terminal adapter, and the like is connected. The communication unit 79 performs communication processing via a network (not shown).
[0112]
A drive 80 is connected to the input / output interface 75 as necessary, and a magnetic disk 81, an optical disk 82, a magneto-optical disk 83, a semiconductor memory 84, or the like is appropriately mounted, and a computer program read from the drive is required. Is installed in the storage unit 78 according to the above.
[0113]
When a series of processing is executed by software, a program constituting the software may execute various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a network or a recording medium into a general-purpose personal computer or the like.
[0114]
In the present specification, the step of describing the program recorded in the recording medium is not limited to the processing performed in time series according to the described order, but is not necessarily performed in time series, either in parallel or individually. The process to be executed is also included.
[0115]
Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.
[0116]
【The invention's effect】
  As described above, according to the video signal processing apparatus and method and the program of the present invention, a video channel in which a video signal, an audio signal, and a data signal are allocated to predetermined bits in a time slot that is an integer multiple of 8 bits; One or more specific time slots that are multiplexed and output to a synthesized signal composed of a data channel in which audio signals and data signals are assigned to the surplus bits, and are located in the blanking period of the video signal , Assigning an 8B / 10B code synchronization code to a time slot in which the data channel is no signal, converting the synthesized signal to an 8B / 10B code, transmitting an 8B / 10B code, and8B / 10B The other party of the code isControl the phase of 8B / 10B codeSometimes referred toSince the Genlock control signal is further multiplexed with the composite signal, the data between the video devices can be transmitted more reliably over a long distance.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of a camera control system to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration example of the camera head of FIG.
FIG. 3 is a diagram illustrating parameters in each part of the camera head in FIG. 2;
4 is a block diagram illustrating a configuration example of the CCU in FIG. 1. FIG.
5 is a diagram for explaining a configuration example of a transmission frame of the camera control system of FIG. 1; FIG.
6 is a diagram for explaining scan parameters of the camera control system of FIG. 1; FIG.
FIG. 7 is a diagram illustrating a data subchannel and a comma code.
8 is a diagram for explaining another configuration example of a transmission frame of the camera control system in FIG. 1. FIG.
9 is a diagram illustrating still another configuration example of the transmission frame of the camera control system in FIG. 1. FIG.
10 is a diagram illustrating still another configuration example of a transmission frame of the camera control system in FIG. 1. FIG.
11 is a diagram illustrating still another configuration example of the transmission frame of the camera control system in FIG. 1. FIG.
12 is a diagram illustrating still another configuration example of a transmission frame of the camera control system in FIG. 1. FIG.
13 is a flowchart for explaining video signal transmission processing of the camera head of FIG. 2;
14 is a flowchart illustrating video signal reception processing of the CCU of FIG.
15 is a flowchart for explaining video signal transmission processing of the CCU of FIG. 4;
16 is a flowchart for explaining video signal reception processing of the camera head of FIG. 2;
FIG. 17 is a diagram illustrating another configuration example of the video signal processing apparatus.
[Explanation of symbols]
1 camera head, 2 CCU, 12 multiplexer, 13 encoding unit, 14 P / S conversion unit, 17 S / P conversion unit, 18 decoding unit, 19 demultiplexer, 52 multiplexer, 53 encoding unit, 54 P / S conversion Unit, 57 S / P conversion unit, 58 decoding unit, 59 demultiplexer, 60 process control unit, 61 CPU, 62 Genlock generation unit

Claims (10)

In a video signal processing apparatus for serial transmission of video signals, audio signals and data signals,
From the video channel in which the video signal, the audio signal, and the data signal are allocated to predetermined bits in a time slot that is an integer multiple of 8 bits, and the data channel in which the audio signal and the data signal are allocated to the surplus bits A multiplexing means for multiplexing the composed composite signal;
8B / 10B code in the time slot output from the multiplexing means and in one or more specific time slots located in the blanking period of the video signal where the data channel is no signal And encoding means for converting the synthesized signal into an 8B / 10B code,
Transmission means for transmitting the 8B / 10B code,
Said multiplexing means is a video in which the 8B / 10B code of the transmission partner, the Genlock control signal to be referred in controlling the 8B / 10B code phase, characterized by further multiplexing the combined signal Signal processing device. The video signal processing apparatus according to claim 1, wherein the synchronization code of the 8B / 10B code is a comma code. Receiving means for receiving the 8B / 10B code transmitted from the transmission partner ;
Detecting the synchronization code from the 8B / 10B code, and based on the detected synchronization code, decoding means for 10B / 8B decoding the 8B / 10B code into the synthesized signal;
The video signal processing apparatus according to claim 1, further comprising: a decomposing unit that decomposes the synthesized signal into the video signal, the audio signal, and the data signal . The frame period of the video channel is the same period as the line period of the video signal,
The data channel has a multi-frame configuration,
The video signal processing apparatus according to claim 1, wherein a period of the multiframe is the same as a line period of the video signal. The multiplexing means arranges the multiframe synchronization code in an arbitrary subchannel among the subchannels constituting the data channel,
5. The video signal according to claim 4, wherein the encoding means assigns the synchronization code of the 8B / 10B code to a predetermined one of time slots other than the subchannel in which the multiframe synchronization code is arranged. Processing equipment. The video signal processing apparatus according to claim 5, wherein the synchronization code of the 8B / 10B code is used as the synchronization code of the data channel. The video signal processing apparatus according to claim 4, wherein the multiplexing unit arranges the synchronization code of the frame within a blanking period of the video channel. The video signal processing apparatus according to claim 7, wherein the synchronization code of the 8B / 10B code is used as the synchronization code of the video channel. In a video signal processing method for a video signal processing apparatus that serially transmits a video signal, an audio signal, and a data signal,
From the video channel in which the video signal, the audio signal, and the data signal are allocated to predetermined bits in a time slot that is an integer multiple of 8 bits, and the data channel in which the audio signal and the data signal are allocated to the surplus bits A multiplexing step for multiplexing into a composed composite signal;
8B / in the time slot output by the processing of the multiplexing step, and in one or more specific time slots in the blanking period of the video signal in which the data channel is no signal. An encoding step of allocating a synchronization code of 10B code and converting the synthesized signal into an 8B / 10B code;
Transmitting the 8B / 10B code, and
In the multiplexing step, and wherein said 8B / 10B code of the transmission partner, Genlock control signal to be referred in controlling the 8B / 10B code phase is further to be multiplexed into the combined signal Video signal processing method. To a computer for a video signal processing device that serially transmits video signals, audio signals, and data signals,
From the video channel in which the video signal, the audio signal, and the data signal are allocated to predetermined bits in a time slot that is an integer multiple of 8 bits, and the data channel in which the audio signal and the data signal are allocated to the surplus bits A multiplexing step for multiplexing into a composed composite signal;
8B / in the time slot output by the processing of the multiplexing step, and in one or more specific time slots in the blanking period of the video signal in which the data channel is no signal. An encoding step of allocating a synchronization code of 10B code and converting the synthesized signal into an 8B / 10B code;
A process including a transmission step of transmitting the 8B / 10B code,
In the multiplexing step, and wherein said 8B / 10B code of the transmission partner, Genlock control signal to be referred in controlling the 8B / 10B code phase is further to be multiplexed into the combined signal Program to do.

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