JP4136844B2 - Electronic component mounting method - Google Patents

Electronic component mounting method Download PDF

Info

Publication number
JP4136844B2
JP4136844B2 JP2003298056A JP2003298056A JP4136844B2 JP 4136844 B2 JP4136844 B2 JP 4136844B2 JP 2003298056 A JP2003298056 A JP 2003298056A JP 2003298056 A JP2003298056 A JP 2003298056A JP 4136844 B2 JP4136844 B2 JP 4136844B2
Authority
JP
Japan
Prior art keywords
electrode
melting point
electronic component
alloy
point metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003298056A
Other languages
Japanese (ja)
Other versions
JP2004111935A (en
Inventor
公三 藤本
和尚 池見
裕彦 渡邉
慶一 松村
将義 下田
克己 谷口
友彰 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Holdings Ltd filed Critical Fuji Electric Holdings Ltd
Priority to JP2003298056A priority Critical patent/JP4136844B2/en
Publication of JP2004111935A publication Critical patent/JP2004111935A/en
Application granted granted Critical
Publication of JP4136844B2 publication Critical patent/JP4136844B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H01L2224/81825—Solid-liquid interdiffusion

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

本発明は、例えば、小型化が必要とされる回路基板あるいはモジュール（マルチチップモジュール）等において、半導体チップ等の電子部品をプリント基板等の回路基板に直接実装する方法に関する。   The present invention relates to a method for directly mounting an electronic component such as a semiconductor chip on a circuit board such as a printed circuit board, for example, in a circuit board or module (multichip module) or the like that needs to be miniaturized.

近年の電子機器等の小型化や高機能化に伴い、回路基板上へ、半導体チップ等の電子部品を直接実装する、いわゆるベアチップ実装と呼ばれる実装方法が広く行なわれている。   With recent downsizing and higher functionality of electronic devices and the like, a so-called bare chip mounting method for mounting electronic components such as semiconductor chips directly on a circuit board is widely performed.

図３（ａ）、（ｂ）には、従来から行なわれているベアチップ実装の一例が示されている。   FIGS. 3A and 3B show an example of conventional bare chip mounting.

図３（ａ）においては、基板５０上に設けられた回路基板電極５１と、半導体チップ６０上に電極パッド６２を介して設けられた、Ａｕ、又は、はんだからなるバンプ（電極）６１とを対向させて接触させた後、はんだ７０によって回路基板電極５１とバンプ６１との接合が行なわれ、更に、絶縁のために、はんだ７０の周囲が樹脂８０で覆われている。   In FIG. 3A, a circuit board electrode 51 provided on the substrate 50 and a bump (electrode) 61 made of Au or solder provided on the semiconductor chip 60 via an electrode pad 62 are shown. After facing each other, the circuit board electrode 51 and the bump 61 are joined by the solder 70, and the periphery of the solder 70 is covered with a resin 80 for insulation.

また、図３（ｂ）においては、同じく基板５０上に設けられた回路基板電極５１と、半導体チップ６０上に電極パッド６２を介して設けられた、Au又ははんだからなるバンプ６１とを対向させ、両者を、導電性粒子９１を含有した樹脂である、異方導電性接着剤（ＡＣＦ）９０で覆うことにより、回路基板電極５１とバンプ６１とを接合し、両者の導通が導電性粒子９１によって行なわれるように構成されている。   In FIG. 3B, a circuit board electrode 51 similarly provided on the substrate 50 and a bump 61 made of Au or solder provided on the semiconductor chip 60 via an electrode pad 62 are opposed to each other. By covering both with an anisotropic conductive adhesive (ACF) 90, which is a resin containing conductive particles 91, the circuit board electrodes 51 and the bumps 61 are joined, and the conduction between the two is determined by the conductive particles 91. It is comprised so that it may be performed by.

上記のような、回路基板電極と、半導体チップ等の電子部品とをバンプで直接接続する方法はフリップチップ技術と呼ばれ、回路基板電極と電子部品とをワイヤで結線するワイヤボンド方式に比べて小型化が可能であることから、従来から広く用いられている実装方法である。   The method of directly connecting a circuit board electrode and an electronic component such as a semiconductor chip as described above is called a flip-chip technique, compared to a wire bonding method in which the circuit board electrode and the electronic component are connected by a wire. Since it can be downsized, it is a mounting method that has been widely used.

また、上記フリップチップ技術に用いられるバンプとして、蒸着法によって合金のはんだバンプを形成することも知られており、例えば、多層膜形成による鉛フリーはんだバンプの形成法として、Ｓｎ1-xＭx（Ｍ：Ａｕ、Ｉｎのうち少なくとも一つ以上を含みかつ０＜ｘ＜０．５）なる組成になるように設定したＳｎおよびＭの膜厚を交互に蒸着して多層膜を形成し、その後マスクを除去して前記多層膜からなる、はんだバンプ前駆体を形成し、つぎにアニールを行ってバンプ前駆体の組成の均一化を行い、更に、前駆体の共晶温度においてリフローさせてはんだバンプを形成することが開示されている（特許文献１参照）。 Further, as a bump to be used in the flip chip technology, it is also known to form solder bumps of alloy by vapor deposition, for example, as a method for forming the lead-free solder bumps according multilayer film formation, Sn 1-x M x (M: Sn and M film thicknesses set to be a composition including at least one of Au and In and 0 <x <0.5) are alternately deposited to form a multilayer film. The solder bump precursor consisting of the multilayer film is formed by removing the mask, and then annealing is performed to homogenize the composition of the bump precursor, and the solder bump is reflowed at the eutectic temperature of the precursor. Is disclosed (see Patent Document 1).

また、蒸着用るつぼ中に、予め所望の組成及び膜厚の合金膜が得られるように調整した組成及び量の母合金を用意し、この母合金を蒸発し切ることによって基板上に目的の合金膜を得ることができ、目的の組成の合金を蒸着するための母合金組成を予め求めおくことによって、任意の組成の合金の蒸着膜を得る合金蒸着方法が開示されている（特許文献２参照）。
特開２００２−４３３４８号公報 特開平５−９７１３号公報 Also, a mother alloy having a composition and amount adjusted in advance so as to obtain an alloy film having a desired composition and film thickness is prepared in a crucible for vapor deposition, and the target alloy is formed on the substrate by completely evaporating the mother alloy. An alloy vapor deposition method is disclosed in which a film can be obtained, and a master alloy composition for vapor deposition of an alloy having a desired composition is obtained in advance to obtain a vapor deposited film of an alloy having an arbitrary composition (see Patent Document 2). ).
JP 2002-43348 A JP-A-5-9713

上記のように、従来のフリップチップ実装技術においては、半導体チップ６０上のバンプ６１と、回路基板上の電極５１との接合手段は、はんだや樹脂接着剤等を介して行われている。   As described above, in the conventional flip chip mounting technique, the bonding means between the bumps 61 on the semiconductor chip 60 and the electrodes 51 on the circuit board is performed via solder, resin adhesive, or the like.

この場合、接合時の加熱温度は、はんだを用いた場合には、はんだ材料の融点に依存するので、通常のはんだでは２００〜３００℃の高温が必要とされ、電子部品への熱的ダメージが生じ易いという問題がある。また、樹脂接着剤の場合においては、加熱温度は１５０〜２００℃と低温であるが、樹脂の硬化に３０〜６０分の長時間を要するという問題があった。   In this case, since the heating temperature at the time of joining depends on the melting point of the solder material when solder is used, a normal solder requires a high temperature of 200 to 300 ° C., and thermal damage to electronic components is caused. There is a problem that it is likely to occur. In the case of a resin adhesive, the heating temperature is as low as 150 to 200 ° C., but there is a problem that it takes a long time of 30 to 60 minutes to cure the resin.

また、強度や疲労寿命等に代表される接合部の信頼性は、介在する接合材料の特性に依存することになる。しかしながら、上記のはんだや樹脂接着剤を接合材とした場合には、高温特性や熱疲労寿命に問題があり、充分な接合部の信頼性が得られないという問題があった。   Further, the reliability of the joint represented by strength and fatigue life depends on the characteristics of the intervening joining material. However, when the above solder or resin adhesive is used as a bonding material, there is a problem in high temperature characteristics and thermal fatigue life, and there is a problem that sufficient reliability of the bonded portion cannot be obtained.

更に、はんだ接合においては、通常厚さで１５μｍ以上の、多量のはんだを供給する必要があるため、３００μｍ以上の接合間隔が必要であり、微細接合が困難である。また、樹脂接着剤による接合においても、絶縁特性や接続抵抗を満足するためには、通常１００μｍ以上の接合間隔が必要とされることから、やはり、１００μｍ未満の接合間隔での微細接合が困難であった。   Furthermore, in solder joining, since it is necessary to supply a large amount of solder having a thickness of usually 15 μm or more, a joining interval of 300 μm or more is necessary, and fine joining is difficult. Also, in joining with a resin adhesive, in order to satisfy the insulating characteristics and connection resistance, a joining interval of 100 μm or more is usually required, so fine joining with a joining interval of less than 100 μm is also difficult. there were.

また、特開２００２−４３３４８号公報の鉛フリーはんだバンプの形成法においては、低温、短時間での接合が不充分であり、例えば、２００℃以下の低温で、かつ、短時間での接合が困難であった。   In addition, in the method for forming lead-free solder bumps disclosed in Japanese Patent Application Laid-Open No. 2002-43348, bonding at a low temperature and in a short time is insufficient. For example, bonding at a low temperature of 200 ° C. or less and in a short time is possible. It was difficult.

また、特開平５−９７１３号公報の合金蒸着方法においては、あらかじめ、るつぼ中の母合金の組成と、蒸着膜における合金組成との関係を求め、その補正曲線から母合金組成を決定する必要があるため、蒸着に至るまでの準備工程が煩雑であるという問題があった。   Further, in the alloy vapor deposition method disclosed in Japanese Patent Laid-Open No. 5-9713, it is necessary to obtain the relationship between the composition of the mother alloy in the crucible and the alloy composition in the deposited film in advance and determine the mother alloy composition from the correction curve. Therefore, there is a problem that the preparation process up to the vapor deposition is complicated.

本発明は、以上の問題点を鑑みなされたもので、半導体チップなどの電子部品の電極と回路基板電極とを対向させて、電子部品を基板上に直接実装する方法において、低温かつ短時間の接合を可能とし、また、より信頼性の高い接合部を得ることができ、更に、微細なピッチでの接合が可能な、電子部品の実装方法を提供することを目的とする。   The present invention has been made in view of the above problems. In a method of mounting an electronic component directly on a substrate by facing an electrode of an electronic component such as a semiconductor chip and a circuit board electrode, the method is performed at a low temperature for a short time. It is an object of the present invention to provide a method for mounting an electronic component that can be bonded, can obtain a more reliable bonded portion, and can be bonded at a fine pitch.

上記目的を達成するため、本発明の電子部品の実装方法は、回路基板上に形成された金属からなる回路電極と、電子部品上に形成された金属からなる素子電極とを接合して、前記電子部品を前記回路基板上に実装する方法において、前記回路電極及び／又は前記素子電極上に、融点が２２０℃以下の２元以上の合金を形成できる、少なくとも２種類以上の金属を２層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることにより、低融点金属層をあらかじめ形成した後、前記回路電極及び前記素子電極を対向させて、少なくとも低融点金属層が溶融する温度で加熱加圧し、前記低融点金属層を、前記回路電極及び前記素子電極中へ固液拡散させることによって、前記回路電極と前記素子電極とを接合することを特徴とする。 In order to achieve the above object, a method for mounting an electronic component according to the present invention comprises joining a circuit electrode made of metal formed on a circuit board and an element electrode made of metal formed on the electronic component, In the method of mounting an electronic component on the circuit board , at least two or more kinds of metals capable of forming a binary or higher alloy having a melting point of 220 ° C. or lower on the circuit electrode and / or the element electrode. After the low-melting metal layer is formed in advance by preheating and reacting the laminated metal layer to form an alloy layer, the circuit electrode and the element electrode are opposed to each other, and at least the low-melting metal heated and pressurized at a temperature at which the layer is melted, the low melting point metal layer, by diffusing the circuit electrode and the solid-liquid to the element electrode in, to and characterized by bonding the element electrode and the circuit electrode .

本発明の方法によれば、電極上に低融点金属層を形成したので、低温、かつ、短時間での接合が可能となる。また、低融点金属層は少なくとも拡散するのに充分な量であればよく、例えば合計厚さ１０μｍあるいはそれ以下の薄膜とすることができるので、メッキや蒸着による微細なパターン形成が容易であり、微細間隔での接合が可能となって、よりコンパクトな実装が可能となる。そして、低融点金属層は、融点が２２０℃以下の２元以上の合金を形成できる、少なくとも２種類以上の金属を２層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることで、合金層における合金組成や供給量のバラツキがなくなり、低温での安定した拡散接合が可能となり、信頼性の高い接合部を得ることができる。更に、低融点金属層の固液拡散による接合方式を採用して、高温特性や熱疲労寿命特性に問題のある、はんだや樹脂接着剤などの接合材を不要としたことにより、接合部の信頼性が向上する。 According to the method of the present invention, since the formation of the low melting point metal layer on the electrode, a low temperature, and it is possible to joint within a short time. In addition, the low melting point metal layer only needs to be an amount sufficient to diffuse at least, for example, it can be a thin film having a total thickness of 10 μm or less, so that it is easy to form a fine pattern by plating or vapor deposition, Joining at fine intervals is possible, and more compact mounting is possible. Then, the low-melting-point metal layer has a melting point to form a 220 ° C. or less of binary or more alloys, and laminating at least two or more metals in two or more layers, is reacted with preheated metal layer the laminated By using the alloy layer, variations in alloy composition and supply amount in the alloy layer are eliminated, stable diffusion bonding at low temperatures is possible, and a highly reliable joint can be obtained. In addition, by adopting a bonding method by solid-liquid diffusion of the low melting point metal layer, it eliminates the need for bonding materials such as solder and resin adhesives that have problems with high temperature characteristics and thermal fatigue life characteristics, thereby making it possible to trust the joints. Improves.

本発明においては、前記低融点金属層が、ＳｎＩｎ又はＳｎＢｉであることが好ましい。これによれば、上記の金属は、いずれも融点が１８０℃以下の低融点であるので、本発明に特に好適に使用可能である。 In the present invention, the low-melting-point metal layer is preferably a SnIn or SnBi. According to this, since all of the above metals have a low melting point of 180 ° C. or less, they can be used particularly preferably in the present invention.

また、本発明においては、前記接合時の加熱温度が、前記低融点金属層の融点より０〜１００℃高い温度であることが好ましい。上記の低融点金属層は、いずれも融点が１８０℃以下の材料であるから、加熱温度もより低温とすることができるので、実装する電子部品への熱によるダメージを防止することができる。 Moreover, in this invention, it is preferable that the heating temperature at the time of the said joining is 0-100 degreeC temperature higher than melting | fusing point of the said low melting metal layer . Since all of the low melting point metal layers are materials having a melting point of 180 ° C. or lower, the heating temperature can be lowered, so that damage to electronic components to be mounted can be prevented.

更に、本発明においては、前記回路電極及び前記素子電極の材質が、Ｃｕ、Ｎｉ、Ａｕより選択される一種又はそれらの合金であることが好ましい。これによれば、Ｃｕ、Ｎｉ、Ａｕより選択される一種又はそれらの合金は、低融点金属が固液拡散しやすいので、本発明に特に好適に用いられる。   Furthermore, in the present invention, the material of the circuit electrode and the element electrode is preferably one kind selected from Cu, Ni, and Au or an alloy thereof. According to this, one kind or an alloy thereof selected from Cu, Ni, and Au is particularly preferably used in the present invention because the low-melting-point metal easily diffuses into solid and liquid.

また、本発明においては、前記回路電極及び前記素子電極表面の表面粗さＲａが０．４〜１０μｍの粗面であって、前記接合時に前記粗面同士が塑性変形して接合可能となるように加圧することが好ましい。これによれば、電極表面が塑性変形するまで加圧するので、例えば、電解メッキ等によって形成される電極のように、表面に析出による凹凸がある場合においても、良好な接合状態を得ることができる。   Further, in the present invention, the surface roughness Ra of the surface of the circuit electrode and the element electrode is a rough surface of 0.4 to 10 μm, and the rough surfaces are plastically deformed at the time of the joining so that the joining is possible. It is preferable to pressurize. According to this, since pressure is applied until the electrode surface is plastically deformed, a good bonding state can be obtained even when the surface has irregularities due to precipitation, such as an electrode formed by electrolytic plating or the like. .

更に、本発明においては、前記回路電極及び前記素子電極の材質が、Ｃｕ、Ｎｉ、Ａｕ、及びそれらの合金より選択される一種の同じ金属からなり、前記加熱加圧は、前記低融点金属層が、前記回路電極及び前記素子電極中に完全に固液拡散して、前記回路電極、前記素子電極及び前記低融点金属層が全体として単一の合金層となるまで行なうことが好ましい。これによれば、低融点金属層が完全に固液拡散して、全体として単一の合金層となり、はんだのように、合金層が接合部に中間層として存在しない。したがって、接合部の信頼性は、介在する接合材料の特性に依存せず、主に電極の母材金属によるので、更に接続部の信頼性を向上することができる。 Furthermore, in the present invention, the circuit electrode and the element electrode are made of the same metal selected from Cu, Ni, Au, and alloys thereof, and the heating and pressing is performed on the low melting point metal layer. However, it is preferable that the solid-liquid diffusion is performed completely in the circuit electrode and the element electrode until the circuit electrode, the element electrode, and the low melting point metal layer become a single alloy layer as a whole. According to this, the low melting point metal layer is completely solid-liquid diffused to become a single alloy layer as a whole, and the alloy layer does not exist as an intermediate layer at the joint portion like solder. Therefore, the reliability of the joint does not depend on the characteristics of the intervening joint material, and mainly depends on the base metal of the electrode, so that the reliability of the joint can be further improved.

また、本発明においては、前記加熱加圧において、前記低融点金属層が、前記回路電極と前記素子電極との間に、中間合金層を形成するまで所定時間維持することが好ましい。これによれば、低融点金属層が、完全には拡散せず、中間合金層を形成する段階まで加熱すれば足りるので、接合に要する時間を大幅に短縮することができる。また、低融点金属の供給量は、中間合金層を形成するための必要量以上が供給されておればよいので、低融点金属の供給量の厳密な管理が不要となる。   In the present invention, it is preferable that the low-melting-point metal layer is maintained for a predetermined time until an intermediate alloy layer is formed between the circuit electrode and the element electrode in the heating and pressing. According to this, since the low melting point metal layer is not completely diffused and it is sufficient to heat to the stage of forming the intermediate alloy layer, the time required for joining can be greatly shortened. In addition, since the supply amount of the low melting point metal has only to be supplied more than the amount necessary for forming the intermediate alloy layer, strict management of the supply amount of the low melting point metal becomes unnecessary.

本発明によれば、従来のはんだや接着剤を使用した接合方式に比べ、低温でかつ短時間での接合が可能となり、接合時の加熱による電子部品の損傷を抑制できるとともに、生産効率を向上できる。また、接合部の信頼性を向上させることができ、更に、微細なピッチでの接合が可能な、電子部品の実装方法を提供できる。   According to the present invention, it is possible to perform bonding at a low temperature and in a short time as compared with a conventional bonding method using solder or adhesive, and it is possible to suppress damage to electronic components due to heating during bonding and improve production efficiency. it can. Moreover, the reliability of a junction part can be improved and the mounting method of an electronic component which can be joined with a fine pitch can be provided.

以下、図面を用いて本発明について説明する。図１には、本発明の電子部品の実装方法の一実施形態が示されている。   Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the electronic component mounting method of the present invention.

図１は本発明の実装方法における電極同士の接合原理を示す工程図である。   FIG. 1 is a process diagram showing the principle of joining electrodes in the mounting method of the present invention.

まず、図１（ａ）に示すように、この実施形態においては、回路基板１０上に形成された金属からなる回路電極１１と、電子部品２０上に形成された金属からなる素子電極２１とが対向するように配置されており、回路電極１１及び素子電極２１上には、低融点金属層３１、３２がそれぞれ形成されている。   First, as shown in FIG. 1A, in this embodiment, a circuit electrode 11 made of metal formed on the circuit board 10 and an element electrode 21 made of metal formed on the electronic component 20 are provided. The low melting point metal layers 31 and 32 are formed on the circuit electrode 11 and the device electrode 21, respectively.

回路基板１０としては、例えば、従来公知のプリント基板等の配線板が使用でき、特に限定されない。また、回路基板１０上に形成された金属からなる回路電極１１は、導電性を有する金属であれば特に限定されないが、低融点金属層３１、３２と固液拡散を行ないやすい点から、Ｃｕ、Ｎｉ、Ａｕより選択される一種又はそれらの合金であることが好ましい。回路基板１０上に回路電極１１を形成する方法としては、従来公知の蒸着やエッチング等によるパターン形成が可能であり特に限定されない。   As the circuit board 10, for example, a conventionally known wiring board such as a printed board can be used, and is not particularly limited. Further, the circuit electrode 11 made of metal formed on the circuit board 10 is not particularly limited as long as it has conductivity, but Cu, Cu, One kind selected from Ni and Au or an alloy thereof is preferable. A method of forming the circuit electrode 11 on the circuit board 10 is not particularly limited, and a pattern formation by a conventionally known vapor deposition or etching is possible.

電子部品２０としては、例えば、半導体チップ等が挙げられるが、これらに限定されるものではない。また、電子部品２０上に形成される素子電極２１としては、上記の回路電極１１と同様に特に限定されないが、低融点金属層３１、３２と固液拡散を行ないやすい点から、やはり、Ｃｕ、Ｎｉ、Ａｕより選択される一種又はそれらの合金であることが好ましい。   Examples of the electronic component 20 include a semiconductor chip, but are not limited thereto. Further, the element electrode 21 formed on the electronic component 20 is not particularly limited as in the case of the circuit electrode 11 described above. However, since it is easy to perform solid-liquid diffusion with the low melting point metal layers 31 and 32, Cu, One kind selected from Ni and Au or an alloy thereof is preferable.

また、素子電極２１は、半導体チップ等の電極パッド上にバンプとして形成されていることが好ましい。これにより、回路基板電極と、半導体チップ等の電子部品とをバンプで直接接続するフリップチップ技術において、本発明の方法が特に好適に使用できる。   The element electrode 21 is preferably formed as a bump on an electrode pad such as a semiconductor chip. As a result, the method of the present invention can be used particularly suitably in flip chip technology in which circuit board electrodes and electronic components such as semiconductor chips are directly connected by bumps.

なお、回路電極１１、素子電極２１の表面粗さは平滑であるほうが接合状態が良好となるので好ましいが、本発明においては、表面粗さＲａが０．４〜１０μｍの粗面であってもよい。   In addition, although it is preferable that the surface roughness of the circuit electrode 11 and the element electrode 21 is smooth because the bonding state becomes better, in the present invention, even if the surface roughness Ra is a rough surface of 0.4 to 10 μm. Good.

次に、低融点金属層３１、３２について説明すると、回路電極１１及び素子電極２１上には、あらかじめ、合計厚さ１０μｍ以下の低融点金属層３１、３２がそれぞれ形成されている。   Next, the low melting point metal layers 31 and 32 will be described. On the circuit electrode 11 and the element electrode 21, low melting point metal layers 31 and 32 having a total thickness of 10 μm or less are formed in advance.

低融点金属層３１、３２に用いられる金属としては、回路電極１１及び素子電極２１と固液拡散によって合金を形成するような金属であればよく、更に、融点が２２０℃以下、より好ましくは１８０℃以下の金属であることが好ましい。これにより、従来用いられている、錫鉛共晶はんだ（融点１８３℃）や、代表的な鉛フリーはんだであるＳｎＡｇ系（融点２１０〜２２３℃）に比べて、低温での接合が可能となるので、電子部品への熱的ダメージを抑えることができる。   The metal used for the low-melting-point metal layers 31 and 32 may be any metal that forms an alloy with the circuit electrode 11 and the element electrode 21 by solid-liquid diffusion, and has a melting point of 220 ° C. or lower, more preferably 180. It is preferable that it is a metal below ℃. As a result, it is possible to perform bonding at a low temperature as compared with conventionally used tin-lead eutectic solder (melting point 183 ° C.) and SnAg-based (melting point 210 to 223 ° C.) which is a typical lead-free solder. Therefore, thermal damage to the electronic component can be suppressed.

このような低融点金属としては、例えば、ＳｎＩｎ、Ｉｎ、Ｂｉ、ＳｎＢｉより選択される一種を少なくとも含有する金属が挙げられる。これらの金属材料は、単独又は複数組み合わせて用いてもよく、また、合金の場合の組成比についても適宜設定可能である。   Examples of such a low melting point metal include a metal containing at least one selected from SnIn, In, Bi, and SnBi. These metal materials may be used alone or in combination, and the composition ratio in the case of an alloy can be appropriately set.

また、上記の金属材料をベース金属として、更に微量の添加元素が含有されていてもよい。このような添加元素としては、例えば、Ｃｕ、Ｎｉ、Ｇｅ、Ｓｂ、Ａｇ、Ｐ等が挙げられる。   Further, a trace amount of an additive element may be contained using the metal material as a base metal. Examples of such additive elements include Cu, Ni, Ge, Sb, Ag, and P.

また、低融点金属層３１、３２の厚さは、両者を合計して１０μｍ以下であり、好ましくは０．１〜１０μｍである。   The total thickness of the low melting point metal layers 31 and 32 is 10 μm or less, preferably 0.1 to 10 μm.

合計厚さが１０μｍを越えると、数分の接合時間では拡散しきれず、低融点金属の状態で電極間に残存しやすくなり、接合部の信頼性が低下するので好ましくない。また、０．１μｍ以下では、充分な固液拡散が起こらないため、電極の表面の酸化膜あるいは電極上に形成された低融点金属層の表面の酸化膜の除去ができず、また、均一な低融点金属層の形成が困難となり、結果として接合が不充分となるので好ましくない。   If the total thickness exceeds 10 μm, it cannot be diffused in a bonding time of several minutes, and it tends to remain between the electrodes in the state of a low melting point metal, which is not preferable because the reliability of the bonding portion is lowered. In addition, when the thickness is 0.1 μm or less, sufficient solid-liquid diffusion does not occur, and therefore, the oxide film on the surface of the electrode or the oxide film on the surface of the low melting point metal layer formed on the electrode cannot be removed. The formation of the low melting point metal layer becomes difficult, and as a result, the bonding becomes insufficient.

低融点金属層３１、３２の形成方法としては、上記の従来公知の薄膜形成法が利用でき特に限定されず、蒸着、スパッタリング、メッキ、エッチング等を適宜用いることができる。また、メタルマスクを用いた蒸着や、フォトレジストを用いたエッチッグ等により、必要に応じてパターン形成して設けることができる。ここで、上記のように、本発明においては接合材となる低融点金属の供給量が非常に少量でよく、低融点金属層３０の厚さを極めて薄くすることができるため、微細なパターニングが可能となる。   As a method for forming the low melting point metal layers 31 and 32, the above-described conventionally known thin film forming method can be used and is not particularly limited, and vapor deposition, sputtering, plating, etching, and the like can be appropriately used. Further, it can be provided by forming a pattern as needed by vapor deposition using a metal mask, etching using a photoresist, or the like. Here, as described above, in the present invention, the amount of the low-melting point metal used as the bonding material may be very small, and the thickness of the low-melting point metal layer 30 can be extremely reduced. It becomes possible.

なお、本発明においては、低融点金属層３１、３２のそれぞれの厚さは異なっていてもよい。また、低融点金属層３１又は３２は、どちらか一方のみが形成されていてもよい。   In the present invention, the thicknesses of the low melting point metal layers 31 and 32 may be different. Further, only one of the low melting point metal layers 31 or 32 may be formed.

上記の低融点金属層３１、３２の形成方法のうち、前記のＳｎＩｎやＳｎＢｉ等の２元以上の合金を形成できる、少なくとも２種類以上の金属を２層以上に積層し、この積層した金属層を予備加熱して反応させて合金層とすることにより形成する方法が好ましく用いられる。   Among the methods for forming the low melting point metal layers 31 and 32, at least two kinds of metals capable of forming a binary alloy such as SnIn and SnBi are laminated in two or more layers, and the laminated metal layers A method of forming the alloy layer by preheating and reacting is preferably used.

例えば、ＳｎＩｎの場合、Ｓｎの融点は２３２℃、Ｉｎの融点は１５７℃であるが、それより低い１２１℃で、ＳｎはＩｎに２６．４％固溶することが知られている。したがって、あらかじめＳｎ層とＩｎ層とを積層しておき、これを予備加熱によって反応させて、低融点金属層３１、３２としてＳｎＩｎ合金層を形成した後に、この合金層を、回路電極１１及び素子電極２１中へ固液拡散させることによって、回路電極１１と素子電極２１とを接合できる。   For example, in the case of SnIn, Sn has a melting point of 232 ° C. and In has a melting point of 157 ° C. It is known that Sn is dissolved in In at 26.4% at a lower temperature of 121 ° C. Therefore, after the Sn layer and the In layer are laminated in advance and reacted by preheating to form the SnIn alloy layer as the low melting point metal layers 31 and 32, the alloy layer is formed on the circuit electrode 11 and the element. The circuit electrode 11 and the element electrode 21 can be joined by solid-liquid diffusion into the electrode 21.

これにより、合金層における合金組成や供給量のバラツキがないので、低温での接合を確実に行なうことができ、信頼性の高い接合部を得ることができる。なお、上記のＳｎＩｎ合金の場合には、最表面がＩｎ層となるように積層することが好ましい。これにより、Ｓｎ層が酸化されるのを防止することができる。   Thereby, since there is no variation in the alloy composition and the supply amount in the alloy layer, it is possible to reliably perform the bonding at a low temperature and obtain a highly reliable bonded portion. In the case of the above SnIn alloy, it is preferable that the outermost surface is an In layer. Thereby, it is possible to prevent the Sn layer from being oxidized.

それぞれの単一金属層の膜厚は、目標とする合金組成に合わせて適宜選択されるが、短時間の予備加熱で合金層が形成される点から薄いほうが好ましく、具体的には、それぞれ０．１〜１μｍの範囲であることが好ましい。また、それぞれの単一金属層は１層づつ設けられていてもよく、複数の層が交互に設けられていてもよい。   The film thickness of each single metal layer is appropriately selected according to the target alloy composition, but it is preferably thinner from the point that the alloy layer is formed by short-time preheating. It is preferable that it is in the range of 1-1 μm. Each single metal layer may be provided one by one, or a plurality of layers may be provided alternately.

その他の低融点金属層３１、３２の形成方法としては、低融点金属がＳｎＩｎやＳｎＢｉ等の２元以上の合金である場合には、合金を蒸発源として蒸着することにより形成し、前記蒸着時に、前記合金の各金属成分の蒸気圧比を制御することによって、目標とする合金組成となるように成膜する方法も好ましく用いられる。   As another method of forming the low melting point metal layers 31 and 32, when the low melting point metal is a binary or more alloy such as SnIn or SnBi, the low melting point metal layers 31 and 32 are formed by vapor deposition using the alloy as an evaporation source. A method of forming a film so as to obtain a target alloy composition by controlling the vapor pressure ratio of each metal component of the alloy is also preferably used.

上記のように、接合時の温度は、低融点金属層３１、３２の融点に依存する。例えばＳｎＩｎ合金においては、共晶温度は１１７℃であり、そのときの共晶組成は、Ｉｎ：Ｓｎ＝５２：４８である。したがって、この共晶組成以外では低融点金属層３１、３２の融点が上昇してしまうので、低温接合を安定的に可能にするには、低融点金属層３１、３２の合金組成をＩｎ：Ｓｎ＝５２：４８に維持することが必要である。   As described above, the bonding temperature depends on the melting points of the low melting point metal layers 31 and 32. For example, in a SnIn alloy, the eutectic temperature is 117 ° C., and the eutectic composition at that time is In: Sn = 52: 48. Accordingly, since the melting point of the low melting point metal layers 31 and 32 is increased except for this eutectic composition, the alloy composition of the low melting point metal layers 31 and 32 is changed to In: Sn in order to enable low temperature bonding stably. It is necessary to maintain = 52: 48.

しかし、通常、母合金を単一の蒸発源とする蒸着法によって合金薄膜層を形成する場合、それぞれの金属成分によって蒸気圧が異なるため、あらかじめＩｎ：Ｓｎ＝５２：４８の母合金を蒸発源としても、ＩｎとＳｎの蒸気圧が同じでないために、形成される蒸着膜の組成は目標からずれてしまう。したがって、蒸着時に、合金の各金属成分の蒸気圧比を制御することによって、目標とする合金組成を維持しながら成膜できる。   However, usually, when the alloy thin film layer is formed by the vapor deposition method using the master alloy as a single evaporation source, the vapor pressure varies depending on the respective metal components. Therefore, the mother alloy of In: Sn = 52: 48 is used in advance as the evaporation source. However, since the vapor pressures of In and Sn are not the same, the composition of the deposited film formed deviates from the target. Therefore, it is possible to form a film while maintaining the target alloy composition by controlling the vapor pressure ratio of each metal component of the alloy during vapor deposition.

特に、あらかじめ蒸発源の合金組成と、蒸着後の合金層の合金組成とが等しくなるような各金属成分の蒸気圧比を求めておき、この蒸気圧比を蒸着中に制御すれば、低融点金属層として、蒸発源の母合金と同じ組成の蒸着膜を得ることができ、上記の目標からのずれを解消できる。このような制御条件である各金属成分の蒸気圧比は、例えば、以下の計算にしたがって求めることができる。   In particular, if the vapor pressure ratio of each metal component is determined in advance so that the alloy composition of the evaporation source and the alloy composition of the alloy layer after vapor deposition are equal, and the vapor pressure ratio is controlled during vapor deposition, the low melting point metal layer As described above, a deposited film having the same composition as the mother alloy of the evaporation source can be obtained, and deviation from the above target can be eliminated. The vapor pressure ratio of each metal component, which is such a control condition, can be obtained, for example, according to the following calculation.

まず、合金蒸気の主成分は、合金に含まれている金属の原子であるから、各成分の分圧を、以下の（１）式のような、希薄溶液の溶媒の蒸気圧に関するＲａｏｕｌｔの法則を拡張適用することにより見積もることができる。   First, since the main component of the alloy vapor is the atoms of the metal contained in the alloy, the partial pressure of each component is determined by Raoult's law regarding the vapor pressure of the solvent of the dilute solution as shown in the following equation (1). Can be estimated by applying

Figure 0004136844
Figure 0004136844

上記の（１）式がそのまま成立する場合は稀であるので、実測のａiがＲａｏｕｌｔの法則からどの程度ずれているかを表すために、以下の（２）式で定義される活量係数γiを用いる。 Since it is rare that the above equation (1) holds as it is, the activity coefficient γ defined by the following equation (2) is used to express how much the actually measured a i deviates from Raoul's law. Use i .

Figure 0004136844
合金のｉ成分に対する部分モル自由エネルギー変化ΔＧiは、以下の（３）式で与えられるので、（２）式を用いて、（４）式のように変形できる。
Figure 0004136844
 Since the partial molar free energy change ΔG i with respect to the i component of the alloy is given by the following equation (3), it can be transformed into equation (4) using equation (2).

Figure 0004136844
Figure 0004136844

Figure 0004136844
ここで、Ｒは気体定数、Ｔは絶対温度である。また、組成Ｘにおける自由エネルギーΔＧiは、以下の（５）式で表すことができる。
Figure 0004136844
 Here, R is a gas constant, and T is an absolute temperature. The free energy ΔG i in the composition X can be expressed by the following equation (5).

Figure 0004136844
ここで、例えば、ＳｎＩｎの共晶合金の場合、上記のように、Ｉｎの組成はＸ＝５２、Ｓｎの組成はＸ＝４８である。
Figure 0004136844
 Here, for example, in the case of a SnIn eutectic alloy, the composition of In is X = 52 and the composition of Sn is X = 48 as described above.

ここで、ＩｎとＣｕとの反応性を考慮して（５）式の各係数にＡij＝−１２９９０、Ｂij＝−１４３８３、Ｃij＝２３９８２、Ｘ＝０．５２を代入すると、 Here, A ij = -12990 to each coefficient in consideration of the reactivity of In and Cu (5) formula, B ij = -14383, Substituting C ij = 23982, X = 0.52 ,

Figure 0004136844
が得られる。同様に、ＳｎとＣｕとの反応性を考慮して、（５）式の各係数にＡij＝−３５４７９、Ｂij＝−１９１８２、Ｃij＝５９４９３、Ｘ＝０．４８を代入すると、
Figure 0004136844
 Is obtained. Similarly, in consideration of the reactivity between Sn and Cu, substituting A ij = −35479, B ij = −19182, C ij = 59493, and X = 0.48 into the coefficients of the equation (5),

Figure 0004136844
が得られる。（３）式と（６）式より、Ｉｎ-Ｃｕ反応における活量ａAを求め、（３）式と（７）式より、Ｓｎ-Ｃｕ反応における活量ａBを求めると、以下の（８）（９）式となる。ただし、Ｒ＝８．３１４[Ｊ・ｍｏｌ-1・Ｋ-1]、Ｔ＝７００Ｋ（４２７℃）である。
Figure 0004136844
 Is obtained. The activity a A in the In—Cu reaction is obtained from the equations (3) and (6), and the activity a B in the Sn—Cu reaction is obtained from the equations (3) and (7). 8) Equation (9) is obtained. However, R = 8.314 [J · mol -1 · K -1], a T = 700K (427 ℃).

Figure 0004136844
Figure 0004136844

Figure 0004136844
次に、真空蒸着における各成分の線束を考えると、２元合金が蒸発しているとき、ある瞬間における表面組成をχA、χBとすれば、蒸発線束比ＪA／ＪBは、以下の（１０）、（１１）式で表される。
Figure 0004136844
 Next, considering the flux of each component in vacuum deposition, when the binary composition is evaporated, if the surface composition at a certain moment is χ A , χ B , the evaporation flux ratio J A / J B is (10) and (11).

Figure 0004136844
Figure 0004136844

Figure 0004136844
この（１０）、（１１）式のＺの値が１となるときが、蒸発成分比が元の合金の組成（Ｉｎの組成：χA＝５２、Ｓｎの組成：χB＝４８）に等しくなる条件である。よって、（１０）式において、Ｉｎの分子量ＭA＝１１４．８１８、Ｓｎの分子量ＭB＝１１８．７１０、ａA＝０．８３５、ａB＝０．６３２、Ｚ＝１を代入して、
Figure 0004136844
 When the value of Z in the equations (10) and (11) is 1, the evaporation component ratio is equal to the original alloy composition (In composition: χ A = 52, Sn composition: χ B = 48). It is a condition. Therefore, in the formula (10), the molecular weight M A of In = 114.818, the molecular weight of Sn M B = 118.710, a A = 0.835, a B = 0.632, Z = 1 is substituted,

Figure 0004136844
が得られる。したがって、この（１２）式を満たす蒸気圧となるような条件下で蒸着することで、Ｉｎ：Ｓｎ＝５２：４８となるような、Ｃｕ上へのＳｎＩｎ共晶合金の成膜が可能となる。
Figure 0004136844
 Is obtained. Therefore, it is possible to form a SnIn eutectic alloy on Cu so that In: Sn = 52: 48 is deposited by vapor deposition under a vapor pressure that satisfies this equation (12). .

なお、上記の蒸気圧比（ｐA／ｐB）は、実際の蒸着時に、蒸発源の温度、蒸着中の真空度を制御することによって制御可能である。このうち、蒸発源である母合金の温度は、電子ビーム蒸着装置の場合、加熱用電子ビームのエネルギーの調整により制御することができる。電子ビームエネルギーの調整により溶融状態の母合金の温度が変化すると、各金属成分の蒸発源からの蒸発速度および活量がそれぞれ変化するが、温度変化に対応する蒸発速度および活量の相対変化率が各金属成分毎に異なることにより、蒸気圧比が変化する。 The vapor pressure ratio (p A / p B ) can be controlled by controlling the temperature of the evaporation source and the degree of vacuum during vapor deposition during actual vapor deposition. Among these, in the case of an electron beam vapor deposition apparatus, the temperature of the mother alloy as an evaporation source can be controlled by adjusting the energy of the heating electron beam. When the temperature of the molten master alloy changes by adjusting the electron beam energy, the evaporation rate and activity from the evaporation source of each metal component change, respectively, but the relative rate of change of the evaporation rate and activity corresponding to the temperature change Is different for each metal component, the vapor pressure ratio changes.

次に、蒸着中の真空度は、蒸着槽内を真空ポンプで真空引きしながら、調整する。真空度の調整により、各金属成分の蒸気圧の和が変化すると、各金属成分のモル分率が変化し、活量が変化するが、真空度の変化に対応する活量の相対変化率が各金属成分毎に異なることにより、蒸気圧比が変化する。   Next, the degree of vacuum during vapor deposition is adjusted while evacuating the vapor deposition tank with a vacuum pump. When the sum of the vapor pressures of each metal component changes due to the adjustment of the degree of vacuum, the molar fraction of each metal component changes and the activity changes, but the relative change rate of the activity corresponding to the change in the degree of vacuum is The vapor pressure ratio changes by being different for each metal component.

蒸発源の温度および蒸着中の真空度のいずれか一方を制御してもよく、両方の制御を組み合わせてもよい。   Either the temperature of the evaporation source or the degree of vacuum during vapor deposition may be controlled, or both controls may be combined.

また、Ｉｎ−Ｃｕ反応およびＳｎ−Ｃｕ反応における活量ａA、ａBを求める際に（５）式に代入した係数Ａij、Ｂij、Ｃijの値は、所定の基準温度条件について得られている物性値であるので、蒸着対象であるＣｕ電極の温度が前記基準温度になるように、蒸着対象に対するヒータ加熱温度を調整する。 Further, the values of the coefficients A ij , B ij , and C ij substituted into the equation (5) when obtaining the activities a A and a B in the In—Cu reaction and the Sn—Cu reaction are obtained for a predetermined reference temperature condition. Therefore, the heater heating temperature for the deposition target is adjusted so that the temperature of the Cu electrode that is the deposition target becomes the reference temperature.

なお、本発明においては、上記の蒸着時の各金属成分の反応過程における蒸気圧比の代わりに、各金属成分の反応過程における蒸気圧比及び活量係数比の積を制御してもよい。   In the present invention, the product of the vapor pressure ratio and the activity coefficient ratio in the reaction process of each metal component may be controlled instead of the vapor pressure ratio in the reaction process of each metal component at the time of vapor deposition.

この場合、例えば、ＳｎＩｎ共晶合金における、ＩｎおよびＳｎの各組成をＷA、ＷB（重量％）で示すと、以下の（１３）、（１４）式となる。 In this case, for example, in SnIn eutectic alloy, the respective compositions of In and Sn W A, if indicated by W B (% by weight), the following (13) and (14).

Figure 0004136844
Figure 0004136844

Figure 0004136844
したがって、上記の（１３）、（１４）式を、（１０）、（１１）式に代入して、蒸発線束重量比ΓA／ΓBは、以下の（１５）式で表される。
Figure 0004136844
 Therefore, by substituting the above equations (13) and (14) into the equations (10) and (11), the evaporative flux weight ratio Γ A / Γ B is expressed by the following equation (15).

Figure 0004136844
（１３）、（１４）式において、Ｉｎの分子量ＭA＝１１４．８１８、Ｓｎの分子量ＭB＝１１８．７１０、Ｉｎの重量％ＷA＝０．５２、Ｓｎの重量％ＷB＝０．４８を代入すると、χA＝０．５２８、χB＝０．４７２を得る。
Figure 0004136844
 (13) and (14), the molecular weight of In M A = 114.818, the molecular weight of Sn M B = 118.710, wt% W of an In A = 0.52, wt% W B = 0 of Sn. Substituting 48, we obtain χ A = 0.528 and χ B = 0.472.

したがって、（１５）式の左辺（ΓA／ΓB）が０．５２／０．４８となるような（γAｐA／γBｐB）の比を計算すると、 Therefore, when calculating the ratio of (15) as the left side (gamma A / gamma B) is 0.52 / 0.48 (γ A p A / γ B p B),

Figure 0004136844
が得られる。したがって、この（１６）式を満たす活量係数及び蒸気圧となるような条件下で蒸着することで、Ｉｎ：Ｓｎ＝５２：４８となるような、Ｃｕ上へのＳｎＩｎ共晶合金の成膜が可能となる。
Figure 0004136844
 Is obtained. Therefore, deposition of a SnIn eutectic alloy on Cu so that In: Sn = 52: 48 is achieved by vapor deposition under conditions such that the activity coefficient and the vapor pressure satisfy the equation (16). Is possible.

なお、上記の蒸気圧比及び活量係数比の積(γAｐA／γBｐB)は、実際の蒸着時に、蒸発源の温度、蒸着中の真空度および蒸着対象の温度を制御することによって制御可能である。 The product of the above vapor pressure ratio and activity coefficient ratio (γ A p A / γ B p B ) controls the temperature of the evaporation source, the degree of vacuum during vapor deposition, and the temperature of the vapor deposition target during actual vapor deposition. It is controllable by.

このうち、蒸発源である母合金の温度は、電子ビーム蒸着装置の場合、加熱用電子ビームのエネルギーの調整により制御することができる。電子ビームエネルギーの調整により溶融状態の母合金の温度が変化すると、各金属成分の蒸発源からの蒸発速度および活量がそれぞれ変化するが、温度変化に対応する蒸発速度および活量の相対変化率が各金属成分毎に異なることにより、蒸気圧比が変化する。   Among these, in the case of an electron beam vapor deposition apparatus, the temperature of the mother alloy as an evaporation source can be controlled by adjusting the energy of the heating electron beam. When the temperature of the molten master alloy changes by adjusting the electron beam energy, the evaporation rate and activity from the evaporation source of each metal component change, respectively, but the relative rate of change of the evaporation rate and activity corresponding to the temperature change Is different for each metal component, the vapor pressure ratio changes.

次に、蒸着中の真空度は、蒸着槽内を真空ポンプで真空引きしながち、調整する。真空度の調整により、各金属成分の蒸気圧の和が変化すると、各金属成分のモル分率が変化し、活量が変化するが、真空度の変化に対応する活量の相対変化率が各金属成分毎に異なることにより、蒸気圧比が変化する。   Next, the degree of vacuum during vapor deposition is adjusted by evacuating the vapor deposition tank with a vacuum pump. When the sum of the vapor pressures of each metal component changes due to the adjustment of the degree of vacuum, the molar fraction of each metal component changes and the activity changes, but the relative change rate of the activity corresponding to the change in the degree of vacuum is The vapor pressure ratio changes by being different for each metal component.

次に、蒸気対象であるＣｕ電極の温度は加熱用ヒータへの供給電力により調整することができる。ヒータへの供給電力の調整により蒸着対象のＣｕ電極の温度が変化すると、各金属成分Ｉｎ、Ｓｎと母材金属Ｃｕとの反応における活量が変化するが、温度変化に対応する活量の相対変化率が各金属成分毎に異なることにより、活量係数比が変化する。   Next, the temperature of the Cu electrode that is the target of vapor can be adjusted by the power supplied to the heater. When the temperature of the Cu electrode to be deposited is changed by adjusting the power supplied to the heater, the activity in the reaction between each of the metal components In and Sn and the base metal Cu changes, but the activity corresponding to the temperature change is relative. When the rate of change differs for each metal component, the activity coefficient ratio changes.

蒸発源の温度，蒸着中の真空度および蒸着対象の温度の各制御項目のいずれか一つの制御項目を制御してもよく、複数の制御項目を組み合わせてもよい。   Any one of the control items of the temperature of the evaporation source, the degree of vacuum during vapor deposition, and the temperature of the vapor deposition target may be controlled, or a plurality of control items may be combined.

なお、条件出しの蒸着プロセスにより目標の膜組成比に対応した制御パラメータ値を求めていく場合、第1回目のプロセスで設定する暫定的な制御パラメータ値を求めるのには、各金属成分の蒸気圧比を制御する方式がより適合しており、その後の第２回目以降のプロセスで設定する制御パラメータの見直し値を求めるのには、各金属成分の蒸気圧比及び活量係数比の積を制御する方式がより適合しているので、条件出しの段階では、両者の方式を組合わせるとより効率的である。   In addition, when obtaining the control parameter value corresponding to the target film composition ratio by the vapor deposition process for which the conditions are set, in order to obtain the temporary control parameter value set in the first process, the vapor of each metal component is obtained. The method of controlling the pressure ratio is more suitable, and the product of the vapor pressure ratio and the activity coefficient ratio of each metal component is controlled in order to obtain a revised value of the control parameter set in the subsequent processes after the second time. Since the methods are more compatible, it is more efficient to combine both methods at the condition determination stage.

また、以上では、低融点金属層として蒸発源の母合金と同じ組成の蒸着膜を得ることができるようにするための方法を述べたが、本発明における低融点金属層の形成方法は、上述のような方法に限定されるものではなく、蒸発源の母合金と異なる組成の蒸着膜を得るようにしてもよい。この場合、蒸発源の母合金の組成比と目標の膜組成比との関係に応じて、各金属成分の蒸気圧比の制御目標値あるいは各金属成分の蒸気圧比及び活量係数比の積の制御目標値が決まる。   In the above description, the method for obtaining a deposited film having the same composition as the mother alloy of the evaporation source as the low melting point metal layer has been described. The method for forming the low melting point metal layer in the present invention is described above. However, the present invention is not limited to such a method, and a deposited film having a composition different from that of the mother alloy of the evaporation source may be obtained. In this case, depending on the relationship between the composition ratio of the mother alloy of the evaporation source and the target film composition ratio, the control target value of the vapor pressure ratio of each metal component or the product of the vapor pressure ratio and activity coefficient ratio of each metal component is controlled. The target value is determined.

次に、図１（ａ）に示す低融点金属層３１、３２が対向した状態から、図１（ｂ）に示すように、電子部品２０を回路基板１０側へ移動させ、低融点金属層３１、３２同士が接触するように配置する。   Next, from the state where the low melting point metal layers 31 and 32 shown in FIG. 1A face each other, the electronic component 20 is moved to the circuit board 10 side as shown in FIG. , 32 are arranged in contact with each other.

そして、この状態で、２００℃以下で加熱加圧を行なうと、図１（ｃ）に示すように、低融点金属層３１、３２が溶融して低融点金属層３０となり、更に、回路電極１１及び素子電極２１中へ固液拡散して、図１（ｄ）に示すように接合が行なわれる。   When heating and pressurization is performed at 200 ° C. or lower in this state, the low melting point metal layers 31 and 32 are melted to form the low melting point metal layer 30 as shown in FIG. Then, solid-liquid diffusion into the element electrode 21 is performed, and bonding is performed as shown in FIG.

なお、上記の電極同士の位置決めや、移動、加熱加圧等の操作は、従来公知の実装設備である、例えば、フリップチップボンダなどを用いて行なうことができる。また、電極同士の位置決めは、カメラ等を用いた座標決定により正確に行なうことができる。   In addition, operations such as positioning, movement, and heating and pressing of the electrodes can be performed using a conventionally known mounting equipment such as a flip chip bonder. Further, the positioning of the electrodes can be accurately performed by coordinate determination using a camera or the like.

このように、本発明においては、加熱加圧を２００℃以下で行なうようにすることができる。これにより、従来のはんだ接合における一般的な加熱温度である、２００〜２５０℃に比べて低温での接合が可能となるので、電子部品２０への熱的ダメージを抑えることができる。この場合、更に、接合時の加熱温度は、低融点金属層３１、３２の融点より０〜１００℃高い温度であることが好ましい。   Thus, in the present invention, heating and pressurization can be performed at 200 ° C. or lower. Thereby, since it becomes possible to join at a low temperature as compared with 200 to 250 ° C., which is a general heating temperature in conventional solder joining, thermal damage to the electronic component 20 can be suppressed. In this case, the heating temperature at the time of joining is preferably 0 to 100 ° C. higher than the melting point of the low melting point metal layers 31 and 32.

また、この実施形態においては、低融点金属層３０が、回路電極１１及び素子電極２１中へ完全に固液拡散するまで、加熱加圧状態が維持される。本発明においては、このように、低融点金属層が、電極中へ完全に固液拡散するまで所定の時間、加熱加圧することが好ましい。   In this embodiment, the heat and pressure state is maintained until the low melting point metal layer 30 is completely solid-liquid diffused into the circuit electrode 11 and the element electrode 21. In the present invention, it is preferable that the low-melting-point metal layer is heated and pressurized for a predetermined time until it completely diffuses into the electrode.

これによって、図１（ｄ）に示すように、接合後の接合部においては、接合電極３５が、全体として単一の合金層として形成される。この接合電極３５は、その中央部分から各電極側に向かって低融点金属の濃度勾配を有するが、全体として単一の合金層となる。   As a result, as shown in FIG. 1D, the bonded electrode 35 is formed as a single alloy layer as a whole in the bonded portion after bonding. The bonding electrode 35 has a low-melting-point metal concentration gradient from the central portion toward each electrode, but as a whole becomes a single alloy layer.

したがって、接合電極３５には、中間合金層が別途形成されていないので、接合部の信頼性は介在する接合材料の特性に依存せず、主に電極の母材金属によることになる。したがって、はんだ等の場合と比較して、接続部の信頼性を向上させることができる。   Therefore, since the intermediate alloy layer is not separately formed on the bonding electrode 35, the reliability of the bonding portion does not depend on the characteristics of the intervening bonding material, and mainly depends on the base metal of the electrode. Therefore, the reliability of the connecting portion can be improved as compared with the case of solder or the like.

このように、電極中へ低融点金属層が完全に固液拡散するのに要する時間は、加熱温度、圧力、電極材料、低融点金属の材料等によって異なるが、通常、１０〜１８０秒である。   As described above, the time required for the solid-liquid diffusion of the low-melting-point metal layer into the electrode varies depending on the heating temperature, pressure, electrode material, low-melting-point metal material, etc., but is usually 10 to 180 seconds. .

また、加圧条件としては、上記の加熱温度、電極材料、低融点金属の材料等によって異なるが、好ましくは１０〜３０ＭＰａである。   The pressurizing condition varies depending on the heating temperature, the electrode material, the low melting point metal material, etc., but is preferably 10 to 30 MPa.

また、上記のように、回路電極１１、素子電極２１の表面粗さＲａが０．４〜１０μｍの粗面である場合においては、接合時に粗面同士が塑性変形して接合可能となるように加圧することが好ましい。これによれば、電極表面が塑性変形するまで加圧するので、電解メッキの析出条件やバラツキ等によって、形成される電極表面に凹凸がある場合においても、良好な接合状態を得ることができる。この場合の加圧条件としては、好ましくは５０〜１００ＭＰａである。   Further, as described above, when the surface roughness Ra of the circuit electrode 11 and the element electrode 21 is a rough surface of 0.4 to 10 μm, the rough surfaces are plastically deformed at the time of bonding so that bonding is possible. It is preferable to apply pressure. According to this, since the pressure is applied until the electrode surface is plastically deformed, a good bonding state can be obtained even when the electrode surface to be formed has irregularities due to electrolytic plating deposition conditions and variations. In this case, the pressurizing condition is preferably 50 to 100 MPa.

なお、前記のように、低融点金属層３１、３２が、２層以上の単一金属層を反応させて得られる合金層からなる場合には、まず、それぞれの単一金属の融点以下の温度で予備加熱を行い、２層以上の単一金属層を固溶させて合金層を形成し、その後、２００℃以下で加熱加圧を行なうことが好ましい。   As described above, when the low melting point metal layers 31 and 32 are made of an alloy layer obtained by reacting two or more single metal layers, first, the temperature is equal to or lower than the melting point of each single metal. It is preferable to perform preheating and to form an alloy layer by dissolving two or more single metal layers, and then heat and press at 200 ° C. or lower.

この場合、予備加熱の温度は、合金層を形成する単一金属層の種類や膜厚によって適宜選択できるが、例えば、Ｓｎ層とＩｎ層とからなる２層構成の場合には、１１０〜１２５℃で予備加熱を行なうことが好ましい。   In this case, the preheating temperature can be appropriately selected depending on the type and film thickness of the single metal layer forming the alloy layer. For example, in the case of a two-layer configuration including an Sn layer and an In layer, 110 to 125 Preheating is preferably performed at 0 ° C.

図２には、本発明の実装方法の他の実施形態が示されている。なお、以下の実施形態の説明においては、前記実施形態と同一部分には同符合を付して、その説明を省略することにする。   FIG. 2 shows another embodiment of the mounting method of the present invention. In the following description of the embodiment, the same parts as those of the above-described embodiment are denoted by the same reference numerals, and the description thereof is omitted.

この実施形態においては、図２（ａ）に示すように、回路電極１１、素子電極２１上に形成された低融点金属層３１、３２を対向させて位置合わせを行い、図２（ｂ）に示すように、低融点金属層３１、３２を接触させる。そして、この状態で、図２（ｃ）に示すように加熱加圧して、低融点金属層３１、３２を溶融させて低融点金属層３０とし、更に、図２（ｄ）に示すように、回路電極１１、素子電極２１とが拡散反応により中間合金層３６を形成するまで加熱加圧を行なう。   In this embodiment, as shown in FIG. 2A, the low-melting point metal layers 31 and 32 formed on the circuit electrode 11 and the device electrode 21 are opposed to each other, and the alignment is performed as shown in FIG. As shown, the low melting point metal layers 31, 32 are brought into contact. In this state, as shown in FIG. 2 (c), heat and pressure are applied to melt the low melting point metal layers 31, 32 to form the low melting point metal layer 30, and as shown in FIG. 2 (d), Heating and pressing are performed until the circuit electrode 11 and the element electrode 21 form the intermediate alloy layer 36 by a diffusion reaction.

そして、中間合金層３６を形成した後、加圧に加えて、図２（ｄ）に示すように、電子部品２０を保持するフリップチップボンダのヘッド部４０によって、電子部品２０を、図２（ｄ）の矢印方向に沿って左右に振動させる。   Then, after forming the intermediate alloy layer 36, in addition to the pressurization, as shown in FIG. 2 (d), the electronic component 20 is moved to the electronic component 20 by the head portion 40 of the flip chip bonder holding the electronic component 20 as shown in FIG. Vibrate left and right along the arrow direction of d).

このように加圧状態で左右に振動させることで、低融点金属中にある酸化物が除去され、対向した両電極の未接触部の接触状態が向上するとともに、加圧、振動により押し出された余剰分の低融点金属が、はみ出し部３６ａとなって接合部の側面外周に突出し、回路電極１１と素子電極２１との接合部として、中間合金層３６のみが介在し、余剰の低融点金属が残存しない接合部を得ることができる。   In this way, the oxide in the low melting point metal is removed by vibrating left and right in a pressurized state, the contact state between the non-contact portions of both opposing electrodes is improved, and the metal is pushed out by pressing and vibration. The surplus low melting point metal becomes a protruding portion 36a and protrudes from the outer periphery of the side surface of the joint portion, and only the intermediate alloy layer 36 is interposed as the joint portion between the circuit electrode 11 and the element electrode 21, and the surplus low melting point metal is formed. A joint that does not remain can be obtained.

上記の加熱加圧工程における、中間合金層３６を形成するのに要する時間は、加熱温度、圧力、電極材料、低融点金属の材料等によって適宜設定されるが、上記の低融点金属を完全に拡散させる実施形態に比べて短く、通常１〜５秒でよい。   The time required for forming the intermediate alloy layer 36 in the heating and pressurizing step is appropriately set depending on the heating temperature, pressure, electrode material, low melting point metal material, etc. Compared to the embodiment to be diffused, it is shorter, usually 1 to 5 seconds.

なお、この接合部における、中間合金層３６の厚さは１〜５μｍであることが好ましい。また、この明確な中間合金層３６の存在は、断面の観察によっても確認でき、また、電気抵抗、熱抵抗等の測定によって非破壊で確認することもできる。   In addition, it is preferable that the thickness of the intermediate alloy layer 36 in this junction part is 1-5 micrometers. The presence of the clear intermediate alloy layer 36 can also be confirmed by observing a cross section, and can also be confirmed nondestructively by measuring electric resistance, thermal resistance, and the like.

この実施形態によれば、低融点金属層が完全には拡散せず、中間合金層を形成する段階まで加熱すれば足りるので、接合に要する時間を大幅に短縮することができる。また、低融点金属の供給量は、中間合金層を形成するための必要量以上が供給されておればよいので、低融点金属の供給量の厳密な管理が不要となる。   According to this embodiment, since the low melting point metal layer does not completely diffuse and it is sufficient to heat up to the stage of forming the intermediate alloy layer, the time required for joining can be greatly shortened. In addition, since the supply amount of the low melting point metal has only to be supplied more than the amount necessary for forming the intermediate alloy layer, strict management of the supply amount of the low melting point metal becomes unnecessary.

参考例１
図１に示す方法を用いて電子部品を回路基板上に実装した。 Reference example 1
The electronic component was mounted on a circuit board using the method shown in FIG.

まず、電子部品としては半導体チップを用い、この半導体チップ上に電極としてＣｕのバンプを形成した。一方、回路基板上にもＣｕ電極を形成した。   First, a semiconductor chip was used as an electronic component, and Cu bumps were formed on the semiconductor chip as electrodes. On the other hand, Cu electrodes were also formed on the circuit board.

次に、低融点金属層として、半導体チップのＣｕバンプ上、及び、回路基板のＣｕ電極上に、それぞれ２μｍ及び２μｍ、合計厚さ４μｍのＳｎＩｎ（融点１１７℃）を蒸着により形成した。   Next, SnIn (melting point: 117 ° C.) having a thickness of 2 μm and 2 μm and a total thickness of 4 μm was formed by vapor deposition on the Cu bump of the semiconductor chip and the Cu electrode of the circuit board as a low melting point metal layer, respectively.

このとき、蒸着方法としては、蒸発源としてＳｎＩｎの母合金（Ｉｎ：Ｓｎ＝５２：４８）を用い、上記の（１２）式における蒸気圧比（ｐA／ｐB）＝０．８１となるように蒸着条件を制御しながら成膜を行った。なお、蒸着装置は電子ビーム蒸着装置を用い、蒸着時の真空度は１０-5Ｐａ、蒸着速度は０．４ｎｍ／ｍｉｎで行った。 At this time, as a vapor deposition method, a SnIn mother alloy (In: Sn = 52: 48) is used as an evaporation source so that the vapor pressure ratio (p A / p B ) = 0.81 in the above equation (12). The film was formed while controlling the deposition conditions. In addition, the vapor deposition apparatus used the electron beam vapor deposition apparatus, the vacuum degree at the time of vapor deposition was 10 <-5 > Pa, and the vapor deposition rate was 0.4 nm / min.

その結果、形成されたＳｎＩｎ薄膜の組成を、断面サンプルのμ−ＡＥＳ分析によって調べたところ、Ｉｎ：Ｓｎ＝５２：４８となっており、目的とする合金組成の低融点金属層が得られていた。   As a result, the composition of the formed SnIn thin film was examined by μ-AES analysis of a cross-sectional sample. As a result, In: Sn = 52: 48, and a low melting point metal layer having an intended alloy composition was obtained. It was.

そして、図１（ａ）に示すように、半導体チップのＣｕバンプと、回路基板のＣｕ電極の位置を合わせた後、図１（ｂ）に示すように電極を接触させ、図１（ｃ）に示すように、ＳｎＩｎの融点より２０℃高い、温度１３７℃、圧力９０ＭＰａで、３０秒間加熱加圧して接合した。   Then, as shown in FIG. 1A, after aligning the positions of the Cu bumps of the semiconductor chip and the Cu electrodes of the circuit board, the electrodes are brought into contact as shown in FIG. As shown in FIG. 4, the bonding was performed by heating and pressing for 30 seconds at a temperature of 137 ° C. and a pressure of 90 MPa, which is 20 ° C. higher than the melting point of SnIn.

その結果、図１（ｄ）に示すように、ＳｎＩｎは、Ｃｕ電極中へ完全に拡散され、中間合金層が存在しない、全体として１つの合金層である接合部が得られていることが、高真空走査型電子顕微鏡による断面観察と、Ｘ線マイクロアナライザ（ＥＰＭＡ）による接合界面の元素分析によって確認できた。   As a result, as shown in FIG. 1 (d), SnIn is completely diffused into the Cu electrode, and there is no intermediate alloy layer, and a joint portion that is one alloy layer as a whole is obtained. This could be confirmed by cross-sectional observation with a high vacuum scanning electron microscope and elemental analysis of the bonding interface with an X-ray microanalyzer (EPMA).

参考例２
蒸着による低融点金属層の形成において、上記の（１６）式における蒸気圧比と活量係数比の積（γAｐA／γBｐB）＝０．９８となるように制御しながら成膜を行った以外は参考例１と同様の条件で、半導体チップと回路基板との接合を行った。 Reference example 2
In the formation of the low melting point metal layer by vapor deposition, film formation is performed while controlling the product of the vapor pressure ratio and the activity coefficient ratio (γ A p A / γ B p B ) = 0.98 in the above equation (16). The semiconductor chip and the circuit board were bonded to each other under the same conditions as in Reference Example 1 except that.

その結果、形成されたＳｎＩｎ薄膜の組成はＩｎ：Ｓｎ＝５２：４８となっており、目的とする合金組成の低融点金属層が得られていた。   As a result, the composition of the formed SnIn thin film was In: Sn = 52: 48, and a low melting point metal layer having an intended alloy composition was obtained.

また、接合後は、図１（ｄ）に示すように、ＳｎＩｎは、Ｃｕ電極中へ完全に拡散され、中間合金層が存在しない、全体として１つの合金層である接合部が得られていることが、高真空走査型電子顕微鏡による断面観察と、Ｘ線マイクロアナライザ（ＥＰＭＡ）による接合界面の元素分析によって確認できた。   Further, after bonding, as shown in FIG. 1 (d), SnIn is completely diffused into the Cu electrode, and an intermediate alloy layer is not present, and a bonded portion which is one alloy layer as a whole is obtained. This can be confirmed by cross-sectional observation with a high vacuum scanning electron microscope and elemental analysis of the bonding interface with an X-ray microanalyzer (EPMA).

実施例１
図１に示す方法を用いて電子部品を回路基板上に実装した。 Example 1
The electronic component was mounted on a circuit board using the method shown in FIG.

まず、電子部品としては半導体チップを用い、この半導体チップ上に電極としてＣｕのバンプを形成した。一方、回路基板上にもＣｕ電極を形成した。   First, a semiconductor chip was used as an electronic component, and Cu bumps were formed on the semiconductor chip as electrodes. On the other hand, Cu electrodes were also formed on the circuit board.

次に、低融点金属層として、半導体チップのＣｕバンプ上、及び、回路基板のＣｕ電極上のそれぞれに、単一金属層として、Ｓｎ層０．４８μｍ、Ｉｎ層０．５２μｍを順に積層し、合計厚さ１μｍとなるように蒸着により形成した。   Next, as a low melting point metal layer, a Sn layer 0.48 μm and an In layer 0.52 μm are sequentially laminated as a single metal layer on the Cu bump of the semiconductor chip and the Cu electrode of the circuit board, respectively. It was formed by vapor deposition so as to have a total thickness of 1 μm.

そして、図１（ａ）に示すように、半導体チップのＣｕバンプと、回路基板のＣｕ電極の位置を合わせた後、図１（ｂ）に示すように電極を接触させ、温度１２０℃で１０秒間の予備加熱を行い、Ｓｎ層とＩｎ層とを固溶させてＳｎＩｎの合金層を得た。   Then, as shown in FIG. 1A, after aligning the positions of the Cu bumps of the semiconductor chip and the Cu electrodes of the circuit board, the electrodes are brought into contact as shown in FIG. Pre-heating for 2 seconds was performed to solidify the Sn layer and the In layer to obtain an SnIn alloy layer.

その後、図１（ｃ）に示すように、ＳｎＩｎの融点より２０℃高い、温度１３７℃、圧力９０ＭＰａで、３０秒間加熱加圧して接合した。   Thereafter, as shown in FIG. 1 (c), bonding was performed by heating and pressing at a temperature of 137 ° C. and a pressure of 90 MPa, which is 20 ° C. higher than the melting point of SnIn, for 30 seconds.

その結果、図１（ｄ）に示すように、ＳｎＩｎは、Ｃｕ電極中へ完全に拡散され、中間合金層が存在しない、全体として１つの合金層である接合部が得られていることが、高真空走査型電子顕微鏡による断面観察と、Ｘ線マイクロアナライザ（ＥＰＭＡ）による接合界面の元素分析によって確認できた。   As a result, as shown in FIG. 1 (d), SnIn is completely diffused into the Cu electrode, and there is no intermediate alloy layer, and a joint portion that is one alloy layer as a whole is obtained. This could be confirmed by cross-sectional observation with a high vacuum scanning electron microscope and elemental analysis of the bonding interface with an X-ray microanalyzer (EPMA).

本発明は、例えば、小型化が必要とされる回路基板あるいはモジュール（マルチチップモジュール）等において、半導体チップ等の電子部品をプリント基板等の回路基板への直接実装に好適に利用できる。   INDUSTRIAL APPLICABILITY The present invention can be suitably used for directly mounting an electronic component such as a semiconductor chip on a circuit board such as a printed circuit board, for example, in a circuit board or module (multi-chip module) that needs to be downsized.

本発明の実装方法の一実施形態における電極同士の接合原理を示す工程図であって、（ａ）電極同士を対向させた状態、（ｂ）電極同士を接触させた状態、（ｃ）加熱加圧を行なっている接合部の状態、（ｄ）接合後の状態を示す図である。It is process drawing which shows the joining principle of the electrodes in one Embodiment of the mounting method of this invention, Comprising: (a) The state which made electrodes oppose, (b) The state which made electrodes contact, (c) Heating heating It is a figure which shows the state of the junction part which is performing pressure, and the state after (d) joining. 本発明の実装方法の他の実施形態における電極同士の接合原理を示す概念図であって、（ａ）電極同士を対向させた状態、（ｂ）電極同士を接触させた状態、（ｃ）加熱加圧を行なっている接合部の状態、（ｄ）電子部品の振動を行なっている状態、（ｅ）接合後の接合部の状態を示す図である。It is a conceptual diagram which shows the joining principle of the electrodes in other embodiment of the mounting method of this invention, Comprising: (a) The state which made electrodes oppose, (b) The state which made electrodes contact, (c) Heating It is a figure which shows the state of the junction part which is pressing, (d) the state which is vibrating the electronic component, and (e) the state of the junction part after joining. 従来技術における基板へ電子部品を実装した状態を示す概略図である。It is the schematic which shows the state which mounted the electronic component on the board | substrate in a prior art.

符号の説明Explanation of symbols

１０：回路基板
１１：回路電極
２０：電子部品
２１：素子電極
３０、３１、３２：低融点金属層
３５：接合電極
３６：中間合金層
３６ａ：はみ出し部
４０：ヘッド部
10: Circuit board 11: Circuit electrode 20: Electronic component 21: Element electrodes 30, 31, 32: Low melting point metal layer 35: Bonding electrode 36: Intermediate alloy layer 36a: Overhanging portion 40: Head portion

Claims (7)

回路基板上に形成された金属からなる回路電極と、電子部品上に形成された金属からなる素子電極とを接合して、前記電子部品を前記回路基板上に実装する方法において、
前記回路電極及び／又は前記素子電極上に、融点が２２０℃以下の２元以上の合金を形成できる、少なくとも２種類以上の金属を２層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることにより、低融点金属層をあらかじめ形成した後、前記回路電極及び前記素子電極を対向させて、少なくとも低融点金属層が溶融する温度で加熱加圧し、前記低融点金属層を、前記回路電極及び前記素子電極中へ固液拡散させることによって、前記回路電極と前記素子電極とを接合することを特徴とする電子部品の実装方法。 In the method of mounting the electronic component on the circuit board by bonding the circuit electrode made of metal formed on the circuit board and the element electrode made of metal formed on the electronic component,
On the circuit electrode and / or the element electrode , at least two kinds of metals capable of forming a binary alloy having a melting point of 220 ° C. or lower are laminated in two or more layers, and the laminated metal layer is preheated. After the low melting point metal layer is formed in advance by reacting to form an alloy layer, the circuit electrode and the element electrode are opposed to each other and heated and pressed at a temperature at which the low melting point metal layer melts, A method of mounting an electronic component, comprising joining a circuit electrode and the element electrode by solid-liquid diffusion of a metal layer into the circuit electrode and the element electrode. 前記低融点金属層が、ＳｎＩｎ又はＳｎＢｉである請求項１に記載の電子部品の実装方法。 The electronic component mounting method according to claim 1, wherein the low melting point metal layer is SnIn or SnBi . 前記接合時の加熱温度が、前記低融点金属層の融点より０〜１００℃高い温度である請求項２に記載の電子部品の実装方法。 The method for mounting an electronic component according to claim 2, wherein the heating temperature at the time of joining is 0 to 100 ° C. higher than the melting point of the low melting point metal layer . 前記回路電極及び前記素子電極の材質が、Ｃｕ、Ｎｉ、Ａｕより選択される一種又はそれらの合金である請求項１〜３のいずれか１つに記載の電子部品の実装方法。   The electronic component mounting method according to any one of claims 1 to 3, wherein a material of the circuit electrode and the element electrode is one selected from Cu, Ni, and Au or an alloy thereof. 前記回路電極及び前記素子電極表面の表面粗さＲａが０．４〜１０μｍの粗面であって、前記接合時に前記粗面同士が塑性変形して接合可能となるように加圧する請求項１〜４のいずれか１つに記載の電子部品の実装方法。   The surface roughness Ra of the surface of the circuit electrode and the element electrode is a rough surface of 0.4 to 10 μm, and pressurization is performed so that the rough surfaces are plastically deformed and can be joined at the time of joining. 5. The electronic component mounting method according to any one of 4 above. 前記回路電極及び前記素子電極の材質が、Ｃｕ、Ｎｉ、Ａｕ、及びそれらの合金より選択される一種の同じ金属からなり、前記加熱加圧は、前記低融点金属層が、前記回路電極及び前記素子電極中に完全に固液拡散して、前記回路電極、前記素子電極及び前記低融点金属層が全体として単一の合金層となるまで行なう請求項１〜５のいずれか１つに記載の電子部品の実装方法。 The material of the circuit electrode and the element electrode, Cu, becomes Ni, Au, and the same metal of one selected from the alloys thereof, the heat and pressure, the low melting point metal layer, the circuit electrode and the 6. The process according to claim 1, wherein the solid-liquid diffusion is performed completely in the element electrode until the circuit electrode, the element electrode, and the low-melting point metal layer become a single alloy layer as a whole. Electronic component mounting method. 前記加熱加圧は、前記低融点金属層が、前記回路電極と前記素子電極との間に中間合金層を形成するまで行なう請求項１〜５のいずれか１つに記載の電子部品の実装方法。   The electronic component mounting method according to claim 1, wherein the heating and pressing are performed until the low melting point metal layer forms an intermediate alloy layer between the circuit electrode and the element electrode. .
JP2003298056A 2002-08-30 2003-08-22 Electronic component mounting method Expired - Fee Related JP4136844B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003298056A JP4136844B2 (en) 2002-08-30 2003-08-22 Electronic component mounting method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002254941 2002-08-30
JP2003298056A JP4136844B2 (en) 2002-08-30 2003-08-22 Electronic component mounting method

Publications (2)

Publication Number Publication Date
JP2004111935A JP2004111935A (en) 2004-04-08
JP4136844B2 true JP4136844B2 (en) 2008-08-20

Family

ID=32301373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003298056A Expired - Fee Related JP4136844B2 (en) 2002-08-30 2003-08-22 Electronic component mounting method

Country Status (1)

Country Link
JP (1) JP4136844B2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4136845B2 (en) 2002-08-30 2008-08-20 富士電機ホールディングス株式会社 Manufacturing method of semiconductor module
US20070152025A1 (en) * 2004-03-02 2007-07-05 Fuji Electric Holdings Co., Ltd. Electronic part mounting method
JP5696173B2 (en) * 2005-08-12 2015-04-08 アンタヤ・テクノロジーズ・コープ Solder composition
EP2052805B1 (en) 2006-08-04 2016-09-28 Panasonic Intellectual Property Management Co., Ltd. Bonding material, bonded portion and circuit board
JP4822526B2 (en) * 2006-09-15 2011-11-24 株式会社豊田中央研究所 Zygote
WO2010021267A1 (en) 2008-08-21 2010-02-25 株式会社村田製作所 Electronic component and method for manufacturing the same
JP5537143B2 (en) * 2009-12-15 2014-07-02 株式会社不二工機 Fusible stopper
JP5630060B2 (en) * 2010-04-02 2014-11-26 富士通株式会社 Solder bonding method, semiconductor device and manufacturing method thereof
CN102275043A (en) * 2010-06-10 2011-12-14 中国科学院金属研究所 Method for eliminating brittleness of connecting interface between SnBi soldering flux and Cu substrate
JP6035714B2 (en) * 2011-08-17 2016-11-30 ソニー株式会社 SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE
DE112013007187B4 (en) * 2013-09-13 2023-08-10 Ev Group E. Thallner Gmbh Process for applying a bonding layer
JP7014645B2 (en) * 2018-03-06 2022-02-01 シャープ株式会社 Semiconductor light emitting device
JP2022043722A (en) * 2020-09-04 2022-03-16 株式会社新菱 Sn-In-BASED LOW MELTING POINT BONDING MEMBER AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR ELECTRONIC CIRCUIT AND MOUNTING METHOD THEREOF

Also Published As

Publication number Publication date
JP2004111935A (en) 2004-04-08

Similar Documents

Publication Publication Date Title
US8013428B2 (en) Whisker-free lead frames
EP1386356B1 (en) Fluxless flip chip interconnection
JP2007019360A (en) Mounting method of electric component
KR101805147B1 (en) Joint structure manufacturing method, heating and melting treatment method, and system for same
JP4136844B2 (en) Electronic component mounting method
KR102121176B1 (en) Method for producing semiconductor package
JP4136845B2 (en) Manufacturing method of semiconductor module
JP4552934B2 (en) Electronic component mounting method
TWI301738B (en) Method of mounting an electronic part
JP2006135264A (en) Method for manufacturing electronic component, and electronic component using the method
JP5035134B2 (en) Electronic component mounting apparatus and manufacturing method thereof
JP2007044754A (en) Metal plate joining method
US7750484B2 (en) Semiconductor device with flip-chip connection that uses gallium or indium as bonding material
JP2001298051A (en) Solder connecting part
JPH02117772A (en) Bonding of metal surface
JP3998484B2 (en) How to connect electronic components
JP5376356B2 (en) Electronic element mounting method and electronic component mounted by the mounting method
JP4508189B2 (en) Manufacturing method of semiconductor module
JP2009010302A (en) Method for forming solder paste layer
JP4590783B2 (en) Method for forming solder balls
JPH07235763A (en) Manufacture of electronic circuit
KR102181706B1 (en) Method for producing semiconductor chip
JP2009194357A (en) Semiconductor device and method of manufacturing the same
KR20130100441A (en) Manufacturing method for flip chip packages using bumps of complex structure and flip chip packages produced using the same method
US5537739A (en) Method for electoconductively connecting contacts

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051114

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070626

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070703

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070831

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080219

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080416

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080513

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080603

R150 Certificate of patent or registration of utility model

Ref document number: 4136844

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110613

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110613

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120613

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130613

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees