JP4134900B2 - Electronic device package - Google Patents

Electronic device package Download PDF

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JP4134900B2
JP4134900B2 JP2003420643A JP2003420643A JP4134900B2 JP 4134900 B2 JP4134900 B2 JP 4134900B2 JP 2003420643 A JP2003420643 A JP 2003420643A JP 2003420643 A JP2003420643 A JP 2003420643A JP 4134900 B2 JP4134900 B2 JP 4134900B2
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lid member
electrode
electronic
semiconductor element
internal electrode
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JP2005183571A (en
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和司 東
伸治 石谷
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2003420643A priority Critical patent/JP4134900B2/en
Priority to US10/581,792 priority patent/US7692292B2/en
Priority to CN200810169256XA priority patent/CN101369560B/en
Priority to PCT/JP2004/017931 priority patent/WO2005055317A1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Description

本発明は、密閉された内部空間に電子素子を備える電子素子パッケージおよびその製造方法に関する。   The present invention relates to an electronic device package including an electronic device in a sealed internal space and a manufacturing method thereof.

従来より、半導体素子、表面弾性波素子、その他様々な電子素子を、大気中に存在する水分や酸素等の影響から守る一手法として、容器の内部に電子素子を収納し、容器内部を密閉して電子素子を封止する技術が知られている。   Conventionally, as a technique for protecting semiconductor elements, surface acoustic wave elements, and other various electronic elements from the effects of moisture, oxygen, etc. present in the atmosphere, the electronic elements are stored inside the container and the container is sealed. A technique for sealing an electronic element is known.

特許文献1では、回路部品を密閉空間内に収納する電子回路モジュールの製造において、抵抗やコンデンサ等の回路部品が実装されたフレキシブル回路基板が内面に貼り付けられた箱形ケースに、回路部品が実装された面を内側に向けて硬質回路基板を嵌め込むことにより、ケース内部の空隙部を有効に活用する技術が開示されている。
特開昭61−278198号公報
In Patent Document 1, in the manufacture of an electronic circuit module that stores circuit components in a sealed space, the circuit components are mounted on a box-shaped case in which a flexible circuit board on which circuit components such as resistors and capacitors are mounted is attached to the inner surface. There has been disclosed a technique for effectively utilizing a gap portion inside a case by fitting a hard circuit board with a mounted surface facing inward.
JP-A 61-278198

ところで、近年の電子機器の小型化に伴って電子素子の微小化が進み、微小な電子素子の配置の更なる高密度化も求められている。特許文献1に開示される電子回路モジュールでは、容器内部にフレキシブル回路基板を収納することが前提となっているため、ICのベアチップ等の微小な電子部品に対してフレキシブル回路基板が相対的に厚くなり、電子素子の微小化に合わせた高密度化およびパッケージの小型化が困難となる。   By the way, with the recent miniaturization of electronic devices, the miniaturization of electronic elements has progressed, and further increase in the density of the arrangement of minute electronic elements is also required. The electronic circuit module disclosed in Patent Document 1 is based on the premise that the flexible circuit board is housed inside the container. Therefore, the flexible circuit board is relatively thick with respect to minute electronic components such as bare IC chips. Therefore, it is difficult to increase the density and reduce the size of the package in accordance with the miniaturization of electronic elements.

本発明は、上記課題に鑑みなされたものであり、微小な電子素子の高密度な配置に適した電子素子パッケージを提供することを目的としている。   The present invention has been made in view of the above problems, and an object thereof is to provide an electronic element package suitable for high-density arrangement of minute electronic elements.

請求項1記載の発明は、外面に外部電極を有し、内面に内部電極を有し、前記外部電極と内部電極とをビアを介して接続し、かつ、内部電極に電子素子をバンプにて接続した上蓋部材と、
外面に外部電極を有し、内面に内部電極を有し、前記外部電極と内部電極とをビアを介して接続し、かつ、内部電極に電子素子をバンプにて接続した下蓋部材と、
複数の側壁部材からなり、少なくとも一つの側壁部材は、その外面に外部電極を有し、内面に内部電極を有し、前記外部電極と内部電極とをビアを介して接続したものであり、かつ、前記内部電極に前記電子素子をバンプにて接続したものであるところの前記上蓋部材と前記下蓋部材とを接続する筒状部材と、
前記筒状部材に設けられ前記上蓋部材及び前記下蓋部材と前記筒状部材とを接着して内部空間を密閉する金属部を備え、
前記金属部は金からなるものとし、前記内部空間が減圧状態または不活性ガスで充填されていることを特徴とする電子素子パッケージを用いる。
The invention according to claim 1 has an external electrode on the outer surface, an internal electrode on the inner surface, connects the external electrode and the internal electrode through vias, and bumps an electronic element to the internal electrode A connected top lid member;
An outer electrode on the outer surface, an inner electrode on the inner surface, the external electrode and the internal electrode are connected via vias, and a lower lid member in which an electronic element is connected to the internal electrode by a bump;
It comprises a plurality of side wall members, and at least one side wall member has an external electrode on its outer surface, an internal electrode on its inner surface, and the external electrode and the internal electrode are connected via vias, and A cylindrical member for connecting the upper lid member and the lower lid member , wherein the electronic element is connected to the internal electrode by a bump ,
A metal part that is provided on the cylindrical member and seals the internal space by bonding the upper lid member and the lower lid member and the cylindrical member;
The metal part is made of gold, and an electronic device package is used in which the internal space is filled with a reduced pressure state or an inert gas.

本発明では、電子素子パッケージの構造を微小な電子素子の高密度な配置に適したものとすることができる。   In the present invention, the structure of the electronic element package can be made suitable for high-density arrangement of minute electronic elements.

請求項2ないし4並びに請求項13および14の発明では、電子素子パッケージを容易に製造することができる。   In the inventions of claims 2 to 4 and claims 13 and 14, an electronic element package can be easily manufactured.

請求項5の発明では、電子素子パッケージの製造コストを削減することができる。   In the invention of claim 5, the manufacturing cost of the electronic device package can be reduced.

請求項6および15の発明では、容器本体と蓋体とを低温にて接着することができる。   In the inventions of claims 6 and 15, the container body and the lid can be bonded at a low temperature.

図1は、本発明の第1の実施の形態に係る電子素子パッケージ1の構成を示す断面図である。電子素子パッケージ1は、内部に電子素子である半導体素子61が封止されたパッケージ(すなわち、電子素子を密閉空間内に設けてパッケージ化したもの)であり、2つの半導体素子61、および、2つの半導体素子61を収納する内部空間11を形成する容器10を備える。   FIG. 1 is a cross-sectional view showing a configuration of an electronic device package 1 according to a first embodiment of the present invention. The electronic element package 1 is a package in which a semiconductor element 61 as an electronic element is sealed (that is, a package in which an electronic element is provided in a sealed space), and includes two semiconductor elements 61 and 2. The container 10 which forms the internal space 11 which accommodates the one semiconductor element 61 is provided.

図2は、電子素子パッケージ1を示す分解斜視図である。容器10は、Z方向の両端に開口を有する筒状部材4、筒状部材4の(+Z)側の開口を塞ぐ上蓋部材2、および、筒状部材4の(−Z)側の開口を塞ぐ下蓋部材3を備える。上蓋部材2、下蓋部材3および筒状部材4は樹脂により形成される。筒状部材4の(+Z)側および(−Z)側の端面には、金(Au)により形成される金属部511および521がそれぞれ設けられる。また、上蓋部材2の(−Z)側の面(内部空間11の上側の面を形成する面であり、以下、「上面」という。)21、および、下蓋部材3の(+Z)側の面(内部空間11の下側の面を形成する面であり、以下、「下面」という。)31のうち筒状部材4が接着される領域には、金により形成される金属部512および522がそれぞれ設けられる。内部空間11の上面21および下面31には、半導体素子61が1つずつ実装される。   FIG. 2 is an exploded perspective view showing the electronic device package 1. The container 10 closes the tubular member 4 having openings at both ends in the Z direction, the upper lid member 2 that closes the (+ Z) side opening of the tubular member 4, and the (−Z) side opening of the tubular member 4. A lower lid member 3 is provided. The upper lid member 2, the lower lid member 3, and the cylindrical member 4 are formed of resin. Metal parts 511 and 521 formed of gold (Au) are provided on the (+ Z) side and (−Z) side end faces of the cylindrical member 4, respectively. Further, the (−Z) side surface of the upper lid member 2 (the surface forming the upper surface of the internal space 11, hereinafter referred to as “upper surface”) 21, and the (+ Z) side surface of the lower lid member 3. Metal portions 512 and 522 formed of gold are formed in the region of the surface 31 (which is a surface forming the lower surface of the internal space 11 and hereinafter referred to as “lower surface”) 31 to which the tubular member 4 is bonded. Are provided respectively. One semiconductor element 61 is mounted on each of the upper surface 21 and the lower surface 31 of the internal space 11.

図1に示すように、電子素子パッケージ1では、金属部521および522が接合されて金属層52が形成されることにより筒状部材4と下蓋部材3とが接着され、また、金属部511および512が接合されて金属層51が形成されることにより筒状部材4と上蓋部材2とが接着される。このように、上蓋部材2および下蓋部材3が筒状部材4の両端の開口を塞いで取り付けられることにより、上蓋部材2、下蓋部材3および筒状部材4の内側を向く面により内部空間11が形成され、筒状部材4の内側の面41が内部空間11の側面を形成する。以下の説明では、面41を「側面」と呼ぶ。   As shown in FIG. 1, in the electronic device package 1, the metal parts 521 and 522 are joined to form the metal layer 52, whereby the tubular member 4 and the lower lid member 3 are bonded, and the metal part 511. And 512 are joined to form the metal layer 51, whereby the tubular member 4 and the upper lid member 2 are bonded. Thus, the upper lid member 2 and the lower lid member 3 are attached by closing the openings at both ends of the cylindrical member 4, so that the inner space is defined by the surfaces facing the inner sides of the upper lid member 2, the lower lid member 3, and the cylindrical member 4. 11 is formed, and the inner surface 41 of the tubular member 4 forms the side surface of the internal space 11. In the following description, the surface 41 is referred to as a “side surface”.

上蓋部材2は、内部空間11の上面21上に形成された内部電極22、および、(+Z)側の面(すなわち、容器10の外表面であって上面21の外側の面)211上に形成された外部電極23を備える多層基板であり、内部電極22と外部電極23とは上蓋部材2を貫通するビア24によって電気的に接続される。上面21に実装される半導体素子61は、内部電極22およびビア24を介して外部電極23と電気的に接続される。   The upper lid member 2 is formed on the internal electrode 22 formed on the upper surface 21 of the internal space 11 and the (+ Z) side surface (that is, the outer surface of the container 10 and the outer surface of the upper surface 21) 211. The internal electrode 22 and the external electrode 23 are electrically connected by a via 24 penetrating the upper lid member 2. The semiconductor element 61 mounted on the upper surface 21 is electrically connected to the external electrode 23 through the internal electrode 22 and the via 24.

下蓋部材3は、下面31上に形成された内部電極32、および、(−Z)側の面(すなわち、容器10の外表面であって下面31の外側の面)311上に形成された外部電極33を備える多層基板であり、内部電極32と外部電極33とは下蓋部材3を貫通するビア34によって電気的に接続される。下面31に実装される半導体素子61は、内部電極32およびビア34を介して外部電極33と電気的に接続される。   The lower lid member 3 is formed on the internal electrode 32 formed on the lower surface 31 and the (−Z) side surface (that is, the outer surface of the container 10 and the outer surface of the lower surface 31) 311. The multilayer substrate includes an external electrode 33, and the internal electrode 32 and the external electrode 33 are electrically connected by a via 34 that penetrates the lower lid member 3. The semiconductor element 61 mounted on the lower surface 31 is electrically connected to the external electrode 33 through the internal electrode 32 and the via 34.

半導体素子61は、いわゆるICのベアチップであり、半導体素子61の実装面のランド上に形成された金属のバンプ62が、上蓋部材2の内部電極22、または、下蓋部材3の内部電極32に電気的に接合されることにより上蓋部材2または下蓋部材3に実装される。   The semiconductor element 61 is a so-called IC bare chip, and metal bumps 62 formed on lands on the mounting surface of the semiconductor element 61 are formed on the internal electrode 22 of the upper lid member 2 or the internal electrode 32 of the lower lid member 3. It is mounted on the upper lid member 2 or the lower lid member 3 by being electrically joined.

図3は、電子素子パッケージ1の製造工程を示す図である。電子素子パッケージ1が製造される際には、まず、上蓋部材2、下蓋部材3および筒状部材4のそれぞれの接着部位に金メッキが施され、金属部512,522,511および521が形成される(ステップS11)。   FIG. 3 is a diagram illustrating a manufacturing process of the electronic element package 1. When the electronic device package 1 is manufactured, first, gold plating is applied to the bonding portions of the upper lid member 2, the lower lid member 3, and the tubular member 4 to form metal parts 512, 522, 511, and 521. (Step S11).

続いて、上蓋部材2、下蓋部材3、筒状部材4および2つの半導体素子61が、接合装置のロードロック内に搬入され、ロードロックに接続される真空ポンプによりロードロック内が減圧された後、予め減圧状態(好ましくは、真空状態)とされているチャンバ内に搬入されて所定の位置に配置される。次に、チャンバ内の減圧(真空)環境下において、1つの半導体素子61のバンプ62、および、上蓋部材2の内部電極22にアルゴン(Ar)の高速原子ビーム(Fast Atom Beam:以下、「FAB」という。)が照射され、バンプ62および内部電極22の表面が洗浄される(すなわち、表面の不要な物質の除去および表面の活性化が行われる。)(ステップS12)。このとき、バンプ62および内部電極22の温度は、表面の活性化の促進、および、高温加熱による半導体素子61の損傷防止の観点から、室温以上150℃以下とされることが好ましく、必要に応じてレーザ光の照射等により加熱される。その後、バンプ62と内部電極22とを互いに接触させる金属接合により半導体素子61が上蓋部材2に実装される(ステップS13)。   Subsequently, the upper lid member 2, the lower lid member 3, the cylindrical member 4 and the two semiconductor elements 61 were carried into the load lock of the bonding apparatus, and the pressure inside the load lock was reduced by a vacuum pump connected to the load lock. After that, it is carried into a chamber that has been previously in a reduced pressure state (preferably in a vacuum state) and placed at a predetermined position. Next, in a reduced pressure (vacuum) environment in the chamber, a fast atom beam (hereinafter referred to as “FAB”) of argon (Ar) is applied to the bumps 62 of one semiconductor element 61 and the internal electrode 22 of the upper lid member 2. The surface of the bump 62 and the internal electrode 22 is cleaned (that is, unnecessary substances on the surface are removed and the surface is activated) (step S12). At this time, the temperature of the bump 62 and the internal electrode 22 is preferably set to room temperature or higher and 150 ° C. or lower from the viewpoint of promoting activation of the surface and preventing damage to the semiconductor element 61 due to high temperature heating. And heated by laser light irradiation. Thereafter, the semiconductor element 61 is mounted on the upper lid member 2 by metal bonding for bringing the bump 62 and the internal electrode 22 into contact with each other (step S13).

もう1つの半導体素子61についても同様に、減圧(真空)環境下にて半導体素子61のバンプ62、および、下蓋部材3の内部電極32にFABが照射され(ステップS14)、バンプ62および内部電極32を互いに接触させる金属接合により下蓋部材3に実装される(ステップS15)。なお、バンプ62に代わるバンプが予め内部電極22および内部電極32上にそれぞれ形成されていてもよい。この場合、半導体素子61のランドとバンプとがFABにより洗浄された後に接合される。また、上蓋部材2への半導体素子61の実装は、下蓋部材3への実装の後に行われてもよい。   Similarly, another semiconductor element 61 is irradiated with FAB on the bumps 62 of the semiconductor element 61 and the internal electrode 32 of the lower lid member 3 in a reduced pressure (vacuum) environment (step S14). The electrodes 32 are mounted on the lower lid member 3 by metal bonding that brings them into contact with each other (step S15). Note that bumps instead of the bumps 62 may be formed on the internal electrode 22 and the internal electrode 32 in advance. In this case, the lands and bumps of the semiconductor element 61 are bonded after being cleaned by FAB. Further, the mounting of the semiconductor element 61 on the upper lid member 2 may be performed after the mounting on the lower lid member 3.

上蓋部材2および下蓋部材3のそれぞれに半導体素子61が実装されると、チャンバ内の減圧(真空)環境下において下蓋部材3の金属部522、および、筒状部材4の(−Z)側の金属部521にFABが照射され、両金属部の表面が洗浄される(ステップS16)。このとき両金属部は、温度が室温以上150℃以下となるよう、必要に応じてレーザ光の照射等により加熱される。続いて、金属部522と金属部521とを互いに接触させることにより、両金属部が金属接合されて金属層52が形成され、下蓋部材3と筒状部材4とが接着される(ステップS17)。   When the semiconductor element 61 is mounted on each of the upper lid member 2 and the lower lid member 3, the metal portion 522 of the lower lid member 3 and the (−Z) of the cylindrical member 4 in a reduced pressure (vacuum) environment in the chamber. The metal part 521 on the side is irradiated with FAB, and the surfaces of both metal parts are cleaned (step S16). At this time, both the metal parts are heated by laser light irradiation or the like as necessary so that the temperature is not lower than room temperature and not higher than 150 ° C. Subsequently, by bringing the metal part 522 and the metal part 521 into contact with each other, the metal parts are joined to each other to form the metal layer 52, and the lower lid member 3 and the tubular member 4 are bonded (step S17). ).

次に、減圧(真空)環境下において上蓋部材2の金属部512、および、筒状部材4の(+Z)側の金属部511にFABが照射され、両金属部の表面が洗浄される(ステップS18)。このとき両金属部は、温度が室温以上150℃以下となるよう、必要に応じてレーザ光の照射等により加熱される。その後、金属部512と金属部511とを互いに接触させることにより、両金属部が金属接合されて金属層51が形成される。下蓋部材3により(−Z)側の開口を塞がれた筒状部材4と上蓋部材2とは金属層51により接着され、2つの半導体素子61が収納される内部空間11が減圧(真空)状態にて密閉される(ステップS19)。   Next, in a reduced pressure (vacuum) environment, the metal part 512 of the upper lid member 2 and the metal part 511 on the (+ Z) side of the tubular member 4 are irradiated with FAB, and the surfaces of both metal parts are cleaned (step) S18). At this time, both the metal parts are heated by laser light irradiation or the like as necessary so that the temperature is not lower than room temperature and not higher than 150 ° C. Thereafter, the metal part 512 and the metal part 511 are brought into contact with each other, whereby the metal parts are metal-bonded to form the metal layer 51. The cylindrical member 4 whose upper side on the (−Z) side is closed by the lower lid member 3 and the upper lid member 2 are bonded by a metal layer 51, and the internal space 11 in which the two semiconductor elements 61 are accommodated is decompressed (vacuum). ) In a closed state (step S19).

以上のように、下蓋部材3、上蓋部材2および筒状部材4が、実装された2つの半導体素子61を内側(内部空間11側)に向けつつ接着されることにより容器10が形成されて電子素子パッケージ1が製造される。なお、半導体素子61の実装、および、各金属部の接合は不活性ガス環境下にて行われてもよく、この場合、半導体素子61が封止される内部空間11には不活性ガスが封入される。また、不活性ガス環境下における封止時にチャンバ内が減圧(大気圧から1Pa(パスカル)〜10Pa程度の減圧でよい。)されてもよい。   As described above, the container 10 is formed by bonding the lower lid member 3, the upper lid member 2, and the cylindrical member 4 with the two mounted semiconductor elements 61 facing inward (inside the internal space 11). The electronic element package 1 is manufactured. The mounting of the semiconductor element 61 and the joining of each metal part may be performed in an inert gas environment. In this case, an inert gas is sealed in the internal space 11 in which the semiconductor element 61 is sealed. Is done. Further, the inside of the chamber may be depressurized at the time of sealing in an inert gas environment (from atmospheric pressure to 1 Pa (pascal) to 10 Pa may be reduced).

電子素子パッケージ1では、上面21に実装された半導体素子61と外部電極23、および、下面31に実装された半導体素子61と外部電極33とが互いに電気的に接続されているため、電子素子パッケージ1が外部基板に実装されることにより、外部基板と2つの半導体素子61とが電気的に接続される。電子素子パッケージ1の外部基板への実装は、例えば、外部電極33が異方導電性樹脂フィルムを介して外部基板上の電極と接続され、外部電極23がワイヤボンディングにより外部基板上の電極と接続されることにより行われ、複数の電子素子パッケージ1が外部基板上に高密度にて配置される。   In the electronic element package 1, the semiconductor element 61 and the external electrode 23 mounted on the upper surface 21 and the semiconductor element 61 and the external electrode 33 mounted on the lower surface 31 are electrically connected to each other. By mounting 1 on the external substrate, the external substrate and the two semiconductor elements 61 are electrically connected. For example, the external element 33 is connected to an electrode on the external substrate through an anisotropic conductive resin film, and the external electrode 23 is connected to an electrode on the external substrate by wire bonding. As a result, the plurality of electronic device packages 1 are arranged on the external substrate at a high density.

以上に説明したように、電子素子パッケージ1では、2つの半導体素子61が外部電極が形成された多層基板である上蓋部材2および下蓋部材3にそれぞれ直接実装されるため、パッケージの構造を微小な電子素子の高密度な配置に適したものとすることができる。また、半導体素子61がそれぞれ実装された上蓋部材2および下蓋部材3により筒状部材4の両端の開口が塞がれて容器10が形成されることにより、2つの半導体素子61が内部空間11の対向する2つの面(上面21および下面31)に実装されるため、電子素子パッケージ1を容易に製造することができる。   As described above, in the electronic element package 1, since the two semiconductor elements 61 are directly mounted on the upper lid member 2 and the lower lid member 3 which are multilayer substrates on which external electrodes are formed, the package structure is very small. The electronic device can be suitable for high-density arrangement of electronic devices. Further, the opening 10 at both ends of the cylindrical member 4 is closed by the upper lid member 2 and the lower lid member 3 on which the semiconductor elements 61 are mounted, so that the container 10 is formed. Are mounted on the two opposing surfaces (upper surface 21 and lower surface 31), the electronic element package 1 can be easily manufactured.

電子素子パッケージ1では、溶接等による場合に比べて低温(通常のはんだやガラスパウダー接合に比べて低温であり、好ましくは、室温以上150℃以下)にて筒状部材4とと上蓋部材2および下蓋部材3とがそれぞれ接着され、半導体素子61が収納された内部空間11が密閉される。その結果、耐熱性の低い半導体素子61であっても熱による損傷を与えることなく低温にて内部空間11に収納することができる。また、セラミックや金属等に比べて耐熱性は低いが安価な樹脂製の上蓋部材2、下蓋部材3および筒状部材4を使用することができ、電子素子パッケージ1の製造コストを削減することができる。   In the electronic element package 1, the tubular member 4, the upper lid member 2, and the upper cover member 2 at a lower temperature than those obtained by welding or the like (lower temperature than normal solder or glass powder bonding, preferably from room temperature to 150 ° C.). The lower lid member 3 is bonded to each other, and the internal space 11 in which the semiconductor element 61 is accommodated is sealed. As a result, even the semiconductor element 61 having low heat resistance can be stored in the internal space 11 at a low temperature without being damaged by heat. In addition, the lower cover member 2, lower cover member 3, and cylindrical member 4 made of resin, which have lower heat resistance than ceramics and metals, but are inexpensive, can be used, and the manufacturing cost of the electronic element package 1 is reduced. Can do.

電子素子パッケージ1では、各金属部が原子間の強い結合力により接合されるため、各部材同士の接着の信頼性が高められるとともに高い密閉性を有する内部空間11を形成することができる。また、金属層51および52が化学的に安定した(化学変化しにくい)金により形成されるため、内部空間11の密閉の信頼性が向上される。   In the electronic element package 1, the metal parts are bonded by a strong bonding force between atoms, so that the reliability of adhesion between the members can be improved and the internal space 11 having high hermeticity can be formed. Further, since the metal layers 51 and 52 are made of chemically stable (not easily chemically changed) gold, the reliability of sealing the internal space 11 is improved.

さらに、内部空間11が減圧(真空)状態あるいは不活性ガス雰囲気とされるため、半導体素子61を大気中に存在する水分や酸素等の影響から守ることができ、これらの影響による半導体素子61の性能劣化を抑制することができる。このように、電子素子パッケージ1は、耐熱性が低く、かつ、耐湿性も低い半導体素子61の封止にも適している。   Furthermore, since the internal space 11 is in a reduced pressure (vacuum) state or an inert gas atmosphere, the semiconductor element 61 can be protected from the influence of moisture, oxygen, etc. existing in the atmosphere. Performance degradation can be suppressed. Thus, the electronic element package 1 is suitable for sealing the semiconductor element 61 having low heat resistance and low moisture resistance.

図4は、本発明の第2の実施の形態に係る電子素子パッケージ1aの構成を示す断面図である。電子素子パッケージ1aは、図1に示す電子素子パッケージ1の筒状部材4に代えて、2つの半導体素子61が実装された樹脂製の筒状部材4aを備える。その他の構成は図1と同様であり、以下の説明において同符号を付す。図4に示すように、電子素子パッケージ1aでは、内部空間11の上面21および下面31、並びに、側面のうちX方向に略垂直に対向する2つの面(以下、「実装側面」という。)410のそれぞれに1つずつ、合計4つの半導体素子61が実装される。   FIG. 4 is a cross-sectional view showing a configuration of an electronic element package 1a according to the second embodiment of the present invention. The electronic element package 1a includes a resin-made cylindrical member 4a on which two semiconductor elements 61 are mounted, instead of the cylindrical member 4 of the electronic element package 1 shown in FIG. Other configurations are the same as those in FIG. 1, and the same reference numerals are given in the following description. As shown in FIG. 4, in the electronic element package 1 a, the upper surface 21 and the lower surface 31 of the internal space 11 and two surfaces (hereinafter referred to as “mounting side surfaces”) 410 that are substantially perpendicular to the X direction among the side surfaces. A total of four semiconductor elements 61 are mounted, one for each.

図5は、筒状部材4aおよび筒状部材4aに実装される半導体素子61を示す分解斜視図である。筒状部材4aは、それぞれに1つの半導体素子61が実装される2つの側壁部材45、および、2つの側壁部材45を接続する2つの接続部材46を備える。側壁部材45の実装側面410のうち接続部材46が接着される領域には、金(Au)により形成される金属部531が設けられる。接続部材46の接着部位であるX方向の両端面にも同様に、金(Au)により形成される金属部532が設けられ、金属部531と金属部532とが金属接合されることにより側壁部材45と接続部材46とが接着されて筒状部材4aが形成される。   FIG. 5 is an exploded perspective view showing the tubular member 4a and the semiconductor element 61 mounted on the tubular member 4a. The cylindrical member 4 a includes two side wall members 45 on which one semiconductor element 61 is mounted, and two connection members 46 that connect the two side wall members 45. A metal portion 531 formed of gold (Au) is provided in a region of the mounting side surface 410 of the side wall member 45 to which the connection member 46 is bonded. Similarly, metal parts 532 formed of gold (Au) are also provided on both end faces in the X direction, which are adhesion parts of the connection member 46, and the metal part 531 and the metal part 532 are metal-bonded to form a side wall member. 45 and the connecting member 46 are bonded together to form the tubular member 4a.

側壁部材45は、樹脂により形成される平坦な多層基板であり、図4に示すように実装側面410上に形成された内部電極42、および、実装側面410の外側の面411上に形成された外部電極43を備え、内部電極42と外部電極43とは側壁部材45を貫通するビア44によって電気的に接続される。筒状部材4aでは、半導体素子61が側壁部材45に実装されることにより、外部電極43と電気的に接続される。   The side wall member 45 is a flat multilayer substrate formed of resin, and is formed on the inner electrode 42 formed on the mounting side surface 410 and the outer surface 411 of the mounting side surface 410 as shown in FIG. The external electrode 43 is provided, and the internal electrode 42 and the external electrode 43 are electrically connected by a via 44 penetrating the side wall member 45. In the tubular member 4 a, the semiconductor element 61 is mounted on the side wall member 45 so that it is electrically connected to the external electrode 43.

図6は、電子素子パッケージ1aの製造工程の一部を示す図である。電子素子パッケージ1aが製造される際には、図3のステップS12〜S19の工程に先立って図6に示す工程が実施される。まず、図5に示す側壁部材45および接続部材46のそれぞれの接着部位に金メッキが施され、金属部531および532が形成される(ステップS21)。   FIG. 6 is a diagram showing a part of the manufacturing process of the electronic element package 1a. When the electronic device package 1a is manufactured, the steps shown in FIG. 6 are performed prior to the steps S12 to S19 in FIG. First, gold plating is applied to the adhesion portions of the side wall member 45 and the connection member 46 shown in FIG. 5 to form metal portions 531 and 532 (step S21).

続いて、図4に示す上蓋部材2および下蓋部材3のそれぞれの接着部位に金メッキが施され、金属部512および522が形成される。また、筒状部材4aを形成する側壁部材45および接続部材46のZ方向の端面(互いに接着されて筒状部材4aが形成された際の筒状部材4aの接着部位に相当する部位)に金メッキが施され、金属部511および521(正確には、筒状部材4aが形成された際に環状の金属部511および521となる金属部)がそれぞれ形成される(ステップS22)。   Subsequently, the gold plating is applied to the bonding portions of the upper lid member 2 and the lower lid member 3 shown in FIG. 4 to form the metal portions 512 and 522. Further, the side wall member 45 forming the cylindrical member 4a and the end surface in the Z direction of the connection member 46 (the portion corresponding to the bonding portion of the cylindrical member 4a when bonded to each other to form the cylindrical member 4a) are gold-plated. Are applied to form metal parts 511 and 521 (more precisely, metal parts that become annular metal parts 511 and 521 when cylindrical member 4a is formed) (step S22).

上記の各金属部の形成が終了すると、上蓋部材2、下蓋部材3、側壁部材45、接続部材46および4つの半導体素子61が、接合装置のロードロックを経由して予め減圧(真空)状態とされているチャンバ内に配置され、2つの半導体素子61のバンプ62、および、2つの側壁部材45の内部電極42にFABが照射されて表面が洗浄される(ステップS23)。その後、バンプ62と内部電極42とを互いに接触させる金属接合により、2つの側壁部材45の実装側面410のそれぞれに1つの半導体素子61が実装される(ステップS24)。   When the formation of each metal part is completed, the upper lid member 2, the lower lid member 3, the side wall member 45, the connection member 46, and the four semiconductor elements 61 are previously in a reduced pressure (vacuum) state via the load lock of the bonding apparatus. The bumps 62 of the two semiconductor elements 61 and the internal electrodes 42 of the two side wall members 45 are irradiated with FAB to clean the surface (step S23). Thereafter, one semiconductor element 61 is mounted on each of the mounting side surfaces 410 of the two side wall members 45 by metal bonding in which the bump 62 and the internal electrode 42 are brought into contact with each other (step S24).

続いて、チャンバ内の減圧(真空)環境下において、図5に示す側壁部材45の金属部531および532にアルゴンのFABが照射され、両金属部の表面が洗浄される(ステップS25)。このとき両金属部は、温度が室温以上150℃以下となるよう、必要に応じてレーザ光の照射等により加熱される。次に、金属部531と金属部532とを互いに接触さて両金属部を金属接合する作業を繰り返して2つの側壁部材45と2つの接続部材46とが順次接着され、筒状部材4aが形成される(ステップS26)。   Subsequently, in a reduced pressure (vacuum) environment in the chamber, the metal parts 531 and 532 of the side wall member 45 shown in FIG. 5 are irradiated with argon FAB, and the surfaces of both metal parts are cleaned (step S25). At this time, both the metal parts are heated by laser light irradiation or the like as necessary so that the temperature is not lower than room temperature and not higher than 150 ° C. Next, the metal part 531 and the metal part 532 are brought into contact with each other and the work of metal joining the two metal parts is repeated, whereby the two side wall members 45 and the two connection members 46 are sequentially bonded to form the cylindrical member 4a. (Step S26).

その後、未実装の2つの半導体素子61のうち1つの半導体素子61のバンプ62、および、上蓋部材2の内部電極22にFABが照射され(図3:ステップS12)、バンプ62と内部電極22とが金属接合されて半導体素子61が上蓋部材2に実装される(ステップS13)。同様に、もう1つの半導体素子61のバンプ62、および、下蓋部材3の内部電極32にFABが照射され(ステップS14)、バンプ62と内部電極32とが金属接合されて半導体素子61が下蓋部材3に実装される(ステップS15)。   Thereafter, the FAB is irradiated to the bumps 62 of one of the two unmounted semiconductor elements 61 and the internal electrode 22 of the upper lid member 2 (FIG. 3: step S12). Are bonded to each other and the semiconductor element 61 is mounted on the upper lid member 2 (step S13). Similarly, the bump 62 of the other semiconductor element 61 and the internal electrode 32 of the lower lid member 3 are irradiated with FAB (step S14), and the bump 62 and the internal electrode 32 are metal-bonded to bring the semiconductor element 61 down. It is mounted on the lid member 3 (step S15).

続いて、下蓋部材3の金属部522、および、筒状部材4aの金属部521にFABが照射され(ステップS16)、両金属部が金属接合されて下蓋部材3と筒状部材4aとが接着される(ステップS17)。そして、上蓋部材2の金属部512、および、筒状部材4aの金属部511にFABが照射され(ステップS18)、両金属部が金属接合されて上蓋部材2と筒状部材4aとが接着され、4つの半導体素子61が収納される内部空間11が減圧(真空)状態にて密閉される(ステップS19)。以上のように、下蓋部材3、上蓋部材2および2つの側壁部材45が、実装された半導体素子61を内側(内部空間11側)に向けつつ互いに、あるいは、接続部材46と接着されることにより容器10が形成され、4つの半導体素子61が収納される電子素子パッケージ1aが製造される。   Subsequently, the metal part 522 of the lower lid member 3 and the metal part 521 of the cylindrical member 4a are irradiated with FAB (step S16), and both the metal parts are metal-bonded to form the lower lid member 3 and the cylindrical member 4a. Is bonded (step S17). Then, the metal part 512 of the upper lid member 2 and the metal part 511 of the cylindrical member 4a are irradiated with FAB (step S18), both the metal parts are metal-bonded, and the upper lid member 2 and the cylindrical member 4a are bonded. The internal space 11 in which the four semiconductor elements 61 are accommodated is sealed in a reduced pressure (vacuum) state (step S19). As described above, the lower lid member 3, the upper lid member 2, and the two side wall members 45 are bonded to each other or the connection member 46 while the mounted semiconductor element 61 faces the inner side (inside the internal space 11). Thus, the container 10 is formed, and the electronic element package 1a in which the four semiconductor elements 61 are accommodated is manufactured.

なお、下蓋部材3および上蓋部材2への半導体素子61の実装は、側壁部材45と接続部材46との接着に先立って行われてもよく、また、各部材への実装の順番は適宜入れ替えられてもよい。また、上蓋部材2および下蓋部材3と筒状部材4aとの接着は不活性ガス環境下にて行われてもよく、この場合、内部空間11には不活性ガスが封入される。さらには、不活性ガス環境下における封止時にチャンバ内が減圧(大気圧から1Pa(パスカル)〜10Pa程度の減圧でよい。)されてもよい。   The mounting of the semiconductor element 61 on the lower lid member 3 and the upper lid member 2 may be performed prior to the bonding of the side wall member 45 and the connection member 46, and the order of mounting on each member is appropriately changed. May be. The upper lid member 2 and the lower lid member 3 may be bonded to the cylindrical member 4a under an inert gas environment. In this case, the internal space 11 is filled with an inert gas. Further, the inside of the chamber may be depressurized (sealed from atmospheric pressure to 1 Pa (pascal) to 10 Pa may be sufficient) during sealing in an inert gas environment.

以上に説明したように、電子素子パッケージ1aでは、4つの半導体素子61を外部電極が形成された多層基板を組み合わせて形成される内部空間11の上面21、下面31および側面41(の実装側面410)に直接実装することにより、パッケージの構造を微小な電子素子の高密度な配置により適したものとすることができる。また、平坦な部材である上蓋部材2、下蓋部材3および側壁部材45に半導体素子61を実装した後に各部材を接着して容器10を形成するため、容器10内部に半導体素子61を容易に実装することができ、電子素子パッケージ1aを容易に製造することができる。   As described above, in the electronic device package 1a, the upper surface 21, the lower surface 31 and the side surface 41 (mounting side surface 410) of the internal space 11 formed by combining the four semiconductor elements 61 with the multilayer substrate on which the external electrodes are formed. ), The package structure can be more suitable for high-density arrangement of minute electronic elements. Further, since the container 10 is formed by adhering each member after the semiconductor element 61 is mounted on the upper cover member 2, the lower cover member 3, and the side wall member 45, which are flat members, the semiconductor element 61 is easily placed inside the container 10. The electronic device package 1a can be easily manufactured.

電子素子パッケージ1aは、電子素子パッケージ1と同様に、耐熱性の低い半導体素子61であっても熱による損傷を与えることなく低温にて内部空間11に収納することができ、安価な樹脂製の部材を使用可能とすることで電子素子パッケージ1aの製造コストを削減することができる。   Similarly to the electronic element package 1, the electronic element package 1a can be housed in the internal space 11 at a low temperature without being damaged by heat even if the semiconductor element 61 has low heat resistance, and is made of an inexpensive resin. By making the members usable, the manufacturing cost of the electronic element package 1a can be reduced.

さらに、内部空間11を減圧(真空)状態あるいは不活性ガス雰囲気として半導体素子61を大気中に存在する水分や酸素等の影響から守ることができる。また、容器10を形成する各部材が金により形成される各金属部の原子間の結合により接着されているため、高い密閉性を有する内部空間11を形成することができるだけでなく、内部空間11の密閉の信頼性も向上される。   Furthermore, the semiconductor element 61 can be protected from the influence of moisture, oxygen, etc. existing in the atmosphere by setting the internal space 11 to a reduced pressure (vacuum) state or an inert gas atmosphere. In addition, since each member forming the container 10 is bonded by bonding between atoms of each metal part formed of gold, not only the internal space 11 having high hermeticity can be formed, but also the internal space 11 The reliability of sealing is also improved.

図7は、本発明の第3の実施の形態に係る電子素子パッケージ1bの構成を示す断面図である。電子素子パッケージ1bは、半導体素子61の実装方法が異なる点を除き、図1に示す電子素子パッケージ1と同様であり、以下の説明において同符号を付す。   FIG. 7 is a cross-sectional view showing a configuration of an electronic device package 1b according to the third embodiment of the present invention. The electronic element package 1b is the same as the electronic element package 1 shown in FIG. 1 except that the mounting method of the semiconductor element 61 is different, and the same reference numerals are given in the following description.

図7に示す電子素子パッケージ1bでは、2つの半導体素子61はそれぞれ、内部空間11の上面21および下面31上に付与された熱硬化性を有する樹脂7を介してそれぞれの面に実装される。   In the electronic device package 1 b shown in FIG. 7, the two semiconductor devices 61 are mounted on the respective surfaces via the thermosetting resin 7 provided on the upper surface 21 and the lower surface 31 of the internal space 11.

図8は、電子素子パッケージ1bの製造工程のうち半導体素子61の実装工程を示す図であり、図3中のステップS12〜S15に対応する。図7に示す電子素子パッケージ1bでは、まず、上蓋部材2の内部電極22および下蓋部材3の内部電極32上に樹脂7が付与される(ステップS31)。樹脂7は、導電性粒子が内部に均一に分散した絶縁性樹脂により形成される異方導電性樹脂フィルム(ACF(Anisotropic Conductive Film))である。1つの半導体素子61が、上蓋部材2上に付与された樹脂7上から押圧されて加熱されることにより上蓋部材2に固着され、バンプ62が内部電極22と樹脂7内の導電性粒子を介して電気的に接合されることにより上蓋部材2に実装される(ステップS32)。もう1つの半導体素子61も同様に、下蓋部材3に付与された樹脂7上から押圧されて加熱されることによりバンプ62が内部電極32に接続され、下蓋部材3に実装される(ステップS33)。この場合、半導体素子61の実装はチャンバ内にて行われる必要はない。   FIG. 8 is a diagram showing a mounting process of the semiconductor element 61 in the manufacturing process of the electronic element package 1b, and corresponds to steps S12 to S15 in FIG. In the electronic device package 1b shown in FIG. 7, first, the resin 7 is applied on the internal electrode 22 of the upper lid member 2 and the internal electrode 32 of the lower lid member 3 (step S31). The resin 7 is an anisotropic conductive resin film (ACF (Anisotropic Conductive Film)) formed of an insulating resin in which conductive particles are uniformly dispersed inside. One semiconductor element 61 is pressed and heated from above the resin 7 applied on the upper lid member 2 to be fixed to the upper lid member 2, and the bump 62 is interposed between the internal electrode 22 and the conductive particles in the resin 7. Then, it is mounted on the upper lid member 2 by being electrically joined (step S32). Similarly, the other semiconductor element 61 is pressed and heated from above the resin 7 applied to the lower lid member 3 so that the bumps 62 are connected to the internal electrode 32 and mounted on the lower lid member 3 (step). S33). In this case, the semiconductor element 61 need not be mounted in the chamber.

なお、樹脂7として、異方導電性樹脂ペースト(ACP(Anisotropic Conductive Paste))、非導電性樹脂フィルム(NCF(Non-Conductive Film))、あるいは、非導電性樹脂ペースト(NCP(Non-Conductive Paste))が用いられてもよく、これらの樹脂は加熱処理以外の他の処理により硬化する性質を有していてもよい。いずれの場合であっても、半導体素子61を外部電極が形成された多層基板である上蓋部材2および下蓋部材3に直接実装することができるため、電子素子パッケージ1bの構造を微小な電子素子の高密度な配置に適したものとすることができる。   As the resin 7, anisotropic conductive resin paste (ACP (Anisotropic Conductive Paste)), non-conductive resin film (NCF (Non-Conductive Film)), or non-conductive resin paste (NCP (Non-Conductive Paste)). )) May be used, and these resins may have a property of being cured by a treatment other than the heat treatment. In any case, since the semiconductor element 61 can be directly mounted on the upper lid member 2 and the lower lid member 3 that are multilayer substrates on which external electrodes are formed, the structure of the electronic element package 1b can be reduced to a minute electronic element. It can be suitable for a high density arrangement.

図9は、本発明の第4の実施の形態に係る電子素子パッケージ1cの構成を示す断面図である。電子素子パッケージ1cは、図1に示す電子素子パッケージ1の筒状部材4、下蓋部材3および両部材を接着する金属層52に代えて、キャビティ(凹部)13を有する部材(以下、「キャビティ基板」という。)12を備える。その他の構成は図1と同様であり、以下の説明において同符号を付す。電子素子パッケージ1cでは、キャビティ基板12と上蓋部材2とが接着されて容器10が形成される。   FIG. 9 is a cross-sectional view showing a configuration of an electronic device package 1c according to the fourth embodiment of the present invention. An electronic element package 1c is a member having a cavity (recessed portion) 13 (hereinafter referred to as "cavity") instead of the cylindrical member 4, the lower lid member 3 and the metal layer 52 for bonding both members of the electronic element package 1 shown in FIG. Substrate)) 12. Other configurations are the same as those in FIG. 1, and the same reference numerals are given in the following description. In the electronic device package 1c, the cavity substrate 12 and the upper lid member 2 are bonded to form the container 10.

キャビティ基板12は、底部となる平坦なセラミック基板上に側壁となるセラミック層を積層することにより形成される。通常、1枚のセラミック基板上に格子状に複数のキャビティが形成され、この基板を切り分けることによりキャビティ基板12が形成される。   The cavity substrate 12 is formed by laminating a ceramic layer serving as a side wall on a flat ceramic substrate serving as a bottom. Usually, a plurality of cavities are formed in a lattice pattern on one ceramic substrate, and the cavity substrate 12 is formed by cutting the substrates.

キャビティ基板12の底部および側壁はそれぞれ、図1に示す下蓋部材3および筒状部材4と同等の役割を果たし、キャビティ13の底面(キャビティ基板12の底部の(+Z)側の面、すなわち、内部空間11の下面31)には半導体素子61が実装される。電子素子パッケージ1cは、上蓋部材2の(−Z)側の面、すなわち、内部空間11の上面21となる面であってキャビティ13の開口部を塞ぐ面にもう1つの半導体素子61が実装された状態にて、上蓋部材2とキャビティ基板12とが第1の実施の形態と同様の手法(図3のステップS18,S19)にて金属層51により接着されることにより内部空間11が密閉されて形成される。このため、電子素子パッケージ1cを容易に製造することができる。なお、半導体素子61の実装は第1の実施の形態と同様に金属接合により行われてもよく、第3の実施の形態のように樹脂を介して行われてもよい。   The bottom and side walls of the cavity substrate 12 play the same role as the lower lid member 3 and the cylindrical member 4 shown in FIG. 1, respectively, and the bottom surface of the cavity 13 (the (+ Z) side surface of the bottom of the cavity substrate 12, that is, A semiconductor element 61 is mounted on the lower surface 31) of the internal space 11. In the electronic element package 1 c, another semiconductor element 61 is mounted on the (−Z) side surface of the upper lid member 2, that is, the surface that becomes the upper surface 21 of the internal space 11 and closes the opening of the cavity 13. In this state, the upper lid member 2 and the cavity substrate 12 are bonded by the metal layer 51 by the same method (steps S18 and S19 in FIG. 3) as in the first embodiment, so that the internal space 11 is sealed. Formed. For this reason, the electronic element package 1c can be manufactured easily. The mounting of the semiconductor element 61 may be performed by metal bonding as in the first embodiment, or may be performed via a resin as in the third embodiment.

以上、本発明の実施の形態について説明してきたが、本発明は上記実施の形態に限定されるものではなく、様々な変更が可能である。例えば、上蓋部材2、下蓋部材3および筒状部材4は、製造コスト削減の観点からは樹脂により形成されることが好ましいが、金属やセラミック等の他の材料により形成されてもよい。また、容器10を形成する各部材を接着する金属部は、内部空間11の密閉の信頼性向上の観点から金により形成されることが好ましいが、他の様々な金属により形成されてもよい。   Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the upper lid member 2, the lower lid member 3, and the cylindrical member 4 are preferably formed of a resin from the viewpoint of manufacturing cost reduction, but may be formed of other materials such as metal or ceramic. Moreover, although the metal part which adhere | attaches each member which forms the container 10 is preferable to form with gold | metal | money from a viewpoint of the reliability improvement of the sealing of the internal space 11, it may be formed with other various metals.

上記実施の形態では、FABとしてアルゴンが使用されるが、窒素、水素等の他の原子もFABとして利用可能である。また、FABに代えて、イオンビーム等の他のエネルギー波により金属部や電極の洗浄が行われてもよい。   In the above embodiment, argon is used as the FAB, but other atoms such as nitrogen and hydrogen can also be used as the FAB. Further, instead of FAB, the metal part and the electrode may be cleaned by other energy waves such as an ion beam.

容器10は、必ずしも上記実施の形態に示す形状の部材の接着により形成される必要はなく、他の様々な形状を有する部材が接着されることにより形成されてもよい。例えば、それぞれキャビティ構造を有する2つの基板が、キャビティの開口部を互いに塞ぐように接着されて内部空間11が形成されてもよい。また、部材同士の接着は、樹脂を主成分とする接着剤等により行われてもよい。   The container 10 does not necessarily have to be formed by bonding the members having the shapes shown in the above embodiment, and may be formed by bonding members having other various shapes. For example, the internal space 11 may be formed by bonding two substrates each having a cavity structure so as to close the opening of the cavity. Moreover, adhesion | attachment of members may be performed by the adhesive agent etc. which have resin as a main component.

半導体素子61の実装は上記以外の手法により行われてもよく、例えば、バンプ62と内部電極22とが当接した状態で、半導体素子61が押圧されつつ超音波振動が付与されることによりバンプ62と内部電極22とが接合されて実装されてもよい。また、複数の半導体素子61が実装される容器10の面は、上記実施の形態に示す組み合わせに限定されるわけではなく、適宜変更されてよい。すなわち、内部空間11の上面21、下面31および4つの側面41のうちの少なくとも一の面と他の一の面に電子素子を実装することにより、微小な電子素子の高密度配置が実現される。   The mounting of the semiconductor element 61 may be performed by a method other than the above. For example, the bump is formed by applying ultrasonic vibration while the semiconductor element 61 is pressed while the bump 62 and the internal electrode 22 are in contact with each other. 62 and the internal electrode 22 may be joined and mounted. Further, the surface of the container 10 on which the plurality of semiconductor elements 61 are mounted is not limited to the combination shown in the above embodiment, and may be changed as appropriate. That is, by mounting electronic elements on at least one of the upper surface 21, the lower surface 31 and the four side surfaces 41 of the internal space 11 and the other surface, a high-density arrangement of minute electronic elements is realized. .

電子素子パッケージ1は、半導体素子以外の様々な種類の電子素子、例えばSAW(Surface Acoustic Wave:表面弾性波)フィルタ等を収納する電子素子パッケージとしても利用可能である。   The electronic element package 1 can also be used as an electronic element package that houses various types of electronic elements other than semiconductor elements, such as SAW (Surface Acoustic Wave) filters.

本発明は、半導体素子やその他様々な種類の電子素子を収納する電子素子パッケージにおいて利用可能である。   The present invention can be used in an electronic device package that houses a semiconductor device and various other types of electronic devices.

第1の実施の形態に係る電子素子パッケージの構成を示す断面図Sectional drawing which shows the structure of the electronic element package which concerns on 1st Embodiment 電子素子パッケージを示す分解斜視図An exploded perspective view showing an electronic device package 電子素子パッケージの製造工程を示す図Diagram showing manufacturing process of electronic device package 第2の実施の形態に係る電子素子パッケージの構成を示す断面図Sectional drawing which shows the structure of the electronic element package which concerns on 2nd Embodiment 筒状部材および筒状部材に実装される半導体素子を示す分解斜視図The exploded perspective view which shows the semiconductor element mounted in a cylindrical member and a cylindrical member 電子素子パッケージの製造工程を示す図Diagram showing manufacturing process of electronic device package 第3の実施の形態に係る電子素子パッケージの構成を示す断面図Sectional drawing which shows the structure of the electronic element package which concerns on 3rd Embodiment 半導体素子の実装工程を示す図Diagram showing the mounting process of semiconductor elements 第4の実施の形態に係る電子素子パッケージの構成を示す断面図Sectional drawing which shows the structure of the electronic element package which concerns on 4th Embodiment

符号の説明Explanation of symbols

1,1a,1b,1c 電子素子パッケージ
2 上蓋部材
3 下蓋部材
4,4a 筒状部材
7 樹脂
10 容器
11 内部空間
12 キャビティ基板
13 キャビティ
21 上面
22,32,42 内部電極
23,33,43 外部電極
31 下面
41 側面
51 金属層
61 半導体素子
62 バンプ
211,311,411 面
511,512 金属部
S11〜S19,S21〜S26,S31〜S33 ステップ
1, 1a, 1b, 1c Electronic device package 2 Upper lid member 3 Lower lid member 4, 4a Cylindrical member 7 Resin 10 Container 11 Internal space 12 Cavity substrate 13 Cavity 21 Upper surface 22, 32, 42 Internal electrodes 23, 33, 43 External Electrode 31 Lower surface 41 Side surface 51 Metal layer 61 Semiconductor element 62 Bump 211, 311, 411 Surface 511, 512 Metal part
Steps S11 to S19, S21 to S26, S31 to S33

Claims (1)

外面に外部電極を有し、内面に内部電極を有し、前記外部電極と内部電極とをビアを介して接続し、かつ、内部電極に電子素子をバンプにて接続した上蓋部材と、
外面に外部電極を有し、内面に内部電極を有し、前記外部電極と内部電極とをビアを介して接続し、かつ、内部電極に電子素子をバンプにて接続した下蓋部材と、
複数の側壁部材からなり、少なくとも一つの側壁部材は、その外面に外部電極を有し、内面に内部電極を有し、前記外部電極と内部電極とをビアを介して接続したものであり、かつ、前記内部電極に前記電子素子をバンプにて接続したものであるところの前記上蓋部材と前記下蓋部材とを接続する筒状部材と、
前記筒状部材に設けられ前記上蓋部材及び前記下蓋部材と前記筒状部材とを接着して内部空間を密閉する金属部を備え、
前記金属部は金からなるものとし、前記内部空間が減圧状態または不活性ガスで充填されていることを特徴とする電子素子パッケージ。
An external electrode on the outer surface, an internal electrode on the inner surface, the external electrode and the internal electrode are connected via vias, and an upper lid member in which an electronic element is connected to the internal electrode by a bump;
An outer electrode on the outer surface, an inner electrode on the inner surface, the external electrode and the internal electrode are connected via vias, and a lower lid member in which an electronic element is connected to the internal electrode by a bump;
It comprises a plurality of side wall members, and at least one side wall member has an external electrode on its outer surface, an internal electrode on its inner surface, and the external electrode and the internal electrode are connected via vias, and A cylindrical member for connecting the upper lid member and the lower lid member , wherein the electronic element is connected to the internal electrode by a bump ,
A metal part that is provided on the cylindrical member and seals the internal space by bonding the upper lid member and the lower lid member and the cylindrical member;
The electronic device package according to claim 1, wherein the metal part is made of gold, and the internal space is filled with a reduced pressure state or an inert gas.
JP2003420643A 2003-12-05 2003-12-18 Electronic device package Expired - Fee Related JP4134900B2 (en)

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