JP4093818B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4093818B2
JP4093818B2 JP2002230409A JP2002230409A JP4093818B2 JP 4093818 B2 JP4093818 B2 JP 4093818B2 JP 2002230409 A JP2002230409 A JP 2002230409A JP 2002230409 A JP2002230409 A JP 2002230409A JP 4093818 B2 JP4093818 B2 JP 4093818B2
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Prior art keywords
groove
die pad
semiconductor element
conductive foil
insulating resin
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Expired - Fee Related
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JP2002230409A
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Japanese (ja)
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JP2004071898A (en
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幸嗣 高橋
則明 坂本
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to JP2002230409A priority Critical patent/JP4093818B2/en
Priority to TW092118684A priority patent/TWI240603B/en
Priority to KR1020030053069A priority patent/KR20040026129A/en
Priority to CNB031526179A priority patent/CN100492632C/en
Publication of JP2004071898A publication Critical patent/JP2004071898A/en
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Publication of JP4093818B2 publication Critical patent/JP4093818B2/en
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Description

【０００１】
【発明の属する技術分野】
本発明は半導体素子を固着するロウ材の流出を防止することができる回路装置およびその製造方法に関するものである。
【０００２】
【従来の技術】
従来、電子機器にセットされる回路装置は、携帯電話、携帯用のコンピューター等に採用されるため、小型化、薄型化、軽量化が求められている。例えば、回路装置として半導体装置を例にして述べると、一般的な半導体装置として、従来通常のトランスファーモールドで封止されたパッケージ型半導体装置がある。この半導体装置は、図１１のように、プリント基板ＰＳに実装される。
【０００３】
またこのパッケージ型半導体装置６１は、半導体チップ６２の周囲を樹脂層６３で被覆し、この樹脂層６３の側部から外部接続用のリード端子６４が導出されたものである。しかし、このパッケージ型半導体装置６１は、リード端子６４が樹脂層６３から外に出ており、全体のサイズが大きく、小型化、薄型化および軽量化を満足するものではなかった。そのため、各社が競って小型化、薄型化および軽量化を実現すべく、色々な構造を開発し、最近ではＣＳＰ（チップサイズパッケージ）と呼ばれる、チップのサイズと同等のウェハスケールＣＳＰ、またはチップサイズよりも若干大きいサイズのＣＳＰが開発されている。
【０００４】
図１２は、支持基板としてガラスエポキシ基板６５を採用した、チップサイズよりも若干大きいＣＳＰ６６を示すものである。ここではガラスエポキシ基板６５にトランジスタチップＴが実装されたものとして説明していく。
【０００５】
このガラスエポキシ基板６５の表面には、第１の電極６７、第２の電極６８およびダイパッド６９が形成され、裏面には第１の裏面電極７０と第２の裏面電極７１が形成されている。そしてスルーホールＴＨを介して、前記第１の電極６７と第１の裏面電極７０が、第２の電極６８と第２の裏面電極７１が電気的に接続されている。またダイパッド６９には前記ベアのトランジスタチップＴが固着され、トランジスタのエミッタ電極と第１の電極６７が金属細線７２を介して接続され、トランジスタのベース電極と第２の電極６８が金属細線７２を介して接続されている。更にトランジスタチップＴを覆うようにガラスエポキシ基板６５に樹脂層７３が設けられている。
【０００６】
前記ＣＳＰ６６は、ガラスエポキシ基板６５を採用するが、ウェハスケールＣＳＰと違い、チップＴから外部接続用の裏面電極７０、７１までの延在構造が簡単であり、安価に製造できるメリットを有する。また前記ＣＳＰ６６は、図１１のように、プリント基板ＰＳに実装される。プリント基板ＰＳには、電気回路を構成する電極、配線が設けられ、前記ＣＳＰ６６、パッケージ型半導体装置６１、チップ抵抗ＣＲまたはチップコンデンサＣＣ等が電気的に接続されて固着される。そしてこのプリント基板で構成された回路は、色々なセットの中に取り付けられていた。
【０００７】
【発明が解決しようとする課題】
しかしながら、上述したような半導体装置では、トランジスタＴは、ダイパット６９上に塗布された半田等のロウ材を融解させるリフロー工程により固着されていた。従って、トランジスタＴを融解した半田上に載置すると、半田がダイパッド６９上から流出して、ダイパッド６９と他の電極とがショートしてしまう問題があった。
【０００８】
更に、ダイパッド６９から流出した半田が、第２の電極６８に到達してしまうのを防止するために、ダイパッド６９と第２の電極６８とは離間させており、このことが装置全体の大型化を招いていた。
【０００９】
本発明はこのような問題を鑑みて成されたものであり、本発明の主な目的は、ロウ材を介して半導体素子をダイパッドに実装する際に、ロウ材がダイパッドから流出するのを防止する回路装置を提供することにある。
【００１０】
【課題を解決するための手段】
本発明の半導体装置の製造方法は、ダイパッドを含む導電パターンが凸状を呈するように上面から分離溝が形成されると共に、前記ダイパッドの領域内に前記分離溝よりも浅い溝が形成された導電箔を用意する第１工程と、前記溝に囲まれる領域の前記ダイパッドの上面に、溶融された半田を介して半導体素子を固着する第２工程と、前記半導体素子および前記導電箔の上面が被覆されると共に、前記分離溝および前記溝に充填されるように絶縁性樹脂を形成する第３工程と、前記分離溝に充填された前記絶縁性樹脂が露出するまで前記導電箔を裏面から除去する第４工程と、を具備し、前記第１工程では、前記分離溝が形成される領域に第１開口部を有し、前記溝が形成される領域に前記第１開口部よりも幅が狭い第２開口部を有するエッチングマスクにより前記導電箔の上面を被覆してエッチングを行うことにより、前記溝を前記分離溝よりも浅く形成し、前記第４工程では、前記分離溝に充填された前記絶縁性樹脂が露出すると共に、前記溝に充填された前記絶縁性樹脂が露出しない様に、前記導電箔を裏面から除去することを特徴とする。
【００２３】
【発明の実施の形態】
（回路装置１０の構成を説明する第１の実施の形態）
図１を参照して、本発明の回路装置１０の構成等を説明する。図１（Ａ）は回路装置１０の平面図であり、図１（Ｂ）は回路装置１０の断面図である。
【００２４】
図１（Ａ）および図１（Ｂ）を参照して、回路装置１０は次のような構成を有する。即ち、ロウ材１９を介して実装される半導体素子１３とほぼ同等の大きさに形成されたダイパッド１１と、ダイパッド１１に近接して設けられたボンディングパッド１２と、半導体素子１３を囲むようにダイパッド１１の周辺部に形成され且つロウ材１９が流出するのを防止する溝１４と、ダイパッド１１およびボンディングパッド１２の裏面を露出させてダイパッド１１、ボンディングパッド１２および半導体素子１３を封止する絶縁性樹脂１６等から回路装置１０は構成されている。このような各構成要素を以下にて説明する。
【００２５】
ダイパッド１１は、半導体素子１３が実装される導電パターンであり、銅箔等の金属から成り、裏面を露出させて絶縁性樹脂１６に埋め込まれている。そしてダイパッド１１の平面的な大きさは、実装される半導体素子よりも若干大きく形成され、その周辺部には溝１４が形成されている。同図（Ａ）では、ダイパッド１１が中央部に形成され、ＩＣチップ等から成る半導体素子１３がロウ材１９を介して実装されている。また、半導体素子１３が実装される領域に対応するダイパッド１１の表面には、Ａｇ等から成るメッキ膜が形成されている。
【００２６】
ボンディングパッド１２は、金属細線１５がボンディングされる導電パターンであり、裏面を露出させて絶縁性樹脂１６に埋め込まれている。ここでは、装置の中央部に形成されたダイパッド１１を囲むように円形状の多数個のボンディングパッド１２が形成されている。同図（Ａ）に於いて、ダイパッド１１の左右両側に形成されたボンディングパッド１２Ａは、電気的に独立して設けられている。そして、ダイパッド１１の上下両側に形成されたボンディングパッド１２Ｂは、ダイパッド１１と連続して形成されており、電気的にも繋がっている。そして、ボンディングパッド１２の表面には、ボンディングされる金属細線の接着性を向上させるために、Ａｇ等から成るメッキ膜が形成されている。
【００２７】
半導体素子１３は、ロウ材１９を介してダイパッド１１の表面に実装され、ここでは半導体素子のなかでも比較的大型のＩＣチップがロウ材１９を介して実装されている。そして、金属細線１５を介して、半導体素子１３の表面に形成された電極と、ボンディングパッド１２とは電気的に接続されている。また、電気的にダイパッド１１と接続されたボンディングパッド１２も、金属細線１５を介して半導体素子１３に電気的に接続されている。ここで使用するロウ材としては、半田やＡｇペースト等の導電性接着剤を使用することができる。更に、絶縁性樹脂を用いて、半導体素子１３をダイパッド１１に実装することも可能である。
【００２８】
溝１４は、半導体素子１３を囲むようにダイパッド１１の周辺部に形成されており、絶縁性樹脂１６が充填されている。また、溝１４の深さは、ダイパッド１１の厚みよりも浅く形成されている。このように、半導体素子１３が実装される領域を囲むように溝１４を形成することにより、融解したロウ材１９上部に半導体素子１３を実装する工程で、ダイパッド１１からロウ材１９が流出するのを防止することができる。具体的には、半導体素子１３が実装される領域からロウ材１９が流出しても、溝１４にロウ材１９が貯留される。従って、溝１４は、ロウ材１９がダイパッド１１から流出するのを防止する阻止領域として機能している。また、溝１４の製造方法に関しては後述するが、溝１４は分離溝１６と共にエッチングにより製造される。従って、溝１４の断面の幅は、分離溝１６の幅よりも狭く形成されている。
【００２９】
絶縁性樹脂１６は、ダイパッド１１およびボンディングパッド１２の裏面を露出させて、全体を封止している。更に、ダイパッド１１の表面に形成された溝１４にも絶縁性樹脂１６は充填されている。ここでは、半導体素子１３、金属細線１５、ダイパッド１１およびボンディングパッド１２を封止している。絶縁性樹脂１６の材料としては、トランスファーモールドにより形成される熱硬化性樹脂や、インジェクションモールドにより形成される熱可塑性樹脂を採用することができる。
【００３０】
ロウ材１９は、半田やＡｇペースト等の導電性のペーストであり、半導体素子１３とダイパッド１１とを接着させる働きを有する。ロウ材１９は導電性の材料であるので、半導体素子１３の裏面とダイパッド１１とは電気的に接続される。また、ダイパッド１１の上下両側に形成されたボンディングパッド１２Ｂは、ダイパッド１１と電気的にも接続している。従って、金属細線１５を用いて、半導体素子１３の電極とボンディングパッド１２Ｂとを接続することにより、半導体素子１３の表面に形成された回路と半導体素子１３の裏面とを電気的に接続することができる。
【００３１】
図２を参照して、回路装置の裏面に形成される外部電極１７について説明する。外部電極１７は、ダイパッド１１を囲むようにして設けられたボンディングパッド１２の裏面に形成されている。更に、ダイパッド１１の裏面にも多数個の外部電極が設けられており、従って、外部電極１７は、回路装置１０裏面の全域にマトリックス状に等間隔に多数個が設けられている。このことにより、外部電極１７を介して、マザーボード等の実装基板に回路装置１０を実装した際に、外部電極１７に作用する応力を小さくすることができる。
【００３２】
図２（Ｂ）を参照して、ダイパッド１１の裏面に形成される外部電極１７の位置および大きさは、レジスト１８の開口部により規制されている。そして、ボンディングパッド１２の裏面に形成される外部電極１７の位置および大きさは、ボンディングパッド１２の裏面により形成されている。ボンディングパッド１２の材料である銅等の金属は濡れ性が良い材料であり、この濡れ性により外部電極１７の位置および大きさは規制されている。このように、ボンディングパッド１２の裏面に形成される外部電極１７の位置および大きさを、ボンディングパッド１２の濡れ性を用いて規制することにより、レジスト１８の開口部の位置がずれた場合でも精度良く外部電極１７を形成することができる。
【００３３】
本発明の特徴は、半導体素子１３を囲むようにダイパッド１１の周辺部に溝１４を形成したことにある。即ち、融解されたロウ材１９に半導体素子１３を実装すると、半導体素子１３の重み等によりロウ材１９は周囲に広がるが、周囲に広がったロウ材１９は溝１４に貯留されるので、ダイパッド１１の表面からロウ材１９が流出してしまうのを防止することができる。従って、流出したロウ材１９がボンディングパッド１２に接触することによるパッド同士のショートを防止することができる。また、このことにより、ダイパッド１１をそこに実装される半導体素子１３とほぼ同等に形成することができる。更には、ダイパッド１１とボンディングパッド１２とを接近させて形成することが可能となり、回路装置１０全体のサイズを小さくすることができる。更にまた、このようにダイパッド１１の表面に溝１４を形成することにより、ダイパッド１１と絶縁性樹脂１６とか接触する面積を増大させることなできるので、ダイパッド１１と絶縁性樹脂１３との接着力を向上させることができる。
【００３４】
図３を参照して、他の形態の回路装置１０Ａを説明する。図３（Ａ）は回路装置１０Ａの断面図であり、図３（Ｂ）は図３（Ａ）のＸ−Ｘ’線での断面図である。回路装置１０Ａは、図１で説明した回路装置１０とほぼ同様の構成を有し、ダイパッド１１の表面に形成された溝１４で囲まれる領域に、更に、格子状に溝１４Ａが形成されている。
【００３５】
溝１４は、半導体素子１３を固着させるロウ材１９がダイパッド１１の表面から流出してしまうのを防止するのを目的として、ダイパッド１１の周辺部に設けられている。更にここでは、溝１４で囲まれる領域に、格子状に溝１４Ａが形成されている。格子状に形成される溝１４Ａも、溝１４と同じ断面形状を有する。このように格子状に溝１４を形成することにより、より多量のロウ材１９を、溝１４に貯留させることができるので、ロウ材１９がダイパッド１１の表面から流出してしまうのを防止することができる。更に、ダイパッド１１と絶縁性樹脂１６とが接触する面積を更に増大させることができるので、ダイパッド１１と絶縁性樹脂１６との密着性を向上させることができる。
【００３６】
溝１４を設けることの更なるメリットを述べる。ロウ材１９は、ディスペンサ等のロウ材を供給する機械を用いて、ダイパッド１１の表面に塗布されるが、このディスペンサで供給できるロウ材２０の最小塗布量は決まっている。従って、半導体素子１３をダイパッド１１に実装するのに必要なロウ材１９の量よりも、ディスペンサの最小塗布量が多い場合には、ロウ材１９がダイパッド１１の表面から流出する恐れがある。このことから、溝１４を設けることにより、ロウ材１９が流出してしまうのを防止することができる。
【００３７】
（回路装置１０の製造方法を説明する第２の実施の形態）
本実施例では、回路装置１０の製造方法を説明する。本実施の形態では、回路装置１０は次の様な工程で製造される。即ち、導電箔４０を用意する工程と、導電箔４０にその厚みよりも浅い分離溝１６を形成して複数個の回路装置部４５を構成するダイパッド１１およびボンディングパッド１２を形成すると同時に、固着予定の半導体素子１３の領域を囲むようにダイパッド１１に分離溝１６よりも浅い溝１４を形成する工程と、ダイパッド１１にロウ材１９を介して半導体素子１３を固着する工程と、半導体素子１３と所望のボンディングパッド１２とのワイヤボンディングを行う工程と、半導体素子１３を被覆し、分離溝１６および溝１４に充填されるように絶縁性樹脂１６で共通モールドする工程と、絶縁性樹脂１６が露出するまで導電箔４０の裏面を除去する工程と、絶縁性樹脂１６をダイシングすることにより各回路装置１０に分離する工程とから構成されている。以下に、本発明の各工程を図４〜図１０を参照して説明する。
【００３８】
本発明の第１の工程は、図４から図６に示すように、導電箔４０を用意し、導電箔４０にその厚みよりも浅い分離溝１６を形成して複数個の回路装置部４５を構成するダイパッド１１およびボンディングパッド１２を形成すると同時に、固着予定の半導体素子１３の領域を囲むようにダイパッド１１に分離溝１６よりも浅い溝１４を形成することにある。
【００３９】
本工程では、まず図４（Ａ）の如く、シート状の導電箔４０を用意する。この導電箔４０は、ロウ材の付着性、ボンディング性、メッキ性が考慮されてその材料が選択され、材料としては、Ｃｕを主材料とした導電箔、Ａｌを主材料とした導電箔またはＦｅ−Ｎｉ等の合金から成る導電箔等が採用される。
【００４０】
導電箔の厚さは、後のエッチングを考慮すると１０μｍ〜３００μｍ程度が好ましいが、３００μｍ以上でも１０μｍ以下でも基本的には良い。後述するように、導電箔４０の厚みよりも浅い分離溝１６が形成できればよい。
【００４１】
尚、シート状の導電箔４０は、所定の幅、例えば４５ｍｍでロール状に巻かれて用意され、これが後述する各工程に搬送されても良いし、所定の大きさにカットされた短冊状の導電箔４０が用意され、後述する各工程に搬送されても良い。
【００４２】
具体的には、図４（Ｂ）に示す如く、短冊状の導電箔４０に多数の回路装置部４５が形成されるブロック４２が４〜５個離間して並べられる。各ブロック４２間にはスリット４３が設けられ、モールド工程等での加熱処理で発生する導電箔４０の応力を吸収する。また導電箔４０の上下周端にはインデックス孔４４が一定の間隔で設けられ、各工程での位置決めに用いられる。続いて、導電パターンを形成する。
【００４３】
まず、図５に示す如く、導電箔６０の上に、ホトレジスト（耐エッチングマスク）ＰＲを形成し、導電パターン５１となる領域を除いた導電箔４０が露出するようにホトレジストＰＲをパターニングする。そして、図６（Ａ）に示す如く、導電箔４０を選択的にエッチングする。ここでは、導電パターン５１は、各回路装置部４５のダイパッド１１およびボンディングパッド１２を形成している。
【００４４】
図６（Ａ）を参照して、溝１４および分離溝１６が形成される箇所にはホトレジストの開口部が設けられている。そして、溝１４が形成される箇所の開口部の幅は、分離溝１６が形成される箇所よりもその幅が狭く形成されている。具体的にその幅は半分以下に形成される。エッチングによる導電箔４０の除去は等方性を持って行われるので、このように溝１４に対応するホトレジストの開口部を狭く形成することにより、溝１４の深さを分離溝１６よりも浅く形成することができる。なお、上記したエッチングの工程は、エッチャント液に導電箔４０をデッピングさせることにより行うことができる。
【００４５】
図６（Ｂ）にダイパッド１１およびボンディングパッド１２を形成する導電パターン５１を示す。本図は図４（Ｂ）で示したブロック４２の１個を拡大したもの対応する。ハッチング部分の１個が１つの回路装置部４５であり、１つのブロック４２には２行２列のマトリックス状に多数の回路装置部４５が配列され、各回路装置部４５毎に同一の導電パターン５１が設けられている。各ブロックの周辺には枠状のパターン４６が設けられ、それと少し離間しその内側にダイシング時の位置合わせマーク４７が設けられている。枠状のパターン４６はモールド金型との嵌合に使用し、また導電箔４０の裏面エッチング後には絶縁性樹脂１６の補強をする働きを有する。また、各回路装置部に於いて、ダイパッド１１の上下両側に形成されるボンディングパッド１２は、ダイパッド１１と一体化されており、電気的にも両者は接続している。
【００４６】
本発明の第２の工程は、図７に示す如く、各回路装置部４５のダイパッド１１にロウ材１９を介して半導体素子１３を固着することにある。
【００４７】
図７（Ａ）を参照して、ダイパッド１１にロウ材１９を介して半導体素子１３を実装する。ここで、ロウ材１９としては、半田またはＡｇペースト等の導電性のペーストが使用される。本工程では、ロウ材１９は融解した状態であるので、ロウ材１９の上部に半導体素子１３を載置することにより、半導体素子１３の重み等によりロウ材１９は周囲に広がる。ここで、半導体素子１３が載置される領域を囲むように、ダイパッド１１の周辺部には溝１４が形成されているので、広がったロウ材１９はダイパッド１１から流出しない。溝１４に到達したロウ材１９は、溝１４に流れ込む形となるので、溝１４は半田の流出を阻止する阻止領域として機能している。更に、絶縁性樹脂を用いて、半導体素子１３をダイパッド１１に実装することも可能である。
【００４８】
本発明の第３の工程は、図８に示す如く、半導体素子１３と所望のボンディングパッド１２とのワイヤボンディングを行うことにある。
【００４９】
具体的には、各回路装置部に実装された半導体素子１３の電極と所望のボンディングパッド１２とを、熱圧着によるボールボンディング及び超音波によるウェッヂボンディングにより一括してワイヤボンディングを行う。
【００５０】
本発明の第４の工程は、図９に示す如く、半導体素子１３を被覆し、分離溝１６および溝１４に充填されるように絶縁性樹脂１６で共通モールドすることにある。
【００５１】
本工程では、図９（Ａ）に示すように、絶縁性樹脂１６は半導体素子１３および複数のダイパッド１１およびボンディングパッド１２を完全に被覆し、分離溝１６および溝１４には絶縁性樹脂１６が充填され、分離溝４１と嵌合して強固に結合する。そして絶縁性樹脂１６によりダイパッド１１およびボンディングパッド１２が支持されている。
【００５２】
また本工程では、トランスファーモールド、インジェクションモールド、またはポッティングにより実現できる。樹脂材料としては、エポキシ樹脂等の熱硬化性樹脂がトランスファーモールドで実現でき、ポリイミド樹脂、ポリフェニレンサルファイド等の熱可塑性樹脂はインジェクションモールドで実現できる。
【００５３】
更に、本工程でトランスファーモールドあるいはインジェクションモールドする際に、図９（Ｂ）に示すように各ブロック４２は１つの共通のモールド金型に回路装置部６３を納め、各ブロック毎に１つの絶縁性樹脂１６で共通にモールドを行う。このために従来のトランスファーモールド等の様に各回路装置部を個別にモールドする方法に比べて、大幅な樹脂量の削減が図れる。
【００５４】
本工程の特徴は、絶縁性樹脂１６を被覆するまでは、導電パターン５１となる導電箔４０が支持基板となることである。従来では、本来必要としない支持基板を採用して導電パターンを形成しているが、本発明では、支持基板となる導電箔４０は、電極材料として必要な材料である。そのため、構成材料を極力省いて作業できるメリットを有し、コストの低下も実現できる。
【００５５】
また分離溝４１は、導電箔の厚みよりも浅く形成されているため、導電箔４０が導電パターン５１として個々に分離されていない。従ってシート状の導電箔４０として一体で取り扱え、絶縁性樹脂１６をモールドする際、金型への搬送、金型への実装の作業が非常に楽になる特徴を有する。
【００５６】
本発明の第５の工程は、絶縁性樹脂が露出するまで導電箔４０の裏面を除去することにある。
【００５７】
本工程は、導電箔４０の裏面を化学的および／または物理的に除き、導電パターン５１として分離するものである。この工程は、研磨、研削、エッチング、レーザの金属蒸発等により施される。
【００５８】
実験では導電箔４０を全面ウェトエッチングし、分離溝４１から絶縁性樹脂１６を露出させている。この露出される面を図９（Ａ）では点線で示している。その結果、導電パターン５１となって分離される。この結果、絶縁性樹脂１６に導電パターン５１の裏面が露出する構造となる。すなわち、分離溝４１に充填された絶縁性樹脂１６の表面と導電パターン５１の表面は、実質的に一致している構造となっている。
【００５９】
更に、導電パターン５１の裏面処理を行い、例えば図１に示す最終構造を得る。すなわち、必要によって露出した導電パターン５１に半田等の導電材を被着し、回路装置として完成する。
【００６０】
更にまた、本工程に於いては、分離溝１６に充填された絶縁性樹脂１６は裏面に露出するが、溝１４に充填された絶縁性樹脂１６は裏面に露出しない。
【００６１】
本発明の第６の工程は、図１０に示す如く、絶縁性樹脂１６を各回路装置部４５毎にダイシングにより分離することにある。
【００６２】
本工程では、ブロック４２をダイシング装置の載置台に真空で吸着させ、ダイシングブレード４９で各回路装置部４５間のダイシングライン（一点鎖線）に沿って分離溝４１の絶縁性樹脂１６をダイシングし、個別の回路装置に分離する。
【００６３】
本工程で、ダイシングブレード４９はほぼ絶縁性樹脂１６を切断する切削深さで行い、ダイシング装置からブロック４２を取り出した後にローラでチョコレートブレークするとよい。ダイシング時は予め前述した第１の工程で設けた各ブロックの位置合わせマーク４７を認識して、これを基準としてダイシングを行う。周知ではあるが、ダイシングは縦方向にすべてのダイシングラインをダイシングをした後、載置台を９０度回転させて横方向のダイシングライン７０に従ってダイシングを行う。
【００６４】
【発明の効果】
本発明では、以下に示すような効果を奏することができる。
【００６５】
第１に、本発明では、半導体素子１３を囲むようにダイパッド１１の周辺部に溝１４を設けて、半導体素子１３を固着するロウ材１９が流出するのを防止したので、流出したロウ材１９により、導電パターン同士がショートしてしまうのを防止することができる。
【００６６】
第２に、溝１４により、ロウ材１９の流出を防止することができるので、ダイパッド１１とボンディングパッド１２とを接近させることが可能となり、装置全体を小型化することができる。
【００６７】
第３に、半導体素子１３を実装する工程に於いて、ボンディングパッド１２の周辺部に設けた溝１４がロウ材の流出を阻止する阻止領域として機能し、ロウ材１９が外部に流出ことによる導電パターン同士のショートを防止することができる。
【図面の簡単な説明】
【図１】本発明の回路装置を説明する平面図（Ａ）、断面図（Ｂ）である。
【図２】本発明の回路装置を説明する裏面図（Ａ）、断面図（Ｂ）である。
【図３】本発明の回路装置を説明する断面図（Ａ）、平面図（Ｂ）である。
【図４】本発明の回路装置の製造方法を説明する断面図（Ａ）、平面図（Ｂ）である。
【図５】本発明の回路装置の製造方法を説明する断面図である。
【図６】本発明の回路装置の製造方法を説明する断面図（Ａ）、平面図（Ｂ）である。
【図７】本発明の回路装置の製造方法を説明する断面図（Ａ）、平面図（Ｂ）である。
【図８】本発明の回路装置の製造方法を説明する断面図（Ａ）、平面図（Ｂ）である。
【図９】本発明の回路装置の製造方法を説明する断面図（Ａ）、平面図（Ｂ）である。
【図１０】本発明の回路装置の製造方法を説明する平面図である。
【図１１】従来の回路装置を説明する断面図である。
【図１２】従来の回路装置を説明する断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit device capable of preventing outflow of a brazing material for fixing a semiconductor element, and a method for manufacturing the circuit device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a circuit device set in an electronic device is employed in a mobile phone, a portable computer, and the like, and thus, a reduction in size, thickness, and weight are required. For example, a semiconductor device as an example of a circuit device will be described. As a general semiconductor device, there is a package type semiconductor device sealed by a conventional transfer mold. This semiconductor device is mounted on a printed circuit board PS as shown in FIG.
[0003]
In the package type semiconductor device 61, the semiconductor chip 62 is covered with a resin layer 63, and lead terminals 64 for external connection are led out from the side portions of the resin layer 63. However, the package type semiconductor device 61 has the lead terminals 64 protruding from the resin layer 63 and has a large overall size, which does not satisfy the reduction in size, thickness and weight. Therefore, various companies have competed to develop various structures to achieve miniaturization, thinning, and weight reduction, and recently called CSP (chip size package), wafer scale CSP equivalent to chip size, or chip size A slightly larger CSP has been developed.
[0004]
FIG. 12 shows a CSP 66 that employs a glass epoxy substrate 65 as a support substrate and is slightly larger than the chip size. Here, description will be made assuming that the transistor chip T is mounted on the glass epoxy substrate 65.
[0005]
A first electrode 67, a second electrode 68, and a die pad 69 are formed on the surface of the glass epoxy substrate 65, and a first back electrode 70 and a second back electrode 71 are formed on the back surface. The first electrode 67 and the first back electrode 70, and the second electrode 68 and the second back electrode 71 are electrically connected through the through hole TH. Further, the bare transistor chip T is fixed to the die pad 69, the emitter electrode of the transistor and the first electrode 67 are connected via the fine metal wire 72, and the base electrode of the transistor and the second electrode 68 are connected to the fine metal wire 72. Connected through. Further, a resin layer 73 is provided on the glass epoxy substrate 65 so as to cover the transistor chip T.
[0006]
The CSP 66 employs a glass epoxy substrate 65, but unlike the wafer scale CSP, the extending structure from the chip T to the backside electrodes 70 and 71 for external connection is simple and has the merit that it can be manufactured at low cost. The CSP 66 is mounted on the printed circuit board PS as shown in FIG. The printed circuit board PS is provided with electrodes and wirings constituting an electric circuit, and the CSP 66, the package type semiconductor device 61, a chip resistor CR, a chip capacitor CC, and the like are electrically connected and fixed. And the circuit comprised with this printed circuit board was attached in various sets.
[0007]
[Problems to be solved by the invention]
However, in the semiconductor device as described above, the transistor T is fixed by a reflow process in which a brazing material such as solder applied on the die pad 69 is melted. Therefore, when the transistor T is placed on the melted solder, there is a problem that the solder flows out from the die pad 69 and the die pad 69 and other electrodes are short-circuited.
[0008]
Further, in order to prevent the solder flowing out from the die pad 69 from reaching the second electrode 68, the die pad 69 and the second electrode 68 are separated from each other, which increases the size of the entire apparatus. Was invited.
[0009]
The present invention has been made in view of such problems, and the main object of the present invention is to prevent the brazing material from flowing out of the die pad when the semiconductor element is mounted on the die pad via the brazing material. An object of the present invention is to provide a circuit device.
[0010]
[Means for Solving the Problems]
In the method of manufacturing a semiconductor device according to the present invention, the separation groove is formed from the upper surface so that the conductive pattern including the die pad has a convex shape, and the groove having the shallower groove than the separation groove is formed in the region of the die pad. A first step of preparing a foil; a second step of fixing a semiconductor element on the upper surface of the die pad in a region surrounded by the groove through a melted solder; and covering the upper surface of the semiconductor element and the conductive foil. And a third step of forming an insulating resin so as to fill the separation groove and the groove, and removing the conductive foil from the back surface until the insulating resin filled in the separation groove is exposed. And a fourth step, wherein the first step has a first opening in the region where the separation groove is formed, and the width is narrower than the first opening in the region where the groove is formed. An edge having a second opening The upper surface of the conductive foil is covered with an etching mask and etched to form the groove shallower than the separation groove. In the fourth step, the insulating resin filled in the separation groove is exposed. The conductive foil is removed from the back surface so that the insulating resin filled in the groove is not exposed .
[0023]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment illustrating the configuration of the circuit device 10)
With reference to FIG. 1, the configuration of the circuit device 10 of the present invention will be described. FIG. 1A is a plan view of the circuit device 10, and FIG. 1B is a cross-sectional view of the circuit device 10.
[0024]
Referring to FIGS. 1A and 1B, circuit device 10 has the following configuration. That is, the die pad 11 formed to be approximately the same size as the semiconductor element 13 mounted via the brazing material 19, the bonding pad 12 provided close to the die pad 11, and the die pad so as to surround the semiconductor element 13. Insulation that seals the die pad 11, the bonding pad 12, and the semiconductor element 13 by exposing the back surface of the die pad 11 and the bonding pad 12 to the groove 14 that prevents the brazing material 19 from flowing out. The circuit device 10 is composed of the resin 16 or the like. Each of these components will be described below.
[0025]
The die pad 11 is a conductive pattern on which the semiconductor element 13 is mounted, is made of a metal such as copper foil, and is embedded in the insulating resin 16 with its back surface exposed. The planar size of the die pad 11 is slightly larger than the semiconductor element to be mounted, and a groove 14 is formed in the periphery thereof. In FIG. 1A, a die pad 11 is formed at the center, and a semiconductor element 13 made of an IC chip or the like is mounted via a brazing material 19. A plating film made of Ag or the like is formed on the surface of the die pad 11 corresponding to the region where the semiconductor element 13 is mounted.
[0026]
The bonding pad 12 is a conductive pattern to which the fine metal wire 15 is bonded, and is embedded in the insulating resin 16 with the back surface exposed. Here, a large number of circular bonding pads 12 are formed so as to surround the die pad 11 formed at the center of the apparatus. In FIG. 2A, bonding pads 12A formed on both left and right sides of the die pad 11 are provided electrically independently. The bonding pads 12B formed on both upper and lower sides of the die pad 11 are formed continuously with the die pad 11 and are electrically connected. A plating film made of Ag or the like is formed on the surface of the bonding pad 12 in order to improve the adhesion of the fine metal wires to be bonded.
[0027]
The semiconductor element 13 is mounted on the surface of the die pad 11 via the brazing material 19, and here, a relatively large IC chip is mounted via the brazing material 19 among the semiconductor elements. The electrode formed on the surface of the semiconductor element 13 and the bonding pad 12 are electrically connected via the fine metal wire 15. Further, the bonding pad 12 that is electrically connected to the die pad 11 is also electrically connected to the semiconductor element 13 through the fine metal wire 15. As the brazing material used here, a conductive adhesive such as solder or Ag paste can be used. Furthermore, the semiconductor element 13 can be mounted on the die pad 11 using an insulating resin.
[0028]
The groove 14 is formed in the periphery of the die pad 11 so as to surround the semiconductor element 13 and is filled with an insulating resin 16. Further, the depth of the groove 14 is shallower than the thickness of the die pad 11. Thus, by forming the groove 14 so as to surround the region where the semiconductor element 13 is mounted, the brazing material 19 flows out from the die pad 11 in the process of mounting the semiconductor element 13 on the molten brazing material 19. Can be prevented. Specifically, even if the brazing material 19 flows out of the region where the semiconductor element 13 is mounted, the brazing material 19 is stored in the groove 14. Therefore, the groove 14 functions as a blocking region that prevents the brazing material 19 from flowing out of the die pad 11. Although a method for manufacturing the groove 14 will be described later, the groove 14 is manufactured together with the separation groove 16 by etching. Accordingly, the width of the cross section of the groove 14 is narrower than the width of the separation groove 16.
[0029]
The insulating resin 16 exposes the back surfaces of the die pad 11 and the bonding pad 12 to seal the whole. Further, the insulating resin 16 is filled in the grooves 14 formed on the surface of the die pad 11. Here, the semiconductor element 13, the fine metal wire 15, the die pad 11 and the bonding pad 12 are sealed. As a material of the insulating resin 16, a thermosetting resin formed by transfer molding or a thermoplastic resin formed by injection molding can be employed.
[0030]
The brazing material 19 is a conductive paste such as solder or Ag paste, and has a function of bonding the semiconductor element 13 and the die pad 11. Since the brazing material 19 is a conductive material, the back surface of the semiconductor element 13 and the die pad 11 are electrically connected. The bonding pads 12B formed on the upper and lower sides of the die pad 11 are also electrically connected to the die pad 11. Therefore, by connecting the electrode of the semiconductor element 13 and the bonding pad 12B using the thin metal wire 15, the circuit formed on the surface of the semiconductor element 13 and the back surface of the semiconductor element 13 can be electrically connected. it can.
[0031]
With reference to FIG. 2, the external electrode 17 formed on the back surface of the circuit device will be described. The external electrode 17 is formed on the back surface of the bonding pad 12 provided so as to surround the die pad 11. Furthermore, a large number of external electrodes are also provided on the back surface of the die pad 11, and accordingly, a large number of external electrodes 17 are provided at regular intervals in a matrix form throughout the back surface of the circuit device 10. Thereby, when the circuit device 10 is mounted on a mounting board such as a mother board via the external electrode 17, the stress acting on the external electrode 17 can be reduced.
[0032]
Referring to FIG. 2B, the position and size of external electrode 17 formed on the back surface of die pad 11 are restricted by the opening of resist 18. The position and size of the external electrode 17 formed on the back surface of the bonding pad 12 are formed by the back surface of the bonding pad 12. A metal such as copper which is a material of the bonding pad 12 is a material having good wettability, and the position and size of the external electrode 17 are regulated by this wettability. As described above, by regulating the position and size of the external electrode 17 formed on the back surface of the bonding pad 12 using the wettability of the bonding pad 12, even when the position of the opening portion of the resist 18 is shifted, the accuracy is improved. The external electrode 17 can be formed well.
[0033]
A feature of the present invention is that a groove 14 is formed in the peripheral portion of the die pad 11 so as to surround the semiconductor element 13. That is, when the semiconductor element 13 is mounted on the melted brazing material 19, the brazing material 19 spreads around due to the weight of the semiconductor element 13, but the brazing material 19 spreading around is retained in the groove 14. It is possible to prevent the brazing material 19 from flowing out of the surface. Accordingly, it is possible to prevent the pads from shorting due to the leaked brazing material 19 coming into contact with the bonding pads 12. In addition, this makes it possible to form the die pad 11 substantially equivalent to the semiconductor element 13 mounted thereon. Furthermore, the die pad 11 and the bonding pad 12 can be formed close to each other, and the overall size of the circuit device 10 can be reduced. Furthermore, by forming the groove 14 on the surface of the die pad 11 in this way, the area where the die pad 11 and the insulating resin 16 are in contact with each other can be increased, so that the adhesive force between the die pad 11 and the insulating resin 13 is increased. Can be improved.
[0034]
With reference to FIG. 3, a circuit device 10A of another form will be described. 3A is a cross-sectional view of the circuit device 10A, and FIG. 3B is a cross-sectional view taken along line XX ′ of FIG. 3A. The circuit device 10 </ b> A has substantially the same configuration as the circuit device 10 described in FIG. 1, and grooves 14 </ b> A are further formed in a lattice shape in a region surrounded by the grooves 14 formed on the surface of the die pad 11. .
[0035]
The groove 14 is provided in the peripheral portion of the die pad 11 for the purpose of preventing the brazing material 19 for fixing the semiconductor element 13 from flowing out of the surface of the die pad 11. Further, here, grooves 14 </ b> A are formed in a lattice shape in a region surrounded by the grooves 14. The grooves 14 </ b> A formed in a lattice shape also have the same cross-sectional shape as the grooves 14. By forming the grooves 14 in a lattice shape in this manner, a larger amount of brazing material 19 can be stored in the grooves 14, thereby preventing the brazing material 19 from flowing out of the surface of the die pad 11. Can do. Furthermore, since the area where the die pad 11 and the insulating resin 16 contact can be further increased, the adhesion between the die pad 11 and the insulating resin 16 can be improved.
[0036]
A further merit of providing the groove 14 will be described. The brazing material 19 is applied to the surface of the die pad 11 using a machine for supplying a brazing material such as a dispenser. The minimum amount of the brazing material 20 that can be supplied by the dispenser is determined. Therefore, when the minimum application amount of the dispenser is larger than the amount of the brazing material 19 necessary for mounting the semiconductor element 13 on the die pad 11, the brazing material 19 may flow out from the surface of the die pad 11. Thus, by providing the groove 14, it is possible to prevent the brazing material 19 from flowing out.
[0037]
(Second Embodiment Explaining Method of Manufacturing Circuit Device 10)
In this embodiment, a method for manufacturing the circuit device 10 will be described. In the present embodiment, the circuit device 10 is manufactured by the following process. That is, the step of preparing the conductive foil 40 and the die pad 11 and the bonding pad 12 constituting the plurality of circuit device portions 45 by forming the separation groove 16 shallower than the thickness of the conductive foil 40 and simultaneously fixing the conductive foil 40 are planned. A step of forming a groove 14 shallower than the separation groove 16 in the die pad 11 so as to surround the region of the semiconductor element 13, a step of fixing the semiconductor element 13 to the die pad 11 via a brazing material 19, Wire bonding with the bonding pad 12, a step of covering the semiconductor element 13, and performing a common molding with the insulating resin 16 so as to fill the separation groove 16 and the groove 14, and the insulating resin 16 is exposed. From the step of removing the back surface of the conductive foil 40 and the step of separating each circuit device 10 by dicing the insulating resin 16 It has been made. Below, each process of this invention is demonstrated with reference to FIGS.
[0038]
In the first step of the present invention, as shown in FIGS. 4 to 6, a conductive foil 40 is prepared, and a separation groove 16 shallower than the thickness is formed in the conductive foil 40 to form a plurality of circuit device portions 45. At the same time as forming the die pad 11 and the bonding pad 12, the groove 14 shallower than the separation groove 16 is formed in the die pad 11 so as to surround the region of the semiconductor element 13 to be fixed.
[0039]
In this step, first, a sheet-like conductive foil 40 is prepared as shown in FIG. The conductive foil 40 is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material. As the material, a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al, or Fe is used. A conductive foil made of an alloy such as Ni is employed.
[0040]
The thickness of the conductive foil is preferably about 10 μm to 300 μm in consideration of later etching, but it is basically good if it is 300 μm or more or 10 μm or less. As will be described later, it is sufficient that the separation groove 16 shallower than the thickness of the conductive foil 40 can be formed.
[0041]
In addition, the sheet-like conductive foil 40 is prepared by being wound into a roll with a predetermined width, for example, 45 mm, and this may be conveyed to each step described later, or a strip-shaped cut into a predetermined size. The conductive foil 40 may be prepared and conveyed to each process described later.
[0042]
Specifically, as shown in FIG. 4B, 4 to 5 blocks 42 in which a large number of circuit device portions 45 are formed are arranged on the strip-shaped conductive foil 40 so as to be spaced apart. A slit 43 is provided between each block 42 to absorb the stress of the conductive foil 40 generated by the heat treatment in the molding process or the like. Also, index holes 44 are provided at regular intervals at the upper and lower peripheral ends of the conductive foil 40, and are used for positioning in each step. Subsequently, a conductive pattern is formed.
[0043]
First, as shown in FIG. 5, a photoresist (etching resistant mask) PR is formed on the conductive foil 60, and the photoresist PR is patterned so that the conductive foil 40 excluding the region to be the conductive pattern 51 is exposed. Then, as shown in FIG. 6A, the conductive foil 40 is selectively etched. Here, the conductive pattern 51 forms the die pad 11 and the bonding pad 12 of each circuit device unit 45.
[0044]
Referring to FIG. 6A, a photoresist opening is provided at a location where groove 14 and separation groove 16 are formed. And the width | variety of the opening part of the location in which the groove | channel 14 is formed is narrower than the location in which the isolation | separation groove | channel 16 is formed. Specifically, the width is less than half. Since the conductive foil 40 is removed by isotropic etching, the opening of the photoresist corresponding to the groove 14 is narrowly formed in this manner, so that the depth of the groove 14 is shallower than that of the separation groove 16. can do. Note that the above-described etching step can be performed by dipping the conductive foil 40 in an etchant solution.
[0045]
FIG. 6B shows a conductive pattern 51 for forming the die pad 11 and the bonding pad 12. This figure corresponds to an enlarged view of one of the blocks 42 shown in FIG. One hatched portion is one circuit device unit 45, and in one block 42, a large number of circuit device units 45 are arranged in a matrix of 2 rows and 2 columns, and the same conductive pattern is provided for each circuit device unit 45. 51 is provided. A frame-like pattern 46 is provided in the periphery of each block, and a positioning mark 47 for dicing is provided inside the pattern slightly apart from the frame-like pattern 46. The frame-shaped pattern 46 is used for fitting with the mold, and has a function of reinforcing the insulating resin 16 after the back surface etching of the conductive foil 40. In each circuit device portion, bonding pads 12 formed on both upper and lower sides of the die pad 11 are integrated with the die pad 11 and are electrically connected to each other.
[0046]
The second step of the present invention is to fix the semiconductor element 13 to the die pad 11 of each circuit device section 45 through the brazing material 19 as shown in FIG.
[0047]
With reference to FIG. 7A, the semiconductor element 13 is mounted on the die pad 11 via the brazing material 19. Here, as the brazing material 19, a conductive paste such as solder or Ag paste is used. In this step, since the brazing material 19 is in a molten state, by placing the semiconductor element 13 on the brazing material 19, the brazing material 19 spreads around due to the weight of the semiconductor element 13 and the like. Here, since the groove 14 is formed in the peripheral portion of the die pad 11 so as to surround the region where the semiconductor element 13 is placed, the spread brazing material 19 does not flow out of the die pad 11. Since the brazing material 19 that has reached the groove 14 flows into the groove 14, the groove 14 functions as a blocking region that prevents the solder from flowing out. Furthermore, the semiconductor element 13 can be mounted on the die pad 11 using an insulating resin.
[0048]
The third step of the present invention is to perform wire bonding between the semiconductor element 13 and a desired bonding pad 12 as shown in FIG.
[0049]
Specifically, wire bonding of the electrodes of the semiconductor element 13 and the desired bonding pads 12 mounted on each circuit device unit is performed collectively by ball bonding by thermocompression bonding and wedge bonding by ultrasonic waves.
[0050]
As shown in FIG. 9, the fourth step of the present invention is to cover the semiconductor element 13 and perform common molding with the insulating resin 16 so as to fill the separation groove 16 and the groove 14.
[0051]
In this step, as shown in FIG. 9A, the insulating resin 16 completely covers the semiconductor element 13 and the plurality of die pads 11 and the bonding pad 12, and the insulating resin 16 is formed in the separation grooves 16 and the grooves 14. Filled and fits firmly into the separation groove 41. The die pad 11 and the bonding pad 12 are supported by the insulating resin 16.
[0052]
Further, this step can be realized by transfer molding, injection molding, or potting. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as polyimide resin or polyphenylene sulfide can be realized by injection molding.
[0053]
Further, when performing transfer molding or injection molding in this step, each block 42 stores the circuit device portion 63 in one common mold as shown in FIG. 9B, and one insulating property is provided for each block. The resin 16 is molded in common. For this reason, the amount of resin can be greatly reduced as compared with a method in which each circuit device unit is individually molded, such as a conventional transfer mold.
[0054]
The feature of this step is that the conductive foil 40 that becomes the conductive pattern 51 becomes a support substrate until the insulating resin 16 is coated. Conventionally, the conductive pattern is formed by using a support substrate that is not originally required, but in the present invention, the conductive foil 40 serving as the support substrate is a material necessary as an electrode material. Therefore, there is a merit that the work can be performed with the constituent materials omitted as much as possible, and the cost can be reduced.
[0055]
Further, since the separation groove 41 is formed shallower than the thickness of the conductive foil, the conductive foil 40 is not individually separated as the conductive pattern 51. Therefore, the sheet-like conductive foil 40 can be handled as a unit, and when the insulating resin 16 is molded, it has a feature that the work of transporting to the mold and mounting to the mold becomes very easy.
[0056]
The fifth step of the present invention is to remove the back surface of the conductive foil 40 until the insulating resin is exposed.
[0057]
In this step, the back surface of the conductive foil 40 is chemically and / or physically removed and separated as the conductive pattern 51. This step is performed by polishing, grinding, etching, laser metal evaporation, or the like.
[0058]
In the experiment, the entire surface of the conductive foil 40 is wet-etched to expose the insulating resin 16 from the separation groove 41. The exposed surface is indicated by a dotted line in FIG. As a result, the conductive pattern 51 is separated. As a result, the back surface of the conductive pattern 51 is exposed to the insulating resin 16. That is, the surface of the insulating resin 16 filled in the separation groove 41 and the surface of the conductive pattern 51 are substantially matched.
[0059]
Furthermore, the back surface treatment of the conductive pattern 51 is performed to obtain, for example, the final structure shown in FIG. That is, a conductive material such as solder is deposited on the exposed conductive pattern 51 as necessary to complete the circuit device.
[0060]
Furthermore, in this step, the insulating resin 16 filled in the separation groove 16 is exposed on the back surface, but the insulating resin 16 filled in the groove 14 is not exposed on the back surface.
[0061]
The sixth step of the present invention is to separate the insulating resin 16 by dicing for each circuit device section 45 as shown in FIG.
[0062]
In this step, the block 42 is vacuum-adsorbed on the mounting table of the dicing device, and the insulating resin 16 in the separation groove 41 is diced along a dicing line (one-dot chain line) between the circuit device portions 45 with a dicing blade 49, Separate into separate circuit devices.
[0063]
In this step, the dicing blade 49 may be cut at a cutting depth that substantially cuts the insulating resin 16, and after taking out the block 42 from the dicing apparatus, a chocolate break may be caused by a roller. At the time of dicing, the alignment mark 47 of each block provided in the first step described above is recognized in advance and dicing is performed based on this. As is well known, dicing is performed by dicing all dicing lines in the vertical direction, rotating the mounting table 90 degrees, and performing dicing according to the dicing lines 70 in the horizontal direction.
[0064]
【The invention's effect】
In the present invention, the following effects can be obtained.
[0065]
First, in the present invention, the groove 14 is provided in the periphery of the die pad 11 so as to surround the semiconductor element 13 to prevent the brazing material 19 that fixes the semiconductor element 13 from flowing out. Therefore, it is possible to prevent the conductive patterns from being short-circuited.
[0066]
Second, since the groove 14 can prevent the brazing material 19 from flowing out, the die pad 11 and the bonding pad 12 can be brought close to each other, and the entire apparatus can be downsized.
[0067]
Third, in the process of mounting the semiconductor element 13, the groove 14 provided in the peripheral portion of the bonding pad 12 functions as a blocking region for preventing the brazing material from flowing out, and the electric conduction caused by the brazing material 19 flowing out to the outside. Short circuit between patterns can be prevented.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view illustrating a circuit device according to the present invention.
2A and 2B are a back view and a cross-sectional view illustrating a circuit device according to the present invention.
FIG. 3 is a cross-sectional view (A) and a plan view (B) illustrating a circuit device of the present invention.
4A and 4B are a cross-sectional view (A) and a plan view (B) illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 5 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
6A and 6B are a cross-sectional view (A) and a plan view (B) illustrating a method for manufacturing a circuit device according to the present invention.
7A and 7B are a cross-sectional view (A) and a plan view (B) illustrating a method for manufacturing a circuit device according to the present invention.
FIGS. 8A and 8B are a cross-sectional view (A) and a plan view (B) illustrating a method for manufacturing a circuit device of the present invention. FIGS.
9A and 9B are a cross-sectional view (A) and a plan view (B) illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 10 is a plan view illustrating the method for manufacturing the circuit device according to the present invention.
FIG. 11 is a cross-sectional view illustrating a conventional circuit device.
FIG. 12 is a cross-sectional view illustrating a conventional circuit device.

Claims (5)

ダイパッドを含む導電パターンが凸状を呈するように上面から分離溝が形成されると共に、前記ダイパッドの領域内に前記分離溝よりも浅い溝が形成された導電箔を用意する第１工程と、
前記溝に囲まれる領域の前記ダイパッドの上面に、溶融された半田を介して半導体素子を固着する第２工程と、
前記半導体素子および前記導電箔の上面が被覆されると共に、前記分離溝および前記溝に充填されるように絶縁性樹脂を形成する第３工程と、
前記分離溝に充填された前記絶縁性樹脂が露出するまで前記導電箔を裏面から除去する第４工程と、を具備し、
前記第１工程では、前記分離溝が形成される領域に第１開口部を有し、前記溝が形成される領域に前記第１開口部よりも幅が狭い第２開口部を有するエッチングマスクにより前記導電箔の上面を被覆してエッチングを行うことにより、前記溝を前記分離溝よりも浅く形成し、
前記第４工程では、前記分離溝に充填された前記絶縁性樹脂が露出すると共に、前記溝に充填された前記絶縁性樹脂が露出しない様に、前記導電箔を裏面から除去することを特徴とする半導体装置の製造方法。A first step of preparing a conductive foil in which a separation groove is formed from an upper surface so that a conductive pattern including a die pad has a convex shape, and a groove shallower than the separation groove is formed in the region of the die pad ;
A second step of fixing a semiconductor element to the upper surface of the die pad in a region surrounded by the groove via a molten solder ;
A third step of forming an insulating resin so that upper surfaces of the semiconductor element and the conductive foil are covered, and the separation groove and the groove are filled;
And a fourth step of removing the conductive foil from the back surface until the insulating resin filled in the separation groove is exposed,
In the first step, an etching mask having a first opening in a region where the separation groove is formed and a second opening narrower than the first opening in a region where the groove is formed. By covering the upper surface of the conductive foil and performing etching, the groove is formed shallower than the separation groove,
In the fourth step, the conductive foil is removed from the back surface so that the insulating resin filled in the separation groove is exposed and the insulating resin filled in the groove is not exposed. A method for manufacturing a semiconductor device. 前記分離溝と前記溝とを一度のエッチング工程にて同時に形成することを特徴とする請求項１記載の半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, wherein the separation groove and the groove are simultaneously formed by a single etching process. 前記第２開口部の幅は、前記第１開口部の幅の半分以下であることを特徴とする請求項１記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the width of the second opening is not more than half of the width of the first opening. 前記第２工程では、前記ダイパッドの上面から流出した液状の前記半田を、前記溝に流れ込ませることを特徴とする請求項１記載の半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, the liquid solder that has flowed out from the upper surface of the die pad flows into the groove. 前記第４工程では、前記導電箔を裏面から全面的にエッチングすることを特徴とする請求項１記載の半導体装置の製造方法。  The method of manufacturing a semiconductor device according to claim 1, wherein in the fourth step, the conductive foil is entirely etched from the back surface.
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