JP4068828B2 - Integrated separation-type switching cache memory and processor system having the cache memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a processor system having a cache memory, and more particularly to a processor system having a processor capable of processing a plurality of commands and a cache memory operable in response to an access request from the processor. Further, both the integrated cache memory system and the separated cache memory system can be realized by the same architecture, and the integrated cache memory system can be accelerated at the same speed as the separated cache memory system.
[0002]
[Prior art]
FIG. 1 shows an outline of the transition of the cache memory architecture. Prior to the introduction of the cache memory, the processor CPU and the main memory MM directly exchanged instructions and data as in (1). After that, the main memory MM speed has been determined by the increase in the capacity of the main memory MM and the increase in the speed of the processor CPU.
[0003]
Therefore, as shown in (2), the cache memory UC having a smaller capacity and higher speed than the main memory MM is arranged between the processor CPU and the main memory MM to improve the performance. The initial cache memory UC was an integrated type that handles both instructions and data.
[0004]
Thereafter, the processor CPU and the cache memory UC can be integrated on the same chip by miniaturizing the process as shown in (3). As a result, the number of signal lines connecting the processor CPU and the cache memory UC can be greatly increased. As shown in (4), the cache memory UC can be separated into the instruction cache IC and the data cache DC and simultaneously accessed. Harvard architecture has appeared. And it became common sense that high-performance cache architecture is Harvard architecture.
[0005]
Subsequently, a superscalar or VLIW (Very Long Instruction Word) architecture appeared, enabling a plurality of data accesses simultaneously. For this reason, a processor having a plurality of data cache DC ports as shown in (5) has appeared. In general, the multi-port configuration is such that only accesses to different banks are simultaneously executed by the bank interleaving method.
[0006]
In addition, since the integrated cache memory architecture is less expensive than the Harvard architecture, the low-end version may be the integrated type and the high-end version may be the Harvard architecture in the same processor family. For example, SH-3 described in “Microprocessor Report Vol. 9, no. 3, 3/6/95, p. 12” and “Microprocessor Report Vol. 10, no. 14, 10/28/96, pp. 32- SH-4 described in "35" is the same SuperH series processor, but the former is an integrated type and the latter is a Harvard architecture.
[0007]
In recent years, JAVA is rapidly spreading as a programming language independent of processors. JAVA is a language for rewriting instructions. The complex instruction executed at the first time is rewritten to an instruction that is executed at high speed based on information determined by executing it once. Furthermore, in order to execute a program written in JAVA at high speed, a method of detecting a routine with high execution frequency, rewriting it into a machine language program specific to the processor and executing it at high speed is also a JIT (Just-in-time) compilation method. Generalized.
[0008]
The performance improvement by the cache memory is premised on the spatial and temporal locality of memory access. Therefore, it does not work effectively without the locality. For example, the network processor IXP1200 described in “Microprocessor Report Vol.13, no.12, 9/13/99, pp1, 6-10” does not include a data cache, and directly accesses an external SRAM or SDRAM. In addition, the vector floating point unit VPU of the emotion engine EE described in “Microprocessor Report Vol. 13, No. 5, 4/19/99, pp1, 6-11” has a dedicated RAM instead of a cache. A direct memory access unit controlled by software performs data access to the RAM.
[0009]
[Problems to be solved by the invention]
As a result of the historical transition of the cache architecture as described above, it has become common sense to use a Harvard architecture when emphasizing performance and an integrated cache memory architecture when emphasizing cost. However, due to the improvement in integration due to process miniaturization, the difference in cost between the integrated architecture and the Harvard architecture has become smaller than the cost of the entire chip, and there is an advantage of creating two types of cache memory architecture for each product. It is gone.
[0010]
Further, when a language for rewriting instructions such as JAVA becomes widespread, the Harvard architecture is not always good. In the Harvard architecture, instruction rewriting is generally not detected by hardware. For this reason, when the instruction is rewritten, it must be ensured that the instruction before rewriting is not executed by software responsibility. At the time of instruction rewriting, since the rewritten instruction is handled as data, the rewritten instruction is stored in the data cache DC. At this time, even if the instruction before rewriting exists in the instruction cache IC, it is not updated.
[0011]
The software clears the instruction before rewriting on the instruction cache IC, writes the instruction back to the main memory MM after rewriting on the data cache DC, and then executes the instruction after rewriting. Then, the hardware fetches and executes the rewritten instruction from the main memory MM. Even if the instruction rewrite is detected by hardware, efficient processing is difficult because only the above-described software processing is hardwareized.
[0012]
On the other hand, in the integrated cache memory architecture, instructions on the cache memory UC are rewritten by instruction rewriting. Therefore, if an instruction is fetched from the cache memory UC after instruction rewriting, the instruction after rewriting can be fetched. For this purpose, in a normal pipeline processor, it is only necessary to cancel an executing instruction existing on the pipeline after the instruction is rewritten. Therefore, the integrated cache memory architecture is more suitable for supporting instruction rewriting.
[0013]
Due to the improvement of the degree of integration accompanying the process miniaturization, it is possible to make the main memory MM on-chip in a small-scale system. Also, like the Emotion Engine EE, instructions or data are placed on the on-chip memory, and the instructions and data are transferred to the on-chip memory in advance by direct memory access, etc., so that high-speed access is ensured when actually used. It is also possible to do. In this way, if the instruction or data to be used can be predicted, the speed can be increased even if the memory access has no spatial and temporal locality. In such a situation, a cache memory is unnecessary, or only one of an instruction cache and a data cache is required.
[0014]
In addition, from the era when processor systems were limited to mainframes, workstations, PCs, etc., the era has come to be installed in a wide variety of products such as mobile phones, digital home appliances, and automobiles. The composition is also diversified. Therefore, it is important to have various cache memory configurations with the same processor.
[0015]
A first problem to be solved by the present invention is to achieve simultaneous execution of instruction fetch and data access, which can be achieved only with a Harvard architecture, with an integrated cache memory architecture. This makes it possible to achieve both high performance and ease of instruction rewriting at the same time. In addition, even in the case of an application that wants to cache one of instructions and data intensively, the entire capacity can be utilized without wasting one cache as in the Harvard architecture.
[0016]
A second problem to be solved by the present invention is to realize both an integrated cache memory architecture and a Harvard architecture with the same processor. Furthermore, it is to realize various cache memory configurations with the same processor.
[0017]
[Means for Solving the Problems]
The first problem is solved by forming a plurality of ports in the integrated cache memory. This allows instruction fetches and data access requests to be processed at the same time, achieving the same performance as the Harvard architecture. However, pure multiple ports increase the amount of hardware and reduce the cache memory capacity that can be realized in the same area. Therefore, the cache memory is constituted by a plurality of banks specified by a part of the address, each bank is a one-port cache, and if the instruction fetch and the data access request are for different banks, simultaneous processing is performed, and if the same bank is sequentially processed By processing, the amount of hardware can be reduced and the cache memory capacity can be maintained as compared with a complete multi-port cache memory. Although the capacity of cache memory can be increased along with the process miniaturization, it is necessary to divide the memory mat in order to increase the capacity, and if the divided memory mat is assigned to the bank, it will accompany the bank division. An increase in cost can be avoided.
[0018]
The second problem is solved by using not only a part of the address but also an instruction fetch and a data access request identification signal for specifying the port or bank. When used as an integrated cache memory architecture, a part of the address is used, and when used as a Harvard architecture, an identification signal is used. In this way, by switching signals used for port or bank designation, two cache memory architectures are realized by the same processor. Furthermore, it is possible to change the capacity distribution of the Harvard architecture instruction cache and data cache depending on the signal switching method. Also, the first and second problems can be solved in the same way by making it possible to access a plurality of ways with different addresses.
[0019]
Further, in order to solve the above problems, the present invention provides a processor system having a processor capable of independently processing a plurality of commands and a cache memory that operates in response to an access request from the processor. And a plurality of control commands including instruction fetches transmitted from the processor via the plurality of ports, and a plurality of address signals can be simultaneously processed. is there.
[0020]
Furthermore, the present invention provides a system having a processor capable of independently processing instruction fetch and data access and a cache memory operating in response to an access request from the processor, wherein the cache memory includes a plurality of selectors and a plurality of addresses. It is composed of a plurality of banks specified by a part, each bank is a one-port cache, and if the instruction fetch request and the data access request are for different banks, simultaneous processing is performed, and if the same bank is processed, sequential processing is performed. An object is to provide a processor system.
[0021]
Further, the present invention includes a plurality of banks and a controller that controls the plurality of banks, the controller generates a control signal for writing or reading a command or data to each of the plurality of banks, The control signal is supplied to the plurality of banks under the control of the controller, and the command or data is written or read simultaneously to different banks in the plurality of banks, and the command or data is transferred to the same bank. It is another object of the present invention to provide a cache memory characterized by sequentially performing the writing or reading operation.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. The same reference numerals in the drawings of the respective embodiments indicate the same or equivalent. FIG. 2 shows an example of a processor system to which the present invention is applied. It consists of a processor LSI and a main memory MM. The processor LSI includes a central processing unit CPU, a cache memory CM, an external memory interface EMI, and a peripheral module PM, and is connected by an internal bus IB. The central processing unit CPU includes an instruction fetch unit IFU, an execution unit EXU, and a bus interface unit BIU. The processor and the cache memory CM are integrated on the same LSI chip.
[0023]
The basic operation of the central processing unit CPU is as follows. First, the instruction fetch unit IFU issues an instruction fetch request REQI together with an instruction address AI to the cache memory CM. The cache memory CM returns the read instruction RI to the instruction fetch unit IFU in response to the request REQI. The instruction fetch unit IFU supplies the instruction RI to the execution unit EXU. The execution unit EXU decodes and executes the instruction RI. If the decoded instruction is a memory read instruction, a data access request REQD is issued together with the data address AD. The cache memory CM returns the read data RD to the execution unit EXU in response to the request REQD. If the decoded instruction is a memory write instruction, a data access request REQD is issued together with the data address AD and the write data WD. The cache memory CM writes the data WD in response to the request REQD.
[0024]
When the instruction fetch request REQI or the data access request REQD has a cache miss, the bus interface unit BIU receives the instruction address AI, data address AD, write data WD, and the like related to the request, and externally passes through the internal bus IB. An external memory fetch request is issued to the memory interface EMI. In response to the request, the external memory interface EMI outputs an address A to the main memory MM to issue an external memory fetch request, and the main memory MM returns data D in response thereto. The external memory interface EMI returns data D to the bus interface unit BIU via the internal bus IB. The bus interface unit BIU issues an external access request REQX together with the external address AX and write data WX, and the cache memory CM has a port for processing the external access request REQX (access request from the outside). Write data WX is written accordingly.
[0025]
When the pipeline operation is performed in the central processing unit CPU, the instruction fetch unit IFU fetches the subsequent instruction simultaneously with the instruction processing of the execution unit EXU. Further, if the data access of the execution unit EXU is non-blocking, the data access by the subsequent instruction is performed simultaneously with the external memory access due to the data access miss of the cache memory CM. Therefore, the cache memory CM includes an instruction fetch request and a data access request, or a plurality of control commands composed of any one of the instruction fetch request REQI, the data access request REQD, and the external access request REQX, and an instruction address. An ability to simultaneously process a plurality of address signals including any one of the signal AI and the data address signal AD, or the signal AI, the signal AD, and the external address signal AX is required.
[0026]
FIG. 3 shows a first embodiment of a cache memory CM to which the present invention is applied. The cache memory CM includes a cache control register CCR, a bank signal generation unit BKG (or signal generation unit), a cache control unit CC that controls the CM, and a cache body. BKG generates a plurality of control signals (BKI, BKD, BKX) to be given to CC based on a plurality of address signals.
[0027]
The cache memory main body is divided into four banks BK0 to BK3 designated by specific bits which are a part of the plurality of addresses in each of a plurality of address signals (AI, AD, and AX), and to different banks. Simultaneous access is possible.
[0028]
When specifying each of the plurality of banks in the cache memory, the cache control unit included in the cache memory based on the input of the instruction fetch request or data access request and the plurality of control signals instead of the specific bit By specifying a bank via each of the plurality of selectors under the control of the plurality of generated address selection control signals and write data selection control signals, it operates as an instruction data separation type cache memory.
[0029]
The banks BK0 to BK3 respectively receive access addresses A0 to A3, and further write data W0 to W3 at the time of writing, and perform a read or write operation, and output read data R0 to R3 at the time of reading. Each of the banks BK0 to BK3 is regarded as a one-port cache. Access addresses A0 to A3 are selected from addresses AI, AD, or AX by address selection control signals CA0 to CA3 in address multiplexers (or selectors) AM0 to AM3, respectively. Write data W0 to W3 are selected from write data WD or WX by write data selection control signals CW0 to CW3 in write data multiplexers (or selectors) WM0 to WM3, respectively. Read data RI, RD, and RX are selected from read data R0 to R3 by read data selection control signals CRI, CRD, and CRX in read data multiplexers (or selectors) RMI, RMD, and RMX, respectively. Note that the number assigned to the input signal of each multiplexer in the figure is the bit number of the selection control signal that is asserted when that input is selected.
[0030]
FIG. 4 shows details of the cache control unit CC of the first embodiment. A control signal for each multiplexer of the cache body is generated from the instruction bank BKI, data bank BKD, and external bank BKX from the bank signal generation unit BKG, and the instruction fetch request REQI, data access request REQD, and external access request REQX. .
[0031]
More specifically, the cache control unit has already assigned a data access request to a bank designated based on a control signal in response to an instruction fetch request, a data access request, and a plurality of control signals (BKI, BKD, BKX) inputs. If a data access request is not yet assigned to the bank specified based on the control signal, a plurality of address selection control signals or write data selections are generated. Generate a control signal.
[0032]
The read data selection control signals CRI, CRD, and CRX in FIG. 3 are 4-bit signals that control the 4-input multiplexer. Each of the 2-bit instruction bank BKI, the data bank BKD, and the external bank BKX can be generated by simple decoding and is not shown.
[0033]
Address selection control signals CA0 to CA3 and write data selection control signals CW0 to CW3 cannot be generated unless the priority of instruction fetch, data access, and external access is determined. The simplest priority determination method is to maintain the original sequential execution order of the program. Since external access is caused by a previous cache access miss, the sequential execution order is the fastest. Further, instruction fetch is preparation of subsequent instructions, and the sequential execution order is the slowest. Therefore, the priority is first for external access, second for data access, and third for instruction fetch.
[0034]
However, in a highly optimized program, instructions and data are cached in advance from the main memory MM to the cache memory CM by a prefetch instruction or the like so that a cache miss does not occur when actually used. In such a program, lowering the external access priority improves performance. Since it is difficult to optimize the program so that it is just-on-time caching, when caching with a little extra time, caching is performed earlier than necessary, so it is better not to stall internal operations by waiting for this Because it is good. Therefore, in this embodiment, the priority is set to data access for the first, instruction fetch for the second, and external access for the third.
[0035]
Since the access addresses A0 to A3 shown in FIG. 3 are selected from the addresses AI, AD, or AX, the address multiplexers AM0 to AM3 have 3 inputs, and the control signals CA0 to CA3 have 3 bits. Therefore, as the bit number of the control signal, 2 is assigned to the instruction address, 1 is assigned to the data address, and 0 is assigned to the external address.
[0036]
First, as shown in FIG. 4, when the highest priority data access request REQD is asserted, a bank designated by the data bank BKD is assigned, and bit 1 of the control signal of the assigned bank among the address selection control signals CA0 to CA3 is assigned. Assert. In other words, each of the 4-bit signals obtained by decoding the 2-bit data bank BKD by the data bank decoder BDD and the data access request REQD are ANDed.
[0037]
Next, when the instruction fetch request REQI is asserted, a bank designated by the instruction bank BKI is allocated. At this time, if data access has already been assigned to the bank, the instruction fetch delay signal DLI is asserted and instruction fetch is not assigned. When the allocation is performed, bit 2 of the control signal of the allocated bank is asserted among the address selection control signals CA0 to CA3. That is, the AND logic of each of the 4-bit signals obtained by decoding the 2-bit instruction bank BKI by the instruction bank decoder BDI and the instruction access request REQI is taken, and further, the inverted signal of the bit 1 of the address selection control signals CA0 to CA3 and the AND logic. I take the. Bit 0 of the address selection control signals CA0 to CA3 is asserted when neither data access nor instruction access is performed in the corresponding bank. That is, the AND logic of the inverted signal of bit 1 of the address selection control signals CA0 to CA3 and the inverted signal of the signal obtained by ANDing the instruction access request REQI that is the source of bit 2 and the signal from the BDI. It is a signal taken.
[0038]
Further, a signal obtained by ANDing the 4-bit signal obtained by decoding the 2-bit external bank BKX by the external bank decoder BDX and the external access request REQX is asserted, and an external access request to the corresponding bank is issued. Regardless, if the signal for selecting an external address as the bank address, that is, bit 0 of the address selection control signals CA0 to CA3 is not asserted, the necessary access bank cannot be selected, and the external access delay signal DLX is asserted.
[0039]
Since the write data W0 to W3 shown in FIG. 3 is selected from the write data WD or WX, the write data multiplexers WM0 to WM3 have two inputs and the control signals CW0 to CW3 have two bits. Therefore, the bit number of the control signal is assigned 1 to the data address and 0 to the external address. First, bit 1 of write data selection control signals CW0 to CW3 has the same logic as bit 1 of address selection control signals CA0 to CA3. When there is no data access, the external write data WX shown in FIG. 3 is selected as the write data. Therefore, bit 0 of the write data selection control signals CW0 to CW3 is the inversion of bit 1 as shown in FIG.
[0040]
FIG. 5 shows a first example of the bank signal generator BKG. If the capacity of the cache memory CM is 128 KB and the 4-way set associative method is used, the capacity per way is 32 KB and the index is 15 bits. In the bank interleave method, a part of the index is used for bank designation. In this embodiment, since the number of banks is 4, 2 bits are used for bank designation. Which bit is used for bank designation determines the stall frequency due to bank contention to a minimum, depending on the program. Conversely, it is also possible to create a program that suppresses contention by disclosing bank designation bits to the programmer. In FIG. 5, bits 14 to 0 of the address are used as indexes, and the upper 2 bits of the index are used as bank designation bits. Therefore, bits 14 to 13 are bank designation bits.
[0041]
The bank signal generator BKG is controlled by the bank control field BC of the cache control register CCR. In FIG. 5, the bank control field BC is 1 bit, and the bank multiplexers BMI, BMD, and BMX are controlled to select the upper bits of the 2-bit bank signals BKI, BKD, and BKX. In this embodiment, the lower bits are always bit 13 of addresses AI, AD, and AX. In FIG. 5, the numbers assigned to the input signals of the bank multiplexers BMI, BMD, and BMX are the values of the bank control field BC when the input signals are selected. That is, if the bank control field BC is 1, the bits 14 of the addresses AI, AD, and AX are selected as the upper bits of the bank signals BKI, BKD, and BKX, respectively. On the other hand, if the bank control field BC is 0, the value 0, the value 1, and the external data access signal DA are selected. The external data access signal DA is asserted when the external access is a data system.
[0042]
As a result, if the bank control field BC is 1, the bank signals BKI, BKD, and BKX are bits 14 to 13 of the addresses AI, AD, and AX, respectively. Therefore, the cache memory CM is an integrated 4-bank interleaved cache.
[0043]
If the bank control field BC is 0, the bank signal BKI is 0 or 1 depending on the value of the bit 13 of the address AI, and the bank signal BKD is 2 or 3 depending on the value of the bit 13 of the address AD. BKX is 0 or 1 when the external data access signal DA is negated, or 2 or 3 when asserted, depending on the value of bit 13 of the address AX.
[0044]
Therefore, for instruction fetch and instruction system external access, bank signals BKI and BKX always specify bank 0 or 1, and for data access and data system external access, bank signals BKD and BKX are always bank 2 or Specify 3. As a result, banks 0 and 1 operate as a 2-bank interleave instruction cache, and banks 2 and 3 operate as a 2-bank interleave data cache. Since different banks can be accessed simultaneously, the Harvard architecture is achieved. At this time, bit 14 of the address is always used as a tag. If the bank control field BC is 1, it is redundant to set bit 14 as a tag, but no malfunction occurs. If the bank control field BC is 0, bit 14 is necessary as a tag. If one bit of redundancy is removed, the logic becomes complicated and the speed decreases.
[0045]
FIG. 6 shows a second example of the bank generation unit BKG. Normally, the address space where the program is placed and the address space where the data is placed are often determined in advance by the system. Therefore, if there is an address bit for identifying these two spaces, the instruction bit is designated as a bank designation bit. And data bank conflicts can be avoided. As a result, it is possible to obtain the same performance as the Harvard architecture while being an integrated four-bank interleaved cache.
[0046]
In the example of FIG. 6, the bank control field BC is 2 bits, and in addition to the cases where the bank control field BC of FIG. When the bank control field BC is 2, the bit 20 of the address is selected, and when the bank control field BC is 3, the bit 24 is selected.
[0047]
As a result, bank conflict between instruction and data can be avoided by using bit 20 as a bank designation bit in a relatively small system with a program size of about 1 MB and bit 24 in a slightly larger system of about 16 MB. Also in this case, as in the case of FIG. 5, the bits 24, 20, and 14 are always used as tags.
[0048]
7 to 9 show a first operation example of this embodiment. FIG. 7 shows an example of the operation of the bank generator BKG. In the figure, thick signal lines are asserted, and thin signal lines are negated. In this operation example, it is assumed that the bank control field BC of the cache control register CCR is 1 and the integrated cache mode is set. It is assumed that the instruction address AI, the data address AD, and the external address AX are hexadecimal numbers 00001230, 00102468, and 001048C0, and the instruction fetch request REQI, data access request REQD, and external access request REQX are all asserted.
[0049]
In FIG. 7, hexadecimal numbers are expanded to binary numbers so that the values of bits 14 to 13 are clear. Since bank control field BC is 1, instruction bank multiplexer BMI, data bank multiplexer BMD, and external bank multiplexer BMX select bit 14 of instruction address AI, data address AD, and external address AX, respectively, and 0, 0, and 1 is output. Since a signal obtained by combining the output and the bit 13 that is always used as a bank designation signal is a bank signal, the instruction bank BKI, the data bank BKD, and the external bank BKX are 0, 1, and 2, respectively.
[0050]
FIG. 8 shows an operation example of the cache control unit CC. In the figure, thick signal lines are asserted, and thin signal lines are negated. Instruction bank BKI, data bank BKD, and external bank BKX are decoded by instruction bank decoder BDI, data bank decoder BDD, and external bank decoder BDX, respectively, and bits 0, 1, and 2 of the decoder output are asserted, respectively.
[0051]
Since the instruction fetch request REQI, the data access request REQD, and the external access request REQX are all asserted, the asserted state is maintained even after AND logic with these signals. Then, the AND gate of the priority determination logic asserts the CA2 bit 2, the CA1 bit 1, the CA2 bit 0, and the CA3 bit 0 as the address selection control signal, and the write data selection signal is the CW0 bit 0 and the CW1 bit. Bit 1, bit 0 of CW2, and bit 0 of CW3 are asserted.
[0052]
Further, the instruction fetch delay DLI and the external access delay DLX are negated by the bank conflict determination logic. Although not shown, read data selection signals CRI, CRD, and CRX are simple decodes of instruction bank BKI, data bank BKD, and external bank BKX, so that bits 0, 1, and 2 are asserted, respectively. .
[0053]
FIG. 9 shows an operation example of the cache memory CM. As a control signal CTL from the cache control unit CC, the address selection control signal is bit 2 of CA0, bit 1 of CA1, bit 0 of CA2, bit 0 of CA3, write data selection signal is bit 1 of CW1, and other CW0,2 , 3 bit 0, and CRI bit 0, CRD bit 1 and CRX bit 2 are asserted in the read data selection signal.
[0054]
As a result, the instruction address AI, the data address AD, and the external address AX are selected as the addresses A0 to A3, respectively. As the write data W0 to W3, the write data WD is selected for W1, and the write data WX is selected for the other. Then, read data R0, R1, and R2 are selected as read data RI, RD, and RX, respectively.
[0055]
As described above, if the bank control field BC of the cache control register CCR is set to 1, the integrated cache mode is set, and the bits 14 to 13 used as the bank designation bits are accessed with different addresses, an instruction fetch request, a data access request, and External access requests can be processed simultaneously in different banks. That is, simultaneous processing is executed.
[0056]
10 to 12 show a second operation example of this embodiment. Also in this operation example, it is assumed that the bank control field BC of the cache control register CCR is 1 and the integrated cache mode is set. Then, assume that the instruction address AI, the data address AD, and the external address AX are hexadecimal 00001230, 00101357, and 00100240, and the instruction fetch request REQI, the data access request REQD, and the external access request REQX are all asserted.
[0057]
Then, as shown in FIG. 10, the instruction bank multiplexer BMI, the data bank multiplexer BMD, and the external bank multiplexer BMX all output 0. When further combined with bit 13, instruction bank BKI, data bank BKD, and external bank BKX are all zero.
[0058]
FIG. 11 shows an operation example of the cache control unit CC. The output of the instruction bank decoder BDI, data bank decoder BDD, and external bank decoder BDX is all asserted bit 0, and remains asserted after AND logic with the instruction fetch request REQI, data access request REQD, and external access request REQX . Then, the AND gate of the priority determination logic asserts bit 1 of CA0 and bit 0 of other CA1 to 3 as the address selection control signal, and bit 1 of CW0 and bit 0 of the other CW1 to 3 as the write data selection signal. Is asserted.
[0059]
Further, the instruction fetch delay DLI and the external access delay DLX are asserted by the bank conflict determination logic. That is, instruction fetch and external access are awaited. Although not shown, since the read data selection signals CRI, CRD, and CRX are simple decodes of the instruction bank BKI, the data bank BKD, and the external bank BKX, all 0s are asserted.
[0060]
FIG. 12 shows an operation example of the cache memory CM. As the control signal CTL from the cache control unit CC, the address selection control signal is bit 1 of CA0, bit 0 of other CA1-3, the write data selection signal is bit 1 of CW0, bit 0 of other CW1-3, read data selection All signals have bit 0 asserted.
[0061]
As a result, the data address AD is selected as the address A0, and the external address AX is selected as the other addresses A1 to A3. The write data WD is selected as the write data W0, and the write data WX is selected as the other write data W1 to W3. Then, the read data R0 is selected for all the read data RI, RD, and RX.
[0062]
As described above, when the bank control field BC of the cache control register CCR is set to 1, the integrated cache mode is set, and the bits 14 to 13 used as the bank designation bits are accessed with the same address, only the data access is executed due to the bank conflict. Instruction fetches and external accesses are awaited. That is, sequential processing is executed.
[0063]
13 to 15 show a third operation example. The access request with the same address as in the second operation example is used, and the bank control field BC of the cache control register CCR is set to 0 to set the Harvard architecture mode. External access is data-based access. That is, the external data access signal DA is asserted. Then, since the bank control field BC is 0 as shown in FIG. 13, the instruction bank multiplexer BMI, the data bank multiplexer BMD, and the external bank multiplexer BMX select the value 0, the value 1, and the value 1 of the external data access signal DA, respectively. Output. Since a signal obtained by combining the output and the bit 13 that is always used as the bank designation signal is a bank signal, the instruction bank BKI, the data bank BKD, and the external bank BKX are 0, 2, and 2, respectively.
[0064]
FIG. 14 shows an operation example of the cache control unit CC. The outputs of the instruction bank decoder BDI, data bank decoder BDD, and external bank decoder BDX are asserted with bits 0, 2, and 2, respectively, and after AND logic with the instruction fetch request REQI, data access request REQD, and external access request REQX Keep asserted. Then, by the AND gate of the priority determination logic, the CA2 bit 0, the CA1 bit 0, the CA2 bit 1, and the CA3 bit 0 are asserted as the address selection control signal, the write data selection signal is the CW2 bit 1, and the other CW0. , 1, 3 bit 0 is asserted. The external access delay DLX is asserted by the bank conflict determination logic. That is, external access is awaited. Although not shown, read data selection signals CRI, CRD, and CRX are simple decodes of instruction bank BKI, data bank BKD, and external bank BKX, so that bits 0, 2, and 2 are asserted, respectively. .
[0065]
FIG. 15 shows an operation example of the cache memory CM. As the control signal CTL from the cache control unit CC, the address selection control signal is bit 2 of CA0, bit 0 of CA1, bit 1 of CA2, bit 0 of CA3, the write data selection signal is bit 1 of CW2, other CW0, As for the read data selection signal, CRI bit 0, CRD bit 2, and CRX bit 2 are asserted.
[0066]
As a result, the instruction address AI, the external address AX, the data address AD, and the external address AX are selected as the addresses A0 to A3, respectively. As for the write data W0 to W3, the write data WD is selected for W2, and the write data WX is selected for the other W0, 1, and 3. Then, read data R0, R2, and R2 are selected as read data RI, RD, and RX, respectively.
[0067]
As described above, when the bank control field BC of the cache control register CCR is set to 0 and the Harvard architecture mode is set, bank contention between instruction fetch and data access can be avoided even when accessed with the same address as in the second operation example. On the other hand, bank conflicts between data access and data system external access cannot be avoided, but this cannot be avoided even with a normal Harvard architecture.
[0068]
FIG. 16 shows a fourth operation example of the bank signal generation unit. Although an access request with the same address as that in the second operation example is processed, the bank generator BKG in FIG. 6 is used and the bank control field BC of the cache control register CCR is set to 2. The address bit for distinguishing the address space between the program and data is bit 20.
[0069]
Then, since the bank control field BC is 2 as shown in FIG. 16, the instruction bank multiplexer BMI, the data bank multiplexer BMD, and the external bank multiplexer BMX output 0, 1, and 1, respectively. Since a signal obtained by combining the output and the bit 13 that is always used as the bank designation signal is a bank signal, the instruction bank BKI, the data bank BKD, and the external bank BKX are 0, 2, and 2, respectively. That is, the same bank signal as in the third operation example is output. As a result, the cache control unit CC and the cache memory CM operate in the same manner, and it is possible to avoid contention between instruction fetch and data access as in the Harvard architecture, although it is an integrated cache.
[0070]
To summarize the operation examples of the above-described figures, a plurality of address selection control signals generated by the cache control unit by inputting an instruction fetch request, a data access request, an external access request, and a plurality of control signals (BKI, BKD, BKX). In addition, by controlling the write data selection control signal, a plurality of address signals (AI, AD, AX) and write data (WD, WX) are sent to different banks in the plurality of banks through each of the plurality of selectors. At the same time, a plurality of access addresses are sequentially given to the same bank.
[0071]
Further, in each of the plurality of banks, writing of write data to a plurality of access addresses or reading of data from each access address is arbitrarily performed simultaneously for different banks and sequentially for the same bank. .
[0072]
In particular, in terms of sequential processing, control signals (CA0-3, CW0-3) are supplied to each of a plurality of banks under the control of the cache control unit CC (controller), and instructions or Data write or read operations are sequentially performed.
[0073]
FIG. 17 shows a cache memory CM according to the second embodiment of the present invention. An access request to be preferentially selected for each bank is designated in advance by the bank selection fields BS0 to BS3 of the cache control register CCR. If two or more access requests are received at the same time, an access request with a high priority is assigned to each bank. Accept. The difference from the first embodiment shown in FIG. 3 is that the bank selection fields BS0 to BS3 are output from the cache control register CCR to the cache control unit CC, and the cache control is performed from the input of the instruction fetch request REQI and the data access request REQD. The point is that the signal CTL is generated.
[0074]
FIG. 18 shows the cache control unit CC of the second embodiment. The advantage of this method is that cache access can be started at a high speed because address information that is slower than the access request is not used for bank selection. This is suitable when the cache access speed is more important than the bank usage efficiency. Address selection control signals CA0 to CA3 and write data selection control signals CW0 to CW3 are generated without using bank signals BKI, BKD, and BKX generated from addresses.
[0075]
Address selection control signal CA0 is generated from bank selection field BS0, instruction fetch request REQI and data access request REQD as follows. The bank selection field BS0 is 0 when instruction fetch is prioritized and 1 when data access is prioritized. Bits 2, 1, and 0 of address selection control signal CA0 correspond to instruction address AI, data address AD, and external address AX, respectively.
[0076]
First, bit 2 is asserted when the data fetch request REQD is negated when the instruction fetch request REQI is asserted or when the bank selection field BS0 is 0 and the instruction fetch priority is given. Similarly, bit 1 is asserted when the data access request REQD is asserted, when the instruction fetch request REQI is negated, or when the bank selection field BS0 is 1 and data access is prioritized. Bit 0 is asserted when both the instruction fetch request REQI and the data access request REQD are negated. Similarly, address selection control signals CA1 to CA3 are generated from bank selection fields BS1 to BS3, instruction fetch request REQI and data access request REQD. In the write data selection control signals CW0 to CW3, the bit 1 is the same logic as the bit 1 of the address selection control signals CA0 to CA3, and the bit 0 is the inversion of the bit 1, as in the first embodiment shown in FIG.
[0077]
In this embodiment, the read data selection signals CRI, CRD, and CRX are obtained by decoding the bank signals BKI, BKD, and BKX, respectively. Since bank selection is performed only by the access requests REQI, REQD, and REQX and the bank selection fields BS0 to BS3, it is checked whether a bank necessary for each access is secured. If the bank is not secured, access delay signals DLI, DLD, And assert DLX to wait for access. This check may be performed in parallel with the cache access.
[0078]
Specifically, as in the first embodiment, the bank to be accessed is determined from the bank signal BKI or BKD and the access request REQI or REQD, and the instruction address AI or the address is selected by the address selection control signals CA0 to CA3 in the bank. If the data address AD is not selected, the access delay signal DLI or DLD is asserted, respectively. In this embodiment, since external access always has a low priority in all banks, a bank cannot be secured if an access request REQI or REQD is issued. Therefore, the access delay signal DLX is asserted if REQI or REQD is asserted when the access request REQX is asserted regardless of the bank.
[0079]
In the second embodiment, external access always has the lowest priority, but it is possible to freely change the priority including external access. Although the first and second embodiments are of a four-bank configuration, it is possible for ordinary engineers in the field to which the present invention belongs to expand the present invention in the case of various numbers of banks.
[0080]
FIG. 19 shows a cache memory CM according to the third embodiment of the present invention. Whether all the cache memories having a multi-way configuration are shared by instruction data, or each way is designated for instruction or data. Whereas the number of banks is not a power of 2, it is difficult to realize, while the number of ways can be any number, so that the degree of freedom of design increases. In addition, there is no need for bank interleaving. For example, if a 4-way set associative integrated cache memory is used to share instruction data for all ways, it becomes an integrated type as it is, and if 2 ways are used for instructions and the remaining 2 ways are used for data, a Harvard architecture is obtained. By caching only one of instructions or data for each of the plurality of ways, it is possible to operate as an instruction data separation type cache memory. However, external access and instruction or data access cannot be executed at the same time without bank interleaving. In addition, since it is necessary to specify a different address for each way, a plurality of ways cannot be mounted on one memory mat.
[0081]
The difference between the cache memories CM of the second and third embodiments is the difference between the blocks constituting the CM shown in FIGS. First, the cache memory main body is divided into ways WY0 to WY3 instead of the banks BK0 to BK3, and each way is accessed with a unique address selected by the address multiplexers AM0 to AM3 (or selectors). Since there is no bank, there is no bank generation unit BKG. Also, since external access and instruction or data access cannot be executed at the same time, a dedicated port for external access is unnecessary.
[0082]
FIG. 22 is a diagram showing a processor configuration example when a way is used in the cache memory main body. External access is divided into an instruction system and a data system, and merged into instruction access and data access in advance as in a normal Harvard architecture. A plurality of control commands including an instruction fetch request REQI and a data access request REQD and a plurality of address signals including AI and AD are transmitted from the processor CPU to the cache memory body.
[0083]
The difference between the processor system having the cache memory CM adopting the banks BK0 to BK3 (FIG. 2) and the processor system having the CM adopting the way instead of the bank (FIG. 22) is that from the execution unit EXU. One of the write data WD transmitted to the CM and the write data transmitted from the BIU to the CM is selected by the selector and written to the CM, and the command-based write data WI from the BIU is concurrently sent to the CM. It is to be written.
[0084]
As a result of adopting the processor system shown in FIG. 22, in comparison with the cache memory configuration example shown in FIG. 17, in the cache memory configuration shown in FIG. 19, the address multiplexers AM0 to AM3 receive the write data at the two inputs of the instruction address AI and the data address AD. The external write data WX (FIG. 17) of the multiplexers WM0 to WM3 becomes unnecessary because the instruction system is merged with the instruction system write data WI and the data system is merged with the data system write data WD. As a result of merging instruction-related external access AX (FIG. 17), there is instruction-related write data WI (FIG. 19) that was not present before the merge.
[0085]
Furthermore, the read data selection control signals CRI and CRD, which are simple bank signal decoding results in the bank interleaving method, are generated by the way selection control unit WSC provided in the cache memory CM of FIG. Details of the way selection control unit WSC are shown in FIG. The signals CRI and CRD are generated by AND logic of read data selection control signals CR0 to CR3 from the cache control unit CC (FIG. 21) and hit signals HT0 to HT3 from each way. As shown in FIG. 19, read data RI and RD are read from read data R0 to R3 read from each way WY0 to WY3 through read data multiplexers RMI and RMD, respectively, under the control of read data selection control signals CRI and CRD. The signal to be selected.
[0086]
FIG. 21 shows the cache control unit CC in the cache memory CM of the third embodiment shown in FIG. The cache control register CCR has an integrated bit U (a bit for distinguishing whether the cache memory is an integrated type or a separated type) and a way selection field WS0 to WS3. The integrated bit U indicates that all ways are shared with instruction data. The way selection fields WS0 to WS3 indicate which access is prioritized for each way in the instruction data access conflict when the integrated bit U is asserted. When the integrated bit U is negated, the way selection data Indicates whether it is for use. The way selection fields WS0 to WS3 are set to 0 when an instruction is selected and 1 when data is selected. At this time, the address selection controls CA0 to CA3, write data selection controls CW0 to CW3, and read data selection controls CR0 to CR3 output from the cache control unit CC can all be generated with the same logic. In the figure, 1 and 0 represent bits 1 and 0, respectively, which are instruction system and data system selection control signals.
[0087]
For example, as shown in FIG. 19, bit 0 of the address selection control signal CA0 is a selection control signal for the data address AD of way 0. The condition for selecting the data address AD is that the instruction access request REQI is negated or the way selection field WS0 is 1 when the data access request REQD is asserted in FIG. At this time, the way 0 is either prioritized for data access or for data depending on the value of the integrated bit U. In either case, data access is performed. Bit 1 of the address selection control CA0 is an inverted signal of bit 0. For this reason, in this embodiment, when both of the instruction access request REQI and the data access request REQD are negated, the instruction address AI is selected when either can be selected as the address. Other control signals are similarly generated.
[0088]
The integrated bit U is not required for normal cache access, but is required for replacement of a cache entry. When the integrated bit U is asserted, the replacement entry candidates are all ways. As a result, an integrated cache memory in which instructions and data are mixed is obtained. When the integrated bit U is negated, the way that is a candidate for the replacement entry is a way in which the way selection fields WS0 to WS3 are 0 at the time of instruction replacement, and the way selection fields WS0 to WS3 are 1 at the time of data replacement. Way only. This results in a Harvard architecture because only instructions or data are written for each way.
[0089]
The operation example when the way is used for the cache memory CM described above is summarized. A plurality of address selection control signals and write data selection control generated by the cache control unit CC by inputting the instruction fetch request REQI and the data access request REQD. Depending on the signal, a plurality of address signals (AI, AD) and write data (WI, WD) are passed through each of a plurality of selectors to different ways in a plurality of ways at the same time. Sequentially, a plurality of access addresses or write data are given.
[0090]
Further, in each of the plurality of ways, writing of the write data to the access address or reading of the data from the access address is optionally performed simultaneously for different ways and sequentially for the same way.
[0091]
【The invention's effect】
According to the present invention, it is possible to achieve simultaneous execution of instruction fetch and data access, which can be achieved only with the Harvard architecture, with the integrated cache memory architecture. This makes it possible to simultaneously achieve ease of instruction rewriting and high performance.
[0092]
In addition, even when using an application and wanting to cache one of the instructions and data intensively, the entire capacity can be utilized without wasting one cache as in the Harvard architecture.
[0093]
In addition, both the integrated cache memory architecture and the Harvard architecture can be realized with the same processor. Furthermore, various cache memory configurations can be realized by the same processor.
[Brief description of the drawings]
FIG. 1 is a diagram showing the transition of a cache memory architecture.
FIG. 2 is a diagram illustrating an example of a processor system to which the present invention is applied.
FIG. 3 is a diagram showing a first embodiment of a cache memory to which the present invention is applied;
FIG. 4 is a diagram illustrating a cache control unit according to the first embodiment of this invention.
FIG. 5 is a diagram illustrating a first example of a bank signal generation unit.
FIG. 6 is a diagram illustrating a second example of the bank signal generation unit.
FIG. 7 is a diagram illustrating a first operation example of a bank signal generation unit.
FIG. 8 is a diagram illustrating a first operation example of a cache control unit.
FIG. 9 is a diagram illustrating a first operation example of a cache memory.
FIG. 10 is a diagram illustrating a second operation example of the bank signal generation unit.
FIG. 11 is a diagram illustrating a second operation example of the cache control unit.
FIG. 12 is a diagram illustrating a second operation example of the cache memory.
FIG. 13 is a diagram illustrating a third operation example of the bank signal generation unit.
FIG. 14 is a diagram illustrating a third operation example of the cache control unit.
FIG. 15 is a diagram illustrating a third operation example of the cache memory;
FIG. 16 is a diagram illustrating a fourth operation example of the bank signal generation unit.
FIG. 17 is a diagram showing a second embodiment of a cache memory to which the present invention is applied;
FIG. 18 illustrates a cache control unit according to the second embodiment.
FIG. 19 is a diagram showing a third embodiment of a cache memory to which the present invention is applied.
FIG. 20 is a diagram illustrating a way selection control unit according to a third embodiment;
FIG. 21 is a diagram illustrating a cache control unit according to a third embodiment;
FIG. 22 is a diagram showing an example of a processor system when a way is used instead of a bank in a cache memory to which the present invention is applied.
[Explanation of symbols]
CPU: Central processing unit, IFU: Instruction fetch unit, EXU: Execution unit, BIU: Bus interface unit, AI: Instruction address, AD: Data address, AX: External address, REQI: Instruction fetch request, REQD: Data access request , REQX: external access request, RI, RD, RX: read data, WD, WX: write data.

Claims (16)

In a processor system having a processor capable of independently processing a plurality of commands and a cache memory that operates in response to an access request from the processor,
The cache memory has a plurality of banks and a plurality of ports, and simultaneously processes a plurality of control commands and a plurality of address signals including an instruction fetch transmitted from the processor via the plurality of ports. Is possible, and
The cache memory includes a cache control unit that controls address and data writing of the cache memory, a signal generation unit that generates a control signal that controls the cache control unit, and a bank control field that controls the signal generation unit. A cache control register,
The signal generation unit corresponds to a value of a specific bit provided in an address and outputs the control signal according to the bank control field;
The cache control unit is configured to output an address selection control signal or write data selection control signal for controlling the cache memory address and data writing, respectively in response to said control signal and said access request,
2. The processor system according to claim 1, wherein whether the cache memory functions as an integrated cache memory or a separate cache memory is selected according to the address selection control signal or the write data selection control signal. In a processor system having a processor capable of independently processing instruction fetch and data access and a cache memory operating in response to an access request from the processor ,
The cache memory is composed of a plurality of banks specified by a plurality of selectors and a part of a plurality of addresses, each bank is a one-port cache, and if the instruction fetch request and the data access request are for different banks, Processing, in the case of the same bank, sequentially processing,
The cache memory includes a cache control unit that controls address and data writing of the cache memory, a signal generation unit that generates a control signal that controls the cache control unit, and a bank control field that controls the signal generation unit. A cache control register,
The signal generation unit corresponds to a value of a specific bit provided in an address and outputs the control signal according to the bank control field;
The cache control unit is configured to output an address selection control signal or write data selection control signal for controlling the cache memory address and data writing, respectively in response to said control signal and said access request,
2. The processor system according to claim 1, wherein whether the cache memory functions as an integrated cache memory or a separate cache memory is selected according to the address selection control signal or the write data selection control signal. The processor system according to claim 1, wherein
The plurality of control commands include any one of an instruction fetch request and a data access request, or the instruction fetch request, the data access request, and an external access request, and the plurality of address signals include an instruction address signal and A processor system comprising a data address signal or any one of the instruction address signal, the data address signal, and an external address signal. The processor system according to claim 3, wherein
In response to the instruction fetch request, the data access request, and the input of the control signal, the cache control unit performs further allocation when the data access request is already assigned to the bank designated based on the control signal. A delay signal is generated so as not to be executed, and when the data access request is not yet assigned to the bank designated based on the control signal, the address selection control signal or the write data selection control signal is generated. A featured processor system. The processor system according to claim 3, wherein
Further, the address signal and the data access request and the external access request, and the control of the address selection control signal and the write data selection control signal generated by the cache control unit upon input of the control signal, A processor system characterized in that a plurality of access addresses are given to different banks in a plurality of banks simultaneously and sequentially to the same bank through each of a plurality of selectors from write data. The processor system according to claim 5, wherein
Further, in each of the plurality of banks, the writing of the write data to the plurality of access addresses or the data reading from the access address is performed simultaneously for the different banks and sequentially for the same bank. A processor system that is optionally performed. The processor system according to claim 2, wherein
A part of the plurality of addresses is a specific bit in each of the plurality of addresses, and instruction data is obtained by using the specific bit when designating each of the plurality of banks in the cache memory. A plurality of cache control units that operate as an integrated cache memory and are generated by a cache control unit included in the cache memory based on an input of the control signal generated using a predetermined value instead of a part of the specific bit A processor system which operates as an instruction data separation type cache memory by designating the bank via each of the plurality of selectors under the control of an address selection control signal and a write data selection control signal. The processor system according to any one of claims 3 to 6,
The cache memory further includes a port for processing the external access request that is an external access request, and simultaneously processes at least two requests among the instruction fetch request, the data access request, and the external access request. A processor system characterized by the above. In a processor system having a processor capable of independently processing a plurality of commands and a cache memory that operates in response to an access request from the processor,
The cache memory has a plurality of ports, and is capable of simultaneously processing a plurality of control commands and a plurality of address signals including an instruction fetch transmitted from the processor via the plurality of ports. ,
The plurality of control commands include an instruction fetch request and a data access request, the plurality of address signals include an instruction address signal and a data address signal, the cache memory further includes a cache control unit for controlling the cache memory, the cache A cache control register having an integrated bit and a way selection field for controlling the control unit, a plurality of ways, a plurality of selectors, and a way selection control unit,
The integrated bit is a bit for distinguishing whether the cache memory is integrated or separated,
The cache memory is selected to function as an integrated cache memory or a separate cache memory based on the integrated bit,
The way selection field is a signal indicating a priority for data access and instruction access in each of the plurality of ways according to the value of the integrated bit, or each of the plurality of ways is used for data access and instruction access. A processor system, wherein the signal is switched to a designated signal. The processor system according to claim 9, wherein
Further, each of the plurality of selectors is selected from the plurality of address signals and write data by an address selection control signal and a write data selection control signal generated by the cache control unit upon input of the instruction fetch request and the data access request. Thus, a plurality of access addresses or the write data are given to different ways in the plurality of ways simultaneously and sequentially to the same way . The processor system according to claim 10, wherein
Further, in each of the plurality of ways, writing of write data to the access address or reading of data from the access address is arbitrarily performed simultaneously for the different ways and sequentially for the same way. A processor system characterized by the above. The processor system according to claim 9, wherein
A processor system which operates as an instruction data separation type cache memory by caching only one of an instruction and data for each of the plurality of ways. The processor system according to any one of claims 1 to 12,
A processor system, wherein the processor and the cache memory are integrated on the same chip. Comprising a plurality of banks, a controller for controlling the plurality of banks, the controller generates a control signal for writing or reading instruction or data to each of the plurality of banks, before Symbol plurality of banks A cache memory for simultaneously writing or reading the instruction or data to different banks in the bank,
The cache memory includes a cache control register including a bank control field that controls the controller when generating the control signal;
The controller is the control signal, in correspondence with the value of a specific bit provided to the address, and outputs in response to the bank control field, further, the address of the cache memory in response to said control signal及beauty access request and outputs the address selection control signal or write data selection control signal for controlling data writing, respectively,
The cache memory is selected to function as an integrated cache memory or a separate cache memory in accordance with the address selection control signal or the write data selection control signal. The cache memory according to claim 14, wherein
Further, the address selection control signal or the write data selection control signal is supplied to each of the plurality of banks under the control of the controller , and the command or data write or read operation is sequentially performed on the same bank. Characteristic cache memory. A plurality of ways, and a controller for controlling the plurality of ways, the controller generating a control signal for writing or reading a command or data in each of the plurality of ways; The control signal is supplied to the plurality of ways, the command or data is written to or read from different ways in the plurality of ways at the same time, and the control signal is controlled by the controller. A cache memory that sequentially supplies the instructions or data to the same way and performs write or read operations on the same way,
The cache memory includes a cache control register including an integration bit and a way selection field for controlling the controller when generating the control signal;
The integrated bit is a bit for distinguishing whether the cache memory is integrated or separated,
The cache memory is selected to function as an integrated cache memory or a separate cache memory based on the integrated bit,
The way selection field is a signal indicating a priority for data access and instruction access in each of the plurality of ways according to the value of the integrated bit, or each of the plurality of ways is used for data access and instruction access. A cache memory characterized by being switched to a designated signal.

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