JP4062111B2 - Method for manufacturing light emitting device - Google Patents

Method for manufacturing light emitting device Download PDF

Info

Publication number
JP4062111B2
JP4062111B2 JP2003025094A JP2003025094A JP4062111B2 JP 4062111 B2 JP4062111 B2 JP 4062111B2 JP 2003025094 A JP2003025094 A JP 2003025094A JP 2003025094 A JP2003025094 A JP 2003025094A JP 4062111 B2 JP4062111 B2 JP 4062111B2
Authority
JP
Japan
Prior art keywords
layer
light emitting
substrate
bonding
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003025094A
Other languages
Japanese (ja)
Other versions
JP2004235581A (en
Inventor
和徳 萩本
宣彦 能登
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP2003025094A priority Critical patent/JP4062111B2/en
Priority to US10/718,789 priority patent/US20040104395A1/en
Publication of JP2004235581A publication Critical patent/JP2004235581A/en
Application granted granted Critical
Publication of JP4062111B2 publication Critical patent/JP4062111B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Description

【0001】
【発明の属する技術分野】
この発明は発光素子の製造方法に関する。
【0002】
【従来の技術】
【特許文献1】
特開平7−66455号公報
【特許文献2】
特開2001−339100号公報
【0003】
発光ダイオードや半導体レーザー等の発光素子に使用される材料及び素子構造は、長年にわたる進歩の結果、素子内部における光電変換効率が理論上の限界に次第に近づきつつある。従って、一層高輝度の素子を得ようとした場合、素子からの光取出し効率が極めて重要となる。III−V族化合物半導体、例えば、AlGaInP混晶により発光層部が形成された発光素子は、薄いAlGaInP(あるいはGaInP)活性層を、それよりもバンドギャップの大きいn型AlGaInPクラッド層とp型AlGaInPクラッド層とによりサンドイッチ状に挟んだダブルへテロ構造を採用することにより、高輝度の素子を実現できる。このようなAlGaInPダブルへテロ構造は、AlGaInP混晶がGaAsと格子整合することを利用して、GaAs単結晶基板上にAlGaInP混晶からなる各層をエピタキシャル成長させることにより形成できる。そして、これを発光素子として利用する際には、通常、GaAs単結晶基板をそのまま素子基板として利用することも多い。しかしながら、発光層部を構成するAlGaInP混晶はGaAsよりもバンドギャップが大きいため、発光した光がGaAs基板に吸収されて十分な光取出し効率が得られにくい難点がある。この問題を解決するために、半導体多層膜からなる反射層を基板と発光素子との間に挿入する方法(例えば特許文献1)も提案されているが、積層された半導体層の屈折率の違いを利用するため、限られた角度で入射した光しか反射されず、光取出し効率の大幅な向上は原理的に期待できない。
【0004】
そこで、特許文献2をはじめとする種々の公報には、成長用のGaAs基板を剥離する一方、補強用の素子基板(導電性を有するもの)を、反射用のAu層を介して剥離面に貼り合わせる技術が開示されている。このAu層は反射率が高く、また、反射率の入射角依存性が小さい利点がある。
【0005】
【発明が解決しようとする課題】
しかしながら、上記の方法では、反射層をなすAu層を発光層部に貼り合せる際に、貼り合せ強度の確保が困難であり、剥離等の不具合につながったり、良好な貼り合せ状態が得られないことによる反射率の低下が避けがたかった。また、貼り合せ強度を高めるために、貼り合せの熱処理温度を高くすると、発光層や導電性基板(特にSi基板)とAu層との冶金的な反応が顕著となり、得られる反射面の状態が悪化して反射率の低下を一層招きやすくなる問題がある。
【0006】
本発明の課題は、Au層を有した金属層を介して発光層部と素子基板とを貼り合せた構造を有する発光素子を製造するために、貼り合せの熱処理温が低くとも十分な貼り合せ強度が得られ、かつ、反射面の状態も良好に保つことができる発光素子の製造方法及び発光素子を提供することにある。
【0007】
【課題を解決するための手段及び作用・効果】
上記の課題を解決するために、本発明の発光素子の製造方法は、
III−V族化合物半導体からなる化合物半導体層の一方の主表面を光取出面とし、該化合物半導体層の他方の主表面側に、発光層部からの光を光取出面側に反射させる反射面を有した金属層を介して素子基板が結合され、かつ金属層の反射面を含む部分が純Au(ただし、1質量%以内であれば不可避不純物を含有してもよい)よりなるAu層とされた発光素子を製造するために、
発光層部を有した化合物半導体層の光取出面になるのと反対側の主表面を貼り合わせ側主表面として、該貼り合わせ側主表面に反射面を形成する純Auよりなる貼り合せ用の第一Au層を配置し、
また、第一Au層と化合物半導体層との間に、Auを主成分とする発光層部側接合層を、第一Au層の主表面上に分散する形で配置し、第一Au層の発光層部側接合層が非形成となる領域が反射面とされ、
素子基板の、発光層部側に位置することが予定された主表面を貼り合わせ側主表面として、該貼り合わせ側主表面に純Auよりなる第二Au層を配置し、
それら第一Au層と第二Au層とを密着させ、その状態で180℃よりも高温かつ250℃以下にて貼り合わせ熱処理することにより貼り合わせることを特徴とする。なお、本明細書において「主成分」とは、最も質量含有率の高い成分のことをいう。
【0008】
上記本発明の方法によると、化合物半導体層側と素子基板側に第一及び第二の各Au層を振り分けて形成し、これらを相互に密着させて貼り合せる。Au層同士は比較的低温でも容易に一体化するので、貼り合せの熱処理温度が低くとも十分な貼り合せ強度が得られ、かつ、Au層を含む金属反射層の反射面も良好な状態のものを容易に形成することができる。そして、反射面自体が耐食性の高いAu層にて構成されるので、発光素子の製造工程の途上で、後述の発光層成長用基板の剥離処理や発光層部の面荒らし処理(いわゆるフロスト処理)など、腐食性の高い液を用いた化学的処理を化合物半導体層に施す場合でも、反射面に腐食が浸透する心配がないので製造工程の簡略化を図ることができ、かつ反射面の状態も損なわれにくい。
【0009】
発光層部は、ピーク波長が550nm以上の可視光を発光するものであることが望ましい。図3は、Au層の反射率の波長依存性を示すグラフであるが、波長550nm未満の可視光域に強い吸収があることがわかる。そこで、発光層部のピーク波長が550nm以上とすることで、反射率低下を効果的に抑制でき、発光強度を向上させることができる。また、取り出される光のスペクトルが、吸収により本来の発光スペクトルとは異なるものとなったり、発光色調が変化したりする不具合も生じにくい。この観点で、発光層部の発光の望ましい色調とピーク波長域は、以下の通りである:
・黄緑系:550nm以上580nm未満
・黄色系:580nm以上595nm未満
・アンバー系:595nm以上610nm未満
・オレンジ系:610nm以上630nm未満
・赤色系:630nm以上780nm未満
【0010】
なお、図3から明らかなように、発光層部のピーク波長が、望ましくは580nm以上、より望ましくは600nm以上のとき、より反射率が向上し、発光強度を高めることができる。この観点において、発光層部は、黄色系、アンバー系、オレンジ系あるいは赤色系のものを採用するとき、Au層による反射率を特に高めることができ、発光強度向上効果が顕著となる。
【0011】
具体的には、本発明の発光素子の製造方法は、
化合物半導体よりなる発光層成長用基板上に発光層部をエピタキシャル成長させ、
発光層成長用基板が一体化された状態において、発光層部の貼り合わせ側主表面に第一Au層を形成し、
他方、素子基板の貼り合わせ側主表面に第二Au層を形成し、
第一Au層と第二Au層とを密着させて貼り合わせ、
その貼り合わせ後に、発光層部から発光層成長用基板を化学エッチングにより剥離する工程を採用することができる。
【0012】
該工程によると、発光層成長用基板が一体化された状態において、発光層部の貼り合わせ側主表面に第一Au層と、素子基板の貼り合わせ側主表面に第二Au層とを貼り合せるので、薄層として形成される発光層部を、発光層成長用基板による機械的な補強を伴った形で、貼り合わせのためのハンドリングを行なうことができる。その結果、例えば発光層部を貼り合わせ前に剥離する工程を採用する場合と比較して、発光層部が割れたり欠けたりする不具合発生確率が大幅に低減され、工程も劇的に簡略化できる。この場合、貼り合わせ後に、発光層部から発光層成長用基板を化学エッチングにより剥離することになるが、反射面をなす部分がAu層にて形成されているから、化学エッチングの影響が反射面に及ぶ不具合も極めて生じにくく、エッチング中の発光層の剥離等の懸念も生じない。
【0013】
例えば、発光層部が(AlGa1−xIn1−yP(ただし、0≦x≦1,0≦y≦1)よりなり、発光層成長用基板がGaAs基板よりなる場合、化学エッチングを、アンモニア/過酸化水素混合液を用いてGaAs基板を溶解する形で行なうことができる。アンモニア/過酸化水素混合液は、(AlGa1−xIn1−yPに対するGaAs基板の選択腐食性に優れ、発光層部を該溶液に浸漬するだけでGaAs基板だけを迅速かつ確実に剥離除去することができる。また、反射面を形成するAu層への腐食の心配もない。なお、本発明においては、発光層成長用基板を全てエッチングにより除去することも、「剥離」の概念に属するものとする。
【0014】
他方、(AlGa1−xIn1−yP(ただし、0≦x≦1,0≦y≦1)よりなる発光層部がAlAs剥離層を介して成長用基板をなすGaAs基板上に成長され、化学エッチングを、フッ酸を含有した溶液を用いてAlAs剥離層を溶解する形で行なうこともできる。フッ酸を含有した溶液によりAlAs剥離層を溶解すれば、GaAs基板を発光層部から簡単に剥離することできる。また、反射面を形成するAu層への腐食の心配もない。この場合、GaAs基板は溶解されないので、次の発光層部の成長等に再利用することも可能である。
【0015】
次に、発光層部がIII−V族化合物半導体からなる場合、第一Au層と第二Au層とをいずれもAu含有率が95質量%以上のAu系金属とし、それら第一Au層と第二Au層とを密着させ、その状態で180℃よりも高温かつ360℃以下にて貼り合わせ熱処理することにより貼り合わせることができる。該方法によると、III−V族化合物半導体よりなる化合物半導体層側と素子基板側に第一及び第二の各Au層を振り分けて形成し、これらを相互に密着させて貼り合せる。そして、第一Au層と第二Au層とは、いずれもAu含有率が95質量%以上となることで、180℃よりも高温かつ360℃以下で貼り合わせ熱処理することにより容易に結合する。従って、十分な貼り合せ強度が簡単に得られ、かつ、貼り合わせ熱処理時において、Au層に対する基板側あるいは化合物半導体層側からの拡散や反応の影響が及びにくく、Au層を含む金属反射層の反射面も良好な状態のものを容易に形成することができる。
【0016】
【0017】
また、前述の通り、Au層に対する基板側あるいは化合物半導体層側からの拡散や反応の影響を抑制するため、貼り合わせ熱処理温度の上限は250℃に設定する例えば、素子基板としてはSi基板を用いることができる。Si基板はドーピングにより発光素子として十分な導電性を容易に確保することができ、しかも安価である。しかし、SiはAu中へ拡散を起しやすく、また比較的低温で共晶反応を起しやすい(Au−Si二元系の共晶温度は363℃である)。従って、貼り合わせの熱処理温度が少しでも過度に高くなると、金属反射層中のAu層へ素子基板をなすSiが多量に拡散したり共晶反応を起したりし、反射率の低下を極めて招きやすい。しかしながら本発明のごとく、Au層同士の貼り合わせによりその熱処理温度を250℃以下に設定することで、上記共晶温度よりも十分低い温度で貼り合わせ熱処理を行なうことが可能であり、良好な反射率と貼り合わせ強度とを確保することができる。
【0018】
第一Au層が形成される化合物半導体層がIII−V族化合物半導体にて構成される場合、第一Au層と第二Au層とを密着させて外部の熱源により貼り合わせ熱処理を行う際に、第一Au層側へは化合物半導体層を介して熱が伝達されるが、III−V族化合物半導体は一般に、Siなどの他の半導体と比較すれば熱伝導率が低い。そのため、貼り合わせ熱処理温度が過度に低くなると、III−V族化合物半導体層により第一Au層への熱伝達が阻害され、第二Au層との強固な貼り合わせ状態を得ることができなくなる。そこで、本発明においては、貼り合わせ熱処理温度は180℃よりも高く設定することにより、III−V族化合物半導体層の熱伝導率がそれほど高くないにもかかわらず、第一Au層と第二Au層を十分な強度にて貼り合わせることができるようになる。特に、化合物半導体層が、III族元素がAl、Ga及びInより選ばれる1種以上からなり、V族元素がP及びAsより選ばれる1種以上からなる場合に、該効果は特に顕著となる。
【0019】
素子基板としてSi基板を用いる場合、素子基板の貼り合わせ側主表面に基板側接合層を形成し、該基板側接合層を覆うように第二Au層を形成し、かつ基板側接合層とSi基板との合金化熱処理を行なうことができる。n型のSi基板を用いる場合、基板側接合層は、AuSb合金あるいはAuSn合金にて構成できる。この場合、基板側接合層とSi基板との合金化熱処理を例えば250℃以上500℃以下にて行なうことにより、接触抵抗の低減効果が高められる。
【0020】
本発明においては、第一Au層により反射面を形成することができる。Au層は化学的に安定であり、酸化等による反射率劣化を生じにくいので、反射面の形成材質として好適である。特にSi基板を使用する場合は、反射面をなす第一Au層のAuと、Si基板をなすSiとの共晶反応が進行すると、反射率の低下が特に生じやすいが、本発明の採用によりこのような不具合が極めて効果的に抑制される結果、良好な反射率の反射面をAu層により問題なく形成できる。
【0021】
本発明の発光素子の製造方法においては、Au層により反射面を形成する場合、Au層と化合物半導体層との間に、Auを主成分とする発光層部側接合層を、Au層の主表面上に分散する形で配置することができる。Au層は、発光層部への通電経路の一部をなす。しかし、Au層を化合物半導体よりなる発光層部に直接接合すると、接触抵抗が高くなり、直列抵抗が増加して発光効率が低下する場合がある。Au層を、Au系接合層を介して発光層部に接合することにより接触抵抗の低減を図ることができる。ただし、Au系接合層は、コンタクト確保のために必要な合金成分を比較的多量に配合する必要があり、反射率が若干劣る。そこで、発光層部側接合層をAu層の主表面上に分散形成しておけば、発光層部側接合層の非形成領域ではAu層による高い反射率を確保できる。
【0022】
発光層部側接合層としては、これと接する化合物半導体層をn型のIII−V族化合物半導体(前述の(AlGa1−xIn1−yP(ただし、0≦x≦1,0≦y≦1))にて構成する場合、AuGeNi接合層を採用することにより接触抵抗の低減効果が特に高くなる。この場合、該化合物半導体層の貼り合わせ側主表面にAuGeNi接合層を形成し、該AuGeNi接合層を覆うように前記の第一Au層を形成することができる。AuGeNi接合層と化合物半導体層との合金化熱処理は、例えば350℃以上500℃以下にて行なうことにより、接触抵抗の低減効果が高められる。
【0023】
なお、光取出効果を十分に高めるために、Au層(第一Au層)に対する発光層部側接合層の形成面積率(Au層の全面積にて発光層部側接合層の形成面積を除した値である)は1%以上25%以下とすることが望ましい。発光層部側接合層の形成面積率が1%未満では接触抵抗の低減効果が十分でなくなり、25%を超えると反射強度が低下することにつながる。
【0024】
Au層は、発光層部側接合層よりもAu含有率を高く設定しておくことで、発光層部側接合層の非形成領域において、Au層の反射率を一層高めることができる。
【0025】
なお、本発明において金属層の具体的な形成方法としては、真空蒸着やスパッタリングなどの気相成膜法のほか、無電解メッキあるいは電解メッキなどの電気化学的な成膜法を採用することもできる。
【0026】
【発明の実施の形態】
以下、本発明の実施の形態を添付の図面を参照して説明する。
図1は、本発明の一実施形態である発光素子100を示す概念図である。発光素子100は、素子基板をなす導電性基板であるn型Si(シリコン)単結晶よりなるSi基板7の一方の主表面上に金属層10を介して発光層部24が貼り合わされた構造を有してなる。
【0027】
発光層部24は、ノンドープ(AlGa1−xIn1−yP(ただし、0≦x≦0.55,0.45≦y≦0.55)混晶からなる活性層5を、第一導電型クラッド層、本実施形態ではp型(AlGa1−zIn1−yP(ただしx<z≦1)からなるp型クラッド層6と、前記第一導電型クラッド層とは異なる第二導電型クラッド層、本実施形態ではn型(AlGa1−zIn1−yP(ただしx<z≦1)からなるn型クラッド層4とにより挟んだ構造を有し、活性層5の組成に応じて、発光波長を、緑色から赤色領域(発光波長(ピーク発光波長)が550nm以上670nm以下)にて調整できる。発光素子100においては、金属電極9側にp型AlGaInPクラッド層6が配置されており、金属層10側にn型AlGaInPクラッド層4が配置されている。従って、通電極性は金属電極9側が正である。なお、ここでいう「ノンドープ」とは、「ドーパントの積極添加を行なわない」との意味であり、通常の製造工程上、不可避的に混入するドーパント成分の含有(例えば1013〜1016/cm程度を上限とする)をも排除するものではない。
【0028】
また、発光層部24の基板7に面しているのと反対側の主表面上には、AlGaAsよりなる電流拡散層20が形成され、その主表面の略中央に、発光層部24に発光駆動電圧を印加するための金属電極(例えばAu電極)9が、該主表面の一部を覆うように形成されている。電流拡散層20の主表面における、金属電極9の周囲の領域は、発光層部24からの光取出領域をなす。また、Si単結晶基板7の裏面にはその全体を覆うように金属電極(裏面電極:例えばAu電極である)15が形成されている。金属電極15がAu電極である場合、金属電極15とSi単結晶基板7との間には基板側接合層として、AuSb接合層16が介挿される。なお、AuSb接合層16に代えてAuSn接合層を基板側接合層として用いてもよい。
【0029】
Si単結晶基板7は、Si単結晶インゴットをスライス・研磨して製造されたものであり、その厚みは例えば100μm以上500μm以下である。そして、発光層部24に対し、金属層10を挟んで貼り合わされている。金属層10は全体が純AuよりなるAu層として構成され、発光層部24(化合物半導体層)と接する第一Au層10aと、Si基板7と接する第二Au層10bとが貼り合せ熱処理により貼り合わされたものである。
【0030】
発光層部24と第一Au層10aとの間には、発光層部側接合層としてAuGeNi接合層32(例えばGe:15質量%、Ni:10質量%)が形成されており、素子の直列抵抗低減に貢献している。AuGeNi接合層32は、第一Au層10aの主表面上に分散形成され、その形成面積率は1%以上25%以下である。また、Si単結晶基板7と第二Au層10bとの間には、基板側接合層としてAuSb接合層31(例えばSb:5質量%)が介挿されている。なお、AuSb接合層31に代えてAuSn接合層を用いてもよい。そして、第一Au層10a、第二Au層10b、AuSb接合層31及びAuGeNi接合層32が金属層10を構成し、これが発光層部24とSi基板7とのいずれとも接する形で配置されている
【0031】
発光層部24からの光は、光取出面側に直接放射される光に、金属層10による反射光が重畳される形で取り出される。金属層10の厚さは、反射効果を十分に確保するため、80nm以上とすることが望ましい。また、厚さの上限には制限は特にないが、反射効果が飽和するため、コストとの兼ね合いにより適当に定める(例えば1μm程度)。
【0032】
以下、図1の発光素子100の製造方法について説明する。
まず、図2の工程1に示すように、発光層成長用基板をなす半導体単結晶基板であるGaAs単結晶基板1の主表面に、p型GaAsバッファ層2を例えば0.5μm、AlAsからなる剥離層3を例えば0.5μm、さらにp型AlGaAsよりなる電流拡散層20を例えば5μm、この順序にてエピタキシャル成長させる。また、その後、発光層部24として、1μmのp型AlGaInPクラッド層6、0.6μmのAlGaInP活性層(ノンドープ)5、及び1μmのn型AlGaInPクラッド層4を、この順序にエピタキシャル成長させる。
【0033】
次に、工程2に示すように、発光層部24の主表面に、AuGeNi接合層32を分散形成する。AuGeNi接合層32を形成後、350℃以上500℃以下の温度域で合金化熱処理を行ない、その後、AuGeNi接合層32を覆うように第一Au層10aを形成する。発光層部24とAuGeNi接合層32との間には、上記合金化熱処理により合金化層が形成され、直列抵抗が大幅に低減される。他方、工程3に示すように、別途用意したSi単結晶基板7(n型)の両方の主表面に基板側接合層となるAuSb接合層31,16(前述の通りAuSn接合層でもよい)を形成し、250℃以上359℃以下の温度域で合金化熱処理を行なう。そして、AuSb接合層31上には第二Au層10bを、AuSb接合層16上には裏面電極層15(例えばAu系金属よりなるもの)をそれぞれ形成する。以上の工程で各金属層は、スパッタリングあるいは真空蒸着等を用いて行なうことができる。
【0034】
そして、工程4に示すように、Si単結晶基板7側の第二Au層10bを、発光層部24上に形成された第一Au層10aに重ね合わせて圧迫して、180℃よりも高温かつ250℃以下、例えば250℃にて貼り合せ熱処理することにより、基板貼り合わせ体50を作る。Si単結晶基板7は、第一Au層10a及び第二Au層10bを介して発光層部24に貼り合わせられる。また、第一Au層10aと第二Au層10bとは、上記貼り合せ熱処理を採用することにより十分な強度にて結合され、AuSb接合層31及びAuGeNi接合層32とともに金属層10となる。第一Au層10a及び第二Au層10bが、いずれも酸化しにくいAuを主体に構成されているため、上記貼り合せ熱処理は、例えば大気中でも問題なく行なうことができる。
【0035】
次に、工程5に進み、上記基板貼り合わせ体50を、例えば10%フッ酸水溶液からなるエッチング液に浸漬し、バッファ層2と発光層部24との間に形成したAlAs剥離層3を選択エッチングすることにより、GaAs単結晶基板1(発光層部24からの光に対して不透明である)を、発光層部24とこれに接合されたSi単結晶基板7との積層体50aから剥離する。なお、AlAs剥離層3に代えてAlInPよりなるエッチストップ層を形成しておき、GaAsに対して選択エッチング性を有する第一エッチング液(例えばアンモニア/過酸化水素混合液)を用いてGaAs単結晶基板1をGaAsバッファ層2とともにエッチング除去し、次いでAlInPに対して選択エッチング性を有する第二エッチング液(例えば塩酸:Al酸化層除去用にフッ酸を添加してもよい)を用いてエッチストップ層をエッチング除去する工程を採用することもできる。
【0036】
そして、工程6に示すように、GaAs単結晶基板1の剥離により露出した電流拡散層20の主表面の一部を覆うように、ワイヤボンディング用の電極9(ボンディングパッド:図1)を形成する。以下、通常の方法によりダイシングして半導体チップとし、これを支持体に固着してリード線のワイヤボンディング等を行なった後、樹脂封止をすることにより最終的な発光素子が得られる。
【0037】
なお、素子基板としてSi基板を使用する以外に、他の導電性基板、例えばAl(合金含む)などの金属基板を用いることも可能である。
【0038】
さらに、発光層部24の各層は、AlGaInN混晶により形成することもできる。発光層部24を成長させるための発光層成長用基板は、GaAs単結晶基板に代えて、例えばサファイア基板(絶縁体)やSiC単結晶基板が使用される。また、発光層部24の各層は、上記実施形態では、基板側からn型クラッド層4、活性層5及びp型クラッド層6の順になっていたが、これを反転させ、基板側からp型クラッド、活性層及びn型クラッド層の順に形成してもよい。
【図面の簡単な説明】
【図1】 本発明の適用対象となる発光素子の第一実施形態を積層構造にて示す模式図。
【図2】 図1の発光素子の製造工程の一例を示す説明図。
【図3】 Au層の反射率の波長依存性を示すグラフ。
【符号の説明】
1 GaAs単結晶基板(発光層成長用基板)
4 n型クラッド層(第二導電型クラッド層)
5 活性層
6 p型クラッド層(第一導電型クラッド層)
7 Si単結晶基板(素子基板)
9 金属電極
10 Au層
10a 第一Au層
10b 第二Au層
24 発光層部
31 AuSb層(基板側接合層)
32 AuGeNi接合層31(発光層部側接合層)
100 発光素子
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a light emitting device.
[0002]
[Prior art]
[Patent Document 1]
Japanese Patent Laid-Open No. 7-66455 [Patent Document 2]
Japanese Patent Laid-Open No. 2001-339100
As a result of many years of progress in materials and element structures used in light-emitting elements such as light-emitting diodes and semiconductor lasers, the photoelectric conversion efficiency inside the elements is gradually approaching the theoretical limit. Therefore, when an element with higher luminance is to be obtained, the light extraction efficiency from the element is extremely important. A light emitting device in which a light emitting layer portion is formed of a III-V compound semiconductor, for example, an AlGaInP mixed crystal, includes a thin AlGaInP (or GaInP) active layer, an n-type AlGaInP cladding layer having a larger band gap, and a p-type AlGaInP. By adopting a double hetero structure sandwiched between clad layers, a high-luminance element can be realized. Such an AlGaInP double heterostructure can be formed by epitaxially growing each layer of an AlGaInP mixed crystal on a GaAs single crystal substrate by utilizing the lattice matching of the AlGaInP mixed crystal with GaAs. When this is used as a light emitting element, a GaAs single crystal substrate is usually used as an element substrate as it is. However, since the AlGaInP mixed crystal constituting the light emitting layer has a larger band gap than GaAs, the emitted light is absorbed by the GaAs substrate, and it is difficult to obtain sufficient light extraction efficiency. In order to solve this problem, a method (for example, Patent Document 1) in which a reflective layer made of a semiconductor multilayer film is inserted between a substrate and a light emitting element has also been proposed. Therefore, only light incident at a limited angle is reflected, and a significant improvement in light extraction efficiency cannot be expected in principle.
[0004]
Therefore, in various publications including Patent Document 2, a growth GaAs substrate is peeled off, while a reinforcing element substrate (having conductivity) is placed on a peeling surface through a reflective Au layer. A technique for pasting is disclosed. This Au layer has an advantage that the reflectivity is high and the dependency of the reflectivity on the incident angle is small.
[0005]
[Problems to be solved by the invention]
However, in the above method, it is difficult to secure the bonding strength when the Au layer forming the reflective layer is bonded to the light emitting layer portion, leading to defects such as peeling, and a good bonding state cannot be obtained. It was difficult to avoid a decrease in reflectivity. Further, when the heat treatment temperature for bonding is increased to increase the bonding strength, the metallurgical reaction between the light emitting layer or the conductive substrate (particularly the Si substrate) and the Au layer becomes remarkable, and the state of the obtained reflecting surface is improved. There is a problem that the deterioration of the reflectance is more likely to be caused.
[0006]
An object of the present invention is to produce a light emitting device having a structure in which a light emitting layer portion and an element substrate are bonded together through a metal layer having an Au layer , and sufficient bonding even when the heat treatment temperature of the bonding is low. An object of the present invention is to provide a method for manufacturing a light emitting element and a light emitting element that can obtain strength and can maintain a favorable state of a reflecting surface.
[0007]
[Means for solving the problems and actions / effects]
In order to solve the above problems, a method for manufacturing a light-emitting element of the present invention includes:
One main surface of a compound semiconductor layer made of a III-V compound semiconductor is used as a light extraction surface, and the other main surface side of the compound semiconductor layer is a reflection surface that reflects light from the light emitting layer portion to the light extraction surface side. An Au layer made of pure Au (which may contain inevitable impurities as long as it is within 1% by mass) , wherein the element substrate is bonded through a metal layer having a metal layer, and the reflective surface of the metal layer includes a reflective surface; In order to manufacture a light emitting device,
The main surface opposite to the light extraction surface of the compound semiconductor layer having the light emitting layer portion is used as a bonding-side main surface, and the bonding semiconductor layer is made of pure Au and forms a reflective surface on the bonding-side main surface . Arrange the first Au layer ,
Further, a light-emitting layer side bonding layer mainly composed of Au is disposed between the first Au layer and the compound semiconductor layer so as to be dispersed on the main surface of the first Au layer. The region where the light emitting layer side bonding layer is not formed is a reflective surface,
The main surface of the element substrate, which is scheduled to be located on the light emitting layer portion side, is used as a bonding-side main surface, and a second Au layer made of pure Au is disposed on the bonding-side main surface,
The first Au layer and the second Au layer are brought into close contact with each other and bonded together by heat treatment at a temperature higher than 180 ° C. and 250 ° C. or lower . In the present specification, “main component” refers to a component having the highest mass content.
[0008]
According to the method of the present invention, the first and second Au layers are formed separately on the compound semiconductor layer side and the element substrate side, and these are adhered and bonded together. Since the Au layers are easily integrated even at a relatively low temperature, sufficient bonding strength can be obtained even when the heat treatment temperature for bonding is low, and the reflective surface of the metal reflective layer including the Au layer is also in a good state Can be easily formed. Since the reflective surface itself is composed of a highly corrosion-resistant Au layer , the light emitting layer growth substrate peeling process and the light emitting layer surface roughening process (so-called frost process) described later are performed during the manufacturing process of the light emitting element. Even when chemical treatment using highly corrosive liquids is applied to the compound semiconductor layer, there is no concern that corrosion will permeate the reflective surface, so the manufacturing process can be simplified and the state of the reflective surface Hard to be damaged.
[0009]
The light emitting layer portion preferably emits visible light having a peak wavelength of 550 nm or more. FIG. 3 is a graph showing the wavelength dependence of the reflectance of the Au layer. It can be seen that there is strong absorption in the visible light region with a wavelength of less than 550 nm. Therefore, when the peak wavelength of the light emitting layer portion is set to 550 nm or more, a decrease in reflectance can be effectively suppressed and the light emission intensity can be improved. In addition, the extracted light spectrum is unlikely to be different from the original emission spectrum due to absorption, and the problem that the emission color tone changes is less likely to occur. From this point of view, desirable color tone and peak wavelength range of light emission of the light emitting layer portion are as follows:
Yellowish green: 550 nm to less than 580 nm Yellow: 580 nm to less than 595 nm Amber: 595 nm to less than 610 nm Orange: 610 nm to less than 630 nm Red: 630 nm to less than 780 nm
As is apparent from FIG. 3, when the peak wavelength of the light emitting layer portion is desirably 580 nm or more, more desirably 600 nm or more, the reflectance is further improved and the emission intensity can be increased. From this point of view, when the light emitting layer portion is yellow, amber, orange or red, the reflectance by the Au layer can be particularly increased, and the effect of improving the light emission intensity becomes remarkable.
[0011]
Specifically, the manufacturing method of the light-emitting element of the present invention includes:
A light emitting layer portion is epitaxially grown on a light emitting layer growth substrate made of a compound semiconductor,
In a state where the substrate for light emitting layer growth is integrated, a first Au layer is formed on the main surface of the light emitting layer bonded side,
On the other hand, a second Au layer is formed on the bonding substrate main surface of the element substrate,
Adhering the first Au layer and the second Au layer in close contact,
After the bonding, a step of peeling the light emitting layer growth substrate from the light emitting layer portion by chemical etching can be employed.
[0012]
According to this step, in a state where the substrate for growing the light emitting layer is integrated, the first Au layer is pasted on the main surface of the light emitting layer bonded side and the second Au layer is pasted on the main surface of the element substrate bonded side. Therefore, the light emitting layer portion formed as a thin layer can be handled for bonding in a form accompanied by mechanical reinforcement by the light emitting layer growth substrate. As a result, for example, compared with the case where a process of peeling the light emitting layer part before bonding is employed, the probability of occurrence of a problem that the light emitting layer part is cracked or chipped is greatly reduced, and the process can be simplified dramatically. . In this case, after bonding, the light emitting layer growth substrate is peeled off from the light emitting layer portion by chemical etching. However, since the portion forming the reflective surface is formed of the Au layer , the influence of chemical etching is affected by the reflective surface. In this way, there is no problem such as peeling of the light emitting layer during etching.
[0013]
For example, when the light emitting layer portion is made of (Al x Ga 1-x ) y In 1-y P (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1) and the light emitting layer growth substrate is made of a GaAs substrate, Chemical etching can be performed by dissolving the GaAs substrate using an ammonia / hydrogen peroxide mixture. The ammonia / hydrogen peroxide mixture is excellent in selective corrosion of the GaAs substrate with respect to (Al x Ga 1-x ) y In 1-y P, and only the GaAs substrate is rapidly and simply immersed in the solution. Peeling and removal can be ensured. Further, there is no concern about corrosion of the Au layer forming the reflective surface. In the present invention, removing all of the light emitting layer growth substrate by etching also belongs to the concept of “peeling”.
[0014]
On the other hand, a GaAs substrate in which a light emitting layer portion made of (Al x Ga 1-x ) y In 1-y P (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1) forms a growth substrate through an AlAs release layer It can also be grown and chemical etching can be performed in the form of dissolving the AlAs release layer using a solution containing hydrofluoric acid. If the AlAs release layer is dissolved with a solution containing hydrofluoric acid, the GaAs substrate can be easily released from the light emitting layer portion. Further, there is no concern about corrosion of the Au layer forming the reflective surface. In this case, since the GaAs substrate is not dissolved, it can be reused for the growth of the next light emitting layer.
[0015]
Then, when the light emitting layer portion is made of a Group III-V compound semiconductor, a first Au layer and the second Au layer both the Au content as the Au-based metal over 95 wt%, and their first Au layer The second Au layer can be adhered to each other, and in this state, bonding can be performed by performing a bonding heat treatment at a temperature higher than 180 ° C. and 360 ° C. or less. According to this method, the first and second Au layers are formed separately on the compound semiconductor layer side and the element substrate side made of a III-V group compound semiconductor, and these are adhered and bonded together. The first Au layer and the second Au layer are easily bonded by performing a heat treatment of bonding at a temperature higher than 180 ° C. and 360 ° C. or lower because the Au content is 95% by mass or more. Therefore, sufficient bonding strength can easily be obtained, and, at the time of bonding heat treatment, the Au layer diffusion and effects of the reaction is Oyobi difficult from the substrate side or a compound semiconductor layer side with respect to, the metal reflective layer containing Au layer A reflective surface having a good state can be easily formed.
[0016]
[0017]
As described above, the upper limit of the bonding heat treatment temperature is set to 250 ° C. in order to suppress the influence of diffusion and reaction from the substrate side or the compound semiconductor layer side on the Au layer . For example, a Si substrate can be used as the element substrate. The Si substrate can easily ensure sufficient conductivity as a light emitting element by doping, and is inexpensive. However, Si easily diffuses into Au and tends to cause a eutectic reaction at a relatively low temperature (the eutectic temperature of the Au—Si binary system is 363 ° C.). Therefore, if the heat treatment temperature for the bonding becomes too high even a little, Si forming the element substrate diffuses into the Au layer in the metal reflection layer or causes a eutectic reaction, resulting in a significant decrease in reflectivity. Cheap. However, as in the present invention, by setting the heat treatment temperature to 250 ° C. or less by bonding the Au layers together, it is possible to perform the bonding heat treatment at a temperature sufficiently lower than the eutectic temperature, and good reflection The rate and the bonding strength can be ensured.
[0018]
When the compound semiconductor layer on which the first Au layer is formed is composed of a III-V group compound semiconductor, the first Au layer and the second Au layer are brought into close contact with each other and subjected to bonding heat treatment with an external heat source. Heat is transferred to the first Au layer through the compound semiconductor layer, but the III-V group compound semiconductor generally has a lower thermal conductivity than other semiconductors such as Si. For this reason, when the bonding heat treatment temperature is excessively lowered, heat transfer to the first Au layer is inhibited by the III-V group compound semiconductor layer, and a strong bonding state with the second Au layer cannot be obtained. Therefore, in the present invention, by setting the bonding heat treatment temperature higher than 180 ° C., the first Au layer and the second Au layer are formed even though the thermal conductivity of the III-V compound semiconductor layer is not so high. The layers can be bonded with sufficient strength. In particular, when the compound semiconductor layer is composed of at least one group III element selected from Al, Ga and In and the group V element is composed of one or more selected from P and As, the effect is particularly remarkable. .
[0019]
When a Si substrate is used as the element substrate, a substrate side bonding layer is formed on the bonded main surface of the element substrate, a second Au layer is formed so as to cover the substrate side bonding layer, and the substrate side bonding layer and Si Alloying heat treatment with the substrate can be performed. When an n-type Si substrate is used, the substrate-side bonding layer can be composed of an AuSb alloy or an AuSn alloy. In this case, the effect of reducing contact resistance is enhanced by performing the alloying heat treatment between the substrate-side bonding layer and the Si substrate at, for example, 250 ° C. or more and 500 ° C. or less.
[0020]
In the present invention, the reflective surface can be formed by the first Au layer . Since the Au layer is chemically stable and does not easily cause reflectance deterioration due to oxidation or the like, it is suitable as a material for forming the reflecting surface. In particular, when using a Si substrate, when eutectic reaction between Au of the first Au layer forming the reflective surface and Si forming the Si substrate proceeds, a decrease in reflectance is particularly likely to occur. As a result of suppressing such a defect extremely effectively, a reflective surface having a good reflectance can be formed without any problem by the Au layer .
[0021]
In the method of manufacturing the light emitting device of the present invention, when forming the reflecting surface by Au layer, between the Au layer and the compound semiconductor layer, a light-emitting layer side bonding layer mainly composed of Au, Lord Au layer It can be arranged in a distributed manner on the surface. The Au layer forms a part of a current path to the light emitting layer portion. However, when the Au layer is directly bonded to the light emitting layer portion made of a compound semiconductor, the contact resistance increases, the series resistance increases, and the light emission efficiency may decrease. Contact resistance can be reduced by bonding the Au layer to the light emitting layer portion via an Au-based bonding layer. However, the Au-based bonding layer needs to contain a relatively large amount of alloy components necessary for securing the contact, and the reflectance is slightly inferior. Therefore, the light emitting layer portion side bonding layer if dispersed formed on the main surface of the Au layer can secure a high reflectance by the Au layer in the non-formation region of the light emitting layer side bonding layer.
[0022]
As the light emitting layer portion-side bonding layer, the compound semiconductor layer in contact with the n-type III-V group compound semiconductor (the aforementioned (Al x Ga 1-x ) y In 1-y P (where 0 ≦ x ≦ 1 , 0 ≦ y ≦ 1)), the effect of reducing the contact resistance is particularly enhanced by adopting the AuGeNi bonding layer. In this case, an AuGeNi bonding layer can be formed on the bonded main surface of the compound semiconductor layer, and the first Au layer can be formed so as to cover the AuGeNi bonding layer. The alloying heat treatment between the AuGeNi bonding layer and the compound semiconductor layer is performed at, for example, 350 ° C. or more and 500 ° C. or less, thereby enhancing the contact resistance reduction effect.
[0023]
In order to increase the light extraction effect sufficiently, the area for forming the light emitting layer side bonding layer in the total area of the formation area ratio of the light emitting layer side bonding layer (Au layer to the Au layer (the first Au layer) divided Is preferably 1% or more and 25% or less. If the formation area ratio of the light emitting layer side bonding layer is less than 1%, the effect of reducing the contact resistance is not sufficient, and if it exceeds 25%, the reflection intensity decreases.
[0024]
By setting the Au content of the Au layer higher than that of the light emitting layer portion side bonding layer, the reflectance of the Au layer can be further increased in the non-formation region of the light emitting layer portion side bonding layer.
[0025]
In the present invention, as a specific method for forming the metal layer, in addition to a vapor deposition method such as vacuum deposition or sputtering, an electrochemical deposition method such as electroless plating or electrolytic plating may be employed. it can.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a conceptual diagram showing a light emitting device 100 according to an embodiment of the present invention. The light emitting element 100 has a structure in which a light emitting layer portion 24 is bonded to one main surface of a Si substrate 7 made of n-type Si (silicon) single crystal, which is a conductive substrate constituting an element substrate, with a metal layer 10 interposed therebetween. Have.
[0027]
The light emitting layer portion 24 includes the active layer 5 made of a non-doped (Al x Ga 1-x ) y In 1-y P (where 0 ≦ x ≦ 0.55, 0.45 ≦ y ≦ 0.55) mixed crystal. , the first-conductivity-type cladding layer, in this embodiment the p-type cladding layer 6 made of p-type (Al z Ga 1-z) y in 1-y P ( except x <z ≦ 1), wherein the first conductivity type the second-conductivity-type cladding layer different from the clad layer, in this embodiment interposed by an n-type (Al z Ga 1-z) y in 1-y P ( except x <z ≦ 1) n-type cladding layer 4 made of According to the composition of the active layer 5, the emission wavelength can be adjusted in the green to red region (the emission wavelength (peak emission wavelength) is 550 nm or more and 670 nm or less). In the light emitting device 100, the p-type AlGaInP cladding layer 6 is disposed on the metal electrode 9 side, and the n-type AlGaInP cladding layer 4 is disposed on the metal layer 10 side. Therefore, the conduction polarity is positive on the metal electrode 9 side. The term “non-doped” as used herein means “does not actively add a dopant”, and contains a dopant component inevitably mixed in a normal manufacturing process (for example, 10 13 to 10 16 / cm 3). It is not excluded that the upper limit is about 3 ).
[0028]
A current diffusion layer 20 made of AlGaAs is formed on the main surface of the light emitting layer 24 opposite to the surface facing the substrate 7, and the light emitting layer 24 emits light at substantially the center of the main surface. A metal electrode (for example, Au electrode) 9 for applying a driving voltage is formed so as to cover a part of the main surface. A region around the metal electrode 9 on the main surface of the current diffusion layer 20 forms a light extraction region from the light emitting layer portion 24. Further, a metal electrode (back electrode: for example, an Au electrode) 15 is formed on the back surface of the Si single crystal substrate 7 so as to cover the entire surface. When the metal electrode 15 is an Au electrode, an AuSb bonding layer 16 is interposed between the metal electrode 15 and the Si single crystal substrate 7 as a substrate-side bonding layer. Note that an AuSn bonding layer may be used as the substrate-side bonding layer instead of the AuSb bonding layer 16.
[0029]
The Si single crystal substrate 7 is manufactured by slicing and polishing a Si single crystal ingot, and the thickness thereof is, for example, 100 μm or more and 500 μm or less. Then, the light emitting layer portion 24 is bonded with the metal layer 10 interposed therebetween. The metal layer 10 is entirely configured as an Au layer made of pure Au, and the first Au layer 10a in contact with the light emitting layer portion 24 (compound semiconductor layer) and the second Au layer 10b in contact with the Si substrate 7 are bonded together by heat treatment. It is what was pasted together.
[0030]
An AuGeNi bonding layer 32 (for example, Ge: 15% by mass, Ni: 10% by mass) is formed between the light emitting layer part 24 and the first Au layer 10a as the light emitting layer part side bonding layer, and the series of elements. Contributes to resistance reduction. The AuGeNi bonding layer 32 is dispersedly formed on the main surface of the first Au layer 10a, and the formation area ratio thereof is 1% or more and 25% or less. Further, an AuSb bonding layer 31 (for example, Sb: 5% by mass) is interposed between the Si single crystal substrate 7 and the second Au layer 10b as a substrate-side bonding layer. Note that an AuSn bonding layer may be used instead of the AuSb bonding layer 31. The first Au layer 10a, the second Au layer 10b, the AuSb bonding layer 31, and the AuGeNi bonding layer 32 constitute the metal layer 10, which is disposed in contact with both the light emitting layer portion 24 and the Si substrate 7. Yes .
[0031]
The light from the light emitting layer part 24 is extracted in a form in which the light reflected directly from the light extraction surface is superimposed on the light reflected by the metal layer 10. The thickness of the metal layer 10 is preferably 80 nm or more in order to ensure a sufficient reflection effect. Moreover, although there is no restriction | limiting in particular in the upper limit of thickness, since a reflective effect is saturated, it determines suitably (for example, about 1 micrometer) by balance with cost.
[0032]
Hereinafter, a method for manufacturing the light emitting device 100 of FIG. 1 will be described.
First, as shown in Step 1 of FIG. 2, a p-type GaAs buffer layer 2 is made of, for example, 0.5 μm and AlAs on the main surface of a GaAs single crystal substrate 1 which is a semiconductor single crystal substrate forming a light emitting layer growth substrate. The peeling layer 3 is epitaxially grown in this order, for example, 0.5 μm, and the current diffusion layer 20 made of p-type AlGaAs is, for example, 5 μm. Thereafter, a 1 μm p-type AlGaInP cladding layer 6, a 0.6 μm AlGaInP active layer (non-doped) 5, and a 1 μm n-type AlGaInP cladding layer 4 are epitaxially grown in this order as the light emitting layer portion 24.
[0033]
Next, as shown in step 2, the AuGeNi bonding layer 32 is dispersedly formed on the main surface of the light emitting layer portion 24. After forming the AuGeNi bonding layer 32, an alloying heat treatment is performed in a temperature range of 350 ° C. or more and 500 ° C. or less, and then the first Au layer 10a is formed so as to cover the AuGeNi bonding layer 32. An alloying layer is formed between the light emitting layer portion 24 and the AuGeNi bonding layer 32 by the alloying heat treatment, and the series resistance is greatly reduced. On the other hand, as shown in Step 3, AuSb bonding layers 31 and 16 (which may be AuSn bonding layers as described above) serving as substrate-side bonding layers are formed on both main surfaces of a separately prepared Si single crystal substrate 7 (n-type). Then, an alloying heat treatment is performed in a temperature range of 250 ° C. or more and 359 ° C. or less. Then, the second Au layer 10b is formed on the AuSb bonding layer 31, and the back electrode layer 15 (for example, made of Au-based metal) is formed on the AuSb bonding layer 16. In the above steps, each metal layer can be formed by sputtering or vacuum deposition.
[0034]
Then, as shown in step 4, the second Au layer 10 b on the Si single crystal substrate 7 side is superposed on the first Au layer 10 a formed on the light emitting layer portion 24 and pressed to be higher than 180 ° C. and 250 ° C. or less, for example, by combined thermal treatment bonded at 250 ° C., creating a substrate bonding body 50. The Si single crystal substrate 7 is bonded to the light emitting layer portion 24 via the first Au layer 10a and the second Au layer 10b. Further, the first Au layer 10a and the second Au layer 10b are bonded with sufficient strength by adopting the bonding heat treatment, and become the metal layer 10 together with the AuSb bonding layer 31 and the AuGeNi bonding layer 32. Since both the first Au layer 10a and the second Au layer 10b are mainly composed of Au that is not easily oxidized, the bonding heat treatment can be performed without any problem even in the atmosphere, for example.
[0035]
Next, proceeding to step 5, the substrate bonded body 50 is immersed in an etching solution made of, for example, a 10% hydrofluoric acid aqueous solution, and the AlAs release layer 3 formed between the buffer layer 2 and the light emitting layer portion 24 is selected. By etching, the GaAs single crystal substrate 1 (which is opaque to the light from the light emitting layer portion 24) is peeled from the stacked body 50a of the light emitting layer portion 24 and the Si single crystal substrate 7 bonded thereto. . It should be noted that an etch stop layer made of AlInP is formed in place of the AlAs release layer 3, and a GaAs single crystal is used by using a first etching solution (for example, ammonia / hydrogen peroxide mixed solution) having selective etching properties with respect to GaAs. Etch and remove the substrate 1 together with the GaAs buffer layer 2 and then etch stop using a second etchant that has selective etching properties with respect to AlInP (for example, hydrochloric acid: hydrofluoric acid may be added to remove the Al oxide layer) A step of etching away the layer can also be employed.
[0036]
Then, as shown in step 6, a wire bonding electrode 9 (bonding pad: FIG. 1) is formed so as to cover a part of the main surface of the current diffusion layer 20 exposed by peeling off the GaAs single crystal substrate 1. . Thereafter, the semiconductor chip is diced by a normal method, and this is fixed to a support and wire bonding of a lead wire is performed, followed by resin sealing to obtain a final light emitting element.
[0037]
In addition to using the Si substrate as the element substrate, another conductive substrate, for example, a metal substrate such as Al (including an alloy) can be used.
[0038]
Furthermore, each layer of the light emitting layer portion 24 can also be formed of an AlGaInN mixed crystal. For example, a sapphire substrate (insulator) or a SiC single crystal substrate is used as the light emitting layer growth substrate for growing the light emitting layer portion 24 instead of the GaAs single crystal substrate. In the above embodiment, each layer of the light emitting layer portion 24 is in the order of the n-type cladding layer 4, the active layer 5, and the p-type cladding layer 6 from the substrate side. The clad, the active layer, and the n-type clad layer may be formed in this order.
[Brief description of the drawings]
FIG. 1 is a schematic view showing a first embodiment of a light emitting device to which the present invention is applied in a laminated structure.
FIG. 2 is an explanatory view showing an example of a manufacturing process of the light-emitting element of FIG.
FIG. 3 is a graph showing the wavelength dependence of the reflectance of the Au layer.
[Explanation of symbols]
1 GaAs single crystal substrate (light emitting layer growth substrate)
4 n-type cladding layer (second conductivity type cladding layer)
5 active layer 6 p-type cladding layer (first conductivity type cladding layer)
7 Si single crystal substrate (element substrate)
9 Metal electrode 10 Au layer 10a First Au layer 10b Second Au layer 24 Light-emitting layer part 31 AuSb layer (substrate-side bonding layer)
32 AuGeNi bonding layer 31 (light emitting layer side bonding layer)
100 light emitting device

Claims (8)

III−V族化合物半導体からなる化合物半導体層の一方の主表面を光取出面とし、該化合物半導体層の他方の主表面側に、前記発光層部からの光を前記光取出面側に反射させる反射面を有した金属層を介して素子基板が結合され、かつ前記金属層の前記反射面を含む部分が純AuよりなるAu層とされた発光素子を製造するために、
前記発光層部を有した化合物半導体層の光取出面になるのと反対側の主表面を貼り合わせ側主表面として、該貼り合わせ側主表面に前記反射面を形成する純Auよりなる貼り合せ用の第一Au層を配置し、
また、前記第一Au層と前記化合物半導体層との間に、Auを主成分とする発光層部側接合層を、前記第一Au層の主表面上に分散する形で配置し、前記第一Au層の前記発光層部側接合層が非形成となる領域が前記反射面とされ、
前記素子基板の、前記発光層部側に位置することが予定された主表面を貼り合わせ側主表面として、該貼り合わせ側主表面に純Auよりなる第二Au層を配置し、
それら第一Au層と第二Au層とを密着させ、その状態で180℃よりも高温かつ250℃以下にて貼り合わせ熱処理することにより貼り合わせることを特徴とする発光素子の製造方法。
One main surface of the compound semiconductor layer made of a group III-V compound semiconductor is used as a light extraction surface, and the light from the light emitting layer portion is reflected to the light extraction surface side on the other main surface side of the compound semiconductor layer. In order to manufacture a light emitting device in which an element substrate is bonded through a metal layer having a reflective surface, and a portion including the reflective surface of the metal layer is an Au layer made of pure Au .
Bonding made of pure Au that forms the reflecting surface on the bonding-side main surface, with the main surface opposite to the light extraction surface of the compound semiconductor layer having the light-emitting layer portion as the bonding-side main surface For the first Au layer ,
Further, a light emitting layer side bonding layer mainly composed of Au is disposed between the first Au layer and the compound semiconductor layer so as to be dispersed on the main surface of the first Au layer. The region where the light emitting layer part side bonding layer of one Au layer is not formed is the reflective surface,
The main surface of the element substrate that is scheduled to be located on the light emitting layer portion side is used as a bonding-side main surface, and a second Au layer made of pure Au is disposed on the bonding-side main surface,
A method for manufacturing a light emitting element, comprising : bonding the first Au layer and the second Au layer in close contact with each other by performing a bonding heat treatment at a temperature higher than 180 ° C. and 250 ° C. or lower .
前記発光層部は、ピーク波長が550nm以上の可視光を発光するものであることを特徴とする請求項1記載の発光素子の製造方法。  The method for manufacturing a light-emitting element according to claim 1, wherein the light-emitting layer portion emits visible light having a peak wavelength of 550 nm or more. 化合物半導体よりなる発光層成長用基板上に前記発光層部をエピタキシャル成長させ、
前記発光層成長用基板が一体化された状態において、前記発光層部の前記貼り合わせ側主表面に前記第一Au層を形成し、
他方、前記素子基板の前記貼り合わせ側主表面に前記第二Au層を形成し、
前記第一Au層と第二Au層とを密着させて貼り合わせ、
その貼り合わせ後に、前記発光層部から前記発光層成長用基板を化学エッチングにより剥離することを特徴とする請求項1又は請求項2に記載の発光素子の製造方法。
The light emitting layer portion is epitaxially grown on a light emitting layer growth substrate made of a compound semiconductor,
In the state where the light emitting layer growth substrate is integrated, the first Au layer is formed on the bonded main surface of the light emitting layer portion,
On the other hand, the second Au layer is formed on the bonding side main surface of the element substrate,
Adhering the first Au layer and the second Au layer together,
3. The method for manufacturing a light emitting element according to claim 1, wherein after the bonding, the substrate for growing a light emitting layer is peeled off from the light emitting layer portion by chemical etching.
前記発光層部が(AlGa1−xIn1−yP(ただし、0≦x≦1,0≦y≦1)よりなり、前記発光層成長用基板がGaAs基板よりなり、
前記化学エッチングを、アンモニア/過酸化水素混合液を用いて前記GaAs基板を溶解する形で行なうことを特徴とする請求項3記載の発光素子の製造方法。
The light emitting layer portion is made of (Al x Ga 1-x ) y In 1-y P (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and the light emitting layer growth substrate is made of a GaAs substrate,
4. The method for manufacturing a light-emitting element according to claim 3, wherein the chemical etching is performed by dissolving the GaAs substrate using an ammonia / hydrogen peroxide mixture.
(AlGa1−xIn1−yP(ただし、0≦x≦1,0≦y≦1)よりなる前記発光層部がAlAs剥離層を介して前記発光層成長用基板をなすGaAs基板上に成長され、
前記化学エッチングを、フッ酸を含有した溶液を用いて前記AlAs剥離層を溶解する形で行なうことを特徴とする請求項3記載の発光素子の製造方法。
The light emitting layer portion made of (Al x Ga 1-x ) y In 1-y P (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1) forms the light emitting layer growth substrate via the AlAs release layer. Grown on a GaAs substrate,
4. The method for manufacturing a light-emitting element according to claim 3, wherein the chemical etching is performed in such a manner that the AlAs release layer is dissolved using a solution containing hydrofluoric acid.
前記化合物半導体層は、III族元素がAl、Ga及びInより選ばれる1種以上からなり、V族元素がP及びAsより選ばれる1種以上からなることを特徴とする請求項1ないし請求項5のいずれか1項に記載の発光素子の製造方法。 2. The compound semiconductor layer according to claim 1, wherein the group III element is composed of one or more selected from Al, Ga and In, and the group V element is composed of one or more selected from P and As. 6. The method for producing a light-emitting element according to any one of 5 above . 前記素子基板をSi基板にて構成する請求項1ないし請求項6のいずれか1項に記載の発光素子の製造方法。The manufacturing method of the light emitting element of any one of Claim 1 thru | or 6 which comprises the said element substrate by Si substrate . i基板よりなる前記素子基板の前記貼り合わせ側主表面に基板側接合層を形成し、該基板側接合層を覆うように前記第二Au層を形成し、かつ、前記基板側接合層と前記Si基板との合金化熱処理を行なうことを特徴とする請求項1ないし請求項7のいずれか1項に記載の発光素子の製造方法。A substrate-side bonding layer is formed on the bonded main surface of the element substrate made of an Si substrate, the second Au layer is formed so as to cover the substrate-side bonding layer, and the substrate-side bonding layer and The method for manufacturing a light-emitting element according to claim 1, wherein alloying heat treatment with the Si substrate is performed .
JP2003025094A 2002-11-28 2003-01-31 Method for manufacturing light emitting device Expired - Fee Related JP4062111B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003025094A JP4062111B2 (en) 2003-01-31 2003-01-31 Method for manufacturing light emitting device
US10/718,789 US20040104395A1 (en) 2002-11-28 2003-11-24 Light-emitting device, method of fabricating the same, and OHMIC electrode structure for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003025094A JP4062111B2 (en) 2003-01-31 2003-01-31 Method for manufacturing light emitting device

Publications (2)

Publication Number Publication Date
JP2004235581A JP2004235581A (en) 2004-08-19
JP4062111B2 true JP4062111B2 (en) 2008-03-19

Family

ID=32953456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003025094A Expired - Fee Related JP4062111B2 (en) 2002-11-28 2003-01-31 Method for manufacturing light emitting device

Country Status (1)

Country Link
JP (1) JP4062111B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101337379B1 (en) 2012-06-22 2013-12-05 광전자 주식회사 Algainp light emitting diode with n-type alas bottom window layer and fabrication thereof
US11557691B2 (en) * 2018-02-13 2023-01-17 Osram Oled Gmbh Method of manufacturing a semiconductor device and semiconductor device
US11881544B2 (en) 2013-11-14 2024-01-23 Osram Oled Gmbh Method for producing optoelectronic semiconductor devices and optoelectronic semiconductor device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100862483B1 (en) * 2004-11-03 2008-10-08 삼성전기주식회사 Multiple-wavelength laser diode and fabrication method of the same
KR101047756B1 (en) 2005-06-16 2011-07-07 엘지이노텍 주식회사 Method of manufacturing light emitting diode using silicon nitride (SiN) layer
JP4655920B2 (en) * 2005-12-22 2011-03-23 日立電線株式会社 Semiconductor light emitting device
TWI288979B (en) * 2006-02-23 2007-10-21 Arima Optoelectronics Corp Light emitting diode bonded with metal diffusion and manufacturing method thereof
KR101337617B1 (en) * 2006-11-08 2013-12-06 서울바이오시스 주식회사 Vertical light emitting diode having ohmic electrode pattern and method of fabricating the same
JP5740125B2 (en) * 2010-09-29 2015-06-24 株式会社東芝 Semiconductor light emitting device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101337379B1 (en) 2012-06-22 2013-12-05 광전자 주식회사 Algainp light emitting diode with n-type alas bottom window layer and fabrication thereof
US11881544B2 (en) 2013-11-14 2024-01-23 Osram Oled Gmbh Method for producing optoelectronic semiconductor devices and optoelectronic semiconductor device
US11557691B2 (en) * 2018-02-13 2023-01-17 Osram Oled Gmbh Method of manufacturing a semiconductor device and semiconductor device

Also Published As

Publication number Publication date
JP2004235581A (en) 2004-08-19

Similar Documents

Publication Publication Date Title
TWI405350B (en) Light emitting element and manufacturing method thereof
JP4985067B2 (en) Semiconductor light emitting device
JP3896044B2 (en) Nitride-based semiconductor light-emitting device manufacturing method and product
US20060145177A1 (en) Light emitting device and process for fabricating the same
JP2004207508A (en) Light emitting element and its manufacturing method thereof
JP4121551B2 (en) Light emitting device manufacturing method and light emitting device
JP4110524B2 (en) Light emitting device and method for manufacturing light emitting device
JP4062111B2 (en) Method for manufacturing light emitting device
JP3951300B2 (en) Light emitting device and method for manufacturing light emitting device
JP3997523B2 (en) Light emitting element
JP2005197296A (en) Light-emitting element and its manufacturing process
WO2004097948A1 (en) Light-emitting device and light-emitting device manufacturing method
JP3950801B2 (en) Light emitting device and method for manufacturing light emitting device
JP2005259912A (en) Manufacturing method of light emitting element
JP4114566B2 (en) Semiconductor bonded assembly and method for manufacturing the same, light emitting device and method for manufacturing the same
JP4697650B2 (en) Light emitting element
JP5196288B2 (en) Light emitting device manufacturing method and light emitting device
JP4120796B2 (en) Light emitting device and method for manufacturing light emitting device
JP2005079298A (en) Light emitting element and method of manufacturing the same
JP2004235505A (en) Ohmic electrode structure for light emitting element and semiconductor element
JP4918245B2 (en) Light emitting diode and manufacturing method thereof
JP2005123530A (en) Method for manufacturing light emitting element
JP4108439B2 (en) Light emitting device manufacturing method and light emitting device
JP2005347714A (en) Light emitting device and its manufacturing method
JP2005109220A (en) Light-emitting element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050222

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070913

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071108

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071204

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071217

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4062111

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110111

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110111

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120111

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120111

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130111

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130111

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140111

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees