JP4061535B2 - Communications system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a communication system used in the FA field and the like.
[0002]
[Prior art]
For example, the distributed numerical control device disclosed in Patent Document 1 synchronizes a distributed numerical control device connected to a transmission line with a broadcast signal.
In this case, if the HDLC data format is used, the transmission time changes with zero insertion. For example, in the communication system of Patent Document 2, a maximum length timer is created from the start of reception, and the synchronization signal is received after the reception completion signal is received. Was generated. This method must be set one by one when the number of bytes to be sent changes, and the timer becomes long.
[0003]
[Patent Document 1]
Japanese Patent Publication No. 6-19661 [Patent Document 2]
Japanese Patent No. 2985276 (page 4-5, FIG. 4)
[0004]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems, and an object thereof is to provide a communication system capable of obtaining a synchronous output regardless of the number of transmission bytes.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a communication system using an HDLC data format, wherein the communication system includes a reception sequence circuit (1), a zero delete circuit (2), a flip-flop, and a counter (3). The reception sequence circuit (1) outputs a reception start signal when the addresses coincide with each other, clears the flip-flop and sets the counter (3) to 1H. The zero delete circuit (2) outputs a delete signal when the zero is removed and counts up the counter ( 3 ). The counter ( 3 ) Starts counting from the value where the data for the number of zero deleted by the flip-flop set has increased, When it becomes FH, it outputs a synchronization signal and clears the flip-flop.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows the HDLC data format. In the parts other than PF and F, 0 is inserted when 5 consecutive 1s are in the data, and the receiving side removes 0 after 5 consecutive 1s. is there. It is obvious that in the communication in which 0 is inserted and removed, if reception completion is output at the subsequent F, even if the byte length is the same from the start of reception, it varies depending on the data. In the present invention, a synchronization signal is generated after a certain period of time from completion of reception. The time zero-deleted is subtracted from this time to obtain a synchronization signal. FIG. 2 shows a circuit according to the present invention. When the address matches, the reception sequence circuit 1 clears the reception start signal from the output flip-flop and sets 1H to the counter 3. The zero delete circuit 2 sets zero in the reception sequence. When the signal is removed, the delete signal is output and the counter 3 counts up. When the reception is completed, the flip-flop is set by the signal output from the reception sequence circuit. The count starts, and when it becomes FH, the synchronization signal / INT is output and the flip-flop is cleared. It is clear that this / INT signal is always constant from the start of reception.
[0007]
【The invention's effect】
Synchronous output regardless of the number of transmitted bytes can be obtained with a little additional hardware.
[Brief description of the drawings]
FIG. 1 shows an HDLC data format of the present invention.
FIG. 2 is a circuit of the present invention.
[Explanation of symbols]
1 Reception sequence circuit 2 Zero delete circuit 3 Counter

Claims (1)

In a communication system using the HDLC data format,
The communication system includes a reception sequence circuit (1), a zero delete circuit (2), a flip-flop, and a counter (3).
The reception sequence circuit (1) outputs a reception start signal when the addresses match, clears the flip-flop and sets 1H to the counter (3), and outputs a reception completion signal when the reception is completed. Set
The zero delete circuit (2) outputs a delete signal when zero is removed, and counts up the counter (3).
The counter ( 3 ) starts counting from the value where the data corresponding to the number of zero deleted by the set of flip-flops has increased, outputs a synchronization signal when it becomes FH, and clears the flip-flop. A communication system .

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