JP4039168B2 - Receiving circuit and radio communication apparatus using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a receiving circuit of a wireless communication system such as a wireless LAN and a cellular phone and a wireless communication apparatus using the same, and is particularly suitable for use in a system that requires a high-speed AGC (Automatic Gain Control) circuit such as IEEE802.11a. The present invention relates to a direct conversion type receiving circuit and a wireless communication apparatus using the receiving circuit.
[0002]
[Prior art]
Reception systems in wireless communication systems are roughly divided into a superheterodyne system that converts the received high-frequency signal to an intermediate frequency and processes it, and a direct conversion system that converts the received high-frequency signal directly into a baseband signal for processing. Is done. Among these reception systems, direct conversion receivers (hereinafter referred to as direct conversion receivers) are external parts that do not require an IF (intermediate frequency) stage compared to superheterodyne receivers. Therefore, it is suitable for multi-band, multi-mode receivers and the like because the circuit configuration is relatively simple. For these reasons, a direct conversion receiver has recently been used in many wireless communication systems.
[0003]
FIG. 5 shows the configuration of a direct conversion receiver according to the conventional example (first conventional example). In the figure, one of the high-frequency signals received by the antennas 101A and 101B is selected by the selector switch 102, and one of the high-frequency signals is input to the mixer circuits 105i and 105q via the band-pass filter 103 and the low-noise amplifier 104. As given. The mixer circuit 105i, 105q is supplied with a local signal output from the local oscillator 106 as the other input either directly (phase difference 0 °) or via the 90 ° phase shifter 107 (phase difference 90 °). .
[0004]
The mixer circuit 105i obtains a baseband in-phase component I (hereinafter referred to as an I signal) by mixing a local signal having a phase difference of 0 ° with an input high-frequency signal. The mixer circuit 105q obtains a baseband quadrature component Q (hereinafter referred to as a Q signal) by mixing a local signal having a phase difference of 90 ° with an input high-frequency signal. The I and Q signals are supplied to analog low-pass filters (hereinafter referred to as analog LPF) 108i and 108q. The analog LPFs 108i and 108q have a role of extracting only a signal in a desired band from the received signals.
[0005]
The signals in the desired band extracted by the analog LPFs 108i and 108q are directly supplied to the AGC unit 110 after the signal amplitudes are adjusted by the analog variable gain amplifiers 109i and 109q, and further, AD (analog-digital) converters 111i and 111q. It is converted into a digital signal and supplied to a digital unit 112 including a demodulator (not shown).
[0006]
In the AGC unit 110, automatic gain control (AGC) is performed on the analog variable gain amplifiers 109i and 109q in order to keep the input signals of the AD converters 111i and 111q at an optimum and stable level. The AGC unit 110 includes detection / LPF circuits 113i and 113q, ADCs 114i and 114q, a control logic circuit 115 in the digital unit 112, DA (digital-analog) converters 116i and 116q, and control circuits 117i and 117q. Yes.
[0007]
By the way, in recent years, with an increase in signal transmission speed and tightness of frequency resources, the signal bandwidth tends to increase and the channel spacing tends to narrow. As described above, as the signal bandwidth increases, the analog LPFs 108i and 108q are required to have a high cutoff frequency. Further, since the channel interval is narrowed, the analog LPFs 108i and 108q are required to have characteristics that are sharp (steep) and have small linear distortion (amplitude distortion and phase distortion). However, the analog LPFs 108i, 108q having a sharp cutoff characteristic and a small linear distortion in a wide band can be realized with low power consumption. difficult . It is also difficult to obtain low noise and high linearity characteristics at the same time.
[0008]
A conventional example (second conventional example) shown in FIG. 6 is an improvement measure for the problem of widening the analog LPFs 108i and 108q. In FIG. 6, the same components as those in FIG.
[0009]
In the direct conversion receiver according to the second conventional example, digital low-pass filters (hereinafter referred to as digital LPFs) 201i and 201q, digital variable gain amplifiers, in the digital unit 112, following the AD converters 111i and 111q. The configuration is provided with 202i and 202q. The combination of the analog LPFs 108i and 108q and the digital LPFs 202i and 202q obtains a cutoff characteristic necessary for channel selection.
[0010]
When there is a signal causing interference in the channel adjacent to the desired channel (hereinafter referred to as an adjacent channel signal), the cutoff characteristics of the analog LPFs 108i and 108q are insufficient, so that the input signals of the AD converters 111i and 111q The adjacent channel signal remains. Therefore, the adjacent channel signal is dropped to a desired level by the digital LPFs 202i and 202q. In addition to automatic gain control of the variable gain amplifiers 109i and 109q by the AGC unit 110, the output levels of the digital variable gain amplifiers 202i and 202q are detected by the detection circuits 230i and 203q so that the input level of the demodulation unit becomes optimum and stable. Based on the detected level, the gains of the digital variable gain amplifiers 202 i and 202 q are adjusted by the set value generated by the control logic unit 115.
[0011]
[Problems to be solved by the invention]
As described above, in the direct conversion receiver according to the second conventional example, the digital LPFs 201i and 201q and the digital variable gain are provided in the subsequent stage of the AD converters 111i and 111q in order to solve the problem of the wide band of the analog LPFs 108i and 108q. Amplifiers 202i and 202q are provided so that digital AGC is applied again. However, digital filters generally have a large delay time. For example, when configured with an FIR (Finite Impulse Response) filter, a delay time of about several μsec to several tens of μsec occurs. When a signal is present, the AGC setup time for obtaining an optimum gain value becomes long due to the group delay characteristic.
[0012]
As described above, an increase in the AGC setup time results in degradation of reception quality in packet mode communication such as IEEE802.11a which is a wireless LAN specification. FIG. 7 shows the configuration of a training symbol of IEEE 802.11a. It is necessary to set up AGC within the first 8 μsec of the packet. If the AGC setup is not performed accurately within 8 μsec, the signal level cannot be set correctly, and a packet error may occur.
[0013]
As is clear from the above, in the receiving circuit having the configuration including the digital AGC, particularly when an interference signal exists in the adjacent channel or the next adjacent channel of the desired channel, the setup time of the AGC is determined by the delay characteristics of the digital LPFs 201i and 201q. For example, in packet mode communication, there is a problem that reception quality deteriorates.
[0014]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a receiving circuit capable of performing automatic gain control at high speed and with high accuracy even when receiving interference from adjacent channel signals. And providing a wireless communication apparatus using the same.
[0015]
[Means for Solving the Problems]
A receiving circuit according to the present invention includes an analog filter means for extracting a signal of a desired channel from a signal obtained by frequency conversion of a received signal, an analog variable gain amplifying means for adjusting the amplitude of the signal extracted by the analog filter means, AD conversion means for converting the output signal of the analog variable gain amplification means into a digital signal, digital filter means for extracting a signal of a desired channel from the output signal of the AD conversion means, and amplitude of the signal extracted by the digital filter means Digital variable gain amplifying means for adjusting the output of the channel adjacent to the desired channel included in the output signal or input signal of the analog variable gain amplifying means. If there is a signal The gain value of the digital variable gain amplifying means is set according to the signal level. Control to lower And a feedforward control means. This reception circuit is used as a signal processing unit, for example, a baseband unit, that processes a signal obtained by frequency conversion from a high-frequency signal in a wireless communication device such as a direct conversion receiver.
[0016]
In the receiving circuit having the above configuration or a radio communication apparatus using the same, the digital filter means is combined with the analog filter means to obtain a cutoff characteristic necessary for selecting a desired channel, and a signal of a channel adjacent to the desired channel. Is lowered to a desired level. The feedforward control means detects the signal level of the channel adjacent to the desired channel included in the output signal or input signal of the analog variable gain amplifying means, and determines the gain value of the digital variable gain amplifying means according to the detection level. Control to lower To do. Since this gain control is feedforward control, the gain value of the digital variable gain amplifying means can be increased at high speed without being affected by the digital filter means having a large group delay characteristic even in the case of interference from adjacent channel signals. Can be set.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0018]
[First Embodiment]
FIG. 1 is a block diagram showing a configuration example of a wireless communication apparatus using a receiving circuit according to the first embodiment of the present invention, for example, a direct conversion receiver. The direct conversion receiver according to the present embodiment receives diversity signals with different propagation paths using a plurality of (two in this example) antennas in order to realize high reception sensitivity by preventing quality degradation due to fading. The reception method is adopted. However, the present invention is not limited to application to a receiver of diversity reception system.
[0019]
In FIG. 1, one of the high-frequency signals received by the two antennas 11 </ b> A and 11 </ b> B is selected by the changeover switch 12. The selected high-frequency signal is supplied as an input to each of the mixer circuits 15 i and 15 q via the band-pass filter 13 and the low-noise amplifier 14. On the other hand, the local signal output from the local oscillator 16 is phase-shifted by the 90 ° phase shifter 17 into a local signal having a phase difference of 0 ° and a local signal having a phase difference of 90 °, and then a mixer circuit 15i that is a frequency converter. , 15q as the other input.
[0020]
The mixer circuit 15i obtains a baseband I (in-phase) signal by mixing a local signal having a phase difference of 0 ° with the input high-frequency signal. The mixer circuit 15q obtains a baseband Q (orthogonal) signal by mixing a local signal having a phase difference of 90 ° with an input high-frequency signal. As for the I and Q signals, only the signal components of the desired band are extracted by the analog LPFs 18i and 18q, the signal amplitude is adjusted by the analog variable gain amplifiers 19i and 19q, and then directly supplied to the AGC unit 20, and further, the AD converters 21i, In 21q, the signal is converted into a digital signal and supplied to the digital unit 22.
[0021]
In the AGC unit 20, automatic gain control (AGC) is performed on the analog variable gain amplifiers 19i and 19q in order to keep the input signals of the AD converters 21i and 21q at an optimum and stable level. The AGC unit 20 includes adjacent channel signal detection circuits 23i and 23q, detection circuits 24i and 24q, AD converters 25i and 25q, a control logic circuit 26 in the digital unit 22, DA converters 27i and 27q, and control circuits 28i and 28q. It is the composition which has.
[0022]
In the AGC unit 20, the adjacent channel signal detection circuits 23i and 23q are composed of high-pass filters 231i and 231q, detection circuits 232i and 232q, and AD converters 233i and 233q. Here, the high-pass filters 231i and 231q cut the signal of the desired channel (desired signal) from the output signals of the analog variable gain amplifiers 19i and 19q, and the signal of the channel adjacent to the desired channel (adjacent channel (Signal) only. The detection circuits 232i and 232q detect the level of the adjacent channel signals extracted by the high-pass filters 231i and 231q, and obtain the signal levels Iu and Qu, respectively. The AD converters 233i and 233q convert the signal levels Iu and Qu detected by the detection circuits 232i and 232q into digital signals and supply them to the control logic circuit 26.
[0023]
The detection circuits 24i and 24q detect the levels of the output signals from the analog variable gain amplifiers 19i and 19q. The AD converters 25i and 25q convert the detection levels I1 and Q1 obtained by the detection circuits 24i and 24q into digital signals and supply them to the control logic circuit 26. The control logic circuit 26 sets gain data corresponding to the detection levels I1 and Q1 supplied from the AD converters 25i and 25q, that is, the output signal levels of the analog variable gain amplifiers 19i and 19q. The DA converters 27i and 27q convert the gain data set by the control logic circuit 26 into an analog signal. The control circuits 28i and 28q adjust the gains of the analog variable gain amplifiers 19i and 19q in accordance with the gain data supplied from the DA converters 27i and 27q.
[0024]
Analog variable gain amplifiers 19i, 19q → detection circuits 24i, 24q → AD converters 25i, 25q → control logic circuit 26 → DA converters 27i, 27q → control circuits 28i, 28q → analog variable gain amplifiers 19i, 19q As in the prior art, a feedback analog AGC loop for setting the gain values of the variable gain amplifiers 19i and 19q in accordance with the levels of the output signals of the analog variable gain amplifiers 19i and 19q is formed.
[0025]
In the digital unit 22, in addition to a control logic circuit 26 that constitutes a part of the AGC unit 20, a demodulating unit 29 that demodulates a received signal, and a cascade connection between the AD converters 21 i and 21 q and the demodulating unit 29. Digital LPFs 30i, 30q and digital variable gain amplifiers 31i, 31q are provided. The digital LPFs 30i and 30q are combined with the analog LPFs 18i and 18q, respectively, to obtain a cutoff characteristic required for channel selection and to reduce the adjacent channel signal to a desired level.
[0026]
The control logic circuit 26 adds the signal levels Iu and Qu detected by the adjacent channel signal detection circuits 23i and 23q, and generates a gain control signal Cg = Kg * (Iu + Qu) according to the addition result (Iu + Qu). . Here, Kg is a conversion coefficient for converting from (Iu + Qu) to Cg, and is determined from the characteristics of the digital variable gain amplifiers 31i and 31q and the adjacent channel signal detection circuits 23i and 23q so as to obtain optimum AGC performance. .
[0027]
The gain control signal Cg generated by the control logic circuit 26 is supplied to the digital variable gain amplifiers 31i and 31q, and sets the gain values of the variable gain amplifiers 31i and 31q. With respect to the digital variable gain amplifiers 31i and 31q, the output of the digital LPFs 30i and 30q is bit-shifted, and a simple variable gain circuit of ± 6 dB can be used to speed up the AGC setting.
[0028]
The above-described analog variable gain amplifiers 19i, 19q → adjacent channel signal detection circuits 23i, 23q → control logic circuit 26 → digital variable gain amplifiers 31i, 31q are in accordance with the levels of the output signals of the analog variable gain amplifiers 19i, 19q. A feedforward digital AGC loop for setting the gain values of the digital variable gain amplifiers 31i and 31q is formed.
[0029]
As described above, in the receiving circuit according to the present embodiment, the analog LPFs 18i and 18q are cut off as the signal bandwidth increases by adopting a configuration in which the analog AGC loop and the digital AGC loop are used together. Even if the frequency is increased, the combination of the analog LPFs 18i and 18q and the digital LPFs 30i and 30q can obtain the cutoff characteristics required for channel selection. Therefore, the cutoff characteristics are sharp over a wide band and linear distortion ( Characteristics with small amplitude distortion and phase distortion) can be realized with low power consumption, and low noise and high linearity characteristics can be obtained simultaneously.
[0030]
Moreover, in the receiving circuit according to the present embodiment, since the digital AGC loop is feedforward control, it is not affected by the digital LPFs 30i and 30q having large delay characteristics even when receiving interference from adjacent channel signals. In addition, since the gain values of the digital variable gain amplifiers 31i and 31q can be set at a high speed, the AGC setup can be speeded up. The circuit operation of the feedforward digital AGC loop will be described in more detail below.
[0031]
When an interference signal exists in the adjacent channel, a signal having a spectrum shown in FIG. 2A is input to the analog LPFs 18i and 18q. This signal passes through the analog LPFs 18i and 18q so that the high frequency components are cut, and is output from the analog variable gain amplifiers 19i and 19q as a spectrum signal shown in FIG. Then, the low-frequency component is cut by passing through the high-pass filters 231i and 231q of the adjacent channel signal detection circuits 23i and 23q, and is output as a signal of the spectrum shown in FIG. That is, the signal component of the desired channel is cut, and the signal component of the adjacent channel is extracted.
[0032]
The extracted signal components of adjacent channels are subjected to level detection in the detection circuits 232i and 232q, converted into digital signals in the AD converters 233i and 233q, and sent to the control logic circuit 26. Then, the control logic circuit 26 determines the gain values of the digital variable gain amplifiers 31i and 31q according to the detection level in the detection circuits 232i and 232q, that is, the signal level of the adjacent channel. Specifically, when there is an adjacent channel signal, the control logic circuit 26 controls to decrease the gains of the digital variable gain amplifiers 31i and 31q in accordance with the signal level.
[0033]
The gain values of the digital variable gain amplifiers 31i and 31q are not affected by the digital LPFs 30i and 30q having a large group delay characteristic even when the adjacent channel signal is interfered by the feedforward control by the digital AGC loop described above. Since it can be set at high speed, the AGC setup can be speeded up.
[0034]
[Second Embodiment]
FIG. 3 is a block diagram showing a configuration example of a wireless communication apparatus using the receiving circuit according to the second embodiment of the present invention, for example, a direct conversion receiver. In FIG. 3, the same parts as those in FIG. It is attached.
[0035]
In the receiving circuit according to the present embodiment, in addition to the configuration of the receiving circuit according to the first embodiment described above, detection circuits 33i and 33q for level detecting the output signals of the digital variable gain amplifiers 31i and 31q are provided in the digital unit 22. On the other hand, the control logic circuit 26 sets the gain values of the digital variable gain amplifiers 31i and 31q from the detection levels I2 and Q2 of the detection circuits 33i and 33q and the detection levels Iu and Qu of the adjacent channel signal detection circuits 23i and 23q. It is the composition to do.
[0036]
For example, the control logic circuit 26 calculates Cg = Kg * (Iu + Qu) + K2 * (I2 + Q2). Here, I2 and Q2 are detection levels at the outputs of the digital variable gain amplifiers 31i and 31q. K2 is a conversion coefficient for converting the detection result (I2 + Q2) into the gain control signal Cg.
[0037]
In the receiving circuit according to the second embodiment configured as described above, the gain values of the analog variable gain amplifiers 19i and 19q are set according to the detection levels I1 and Q1 in the detection circuits 24i and 24q by feedback control using the analog AGC loop. In the digital AGC loop, the gain values of the digital variable gain amplifiers 31i and 31q are set according to the detection levels Iu and Qu in the adjacent channel signal detection circuits 23i and 23q and the detection levels I2 and Q2 of the detection circuits 33i and 33q. The
[0038]
Thus, in the digital AGC loop, in addition to the feedforward loop, the output signals of the digital variable gain amplifiers 31i and 31q are level-detected, and the gain values of the digital variable gain amplifiers 31i and 31q are detected using the detection levels I2 and Q2. By forming a feedback loop for setting the gain, the gain values of the digital variable gain amplifiers 31i and 31q can be corrected with finer accuracy in addition to the operational effects of the receiving circuit according to the first embodiment. The performance of the receiving circuit can be further improved.
[0039]
When the detection circuits 33i and 33q are included as components in addition to the adjacent channel signal detection circuits 23i and 23q as in the reception circuit according to the present embodiment, the detection levels I2 and Q2 of the detection circuits 33i and 33q are used. It is also possible to form a feedback loop for setting the gain values of the analog variable gain amplifiers 19i and 19q. Specifically, under the control of the control logic circuit 26, the gain values of the digital variable gain amplifiers 31i and 31q are set using the detection levels Iu and Qu in the adjacent channel signal detection circuits 23i and 23q, while the detection circuit The gain values of the analog variable gain amplifiers 19i and 19q may be set using the detection levels I1 and Q1 at 24i and 24q and the detection levels I2 and Q2 at the detection circuits 33i and 33q.
[0040]
[Third Embodiment]
FIG. 4 is a block diagram showing a configuration example of a wireless communication apparatus using a receiving circuit according to the third embodiment of the present invention, for example, a direct conversion receiver. In FIG. It is attached.
[0041]
In the receiving circuit according to the second embodiment, the detection inputs of the adjacent channel signal detection circuits 23i and 23q are taken out from the output side of the analog variable gain amplifiers 19i and 19q, whereas in the receiving circuit according to the present embodiment, The configuration is such that the detection inputs of the adjacent channel signal detection circuits 23i and 23q are taken out from the input side of the analog variable gain amplifiers 19i and 19q, and the other configurations are the same as those of the reception circuit according to the second embodiment.
[0042]
As described above, even when the adjacent channel signal detection circuits 23i and 23q are configured to level detect the input signals of the analog variable gain amplifiers 19i and 19q, the level detection is performed on the output signals of the analog variable gain amplifiers 19i and 19q. Even in the case of receiving interference due to adjacent channel signals, the gain values of the digital variable gain amplifiers 31i and 31q can be increased at high speed without being affected by the digital LPFs 30i and 30q having large group delay characteristics. Since it can be set, AGC setup can be speeded up.
[0043]
However, in the case of adopting a configuration for level detection of the input signals of the analog variable gain amplifiers 19i and 19q, the input level range of the high-pass filters 231i and 231q is compared with the case of level detection of the output signals of the analog variable gain amplifiers 19i and 19q. large. Therefore, if a logarithmic amplifier is inserted before the high-pass filters 231i and 231q, the input level range of the high-pass filters 231i and 231q can be reduced.
[0044]
The technical idea according to the present embodiment, that is, the configuration for level detection of the input signals of the analog variable gain amplifiers 19i and 19q in the adjacent channel signal detection circuits 23i and 23q, is similarly applied to the reception circuit according to the first embodiment. be able to.
[0045]
In each of the above embodiments, it is assumed that an analog AGC loop and a digital AGC loop are used together. However, it is possible to perform AGC with high speed and high accuracy when receiving interference from adjacent channel signals. From the point of view, the intended purpose can be achieved only by feedforward control by the digital AGC loop.
[0046]
In each of the above embodiments, the adjacent channel signal detection circuits 23i and 23q are provided in both I and Q. However, a configuration in which the adjacent channel signal detection circuits 23i and 23q are provided only on one side may be employed. By adopting this configuration, the circuit configuration can be simplified to the extent that one adjacent channel signal detection circuit can be omitted.
[0047]
Further, in each of the above embodiments, the case where the present invention is applied to a direct conversion type receiver circuit has been described as an example. However, the present invention is not limited to this application example, and a received high-frequency signal is reduced to a low IF (intermediate). Similarly, the present invention can be applied to a low-IF receiving circuit that performs frequency conversion to (frequency).
[0048]
【The invention's effect】
As described above, according to the present invention, the gain control is performed by the feed-forward digital AGC loop, so that the automatic gain control can be performed at high speed and with high accuracy even when the interference is caused by the adjacent channel signal. It becomes possible to do.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a direct conversion receiver using a receiving circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating respective spectra of an analog LPF input signal (a), an analog variable gain amplifier output signal (b), and a high-pass filter output signal (c) in the receiving circuit according to the first embodiment.
FIG. 3 is a block diagram showing a configuration example of a direct conversion receiver using a receiving circuit according to a second embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration example of a direct conversion receiver using a receiving circuit according to a third embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a direct conversion receiver according to a first conventional example.
FIG. 6 is a block diagram showing a configuration of a direct conversion receiver according to a second conventional example.
FIG. 7 is a diagram illustrating a configuration of a training symbol of IEEE 802.11a.
[Explanation of symbols]
18i, 18q ... analog LPF (low-pass filter), 19i, 19q ... analog variable gain amplifier, 20 ... AGC unit, 22 ... digital unit, 23i, 23q ... adjacent channel signal detection circuit, 24i, 24q, 33i, 33q ... detection circuit , 26 ... control logic circuit, 28i, 28q ... control circuit, 29 ... demodulator, 30i, 30q ... digital LPF, 31i, 31q ... digital variable gain amplifier, 231i, 231q ... high pass filter

Claims (10)

Analog filter means for extracting a signal of a desired channel from a signal obtained by frequency-converting a received signal;
Analog variable gain amplifying means for adjusting the amplitude of the signal extracted by the analog filter means;
AD conversion means for converting the output signal of the analog variable gain amplification means into a digital signal;
Digital filter means for extracting a signal of a desired channel from an output signal of the AD conversion means;
Digital variable gain amplifying means for adjusting the amplitude of the signal extracted by the digital filter means;
When there is a signal of a channel adjacent to a desired channel included in the output signal or input signal of the analog variable gain amplifying means, feedforward is controlled so as to lower the gain value of the digital variable gain amplifying means in accordance with the signal level. And a receiving circuit. The receiving circuit according to claim 1, further comprising:
A receiving circuit comprising first feedback control means for adjusting a gain value of the analog variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the analog variable gain amplifying means. The receiving circuit according to claim 1, further comprising:
A receiving circuit comprising second feedback control means for adjusting a gain value of the digital variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the digital variable gain amplifying means. The receiving circuit according to claim 1, further comprising:
First feedback control means for adjusting a gain value of the analog variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the analog variable gain amplifying means;
And a second feedback control means for adjusting a gain value of the digital variable gain amplifying means in accordance with a signal level of a desired channel contained in an output signal of the digital variable gain amplifying means. The receiving circuit according to claim 1, further comprising:
First feedback control means for adjusting a gain value of the analog variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the analog variable gain amplifying means;
And a second feedback control means for adjusting a gain value of the analog variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the digital variable gain amplifying means. Frequency conversion means for performing frequency conversion of the high-frequency signal received by the antenna;
A signal processing unit for processing the signal frequency-converted by the frequency conversion unit;
Demodulating means for demodulating the signal processed by the signal processing unit,
The signal processing unit
Analog filter means for extracting a signal of a desired channel from the signal frequency-converted by the frequency conversion means;
Analog variable gain amplifying means for adjusting the amplitude of the signal extracted by the analog filter means;
AD conversion means for converting the output signal of the analog variable gain amplification means into a digital signal;
Digital filter means for extracting a signal of a desired channel from an output signal of the AD conversion means;
Digital variable gain amplifying means for adjusting the amplitude of the signal extracted by the digital filter means;
When there is a signal of a channel adjacent to a desired channel included in the output signal or input signal of the analog variable gain amplifying means, feedforward is controlled so as to lower the gain value of the digital variable gain amplifying means in accordance with the signal level. And a control means. The signal processing unit further includes:
7. The first feedback control means for adjusting a gain value of the analog variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the analog variable gain amplifying means. Wireless communication device. The signal processing unit further includes:
7. The second feedback control means for adjusting the gain value of the digital variable gain amplifying means according to the signal level of the desired channel contained in the output signal of the digital variable gain amplifying means. Wireless communication device. The signal processing unit further includes:
First feedback control means for adjusting a gain value of the analog variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the analog variable gain amplifying means;
7. A second feedback control means for adjusting a gain value of the digital variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the digital variable gain amplifying means. Wireless communication device. The signal processing unit further includes:
First feedback control means for adjusting a gain value of the analog variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the analog variable gain amplifying means;
7. A second feedback control means for adjusting a gain value of the analog variable gain amplifying means in accordance with a signal level of a desired channel included in an output signal of the digital variable gain amplifying means. Wireless communication device.

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