JP4032535B2 - Data processing circuit, data transmission system and method thereof - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a data processing circuit, a data transmission system, and a data transmission method.
[0002]
[Prior art]
In recent years, an IEEE (The Institute of Electrical and Electronic Engineers) 1394 serial interface that realizes high-speed data transfer and real-time transfer has been standardized as an interface for multimedia data transfer.
Such an IEEE 1394 serial interface data processing circuit is mainly composed of a physical layer circuit that directly drives the IEEE 1394 serial bus and a link layer circuit that controls physical layer data transfer, and includes a plurality of data processing circuits. The physical layer circuit is connected via an IEEE 1394 serial bus, and one or more applications are connected to the link layer circuit of each data processing circuit.
[0003]
In the above-described system using the IEEE 1394 serial interface, a signal is received via an IEEE 1394 serial bus between an application connected to one data processing circuit and an application connected to another data processing circuit. Transmits a signal when a reception permission signal is received, and transmits / receives data once every 125 μs, which is an isocycle, or transmits an acknowledgment signal when a signal is received. Isochronous transfer is performed.
[0004]
[Problems to be solved by the invention]
By the way, in the above-described system using the IEEE 1394 serial bus BUS, MD data read from the MD by a MD (Mini Disk) device connected to one data processing device is transferred to another data processing device via the IEEE 1394 serial bus. In some cases, it is desired to write to the MD using an MD device connected to the.
Here, the MD employs a compression method called ATRAC (Adaptive TRansform Acoustic Coding) in order to ensure long-time recording / reproduction.
In this ATRAC, compression is performed in units of 212 bytes of sampling data. For example, when a plurality of packets including 159 bytes of ATRAC data are continuously transmitted in isochronous transfer, some packets are lost. In addition to the ATRAC data including the lost packet, the ATRAC data before and after being compressed together with the ATRAC data cannot be expanded, and the quality of data obtained on the receiving side is extremely low. There's a problem.
Therefore, conventionally, ATRAC data has not been transmitted through the IEEE 1394 serial bus.
[0005]
Note that the above-described problem similarly exists when various data are transmitted and received via various data transmission paths, in addition to the case where ATRAC data is transmitted via the IEEE1394 serial bus.
[0006]
The present invention has been made in view of the above-described problems of the prior art, and an object thereof is to provide a data processing circuit capable of accurately receiving data via a data transmission path.
It is another object of the present invention to provide a data transmission system and method for accurately transmitting and receiving data via a data transmission path.
[0007]
[Means for Solving the Problems]
  In order to solve the above-described problems of the prior art and achieve the above-described object, the data processing circuit of the present invention includes:A data processing circuit capable of connecting a plurality of applications, including first and second order instruction data indicating the order of the data in the data of the application, and capable of communicating with other data processing circuits via a data transmission path A first storage unit, a first receiving circuit that analyzes the received data and stores the data in the first storage unit, and reads the data stored in the first storage unit; A second receiving circuit that performs processing according to the read data; and at the time of reception, the first and second order instruction data are extracted from the data processed by the second receiving circuit, and the data The continuity detection circuit that generates the first and second order instruction data for the data to be transmitted, a second storage unit, and the continuity detection circuit at the time of transmission. The first transmission circuit that adjusts the data length of the data processed by and stores the data in the second storage unit, reads the data stored in the second storage unit, and reads the first and second A second transmission circuit that adds 2 order instruction data, and a missing data request that requests the missing data to the transmission side when the continuity detection circuit detects a missing data in the data during reception A third transmission circuit for transmitting a signal to the application side, and the continuity detection circuit compares the first order instruction data inputted last time with the first order instruction data inputted at the time of reception. A first detection circuit that detects continuity and outputs a first continuity detection signal indicating a detection result and the first order instruction data input this time, and the continuity of the second order instruction data And show the detection result A second detection circuit for outputting a second continuity detection signal and the second order instruction data; a first continuity detection signal output by the first detection circuit; and the first order instruction data. And comparing the first and second continuity detection signals on the basis of the second continuity detection signal output from the second detection circuit and the second order instruction data, and And a writing circuit for writing the first and second order instruction data, which are determined to be continuous at the end when the continuity detection signal is discontinuous, to a predetermined circuit.
[0008]
In the data processing circuit of the present invention, the data transmitted via the data transmission path is received by the receiving circuit.
Next, the continuity detection circuit monitors the continuity of the received data and detects missing data.
Next, a missing data request signal for requesting the detected missing data is transmitted from the transmission circuit to the transmission side.
Then, on the transmitting side, data requested by the received missing data request signal is transmitted to the data processing circuit via the data transmission path.
According to the data processing circuit of the present invention, missing data can be received, and processing can be performed using the received continuous data.
[0010]
In the data processing circuit of the present invention, it is preferable that the reception circuit stops receiving the data via the data transmission path when the continuity detection circuit detects the missing data. .
[0011]
In the data processing circuit of the present invention, it is preferable that the receiving circuit receives a plurality of packets each including a predetermined amount of the data.
[0012]
  The data transmission system of the present invention isData in which a plurality of applications can be connected, and the data of the application includes first and second order instruction data indicating the order of the data, and the data transmission device and the data reception device are connected via a data transmission path. A transmission system,The data receiving device is:A first storage unit; a first receiving circuit that analyzes the received data and stores the data in the first storage unit; and reads the data stored in the first storage unit and reads the data A second receiving circuit that performs processing according to the data, and at the time of reception, the first and second order instruction data are extracted from the data processed by the second receiving circuit to increase the continuity of the data. A continuity detection circuit that monitors and generates the first and second order instruction data for the data to be transmitted at the time of transmission;The data transmission device includes:A second storage unit that shares the continuity detection circuit, and a first transmission circuit that adjusts the data length of the data processed by the continuity detection circuit during transmission and stores the data in the second storage unit. A second transmission circuit that reads the data stored in the second storage unit and adds the first and second order instruction data, and the continuity detection circuit receives the data in the data during reception. A third transmission circuit that transmits to the application side a missing data request signal for requesting the missing data to the transmission side when the missing data is detected, and the continuity detection circuit receives the data at the time of reception. The first order instruction data and the first order instruction data inputted last time are compared to detect continuity, and the first continuity detection signal indicating the detection result and the first order inputted this time are detected. First to output instruction data A detection circuit; a second detection circuit that detects continuity of the second order instruction data; and outputs a second continuity detection signal indicating the detection result and the second order instruction data; A first continuity detection signal output from one detection circuit and the first order instruction data, and a second continuity detection signal output from the second detection circuit and the second order instruction data. The first and second continuity detection signals are compared based on the first and the second and the second continuity detection signals are determined to be continuous when at least one of the continuity detection signals is discontinuous. And a writing circuit for writing the second order instruction data to a predetermined circuit.
[0013]
In the data transmission system of the present invention, data is transmitted from the data transmission device to the data reception device via the data transmission path.
In the data receiving device, the data transmitted through the data transmission path is received by the receiving circuit.
Then, the continuity detection circuit monitors the continuity of the received data, and detects missing data.
Next, a missing data request signal for requesting the detected missing data is transmitted from the transmission circuit to the data transmission device.
In the data transmission device, the data requested by the received missing data request signal is transmitted again to the data reception device via the data transmission path.
According to the data transmission system of the present invention, since the missing data is transmitted from the data transmission device to the data reception device, the data reception device can perform processing using the received continuous data.
[0014]
  Further, the data transmission method of the present invention includes:A data transmission method capable of connecting a plurality of applications, wherein the data of the application includes first and second order instruction data indicating the order of the data, and transmits and receives data via a data transmission path, The transmission data is generated by adjusting the data length of the data, the first and second order instruction data are added to the transmission data, and the data is transmitted from the transmission side to the reception side via the data transmission path. According to the first step, the second step of detecting missing data by monitoring the continuity of the data received via the data transmission path on the receiving side, and the monitoring result of the data Based on the third step of stopping reception of the data and the first and second order instruction data when it is determined that the data is continuous. A fourth step of generating an insertion signal, a fifth step of transmitting a missing data request signal for requesting the missing data from the reception side to the transmission side by the interrupt signal, and the transmission side And a sixth step of transmitting data specified by the missing data request signal to the receiving side when the missing data request signal is received, and in the second step, the received data The extraction step of extracting the first and second order instruction data from, the first order instruction data and the previous first order instruction data are compared to detect continuity and indicate the detection result A first detection step for outputting a first continuity detection signal and the current first order instruction data; and detecting the continuity of the second order instruction data and detecting the result. A second detection step of outputting a second continuity detection signal indicating the second order indication data and the first order indication data and the first continuity detection signal in the first detection step. And comparing the first and second continuity detection signals based on the second continuity detection signal and the second order instruction data in the second detection step, and at least one of the continuity detection signals. And a writing step of writing the first and second order instruction data determined to have continuity to a predetermined circuit when the sex detection signal is discontinuous.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block configuration diagram showing an embodiment of a communication system 1 according to the present invention using an IEEE 1394 serial interface.
In the communication system 1, an MD device 2 is connected as an application to the link layer circuit 9. In the MD device 2, the MD read block 4 is driven by the DSP 5, and ATRAC data is read from the MD 3.
Then, the ATRAC data read from the MD 3 is transmitted in units of packets via the link layer circuit 9, the physical layer circuit 10, the IEEE 1394 serial bus BUS, the physical layer circuit 11, and the link layer circuit 12. 20 is transmitted.
In the MD device 20, the MD writing block 14 is driven by the DSP 23, and ATRAC data is recorded in the MD 13.
In the present embodiment, the link layer circuit 12 monitors the continuity of the received ATRAC data in units of packets, and when it is determined that there is no continuity, the ATRAC data after the ATRAC data whose continuity has been lost is obtained. An instruction requesting transmission again is transmitted from the host computer 16 to the host computer 6. Accordingly, ATRAC data after ATRAC data whose continuity has been lost is read again from the MD device 2 and transmitted to the MD device 20 in units of packets via the IEEE 1394 serial bus BUS.
[0016]
Hereinafter, the configuration of the communication system 1 will be described.
As shown in FIG. 1, the communication system 1 includes, for example, an MD device 2, a host computer 6, a link layer circuit 9, and a physical layer circuit 10 on one side of an IEEE 1394 serial bus BUS, and the other side. The physical layer 11, the link layer circuit 12, the host computer 16, and the MD device 20 are included.
In this embodiment, the link layer circuit 12 corresponds to the receiving circuit and the continuity detecting circuit of the present invention, and the host computer 16 corresponds to the transmitting circuit of the present invention.
[0017]
Hereinafter, each component will be described in detail.
MD device 2
The MD device 2 includes an MD read block 4 and a DSP 5, and outputs ATRAC data S 5 read from the MD 3 to the link layer circuit 9.
The DSP 5 controls the MD read block 4 based on the control signal S 6 from the host computer 6 and outputs the ATRAC data S 5 read from the MD 3 to the link layer circuit 9.
Here, the ATRAC data S5 is audio data, video data data, computer data, etc. compressed by the ATRAC system in units of 212 bytes.
The MD read block 4 includes a drive system that rotationally drives the MD 3 and a read system such as an optical pickup, and reads the MD 3 based on control from the DSP 5.
[0018]
Host computer 6
The host computer 6 outputs a control signal S6 to the DSP 5.
Further, the host computer 6 inputs a reception packet for asynchronous communication from the host interface circuit 102 of the link layer circuit 9 as necessary, performs predetermined processing, and sends an asynchronous transmission packet to the host interface circuit 102. Is output.
[0019]
Further, the host computer 6 sends the asynchronous communication packet (missing data request signal of the present invention) including the order instruction data present-PES-number and PES-data-counter to the link layer circuit 12 and the physical layer circuit 11. When received from the host computer 16 via the IEEE 1394 serial bus BUS, the physical layer circuit 10 and the link layer circuit 9, the order indication data present-PES-number and PES-data-counter included in the received packet are used. The control signal S6 is output to the DSP 5 so that the specified ATRAC data S5 is read again from the MD3.
Specifically, the order instruction data present-PES-number included in the received packet and the order instruction data PES- obtained by incrementing (increasing) the order instruction data PES-data-counter included in the received packet by one. A control signal S6 indicating that ATRAC data arranged in a later-described transport stream (TS) packet having data-counter is read again from MD3 is output to DSP5.
As described above, the host computer 6 receives the asynchronous communication packet including the order instruction data present-PES-number and PES-data-counter, as will be described later. The application I / F circuit 103 detects the discontinuity of the order instruction data present-PES-number and PES-data-counter included in the received packet for isochronous communication.
[0020]
Link layer circuit 9
The link layer circuit 9 performs control of isochronous transfer and asynchronous transfer and control of the physical layer circuit 10 under the control of the host computer 6.
Here, in isochronous transfer, data is always transmitted and received once every 125 μs that is an isocycle, and in asynchronous transfer, a signal is received from the transmission side when the transmission side receives a reception permission signal that permits reception of the signal. The reception confirmation signal is transmitted from the reception side to the transmission side when the reception side receives the signal.
FIG. 2 is an internal configuration diagram of the link layer circuit 9.
Specifically, as shown in FIG. 2, the link layer circuit 9 includes, for example, a link core 101, a host I / F circuit 102, an application I / F circuit 103, and a transmission FIFO. (AT-FIFO) 104a and reception FIFO (AR-FIFO) 104b, asynchronous communication FIFO 104, self ID resolver (Resolver) 105, isochronous communication pre-transmission processing circuit (TXOPRE) 106, isochronous communication post-transmission processing Circuit (TXOPRO) 107, isochronous communication reception pre-processing circuit (TXIPRE) 108, isochronous communication reception post-processing circuit (TXIPRO) 109, isochronous communication FIFO (I-FIFO) 110, and configuration register (hereinafter referred to as CFR) 111).
[0021]
In the link layer circuit 9 shown in FIG. 2, the application interface circuit 103, the pre-transmission processing circuit 106, the post-transmission processing circuit 107, the pre-reception processing circuit 108, the post-reception processing circuit 109, the FIFO 110, the link core 101 and the CFR 111 are used for isochronous communication. A system circuit is configured.
The host interface circuit 102, the asynchronous communication transmission FIFO 104a, the reception FIFO 104b, the link core 101, and the CFR 111 constitute an asynchronous communication system circuit.
[0022]
[Isochronous communication circuit]
The link core 101 has a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets, an interface circuit with the physical layer circuit 10 that directly drives the IEEE1394 serial bus BUS of these packets, and a cycle timer that is reset every 125 μs. It consists of a cycle monitor and CRC circuit.
The link core 101 outputs an isochronous transmission packet to the physical layer circuit 10 every 125 μs during transmission of isochronous transfer. Further, the link core 101 inputs an isochronous transmission packet from the physical layer circuit 10 every 125 μs when receiving isochronous transfer.
[0023]
At the time of transmission, the application I / F circuit 103 sequentially generates 188-byte transport stream (TS) packets from the ATRAC data S5 input from the DSP 5, and sends the TS packets to the transmission preprocessing circuit 106. Output.
In the payload part (data part) of each TS packet, 159-byte ATRAC data is arranged. At this time, as described above, since ATRAC data is compressed in units of 212 bytes, at least a part of ATRAC data included in the same compression unit is arranged in different TS packets.
Here, a so-called PES (Packetized Elementary Stream) packet is composed of 159 bytes of ATRAC data included in eight consecutive TS packets. PES packets are TS packets used for transmission (accumulation) in an environment where bit errors occur and transmission (accumulation) in an environment where no bit errors occur, as defined in MPEG (Moving Picture coding Experts Group) 2 This is an intermediate stream for enabling conversion between program stream (PS) packets to be used.
[0024]
Hereinafter, the data format of the TS packet will be described.
FIG. 3 is a diagram for explaining the format of the TS packet.
As shown in FIG. 3, the TS packet includes, for example, a 4-byte transport packet header TPH, a 14-byte PES packet header PPH, a 2-byte data header DH, and a 168-byte data body DB. .
[0025]
The transport packet header TPH is, for example, as shown in FIG.
Sync-byte indicating the sync byte (0x47),
Transport-error-indicator indicating error indication,
Playload-unit-start-indicator indicating the unit start display,
Transport-priority indicating the priority of the transport packet,
PID indicating the packet identifier,
Transport-scrambling-control for scramble control,
Adaptation-field-control for adaptation field control and
Continuity-counter to index continuity
Consists of.
[0026]
The PES packet header PPH includes, for example, data indicating the length of the PES packet, whether or not the PES packet can be copied, and identification of the original / copy.
[0027]
The data header DH includes, for example, a data-type indicating whether or not the data is audio data, and a data-transmission and tag indicating whether the data communication path is a satellite or a cable.
In the present embodiment, the data-type indicates music data.
[0028]
The data body DB is, for example, as shown in FIG.
FDF-field-length indicating the data length (number of bytes) of FDF (Fromat Dependent Field),
Audio-data-type-1 to indicate the audio data type,
Audio-data-type-2 to indicate the classification within the audio data type,
Copyright indicating whether or not the music data can be copied,
Stereo-mono to indicate whether the song is stereo or mono,
Emphasis, which indicates whether the song is emphasis or not
Data-start-indicator indicating that the data being transmitted is the first PES packet of music data,
Data-end-indicator indicating that the data being transmitted is the last PES packet of the music data,
Order instruction data PES-data-conuter, which is a 3-bit cyclic count value indicating the number of the eight TS packets transmitting the PES.
Order indication data present-PES-number, which is a 24-bit count value indicating what PES packet the TS packet relates to
Consists of.
In the present embodiment, the data audio-data-type-1 indicates that it is ATRAC.
Further, the order instruction data PES-data-conuter and present-PES-number are used when the continuity of the received ATRAC data is monitored in the application I / F circuit 103 as will be described later.
[0029]
Further, at the time of reception, the application I / F circuit 103 extracts 159-byte ATRAC data shown in FIG. 4 from each TS packet input from the post-reception processing circuit 109, and outputs the ATRAC data to the application side.
The processing at the time of reception in the application I / F circuit 103 will be described in the description of the link layer circuit 12 described later.
[0030]
In addition to MD devices, the application I / F circuit 103 includes, for example, multimedia products such as CD (Compact Disc) players, D / A converters, various computers, consumer products such as set top boxes, and the like. Data storage devices such as hard disks can be connected.
[0031]
The pre-transmission processing circuit 106 inputs a TS packet from the application I / F circuit 103, adjusts the data length in units of quadlets (4 bytes) in order to perform the IEEE 1394 standard isochronous communication, and the FIFO 110 Write to the transmission FIFO 110b.
[0032]
The post-transmission processing circuit 107 reads the TS packet from the transmission FIFO 110b of the FIFO 110, and adds the 1394 header and the CIP headers (Headers) 1 and 2 shown in FIG. 5 to the read TS packet for isochronous communication. The transmission packet is generated, and the transmission packet is output to the transmission circuit of the link core 101.
Specifically, as shown in FIG. 5, a transmission packet for isochronous communication includes a 32-byte 1394 header, a 32-byte header CRC (Cyclic Redundancy Check), a 32-byte CIP header 1, and a 32-byte CIP header 2. It consists of 188 bytes of data and 32 bytes of data CRC.
Here, the TS packet shown in FIG. 3 is arranged in 188 bytes of data.
[0033]
The 1394 header includes a data-length indicating the data length, a tag, a channel indicating the channel number (any one of 0 to 63) to which the packet is transferred, reserved, a speed indicating the transfer speed, and synchronization defined by each application. Consists of the code sy.
The CIP header 1 includes a SID (Source node ID) for a transmission node number, a DBS (Data Block Size) for the length of a data block, and an FN (Fraction Number) for the number of data divisions in packetization. , QPC (Quadlet Padding Count) for the number of quadlets of padding data, SPH for a flag indicating the presence / absence of a source packet header, and DBC for a counter for detecting the number of isochronous packets.
The CIP header 2 includes FMT, FDF (Format Dependent Field) used corresponding to the signal format, and SyncTime for time stamp information.
[0034]
The pre-reception processing circuit 108 receives the reception packet for isochronous communication shown in FIG. 5 that has been transmitted through the IEEE 1394 serial bus BUS via the link core 101, and receives the 1394 header, CIP header 1, 2, etc. of the reception packet. After analyzing the contents, 188-byte data (TS packet) is written in the FIFO 110a for reception of the FIFO 110.
[0035]
The post-reception processing circuit 109 outputs the TS packet read from the reception FIFO 110 a to the application I / F circuit 103. At this time, if the TS packet is encrypted, the post-reception processing circuit 109 decrypts the cipher and outputs it to the application I / F circuit 103.
[0036]
The FIFO 110 includes, for example, a 960 × 32-bit reception FIFO 110a and a 960 × 32-bit transmission FIFO 110b.
[0037]
[Asynchronous circuit]
When performing asynchronous transmission via the IEEE 1394 serial bus BUS, the link core 101 transmits / receives a packet for asynchronous communication while transmitting / receiving a reception permission signal and a reception confirmation signal to / from the other party as described above. Send and receive.
[0038]
The host interface circuit 102 performs arbitration of writing and reading of asynchronous communication packets between the host computer 6 and the transmission FIFO 104a and reception FIFO 104b, and arbitration of transmission / reception of various data from the host computer 6 to the CFR 111. I do.
[0039]
The transmission FIFO 104a stores a transmission packet for asynchronous communication to be transmitted to the IEEE 1394 serial bus BUS, and the reception FIFO 104b stores a reception packet for asynchronous communication transmitted through the IEEE 1394 serial interface bus BUS.
[0040]
The resolver 105 analyzes the content of the self ID packet transmitted through the IEEE1394 serial interface bus BSU at the time of bus reset, and stores it in the CFR 111.
[0041]
Physical layer circuit 10
The physical layer circuit 10 performs arbitration of the IEEE 1394 serial bus BUS.
The physical layer circuit 10 encodes the transmission packet input from the link layer circuit 9 and outputs the encoded packet to the IEEE 1394 serial bus BUS. Further, the physical layer circuit 10 decodes the received packet input from the IEEE 1394 serial bus BUS and outputs the decoded packet to the link layer circuit 9.
[0042]
Physical layer circuit 11
The physical layer circuit 11 is connected to the physical layer circuit 10 via the IEEE 1394 serial bus BUS, and has the same configuration and function as the above-described physical layer circuit 10.
[0043]
Link layer circuit 12
As shown in FIG. 6, the link layer circuit 12 has the same configuration as the link layer circuit 9 shown in FIG. 2 except for the application connected to the application I / F circuit 103.
That is, in the link layer circuit 12, an MD device 20 that writes ATRAC data to the MD 13 as an application is connected to the application I / F circuit 103.
[0044]
Hereinafter, processing at the time of reception in the application I / F circuit 103 of the link layer circuit 12 will be described.
The processing at the time of reception can also be performed in the application I / F circuit 103 of the link layer circuit 9 shown in FIG. 2 under the same situation.
The application I / F circuit 103 analyzes the transport packet header TPH, the PES packet header PPH, the data header DH, and the FDF shown in FIG. 4 of the TS packet shown in FIG. . Then, the application I / F circuit 103 extracts the 159-byte ATRAC data S12 included in the TS packet shown in FIGS. 3 and 4 input from the post-reception processing circuit 109, and outputs this to the DSP 23.
[0045]
At this time, in the present embodiment, the application I / F circuit 103 uses the configuration shown in FIG. 7 and the order instruction data PES-data-conuter and present-PES-number shown in FIG. 4 included in the received TS packet. And the continuity of the received TS packets, that is, the presence or absence of missing TS packets is detected.
[0046]
The application I / F circuit 103 includes, for example, continuity detection circuits 200 and 201 and a CFR write circuit 202 as shown in FIG.
The continuity detection circuit 200 inputs the 3-bit order instruction data PES-data-conuter shown in FIG. 4 included in the TS packet input from the post-reception processing circuit 109, and the input order instruction data PES-data-conuter. And the previously input order instruction data PES-data-conuter, and a continuity detection signal S200 indicating the determination result and the presently input order instruction data PES-data- conuter is output to the CFR writing circuit 202.
The order instruction data PES-data-conuter has 0, 1, 2, 3, 4, 5, 6, 7, 0, 1,. . . Are input to the continuity detection circuit 200 in this order.
[0047]
The continuity detection circuit 201 inputs the 24-bit order instruction data present-PES-number shown in FIG. 4 included in the TS packet input from the post-reception processing circuit 109, and the input order instruction data present-PES-number. Is output, and the continuity detection signal S200 indicating the determination result and the order instruction data present-PES-number input this time are output to the CFR writing circuit 202.
Specifically, the continuity detection circuit 201 determines whether or not the order instruction data present-PES-number is incremented (increased) by 1 for every eight consecutively input TS packets. That is, the order instruction data present-PES-number included in eight consecutively input TS packets indicates the same value, and a value obtained by incrementing the value of the order instruction data present-PES-number by 1, Next, it is determined whether or not the sequential instruction data present-PES-number of eight TS packets that are continuously input are indicated.
[0048]
The CFR writing circuit 202 includes a continuity detection signal S200 and order instruction data PES-data-conuter input from the continuity detection circuit 200, and a continuity detection signal S201 and order instruction data present-PES input from the continuity detection circuit 201. Based on -number, when at least one of continuity detection signals S200 and S201 indicates that there is no continuity, the order that was input and stored when it was determined that there was continuity last time The instruction data PES-data-conuter and present-PES-number are written in the CFR 111.
[0049]
Host computer 16
As described above, the host computer 16 detects the discontinuity of the present-PES-number and PES-data-counter included in the received packet for isochronous communication by the application I / F circuit 103 of the link layer circuit 12. When the present-PES-number and the PES-data-counter of the received packets that are received with continuity are written to the CFR 111 at the end, an interrupt signal is input from the host interface circuit 102 by the write, and the CFR 111 A transmission packet for asynchronous communication including the read present-PES-number and PES-data-counter is output to the link layer circuit 12. The transmission packet is output to the host computer 6 via the link layer circuit 12, the physical layer circuit 11, the IEEE 1394 serial bus BUS, the physical layer circuit 10, and the link layer circuit 9.
Further, the host computer 16 outputs a control signal S16 to the DSP 23.
[0050]
MD device 20
The MD device 20 has an MD write block 14 and a DSP 23 and writes ATRAC data S12 input from the link layer circuit 12 to the MD 13. The DSP 5 controls the MD write block 14 based on the control signal S16 from the host computer 16 and writes the ATRAC data S12 input from the link layer circuit 12 to the MD 13.
The MD writing block 14 has a drive system that rotationally drives the MD 3 and a read system such as an optical pickup.
[0051]
Hereinafter, the operation of the communication system 1 shown in FIG. 1 will be described.
FIG. 8 is a flowchart for explaining the operation of the communication system 1 shown in FIG.
Step S1
First, when an MD reading instruction is performed by a user operating an operation means (not shown), a control signal S6 is output from the host computer 6 to the DSP 5, and the MD reading block 4 performs MD to ATRAC according to the control from the DSP 5. Data S5 is read out. The read ATRAC data S5 is output to the application I / F circuit 103 of the link layer circuit 9 shown in FIG.
[0052]
Next, in the application I / F circuit 103 of the link layer circuit 9, the TS packet shown in FIGS. 3 and 4 including the ATRAC data S5 read from the MD3 is generated, and the TS packet is converted into a pre-transmission processing circuit. In 106, after the data length is adjusted in units of 4 bytes, the data length is stored in the FIFO 110b for transmission of the FIFO 110.
Then, in the post-transmission processing circuit 107, as shown in FIG. 5, a 1394 header and CIP headers (Headers) 1 and 2 are added to the TS packet read from the transmission FIFO 110b to generate a transmission packet for isochronous communication. Is done. The transmission packet is output to the link core 101, and is isochronously transferred to the link layer circuit 12 via the physical layer circuit 10, the IEEE 1394 serial bus BUS, and the physical layer circuit 11 shown in FIG. 1 every 125 μs. Is done.
[0053]
Step S2
A transmission packet from the link layer circuit 9 is input to the reception preprocessing circuit 108 as a reception packet via the link core 101 of the link layer circuit 12 shown in FIG. After the contents of the 1394 header, the CIP headers 1 and 2 are analyzed, a 188-byte TS packet included in the received packet is written into the reception FIFO 110a.
Then, the TS packet is read from the reception FIFO 110 a and output to the application I / F circuit 103 via the post-reception processing circuit 109.
[0054]
Then, in the application I / F circuit 103 shown in FIG. 7 of the link layer circuit 12, whether or not the order instruction data PES-data-conuter and present-PES-number shown in FIG. If it is determined that there is no continuity, the process of step S3 is executed. If it is determined that there is continuity, the process of step S1 is repeated.
[0055]
Step S3
If the application I / F circuit 103 determines in step S2 that the order instruction data PES-data-conuter and present-PES-number included in the TS packet are not continuous, the link core 101 is connected via the CFR 111. An interrupt signal is output to, and reception of the packet for isochronous communication via the IEEE1394 serial bus BUS is stopped.
Step S4
Next, the CFR writing circuit 202 shown in FIG. 7 of the application I / F circuit 103 inputs the order indication data PES-data-conuter and present-PES-, which are inputted and stored when it is determined that there is continuity last time. Write number to CFR111. When the order instruction data PES-data-conuter and present-PES-number are written into the CFR 111, an interrupt signal is output from the host interface circuit 102 to the host computer 16.
[0056]
Step S5
When the host computer 16 receives an interrupt signal from the host interface circuit 102, the host computer 16 reads the order instruction data PES-data-conuter and present-PES-number from the CFR 111, and the read order instruction data PES-data-conuter and present-PES. The transmission packet for asynchronous communication including -number is output to the host interface circuit 102.
The transmission packet for asynchronous communication is stored in the transmission FIFO 104a via the host interface circuit 102 shown in FIG. 6, and then the link core 101, the physical layer circuit 11 shown in FIG. 1, the IEEE 1394 serial bus BUS, and the physical Asynchronous transmission is performed to the link layer circuit 9 via the layer circuit 10.
[0057]
Step S6
In the link layer circuit 9 shown in FIG. 2, the transmission packet for asynchronous communication is stored as a reception packet in the reception FIFO 104b via the resolver 105 and then read out, and is read out through the host interface circuit 102. Is output.
Then, in the host computer 6, a control signal is sent to the DSP 5 so that the ATRAC data after the ATRAC data specified by the order instruction data PES-data-conuter and present-PES-number included in the received packet is read again from the MD3. S6 is output.
Then, the ATRAC data S5 read from the MD3 is subjected to the same process as step S1 described above, and the link layer circuit 9, the physical layer circuit 10, the IEEE 1394 serial bus BUS, and the link layer circuit 12 shown in FIG. Is transmitted to the MD device 20 via the.
[0058]
As described above, according to the communication system 1, when an isochronous communication packet including ATRAC data is transmitted from the MD device 2 to the MD device 20 via the IEEE1394 serial bus BUS, the received isochronous communication packet is received. The link layer circuit 12 detects the continuity of the ATRAC data included in the data, transmits an asynchronous communication packet for identifying the missing ATRAC data to the host computer 6, and includes isochronous data including the ATRAC data after the missing ATRAC data. The communication packet is transmitted again from the link layer circuit 9 to the link layer circuit 12.
Therefore, according to the communication system 1, the MD device 20 can accurately write all ATRAC data read from the MD device 2 to the MD 13. As a result, when the ATRAC data written in the MD 13 is expanded and reproduced, the ATRAC data can be accurately expanded.
That is, according to the communication system 1, it is possible to improve the transmission quality of ATRAC data via the IEEE 1394 serial bus BUS and substantially transmit ATRAC data via the IEEE 1394 serial bus BUS.
[0059]
The present invention is not limited to the embodiment described above.
For example, in the above-described embodiment, the continuity of the ATRAC data is detected using the order instruction data PES-data-conuter and the present-PES-number included in the TS packet. The order instruction data may be used.
[0060]
In the above-described embodiment, the case where a packet including ATRAC data is transmitted by isochronous communication and the missing data request is transmitted by asynchronous communication is exemplified. However, in the present invention, the transmission method of data and missing data request is particularly limited. Not.
[0061]
In the embodiment described above, the case where the MD device 2 and the MD device 20 are connected to the link layer circuit 9 and the link layer circuit 12 as applications, respectively, is exemplified. Is optional.
[0062]
【The invention's effect】
As described above, according to the data processing circuit of the present invention, even when the received data is missing, the missing data request signal is transmitted to the transmitting side, so that the missing data is received again from the transmitting side. Therefore, it is possible to perform processing using continuous data without missing.
In addition, according to the data transmission system of the present invention, when data received by the data receiving device is missing, the missing data is transmitted from the data transmitting device to the data receiving device based on the missing data request signal. In the data receiving apparatus, it is possible to perform processing using continuous data with no omission.
Further, according to the data transmission method of the present invention, when the data received at the receiving side is missing, the missing data request signal is transmitted from the sending side to the receiving side based on the missing data request signal. , It is possible to perform processing using continuous data without missing.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a communication system according to the present invention applied to an IEEE 1394 serial interface.
FIG. 2 is an internal configuration diagram of a link layer circuit on the transmission side;
FIG. 3 is a diagram for explaining a format of a transport packet TS.
4 is a diagram for explaining a format in a data body DB shown in FIG. 3. FIG.
FIG. 5 is a diagram for explaining a format of a packet for isochronous communication transmitted via an IEEE 1394 serial bus.
FIG. 4 is a diagram for explaining a connection form between a link layer circuit on the receiving side and an application;
FIG. 7 is a partial configuration diagram in the application I / F circuit shown in FIG. 6;
FIG. 8 is a flowchart for explaining the operation of the communication system shown in FIG. 1;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Communication system, 2,20 ... MD apparatus, 3,13 ... MD, 5,23 ... DSP, 6,16 ... Host computer, 9,12 ... Link layer circuit, 10,11 ... Physical layer circuit, 101 DESCRIPTION OF SYMBOLS ... Link core, 102 ... Host interface circuit, 103 ... Application I / F circuit, 104 ... Asynchronous communication FIFO, 105 ... Resolver, 106 ... Isochronous communication pre-transmission processing circuit, 107 ... Isochronous communication post-transmission processing circuit, 108 ... pre-reception processing circuit for isochronous communication, 109 ... post-reception processing circuit for isochronous communication, 111 ... CFR, 200, 201 ... continuity detection circuit, 202 ... CFR writing circuit

Claims (14)

A data processing circuit capable of connecting a plurality of applications, including first and second order instruction data indicating the order of the data in the data of the application, and capable of communicating with other data processing circuits via a data transmission path Because
A first storage unit;
A first receiving circuit that analyzes the received data and stores the data in the first storage unit;
A second receiving circuit that reads the data stored in the first storage unit and performs processing according to the read data;
At the time of reception, the first and second order instruction data are extracted from the data processed by the second reception circuit to monitor the continuity of the data, and at the time of transmission, the first data is added to the data to be transmitted. And a continuity detection circuit for generating the second order instruction data;
A second storage unit;
A first transmission circuit that adjusts the data length of the data processed by the continuity detection circuit during transmission and stores it in the second storage unit;
A second transmission circuit that reads the data stored in the second storage unit and adds the first and second order instruction data;
A third transmission circuit for transmitting, to the application side, a missing data request signal for requesting the missing data to the transmission side when the continuity detection circuit detects a missing data in the data at the time of reception; And
The continuity detection circuit includes:
At the time of reception, the continuity is detected by comparing the first order instruction data and the first order instruction data input last time, and the first continuity detection signal indicating the detection result and the first input the current time. A first detection circuit that outputs one order instruction data;
A second detection circuit that detects continuity of the second order instruction data and outputs a second continuity detection signal indicating the detection result and the second order instruction data;
The first continuity detection signal and the first order instruction data output from the first detection circuit, and the second continuity detection signal and the second order instruction output from the second detection circuit. The first and second continuity detection signals are compared based on the data, and when at least one of the continuity detection signals is discontinuous, it is determined that there is continuity at the end. And a data processing circuit including a writing circuit for writing the second order instruction data to a predetermined circuit. The data processing circuit according to claim 1, wherein the continuity detection circuit stops receiving the data via the data transmission path when detecting the missing data. The data processing circuit according to claim 1, wherein the first receiving circuit receives a plurality of packets each including a predetermined amount of the data. The continuity detection circuit detects the missing data for each packet,
The data processing circuit according to claim 3 , wherein the third transmission circuit transmits the missing data request signal for requesting the missing data to the transmission side for each packet. The data is compressed in units of a predetermined amount of continuous data,
The data processing circuit according to claim 3 , wherein at least part of data included in the same compression unit is included in different packets. The data processing circuit according to claim 3 , wherein the packet is transmitted through the data transmission path at a predetermined time interval. The third transmission circuit transmits the missing data request signal to the transmission side when receiving a reception permission signal permitting reception of a signal from the transmission side via the data transmission path, The data processing circuit according to claim 1, wherein a reception confirmation signal is received from the transmission side when the missing data request signal is properly received on the transmission side. The data processing circuit according to claim 1, further comprising: an output circuit that outputs the received data to an application side. The data processing circuit according to claim 1, wherein the data transmission path is a serial bus. Data in which a plurality of applications can be connected, and the data of the application includes first and second order instruction data indicating the order of the data, and the data transmission device and the data reception device are connected via a data transmission path. A transmission system,
The data receiving device is:
A first storage unit;
A first receiving circuit that analyzes the received data and stores the data in the first storage unit;
A second receiving circuit that reads the data stored in the first storage unit and performs processing according to the read data;
At the time of reception, the first and second order instruction data are extracted from the data processed by the second reception circuit to monitor the continuity of the data, and at the time of transmission, the first data is added to the data to be transmitted. And a continuity detection circuit for generating the second order instruction data;
Have
The data transmission device includes:
Sharing the continuity detection circuit;
A second storage unit;
A first transmission circuit that adjusts the data length of the data processed by the continuity detection circuit during transmission and stores it in the second storage unit;
A second transmission circuit that reads the data stored in the second storage unit and adds the first and second order instruction data;
A third transmission circuit for transmitting, to the application side, a missing data request signal for requesting the missing data to the transmission side when the continuity detection circuit detects a missing data in the data at the time of reception; And
The continuity detection circuit includes:
At the time of reception, the continuity is detected by comparing the first order instruction data and the first order instruction data input last time, and the first continuity detection signal indicating the detection result and the first input the current time. A first detection circuit that outputs one order instruction data;
A second detection circuit that detects continuity of the second order instruction data and outputs a second continuity detection signal indicating the detection result and the second order instruction data;
The first continuity detection signal and the first order instruction data output from the first detection circuit, and the second continuity detection signal and the second order instruction output from the second detection circuit. The first and second continuity detection signals are compared based on the data, and when at least one of the continuity detection signals is discontinuous, it is determined that there is continuity at the end. And a writing circuit for writing the second order instruction data to a predetermined circuit. The data transmission system according to claim 10 , wherein the continuity detection circuit stops receiving the data via the data transmission path when detecting the missing data. The data transmission system according to claim 10 , wherein the data transmission device transmits a plurality of packets each including a predetermined amount of the data via the data transmission path. The data is compressed in units of continuous predetermined amount of data,
The data transmission system according to claim 12 , wherein at least part of data included in the same compression unit is included in the different packets. A data transmission method capable of connecting a plurality of applications, including first and second order instruction data indicating the order of the data in the data of the application, and transmitting and receiving data via a data transmission path,
The transmission data is generated by adjusting the data length of the data, the first and second order instruction data are added to the transmission data, and the data is transmitted from the transmission side to the reception side via the data transmission path. A first step to:
A second step of detecting missing data by monitoring continuity of the data received via the data transmission path at the receiving side;
A third step of stopping reception of the data according to the monitoring result of the data;
A fourth step of generating an interrupt signal based on the first and second order instruction data when it is determined that the data is continuous;
A fifth step of transmitting a missing data request signal for requesting the missing data from the reception side to the transmission side by the interrupt signal;
On the transmitting side, upon receiving the missing data request signal, a sixth step of transmitting data specified by the missing data request signal to the receiving side;
Have
In the second step,
An extraction step of extracting the first and second order instruction data from the received data;
The first order instruction data and the previous first order instruction data are compared to detect continuity, and the first continuity detection signal indicating the detection result and the current first order instruction data A first detection step of outputting
A second detection step of detecting continuity of the second order instruction data and outputting a second continuity detection signal indicating the detection result and the second order instruction data;
Based on the first continuity detection signal and the first order instruction data in the first detection step, and the second continuity detection signal and the second order instruction data in the second detection step. The first and second continuity detection signals are compared, and when at least one of the continuity detection signals is discontinuous, the first and second are determined to have continuity at the end. A data transmission method comprising: a writing step of writing the order instruction data into a predetermined circuit.

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