JP4030775B2 - Semiconductor memory circuit, semiconductor device, and semiconductor device manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory circuit, a semiconductor device including at least two memory chips on which the semiconductor memory circuit is mounted, and a semiconductor in which any one memory chip operates. The present invention relates to a method for manufacturing a semiconductor device manufactured as a device.
[0002]
[Prior art]
Describing the prerequisite technology of the present invention, a multi-chip product, that is, a semiconductor device including two memory chips of the same specification (for example, for a large capacity DRAM) uses two memory chips determined as good products by prior inspection. , To be manufactured. Various kinds of characteristic tests (characteristic tests on refresh characteristics and input voltage characteristics at the time of simultaneous operation of two chips) have been performed on the semiconductor device thus manufactured. If a single memory chip is defective, or even if each memory chip itself is not defective, if it is determined to be defective in a test during simultaneous operation of two chips, the semiconductor device is discarded as it is. The fact is that it was disposed of. Incidentally, when a defective address is extracted at the probe inspection stage for the memory chip, only the word line or data line including the defective address is replaced with a relief word line or data line to reduce the defective address. Bit defective memory chips can be relieved.
[0003]
[Problems to be solved by the invention]
As described above, when any one of the memory chips is clearly defective, or even if each memory chip itself is not defective, it was determined to be defective by a test at the time of simultaneous operation of two chips. In some cases, the semiconductor device has been disposed of as it is. However, the probability that all the memory chips in the semiconductor device are defective at the same time is small, and even though any one of the memory chips is a non-defective product, it is discarded from an economic point of view. From the viewpoint of environmental protection, it is not preferable. That is, it is conceivable to utilize a semiconductor device including one good memory chip without disposing of a semiconductor device in which a part of the memory chip is defective. Even if each memory chip itself is not defective, it is conceivable to utilize one of the memory chips even when it is determined to be defective in a test at the time of simultaneous operation of two chips.
[0004]
However, a semiconductor device including at least two memory chips having the same specification is compatible with a semiconductor device including one memory chip having the same specification as a state in which the external pins for memory addressing and the external pins for various control signals are shared. In reality, it is difficult to operate any one of the memory chips while maintaining the performance. This is because a semiconductor device including one memory chip of the same specification cannot always be obtained as being interchangeable due to the arrangement of input / output pins.
[0005]
A first object of the present invention is to provide a semiconductor device including at least two memory chips of the same specification, a memory chip of the same specification as a state in which a memory address specifying external pin and various control signal external pins are shared. An object of the present invention is to provide a semiconductor memory circuit having a basic circuit configuration that is required to operate any one of the memory chips while being compatible with a semiconductor device including the individual semiconductor devices.
[0006]
A second object of the present invention is to provide a semiconductor device including at least two memory chips of the same specification, and a memory chip of the same specification as a state in which a memory address specifying external pin and various control signal external pins are shared. An object of the present invention is to provide a semiconductor device capable of operating any one of the memory chips while being compatible with the semiconductor device including the individual semiconductor devices.
[0007]
A third object of the present invention is to operate one of the memory chips while making a semiconductor device including at least two memory chips of the same specification compatible with a semiconductor device including one memory chip of the same specification. Another object of the present invention is to provide a method of manufacturing a semiconductor device that can be manufactured.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The outline of typical inventions among the inventions disclosed in the present application will be described as follows.
[0010]
According to the semiconductor memory circuit of the present invention, a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of data lines, a circuit for controlling the memory cells, and two types of address signals from the outside The input / output data input / output between the function stop mode circuit for generating the first and second deactivation signals and the outside is input via the standard input / output pin group or the non-standard input / output pin group. An input / output pin group selection switch circuit for selecting whether to output, and the input / output pin group depending on whether or not the included fuse is blown by overcurrent on condition that the first inactivation signal is generated An input / output pin group selection control circuit that selectively controls the selection switch circuit; a power supply availability selection switch circuit that selects whether to supply operating power to the circuit that controls the memory cell; and the second Deactivation And an operation power supply availability selection control circuit that selectively controls the power supply availability selection switch circuit depending on whether or not the included fuse is cut by overcurrent It is a thing.
[0011]
Further, the semiconductor device of the present invention is configured to include at least two memory chips on which the semiconductor memory circuit is mounted, in a state where the memory address designating external pins and various control signal external pins are shared. It is what I did.
[0012]
Furthermore, in the method of manufacturing a semiconductor device according to the present invention, when it is determined that one of the memory chips is to be operated based on the selection result, two types of address signals are sequentially input via the external pins for specifying the memory address. The fuses included in each of the input / output pin group selection control circuit and the operation power supply availability selection control circuit in a state where the first and second deactivation signals are sequentially generated from each of the function stop mode circuits. By selectively disconnecting each of the memory chips by an overcurrent, the one memory chip is input / output via the standard input / output pin group in a state where operating power is supplied to the circuit for controlling the memory cell. The other memory chip is placed in a state where data is input / output, while the non-standard input / output pin is in a state where no operating power is supplied to the circuit controlling the memory cell. In a state where as if input and output data via the group is placed in a state to be input, in which one of the memory chips semiconductor device which operation is to be produced.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
[0014]
First, a manufacturing process of a semiconductor device including two memory chips on which a semiconductor memory circuit of the present invention is mounted will be described. FIG. 1 shows a manufacturing flow in one example. As shown in the drawing, whether or not the memory chip is a non-defective product is selected in a state where the two memory chips are temporarily assembled (processing 1 and 2). If it is a non-defective product, it is assembled as a semiconductor device for the first time (Process 3). Thereafter, the semiconductor device manufactured in this way is subjected to a failure acceleration test, and it is determined again whether or not it is a non-defective product (processes 4 and 5). With this determination, a semiconductor device including two memory chips is obtained as a product for the first time as a non-defective product.
[0015]
If it is determined after the failure acceleration test that the product is not a good product, it is determined whether one of the memory chips is a good product (Process 6). When one of the memory chips is a non-defective product, as will be described later, a function stop process is performed on the defective memory chip, whereby a semiconductor device in which only the non-defective memory chip is utilized can be manufactured ( Process 7). After that, the semiconductor device is selected, but when it is selected as a non-defective product, a semiconductor device that can operate as a product including two memory chips for the first time but also including one bag is obtained as a product. (Process 8).
[0016]
By the way, if it is selected as a defective product in the sorting after the temporary assembly, it is determined whether or not any of the memory chips is a non-defective product. Non-defective memory chips are discarded, and a semiconductor device including only one remaining non-defective memory chip is manufactured (Processing 9 and 10). Although this semiconductor device is also selected, a semiconductor device that can operate as a product including one memory chip for the first time after being selected as a non-defective product is obtained as a product (process 12).
[0017]
Here, the semiconductor memory circuit of the present invention will be described. FIG. 2 shows an example of the circuit configuration. As shown in the figure, in this example, an SDRAM is assumed as the circuit configuration, most of which is an existing circuit, and the function stop mode circuit 38 is added according to the present invention. Various circuits according to the present invention are incorporated in addition to the function stop mode circuit 38. Other than the function stop mode circuit 38, that is, an operation power supply availability selection control circuit, an input / output pin group selection control circuit, etc. Is described later.
[0018]
In the function stop mode circuit 38, when two types of non-normal address signals are sequentially applied from the outside, the function stop mode circuit 38 generates a deactivation signal corresponding to the type of the non-normal address signal. Has been generated. As will be described later, the first deactivation signal is used to selectively cut a fuse included in the input / output pin group selection control circuit due to an overcurrent, and the second deactivation signal is This is used to selectively cut each fuse included in the operation power supply availability selection control circuit due to overcurrent.
[0019]
Incidentally, since the existing circuit is not directly related to the present invention, it is considered that a detailed description thereof is unnecessary, but the following is a simple list of the components.
[0020]
That is, the existing circuit includes a memory array 21 including a plurality of DRAM memory cells provided at intersections of a plurality of word lines and a plurality of data lines, a peripheral circuit for controlling the memory cells, an address buffer 22, a latch circuit 23, 24, predecoders 25 and 26, relief circuits 27 and 28, decoders 29 and 30, sense amplifier 31, main amplifier 32, input buffer 33, output buffer 34, main control circuit / clock generation circuit 35, refresh counter 36, and internal voltage The generating circuit 37 is configured. In the existing circuit configured as described above, the row address strobe signal RAS, the column address strobe signal CAS, the write enable signal WE, and the chip select signal CS are supplied from the outside of the chip in addition to the address signals Add1 to Addn and the clock signal CLK. It is what has been entered.
[0021]
Now, in a state where the external pins for memory address specification and the external pins for various control signals are shared, a semiconductor device including at least two memory chips with the same specification is compatible with a semiconductor device including one memory chip with the same specification. As described above, it is difficult to operate any one of the memory chips while maintaining the characteristics, and the reason is required for the difference in the arrangement of the input / output pins. FIG. 3B shows an example of the arrangement of input / output pins in a semiconductor device including one memory chip having the same specification (memory chip in which the semiconductor memory circuit of the present invention is not mounted). An arrangement example of input / output pins in a semiconductor device including two of As shown in FIG. 3B, the two memory chips are distinguished as an upper chip and a lower chip, but correspond to data input / output pins (pin numbers 5, 11, 44, and 50 corresponding to the lower chip, The standard input / output pin) is compatible with a semiconductor device including one memory chip, but corresponds to the data input / output pin (pin numbers 2, 8, 47, 53) corresponding to the upper chip, As for non-standard input / output pins), it is understood that the semiconductor device including one memory chip is not compatible. Therefore, in order to make the data input / output pin compatible with the upper chip compatible, even when only the upper chip operates, the data input / output pin compatible with the lower chip can be switched by switching the input / output data on the chip. Data may be input / output via the. 3A and 3B, Vcc indicates the operating power supply voltage, Vss indicates the ground potential level, and NC indicates an empty input / output pin. As shown in FIG. 3B, there are a plurality of empty input / output pins. These empty input / output pins are related to the realization of the present invention, as will be described later.
[0022]
FIG. 4 shows a schematic functional configuration (basic configuration) of a memory chip when a semiconductor device including one memory chip on which the semiconductor memory circuit of the present invention is mounted is manufactured. As shown in the figure, when a pad for monitoring an internal chip used only for a vacant pad (probe inspection (inspection for confirmation of self-refresh cycle and voltage generation of a step-down circuit), etc.) is diverted, the laser associated therewith The optional pads ОPPAD1 to OVPAD3 are provided on the chip by using the fuses that are cut off, and each of these optional pads ОPPAD1 to OVPAD3 is left open and melted fuses (hereinafter simply referred to as fuses). Each of the switch circuits SW1 to SW4 is controlled in a predetermined manner via F1 to F3. Among these switch circuits SW1 to SW4, the switch circuit SW3 is open (floating) and turned on, and the switch circuits SW1, SW2, and SW4 are both turned on at the Vss (earth) level. (The same applies to FIGS. 5 to 7 below).
[0023]
Therefore, the switch circuit SW1 is not in the ON state, and no operating power is supplied to the existing circuit by the switch circuit SW1, but the Vss level is given to the switch circuit SW2 through the laser fuse LF. The switch circuit SW2 placed in the ON state supplies the operating power (operating power supply voltage: Vcc) to the existing circuit. When a semiconductor device including one memory chip is manufactured, the laser fuse LF is always in an uncut state, but otherwise, it is always in a cut state. Since the switch circuits SW3 and SW4 are respectively in the ON state and the OFF state, data (chip internal DQ0) is not input / output via the input / output pin of pin number 2 and the DQOP0 pad. The data is input / output via the input / output pin of pin number 5 and the pad for DQ0. This relationship is the same between the input / output pins with the pin numbers 8 and 11, the input / output pins with the pin numbers 47 and 44, and the input / output pins with the pin numbers 53 and 50. That is, in this example, four pairs of switch circuits SW3 and SW4 are provided. Incidentally, in FIG. 4, the double line display regarding the input / output data transfer and the operation power supply indicates that it is in a disconnected state. Such display is the same in the following FIG. 5 to FIG. 7, and the same display is performed for Vss (earth) level supply.
[0024]
FIG. 5 also shows a schematic functional configuration of the memory chip when a semiconductor device including two memory chips on which the semiconductor memory circuit of the present invention is mounted is manufactured. As shown in the figure, in this case, the fuses F1 to F3 are not cut at all in the upper chip and the lower chip, and the option pads ОPPAD1 and OVPAD2 on the upper chip are both set to Vss (grounding) via the empty input / output pins. ), The option pad ОPPAD3 is placed in the open state, while on the lower chip, the option pads ОPPAD1 and OPPAD2 are both in the open state, and the option pad ОPPAD3 is brought to the Vss (ground) level via the empty input / output pin. Each is left.
[0025]
Therefore, in this case, on the upper chip, the switch circuits SW1, SW2, SW3, and SW4 are in the ON state, the OFF state, the OFF state, and the ON state, respectively, while in the lower chip, the switch circuits SW1, SW2, SW3 and SW4 are in an OFF state, an ON state, an ON state, and an OFF state, respectively. In this state, the operation power is supplied to both the existing circuits on the upper chip and the lower chip. In the upper chip, data is input / output via the input / output pin of pin number 2, while in the lower chip, Data is input / output via an input / output pin of pin number 5. This relationship is the same between the input / output pins with the pin numbers 8 and 11, the input / output pins with the pin numbers 47 and 44, and the input / output pins with the pin numbers 53 and 50.
[0026]
Further, FIG. 6 shows a schematic functional configuration of the memory chip when only the upper chip is operated due to a lower chip defect on the semiconductor device including two memory chips on which the semiconductor memory circuit of the present invention is mounted. It is a thing. As shown in the figure, in this case, the fuse F2 on the upper chip and the fuse F3 on the lower chip must be cut (the method for cutting the fuse will be described later), and On the upper chip, option pads ОPPAD1 and OVPAD3 are placed in the Vss (ground) level and open state, respectively, while on the lower chip, option pads ОPPAD1 and ОPPAD2 are placed in the open state and Vss (ground) level, respectively. It has become one.
[0027]
Therefore, in this case, on the upper chip, the switch circuits SW1, SW2, SW3, and SW4 are in an ON state, an OFF state, an ON state, and an OFF state, respectively, while in the lower chip, the switch circuits SW1, SW2, SW3 and SW4 are in an OFF state, an OFF state, an OFF state, and an ON state, respectively. In this state, the operation power is supplied only to the existing circuit on the upper chip, and data is input / output through the input / output pin of pin number 5 in the upper chip. In the lower chip, operating power is not supplied to the existing circuit, and data is input / output via the input / output pin of pin number 2. This relationship is the same between the input / output pins with the pin numbers 8 and 11, the input / output pins with the pin numbers 47 and 44, and the input / output pins with the pin numbers 53 and 50.
[0028]
Further, FIG. 7 shows a schematic functional configuration of the memory chip when only the lower chip is operated due to the upper chip defect on the semiconductor device including two memory chips on which the semiconductor memory circuit of the present invention is mounted. It is shown. As illustrated, in this case, only the fuse F1 is cut on the upper chip, and the fuses F1 to F3 are not cut at all on the lower chip. Also, the option pads ОPPAD2 and OPENPAD3 on the upper chip are placed in the Vss (ground) level and open state, respectively, while the option pads ОPPAD1, ОPPAD2, and OPENPAD3 on the lower chip are open, open, and Vss, respectively. (Earth) level.
[0029]
Therefore, in this case, on the upper chip, the switch circuits SW1, SW2, SW3, and SW4 are in the OFF state, the OFF state, the OFF state, and the ON state, respectively, while in the lower chip, the switch circuits SW1, SW2, SW3 and SW4 are in an OFF state, an ON state, an ON state, and an OFF state, respectively. In this state, the operation power is not supplied to the existing circuit on the upper chip, and data is input / output via the input / output pin of pin number 2 in the upper chip. In the lower chip, data is input / output via the input / output pin of pin number 5 while operating power is supplied to the existing circuit. This relationship is the same between the input / output pins with the pin numbers 8 and 11, the input / output pins with the pin numbers 47 and 44, and the input / output pins with the pin numbers 53 and 50.
[0030]
As described above, in the semiconductor device including two memory chips shown in FIG. 4, even if any one of the memory chips is defective, a plurality of fuses F1 to F3 provided on the memory chips are desired. By being selectively disconnected, the semiconductor device can operate as a semiconductor device including one memory chip. In addition, the semiconductor device can operate with compatibility with a semiconductor device originally manufactured to include one memory chip.
[0031]
Here, a method for selectively cutting each of the fuses F1 to F3 in each of the upper chip and the lower chip will be described as follows.
[0032]
That is, for each of the fuses F1 to F3 on the upper chip, the operation power supply availability selection control circuit or the input / output pin group selection control circuit shown in FIG. 8 (substantially the same configuration as the operation power supply availability selection control circuit). Is provided on the upper chip. The situation is the same for the lower chip. As can be seen from the above description, the address signal Add1-Addn is commonly input to the function stop mode circuit 38 on the upper chip and the function stop mode circuit 38 on the lower chip via the address buffer 22. However, when the fuse is cut, generally, two types of address signals that are not used for normal memory access, that is, two types of non-normal address signals are sequentially applied from the outside. When a non-normal address signal is detected in each of these function stop mode circuits 38, two types (first and second) of deactivation signals (hereinafter referred to as first and second) are detected based on the detection output. These deactivation signals are referred to as first and second chip deactivation signals, respectively). On the condition that the first and second chip deactivation signals are generated, the fuse can be cut for the first time.
[0033]
FIG. 8 shows a configuration of an example of an operation power supply availability selection control circuit for cutting the fuse F1 on the upper chip or the fuse F3 on the lower chip. Here, for example, the fuse F1 is It will be as follows if it explains concretely how this will be cut | disconnected as cut | disconnected.
[0034]
That is, in FIG. 8, the fuse 94 corresponds to the fuse F1, and the pad 95 corresponds to the option pad OPPAD1 on the upper chip. Now, in a normal state, the option pad OPPAD1 on the upper chip is set to the Vss (ground) level via the empty input / output pin, and the existing circuit on the upper chip is set to the operating power supply state. . In the normal state, since the non-normal address signal is not applied, the second chip deactivation signal 81 from the function stop mode circuit 38 is always in the “L (0)” state, and the nMOS transistor 82, The pMOS transistors 83 are placed in the OFF state and the ON state, respectively. Further, the second chip deactivation signal 81 causes both the pMOS transistors 84 and 85 to be in the ON state, and the nMOS transistors 90 and 91 are brought into the ON state by this ON state, whereby the nMOS transistor 93 is ОFF state. Therefore, in a normal state, an overcurrent cannot be passed to the pad 95 via the nMOS transistor 93, the current limiting resistor 92, and the fuse 94, so that the fuse 94 is not cut. In other words, in a normal state, the Vss (ground) level from the pad 95 is given to the switch circuit SW1 on the upper chip through the fuse 94, and therefore the switch circuit SW1 is always in the ON state. The existing circuit on the upper chip is supplied with operating power.
[0035]
Normally, it is in the above state. However, when the defect of the upper chip is found and only the upper chip is put into the non-operating state, a non-normal address signal is applied from the outside in the normal state. It has become. By this non-normal address signal, the second chip deactivation signal 81 in the “H (1)” state is generated from each of the function stop mode circuits 38. The second chip deactivation signal 81 causes the nMOS transistor 82 and the pMOS transistor 83 to be in the ON state and the OFF state, respectively, and the second chip deactivation signal 81 causes both the nMOS transistors 86 and 87 to be turned on. Since the pMOS transistors 88 and 89 are placed in the ON state following the ON state, the second chip deactivation signal 81 is slightly shifted from the “H (1)” state. After a delay, the nMOS transistor 93 is in the ON state. At this time, the forcible Vss (ground) level supply to the switch circuit SW1 by the nMOS transistor 82 has already been completed. Therefore, in this state, the fuse 94 can be cut by passing an overcurrent to the pad 95 via the nMOS transistor 93, the current limiting resistor 92, and the fuse 94. Even after the fuse 94 is cut, the Vss (ground) level from the nMOS transistor 82 is applied to the switch circuit SW1 on the upper chip as the chip operation selection signal, and therefore the switch circuit SW1 is put into the ON state. As a result, the operation power is continuously supplied to the existing circuit on the upper chip, and the second chip deactivation signal 81 is continuously generated. This is to avoid it. After that, once the power supply to the entire semiconductor device is stopped, a semiconductor device in which only the lower chip operates can be easily obtained. The fuse F3 on the lower chip can be similarly cut.
[0036]
As can be seen from FIGS. 5 and 7, only the fuse F1 on the upper chip needs to be cut as described above in order to deactivate only the upper chip. However, in order to put only the lower chip into the non-operating state, as shown in FIGS. 5 and 6, the upper chip fuse F2 and the lower chip fuse F3 need to be cut. . Among them, the fuse F3 on the lower chip is the same as the fuse F1 on the upper chip is cut, and the second option pad OPPAD3 on the lower chip is at the Vss (ground) level. The chip deactivation signal may be generated to cut off. Further, in order to cut the fuse F2 on the upper chip, the first chip deactivation signal is generated in a state where both the option pads ʻOPPAD1 and ʻOPPAD2 on the upper chip are at the Vss (ground) level. Then, it can be cut. When the fuse F2 is cut, the option pad OPPAD1 is also at the Vss (ground) level because it is necessary to supply operating power to the existing circuit. Generally, from the viewpoint of maintaining the operation power supply, the fuse F2 is first cut preferentially, and then the fuses F1 and F3 are cut.
[0037]
FIG. 9 also shows a series of processing flows when the fuse F1 on the upper chip or the fuse F3 on the lower chip is cut. In this case, when it is decided to deactivate the upper chip or the lower chip included in the semiconductor device based on the previous sorting result, the semiconductor device in the power-on state is first A non-normal address signal is input from the outside (process 101). As a result, on the upper chip and the lower chip, a (second) chip deactivation signal in the “H (1)” state is generated (process 102). By this deactivation signal, the upper chip and the lower chip are both forced to be supplied with operating power (process 103).
[0038]
If the chip to be deactivated is the upper chip, only the option pad ОPPAD1 is set to the Vss (ground) level on the upper chip, and any of the option pads ОPPAD1 to OPENPAD3 is open on the lower chip. In this state, an overcurrent is caused to flow through the fuse F1, but if the option pad OPPAD1 on the upper chip cannot be placed at the Vss (ground) level at that time, the The semiconductor device is discarded as a defective assembly (process 104, 105). When the option pad OPPAD1 on the upper chip is at the Vss (ground) level, the fuse F1 is cut by an overcurrent (process 107). Such a situation is the same even when the chip to be deactivated is the lower chip (processing 104, 106, 111).
[0039]
Now, when the fuse F1 on the upper chip or the fuse F3 on the lower chip is completely cut off and the power to the semiconductor device is once turned off, only one of the chips stops functioning. (Processing 108, 112, 109, 113). At that time, if the fuse F2 is cut prior to the fuse F1 on the upper chip or the fuse F3 on the lower chip as necessary, it is compatible with a semiconductor device including only one chip. A semiconductor device is obtained (processing 110).
[0040]
The semiconductor memory circuit, the semiconductor device, and the method for manufacturing the semiconductor device have been described above. Finally, a method for relieving defects of various memory cards and semiconductor devices will be described. For example, if one of the two memory chips in the memory card is defective and the memory card itself is about to be discarded, the remaining one memory chip can be used effectively, This is to prevent the memory card itself from being discarded. In particular, it is effective when the standard of the memory card is unified, that is, when the outer shape of the memory card itself is the same and the storage capacity is commercialized in several stages.
[0041]
First, when one of the two memory chips in the memory card is defective and the memory card itself is about to be discarded, the remaining one memory chip is made effective by mechanical processing. The use case will be described with reference to FIG. As shown in the figure, when a defect is found in the memory card (for example, the storage capacity is 128 GB) 201, the function is not applied to the defective chip function stop processing hole with the card protection sheet peeled off. Stop processing is mechanically performed. If a card protection sheet (indicating that the storage capacity is 64 GB) is pasted after the function stop processing is completed, the card can be effectively reproduced as a memory card with a storage capacity of 64 GB.
[0042]
Further, as shown in FIG. 11A, when the memory card 301 having the same outer dimensions and various storage capacities is commercialized, the defective large storage capacity memory card is shown in FIG. As shown, the medium storage capacity memory card is changed (steps 302 and 303), and the defective medium storage capacity memory card is changed to a small storage capacity memory card (step 304). , 306) When there is a shortage of small memory capacity memory cards in the market, even if it is a good medium memory capacity memory card, the small memory capacity memory card is flexibly changed to the small memory capacity memory card. A card is obtained (processing 305, 306, 307).
[0043]
Furthermore, a mechanical relief method from a defect of a semiconductor device including two memory chips by a three-layer film intermediate layer drawing bonding wire separation method will be described with reference to FIGS. .
[0044]
That is, as shown in FIG. 12A, the semiconductor device 401 includes two memory chips 405 and 406. These memory chips 405 and 406 are respectively connected to bonding pads 407 and 407, respectively. By being connected to an external lead frame 403 via 408 and bonding wires (gold wires or the like) 404 and 409, it can operate as a memory chip for the first time. At that time, the bonding wires 404 and 409 are connected to the bonding pads 407 and 408 in such a state that they pass through the three-layer film (partially exposed to the outside) 402 on the bonding pads 407 and 408. It is. FIG. 12B shows the bonding pad 407 and its periphery in an enlarged state. For example, when it is determined that the upper memory chip 405 is defective, only the intermediate layer (second film layer) of the three-layer film 402 on the memory chip 405 side is pulled from the outside to the outside of the semiconductor device 401. In this case, the bonding wire 404 is easily cut so that the memory chip 405 is completely separated from the outside of the semiconductor device. Thereafter, as shown in FIG. 12C, if unnecessary portions exposed to the outside of the three-layer film 402 are separated, the three-layer film 402 can be shipped as a product.
[0045]
As described above, in the case of the three-layer film intermediate layer lead-out bonding wire pulling method, the semiconductor device is not defective because the intermediate film layer is slightly pulled out of the semiconductor device and the object can be easily achieved as desired. It can be remedied quickly. Here, the material and characteristics of the three-layer film will be supplementarily explained. The frictional resistance state and width of each layer film surface are as shown in FIGS. 13 (A) and 13 (B).
[0046]
That is, the intermediate film layer can be easily pulled out of the semiconductor device, so that the frictional resistance on both sides thereof is minimized and the width is also minimized.
[0047]
FIG. 14 also shows the application of the three-layer film to a memory card. As shown in the figure, the memory card 501 includes five memory chips (A to E). The three-layer films 502 to 506 provided corresponding to each of these memory chips correspond to each other. The intermediate film layer is drawn out from the memory card 501 when the memory chip to be defective is defective. Thus, the memory card 501 can be remedied as a state in which only the defective memory chip is invalidated and the remaining non-defective memory chips are utilized without any disposal.
[0048]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the scope of the invention. Yes.
[0049]
【The invention's effect】
The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.
(1) In a state where the external pins for memory address specification and the external pins for various control signals are shared, a semiconductor device including at least two memory chips with the same specification is compatible with a semiconductor device including one memory chip with the same specification A semiconductor memory circuit having a basic circuit configuration required for operating any one of the memory chips is provided.
(2) A semiconductor device including at least two memory chips each equipped with a semiconductor memory circuit having the same specification as a state in which the external pins for memory address specification and the external pins for various control signals are shared There is provided a semiconductor device capable of operating any one of the memory chips while being compatible with a semiconductor device including one memory chip on which is mounted.
(3) A semiconductor device including at least two memory chips on which semiconductor memory circuits of the same specification are mounted is compatible with a semiconductor device including one memory chip on which semiconductor memory circuits of the same specifications are mounted. Either one of the memory chips can be manufactured to operate.
[Brief description of the drawings]
FIG. 1 is a diagram showing a manufacturing flow in an example of a semiconductor device including two memory chips on which a semiconductor memory circuit of the present invention is mounted.
FIG. 2 is a diagram showing a circuit configuration of an example of a semiconductor memory circuit of the present invention.
FIG. 3 shows an arrangement example of input / output pins in a semiconductor device including one memory chip on which the semiconductor memory circuit of the present invention is not mounted, and input / output pins in a semiconductor device including two memory chips of the same specification. It is a figure which shows the example of arrangement | positioning.
FIG. 4 is a diagram showing a schematic functional configuration (basic configuration) of a memory chip when a semiconductor device including one memory chip on which the semiconductor memory circuit of the present invention is mounted is manufactured;
FIG. 5 is a diagram showing a schematic functional configuration of a memory chip when a semiconductor device including two memory chips on which the semiconductor memory circuit of the present invention is mounted is manufactured;
FIG. 6 is a diagram showing a schematic functional configuration of a memory chip when only the upper chip is operated due to a lower chip defect on a semiconductor device including two memory chips on which the semiconductor memory circuit of the present invention is mounted. is there.
FIG. 7 is a diagram showing a schematic functional configuration of a memory chip when only the lower chip is operated due to an upper chip defect on a semiconductor device including two memory chips on which the semiconductor memory circuit of the present invention is mounted. is there.
FIG. 8 is a diagram showing a configuration of an example of an operation power supply availability selection control circuit or an input / output pin group selection control circuit for cutting a fuse on a memory chip;
FIG. 9 is a diagram showing a series of processing flows when the operating power supply availability control fuse is cut.
FIG. 10 shows that when one of two memory chips in a memory card is defective and the memory card itself is about to be discarded, the remaining one memory chip is mechanically processed. It is a figure for demonstrating the method of using it more effectively.
FIG. 11 is a diagram for explaining a method for relieving a defective memory card from a defect when the memory card itself has the same outer dimensions and various storage capacities have been commercialized.
FIG. 12 is a diagram for explaining a mechanical relief method from a defect of a semiconductor device including two memory chips by a three-layer film intermediate layer drawing bonding wire pulling method;
FIG. 13 is a diagram showing the friction resistance state and width of each layer film surface of the three-layer film.
FIG. 14 is a diagram showing application of the three-layer film to a memory card.
[Explanation of symbols]
SW1, SW2 ... Operation power supply availability selection switch circuit
SW3, SW4 ... Input / output pin group selection switch circuit
ОPPAD1-ОPPAD3 ... Option pad
F1-F3 ... Fuse

Claims (4)

When a semiconductor device is formed by mounting at least two memory chips of the same specification, a semiconductor memory circuit used for the memory chip, and when the memory chip mounting the semiconductor memory circuit is operated simultaneously Input / output data is input / output through the standard input / output pin group and the non-standard input / output pin group. When only one of the memory chips is operated, the input / output data is always input through the standard input / output pin group. Input and output,
A plurality of memory cells provided at the intersections of a plurality of word lines and a plurality of data lines, a circuit for controlling the memory cells, and two types of address signals from the outside, the first and second non-lines selecting a failure mode circuit for generating an operation signal, the input and output data that is input and output between the external or be outputted via the standard input-output pin group, or the non-standard input-output pin group Either the input / output pin group selection switch circuit or the input / output pin group selection switch circuit depending on whether or not the included fuse is cut by an overcurrent on condition that the first deactivation signal is generated An input / output pin group selection control circuit for selecting and controlling the power supply, a power supply enable / disable selection switch circuit for selecting whether or not to supply operation power to the circuit for controlling the memory cell, and generation of the second deactivation signal Subject to , Depending on whether cut by Including the fuse overcurrent, the semiconductor memory circuit having an operation power supply availability selection control circuit for selectively controlling either the power supply availability selection switch circuit. 2. A semiconductor device comprising at least two memory chips on which the semiconductor memory circuit according to claim 1 is mounted, wherein a memory address specifying external pin and various control signal external pins are shared between the memory chips. A semiconductor device characterized by the above.   A plurality of memory cells provided at the intersections of a plurality of word lines and a plurality of data lines, a circuit for controlling the memory cells, and two types of address signals from the outside, the first and second non-lines Input / output that selects input / output data input / output between the function stop mode circuit that generates the activation signal and the outside via the standard input / output pin group or non-standard input / output pin group Select the input / output pin group selection switch circuit depending on whether or not the included fuse is cut by an overcurrent on condition that the first deactivation signal is generated and the pin group selection switch circuit A condition for generating an input / output pin group selection control circuit to be controlled, a power supply availability selection switch circuit for selecting whether or not to supply operating power to the circuit for controlling the memory cell, and generation of the second deactivation signal As included At least two memory chips each including a semiconductor memory circuit including an operation power supply availability selection control circuit that selectively controls the power supply availability selection switch circuit depending on whether or not the fuse being disconnected is cut by overcurrent. This is a manufacturing method for manufacturing a semiconductor device including one and a memory address designating external pin and various control signal external pins in common as one of the memory chips is operated. If it is determined that one of the memory chips is to be operated based on the first, second type of address signals from the function stop mode circuit by sequentially inputting two kinds of address signals through the external pins for specifying the memory address. Input / output pin group selection control circuit, operation power supply availability selection control circuit, and so on. When each fuse included in each is selectively cut by an overcurrent, the one memory chip is connected to the circuit that controls the memory cell in a state in which the operation power is supplied. While the input / output data is input / output via the output pin group, the other memory chip is connected via the non-standard input / output pin group with no operating power supplied to the circuit that controls the memory cell. A semiconductor device manufacturing method in which a semiconductor device in which any one of the memory chips operates is manufactured as a state in which input / output data is input / output. From the fuse cutting start point, once the power is turned on for the semiconductor devices, until it is terminated, from the failure mode circuit respectively, claim 3 which is adapted the non-operation signal is continuously generated The manufacturing method of the semiconductor device of description.

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