JP4007135B2 - Jitter reduction circuit and electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a jitter reduction circuit in which a clock including jitter is used as an input signal, and an output signal with reduced jitter is obtained from the clock.
[0002]
[Prior art]
A reference clock is used in a data transmission / reception circuit and a data processing circuit inside a communication device used for high-speed data communication.
However, due to the accuracy of the reference clock generation circuit, the mixing of noise on the transmission / reception part and the path of the reference clock, etc., jitter that is noise in the time axis direction occurs in the reference clock. This jitter causes data errors and the like, so a highly accurate reference clock that does not generate jitter as much as possible is required.
[0003]
Thus, a jitter reduction circuit that reduces jitter when the reference clock includes jitter is known.
As this jitter reduction circuit, for example, as shown in FIG. 10, a phase synchronization circuit including a phase comparator 1, a low-pass filter 2, and a voltage-controlled crystal oscillator 3 is known.
[0004]
In the jitter reduction circuit having such a configuration, the phase comparator 1 detects the phase difference between the input reference clock and the output signal of the voltage controlled crystal oscillator 3, and outputs a phase difference signal corresponding to the detected phase difference. Output. The low-pass filter 2 integrates the phase difference signal. The voltage-controlled crystal oscillator 3 changes its oscillation frequency according to the output of the low-pass filter 2.
[0005]
By such an operation, the phase of the oscillation output signal of the voltage controlled crystal oscillator 3 and the phase of the input reference clock are synchronized. When the phase is synchronized, the oscillation frequency Fvcxo of the voltage controlled crystal oscillator 3 and the frequency of the input reference clock are synchronized. Fin becomes equal and Fvcxo = Fin.
Therefore, in the conventional jitter reduction circuit shown in FIG. 10, the oscillation frequency of the voltage-controlled crystal oscillator 3 must be increased as the frequency of the input reference clock increases.
[0006]
On the other hand, as another conventional jitter reduction circuit, there is known a conventional PLL circuit in which a constant current source is connected to the input side of a voltage controlled oscillator via a switch controlled by a phase comparator (Patent Document). 1).
[0007]
[Patent Document 1]
JP 2000-183732 A (FIG. 1)
[0008]
[Problems to be solved by the invention]
By the way, as described above, in the conventional jitter reduction circuit shown in FIG. 10, the higher the frequency of the input reference clock, the higher the oscillation frequency of the voltage controlled crystal oscillator. The same applies to the jitter reduction circuit described in Patent Document 1.
[0009]
However, crystal resonators (AT resonators) that determine the oscillation frequency of voltage controlled crystal oscillators are generally only practical up to about 150 [MHz], and it is technically difficult to increase the frequency beyond that frequency. In addition, the cost (production cost) increases.
Accordingly, an object of the present invention is to provide a jitter reduction circuit that enables the use of a voltage-controlled crystal oscillator that is highly accurate but has a low oscillation frequency even when the frequency of the input signal is high, thereby reducing production costs. Is to provide.
[0011]
[Means for Solving the Problems]
In order to solve the above problems and achieve the object of the present invention, the inventions described in claims 1 to 10 are configured as follows.
That is, the invention according to claim 1 compares the phase of the input signal and the feedback signal and outputs an error signal corresponding to the phase difference, and integrates the error signal output from the phase comparator. A low-pass filter, a voltage-controlled crystal oscillator whose oscillation frequency changes according to the output of the low-pass filter, and a frequency multiplier circuit that multiplies the output frequency of the voltage-controlled crystal oscillator to an arbitrary value. The output of the frequency multiplier circuit is fed back to the phase comparator as the feedback signal, and the output of the frequency multiplier circuit is extracted.
The frequency multiplication circuit includes a delay synchronization circuit that generates a multiphase clock based on an output of the voltage controlled crystal oscillator, and a logic synthesis circuit that generates a multiplication clock based on the multiphase clock generated by the delay synchronization circuit; Consists of
The logic synthesis circuit is configured to fix the output terminal to a high level potential for a predetermined time in synchronization with a charge storage unit provided at an output terminal and one rising edge or falling edge of the multiphase clock. And a second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock.
[0012]
According to the second aspect of the present invention, the phase of the input signal and the feedback signal are compared, a phase comparator that outputs an error signal corresponding to the phase difference, and the error signal output from the phase comparator is integrated. A band-pass filter, a voltage-controlled crystal oscillator whose oscillation frequency changes according to the output of the low-pass filter, a frequency multiplier circuit that multiplies the frequency of the output of the voltage-controlled crystal oscillator to an arbitrary value, and the frequency multiplier A frequency divider that divides the output of the circuit, and configured to feed back the output of the frequency divider to the phase comparator as the feedback signal and to take out the output of the frequency multiplier circuit,
The frequency multiplication circuit includes a delay synchronization circuit that generates a multiphase clock based on an output of the voltage controlled crystal oscillator, and a logic synthesis circuit that generates a multiplication clock based on the multiphase clock generated by the delay synchronization circuit; Consists of
The logic synthesis circuit is configured to fix the output terminal to a high level potential for a predetermined time in synchronization with a charge storage unit provided at an output terminal and one rising edge or falling edge of the multiphase clock. And a second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock.
[0013]
According to a third aspect of the present invention, a frequency divider that divides an input signal, a phase comparator that compares the phase of an output signal of the frequency divider and a feedback signal, and outputs an error signal corresponding to the phase difference. A low-pass filter that integrates the error signal output from the phase comparator, a voltage-controlled crystal oscillator whose oscillation frequency changes according to the output of the low-pass filter, and an output of the voltage-controlled crystal oscillator A frequency multiplication circuit that multiplies the frequency to an arbitrary value, the output of the frequency multiplication circuit is fed back to the phase comparator as the feedback signal, and the output of the frequency multiplication circuit is extracted.
The frequency multiplication circuit includes a delay synchronization circuit that generates a multiphase clock based on an output of the voltage controlled crystal oscillator, and a logic synthesis circuit that generates a multiplication clock based on the multiphase clock generated by the delay synchronization circuit; Consists of
The logic synthesis circuit is configured to fix the output terminal to a high level potential for a predetermined time in synchronization with a charge storage unit provided at an output terminal and one rising edge or falling edge of the multiphase clock. 1 switching element, and a second switching element that fixes the output terminal to a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock.
[0014]
According to a fourth aspect of the present invention, a first frequency divider that divides an input signal, an output signal of the first frequency divider and a phase of a feedback signal are compared, and an error signal corresponding to the phase difference is compared. A phase comparator that outputs, a low-pass filter that integrates an error signal output from the phase comparator, a voltage-controlled crystal oscillator whose oscillation frequency changes according to the output of the low-pass filter, and the voltage A frequency multiplication circuit that multiplies the output frequency of the control crystal oscillator to an arbitrary value; and a second frequency divider that divides the output of the frequency multiplication circuit, and outputs the output of the second frequency divider to the A feedback signal is fed back to the phase comparator, and the output of the frequency multiplication circuit is taken out.
The frequency multiplication circuit includes a delay synchronization circuit that generates a multiphase clock based on an output of the voltage controlled crystal oscillator, and a logic synthesis circuit that generates a multiplication clock based on the multiphase clock generated by the delay synchronization circuit; Consists of
The logic synthesis circuit is configured to fix the output terminal to a high level potential for a predetermined time in synchronization with a charge storage unit provided at an output terminal and one rising edge or falling edge of the multiphase clock. And a second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock.
[0015]
The invention according to claim 5 compares the phase of the input signal and the feedback signal and outputs an error signal corresponding to the phase difference, and the error signal output from the first phase comparator. , A voltage controlled crystal oscillator whose oscillation frequency changes according to the output of the first low pass filter, and multiplies the output frequency of the voltage controlled crystal oscillator to an arbitrary value. A frequency multiplication circuit, and configured to feed back the output of the frequency multiplication circuit as the feedback signal to the first phase comparator and to take out the output of the frequency multiplication circuit.
The frequency multiplication circuit includes a delay synchronization circuit that generates a multiphase clock based on an output of the voltage controlled crystal oscillator, and a logic synthesis circuit that generates a multiplication clock based on the multiphase clock generated by the delay synchronization circuit; Consists of
The delay synchronization circuit compares the phase of the output signal of the voltage controlled crystal oscillator and the phase of the feedback signal and outputs an error signal corresponding to the phase difference, and is output from the second phase comparator. A second low-pass filter that integrates the error signal and a plurality of delay elements, and sequentially delays the output signal of the voltage-controlled crystal oscillator to generate a multi-phase clock, and the second low-pass filter A delay circuit in which the delay time of each of the delay elements can be varied according to the output of the first delay circuit, and the output of the last delay element of the plurality of delay elements is fed back to the second phase comparator as the feedback signal. And a multi-phase clock generated by the delay circuit,
The logic synthesis circuit is configured to fix the output terminal to a high level potential for a predetermined time in synchronization with a charge storage unit provided at an output terminal and one rising edge or falling edge of the multiphase clock. And a second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock.
[0016]
The invention according to claim 6 compares the phase of the input signal and the feedback signal and outputs an error signal corresponding to the phase difference, and the error signal output from the first phase comparator. , A voltage controlled crystal oscillator whose oscillation frequency changes according to the output of the first low pass filter, and multiplies the output frequency of the voltage controlled crystal oscillator to an arbitrary value. A frequency multiplication circuit; and a frequency divider that divides the output of the frequency multiplication circuit. The output of the frequency divider is fed back to the first phase comparator as the feedback signal, and the output of the frequency multiplication circuit Configured to take out
The frequency multiplication circuit includes a delay synchronization circuit that generates a multiphase clock based on an output of the voltage controlled crystal oscillator, and a logic synthesis circuit that generates a multiplication clock based on the multiphase clock generated by the delay synchronization circuit; Consists of
The delay synchronization circuit compares the phase of the output signal of the voltage controlled crystal oscillator and the phase of the feedback signal and outputs an error signal corresponding to the phase difference, and is output from the second phase comparator. A second low-pass filter that integrates the error signal and a plurality of delay elements, and sequentially delays the output signal of the voltage-controlled crystal oscillator to generate a multi-phase clock, and the second low-pass filter A delay circuit in which the delay time of each of the delay elements can be varied according to the output of the first delay circuit, and the output of the last delay element of the plurality of delay elements is fed back to the second phase comparator as the feedback signal. And a multi-phase clock generated by the delay circuit,
The logic synthesis circuit is configured to fix the output terminal to a high level potential for a predetermined time in synchronization with a charge storage unit provided at an output terminal and one rising edge or falling edge of the multiphase clock. And a second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock.
[0017]
According to a seventh aspect of the present invention, a frequency divider that divides an input signal, a first phase that compares phases of an output signal of the frequency divider and a feedback signal, and outputs an error signal corresponding to the phase difference. A comparator, a first low-pass filter that integrates an error signal output from the first phase comparator, a voltage-controlled crystal oscillator whose oscillation frequency changes according to the output of the first low-pass filter, A frequency multiplication circuit that multiplies the output frequency of the voltage controlled crystal oscillator to an arbitrary value, and feeds back the output of the frequency multiplication circuit to the first phase comparator as the feedback signal. Configure to retrieve the output,
The frequency multiplication circuit includes a delay synchronization circuit that generates a multiphase clock based on an output of the voltage controlled crystal oscillator, and a logic synthesis circuit that generates a multiplication clock based on the multiphase clock generated by the delay synchronization circuit; Consists of
The delay synchronization circuit compares the phase of the output signal of the voltage controlled crystal oscillator and the phase of the feedback signal and outputs an error signal corresponding to the phase difference, and is output from the second phase comparator. A second low-pass filter that integrates the error signal and a plurality of delay elements, and sequentially delays the output signal of the voltage-controlled crystal oscillator to generate a multi-phase clock, and the second low-pass filter A delay circuit in which the delay time of each of the delay elements can be varied according to the output of the first delay circuit, and the output of the last delay element of the plurality of delay elements is fed back to the second phase comparator as the feedback signal. And a multi-phase clock generated by the delay circuit,
The logic synthesis circuit is configured to fix the output terminal to a high level potential for a predetermined time in synchronization with a charge storage unit provided at an output terminal and one rising edge or falling edge of the multiphase clock. And a second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock.
According to an eighth aspect of the present invention, the first frequency divider for dividing the input signal, the output signal of the first frequency divider and the phase of the feedback signal are compared, and an error signal corresponding to the phase difference is compared. The oscillation frequency changes in accordance with the output of the first phase comparator that outputs the first low-pass filter that integrates the error signal output from the first phase comparator, and the output of the first low-pass filter. A voltage controlled crystal oscillator; a frequency multiplying circuit that multiplies an output frequency of the voltage controlled crystal oscillator to an arbitrary value; and a second frequency divider that divides the output of the frequency multiplying circuit. The output of the frequency divider is fed back to the first phase comparator as the feedback signal, and the output of the frequency multiplication circuit is taken out.
The frequency multiplication circuit includes a delay synchronization circuit that generates a multiphase clock based on an output of the voltage controlled crystal oscillator, and a logic synthesis circuit that generates a multiplication clock based on the multiphase clock generated by the delay synchronization circuit; Consists of
The delay synchronization circuit compares the phase of the output signal of the voltage controlled crystal oscillator and the phase of the feedback signal and outputs an error signal corresponding to the phase difference, and is output from the second phase comparator. A second low-pass filter that integrates the error signal and a plurality of delay elements, and sequentially delays the output signal of the voltage-controlled crystal oscillator to generate a multi-phase clock, and the second low-pass filter A delay circuit in which the delay time of each of the delay elements can be varied according to the output of the first delay circuit, and the output of the last delay element of the plurality of delay elements is fed back to the second phase comparator as the feedback signal. And a multi-phase clock generated by the delay circuit,
The logic synthesis circuit is configured to fix the output terminal to a high level potential for a predetermined time in synchronization with a charge storage unit provided at an output terminal and one rising edge or falling edge of the multiphase clock. And a second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock.
[0018]
The invention according to claim 9 is the jitter reduction circuit according to any one of claims 1 to 8, wherein the logic synthesis circuit includes a plurality of the first switching elements and a plurality of the second switching elements connected in parallel. The first switching element and the second switching element are configured to be alternately conducted in synchronization with a rising edge or a falling edge of each phase of the multiphase clock.
[0019]
According to a tenth aspect of the present invention, in the jitter reduction circuit according to the ninth aspect, the first switching element includes first and second PMOS transistors connected in series between a power supply terminal and an output terminal. A first inverter that inverts any one of the multiphase clocks input to the gate of either of the PMOS transistors and outputs the inverted timing to the other gate by delaying the inversion timing by the predetermined time. The second switching element is input to a gate of either one of the first and second NMOS transistors connected in series between a ground terminal and an output terminal, and the two NMOS transistors. One of the multiphase clocks is inverted, and the inversion timing is delayed by the predetermined time and output to the other gate. It is characterized in that a second inverter.
[0020]
According to the jitter reduction circuit of the present invention having such a configuration, even when the frequency of the input signal is high, it is possible to use a voltage controlled crystal oscillator with high accuracy but low oscillation frequency. Production difficulty can be avoided and production costs can be reduced.
[0021]
In addition, when using an N multiplier circuit of a delay synchronization circuit system (DLL (delay locked loops) system) as a frequency multiplier circuit, it can be multiplied without degrading the low noise characteristics of the voltage controlled crystal oscillator circuit. A highly accurate output required as a jitter reduction circuit can be obtained.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
[1] First embodiment
The configuration of the first embodiment of the jitter reduction circuit of the present invention will be described below with reference to FIG.
As shown in FIG. 1, the jitter reduction circuit according to the first embodiment includes a phase comparator 1, a low-pass filter 2, a voltage control crystal oscillator 3, and a frequency multiplication circuit 4. 4 is taken out, and the output signal of the frequency multiplication circuit 4 is fed back to the input side of the phase comparator 1, thereby forming a feedback loop as a whole.
[0026]
The phase comparator 1 compares the phase of the reference clock, which is an input signal, with the phase of the output signal from the frequency multiplication circuit 4, and outputs an error signal corresponding to the phase difference.
The low-pass filter 2 is a filter that integrates and outputs the error signal output from the phase comparator 1.
The voltage controlled crystal oscillator 3 is an oscillator that oscillates at a predetermined frequency and whose oscillation frequency is controlled according to an output signal from the low-pass filter 2. This voltage controlled crystal oscillator 3 uses a crystal AT resonator, a crystal SAW resonator, a crystal SAW filter, or the like as its oscillation element.
[0027]
The frequency multiplying circuit 4 is a circuit that multiplies the frequency of the output of the voltage controlled crystal oscillator 3 by N (N times). For example, the frequency multiplying circuit 4 is an N of a delay synchronization circuit system (DLL (delay locked loops) system) as shown in FIG. A multiplier circuit is used.
Next, an operation example of the jitter reduction circuit according to the first embodiment having such a configuration will be described.
[0028]
In the phase comparator 1, the phase of the input reference clock and the output signal from the frequency multiplication circuit 4 are compared, and an error signal corresponding to the phase difference is output to the low-pass filter 2.
The error signal is integrated by the low-pass filter 2 and supplied to the voltage controlled crystal oscillator 3, and the oscillation frequency of the voltage controlled crystal oscillator 3 is controlled. The output of the voltage controlled crystal oscillator 3 is fed back to the input side of the phase comparator 1 after the frequency is multiplied by N by the frequency multiplication circuit 4.
[0029]
As a result, the operation is performed so that the phase of the input reference clock and the phase of the output signal of the frequency multiplication circuit 4 coincide. When the phase is synchronized, if the oscillation frequency of the voltage controlled crystal oscillator 3 is Fvcxo and the multiplication number (multiplication value) of the frequency multiplication circuit 4 is N, then Fvcxo = Fin / N.
For this reason, the jitter of the reference clock can be reduced, and the oscillation frequency required for the voltage controlled crystal oscillator 3 can be reduced to 1 / N of the conventional one.
[0030]
Next, as a specific example of the frequency multiplication circuit 4 shown in FIG. 1, the configuration of a DLL type N multiplication circuit will be described with reference to FIG.
As shown in FIG. 2, the N multiplier circuit includes a phase comparator 11, a low-pass filter 12, a delay circuit 13 including a plurality of delay elements, and a multiphase clock logic synthesis circuit 14, and includes a delay circuit. The output signal from the 13th stage delay element is fed back to the input side of the phase comparator 11.
[0031]
In the following example, the case where the multiplication number N of the N multiplication circuit is N = 5 will be described.
The phase comparator 11 receives the output signal of the voltage controlled crystal oscillator 3 shown in FIG. 1 as an input signal, and the input signal and the output signal from the delay element at the final stage of the delay circuit 13 are input. The phase is compared, and an error signal corresponding to the phase difference is output.
[0032]
The low-pass filter 12 includes a capacitor C1 and the like, and the capacitor C1 is charged or discharged according to an error signal output from the phase comparator 11.
For example, as shown in FIG. 3, the delay circuit 13 includes differential delay elements (delay cells) D1 to D10, and these delay elements D1 to D10 are connected in series. The output of the voltage controlled crystal oscillator 3 is inputted to the first-stage delay element D1. Accumulated charges (charge / discharge voltage Vc) of the capacitor C1 are supplied to the delay elements D1 to D10, whereby each delay time of the delay elements D1 to D10 can be controlled.
[0033]
Further, from the non-inverting output terminals of the delay elements D1 to D10, the clocks Ck1B, Ck2, Ck3B, Ck4, Ck5B,..., Whose output phase is delayed by 2π / 10 and inverted are extracted. The clock is supplied to the multiphase clock logic synthesis circuit 14. Further, the clock of the delay element D10 at the final stage is fed back to the input side of the phase comparator 11.
[0034]
Based on the clocks Ck1B, Ck2, Ck3B, Ck4, Ck5B,. It is a circuit that generates directly.
Next, an example of the operation of the DLL type N multiplying circuit having such a configuration will be described.
[0035]
The phase comparator 11 compares the phase of the output signal from the voltage controlled crystal oscillator 3 with the output signal from the delay element D10 in the final stage of the delay circuit 13, and outputs an error signal corresponding to the phase difference. The capacitor C1 is charged or discharged according to the error signal.
In the delay circuit 13, the output signal of the voltage controlled crystal oscillator 3 is sequentially delayed by the delay elements D 1 to D 10, and the output signal of the final stage delay element D 10 is fed back to the input side of the phase comparator 11. Further, the delay times of the delay elements D1 to D10 are controlled by the charge / discharge voltage Vc of the capacitor C1.
[0036]
Further, from the non-inverting output terminals of the delay elements D1 to D10, the clocks Ck1B, Ck2, Ck3B, Ck4, Ck5B,..., Whose output phase is delayed by 2π / 10 and inverted are extracted. The clock is supplied to the multiphase clock logic synthesis circuit 14. Further, the clock of the delay element D10 at the final stage is fed back to the input side of the phase comparator 11.
[0037]
In the multiphase clock logic synthesis circuit 14, based on the clocks Ck 1 B, Ck 2, Ck 3 B, Ck 4, Ck 5 B,... (Multiplication clock) is directly generated and output. This point will be described later.
As described above, according to the N-type multiplier circuit of the DLL system, the jitter characteristic of the input clock is reflected in the output as it is in principle, so that the high-precision output of the voltage-controlled crystal oscillator 3 is multiplied by N without impairing it. Output is obtained.
[0038]
Next, a specific example of the multiphase clock logic synthesis circuit 14 will be described with reference to FIG.
As shown in FIG. 4, the multiphase clock logic synthesis circuit 14 includes five circuit blocks 21 to 25 provided in parallel, and the output terminals 26 to 30 of the circuit blocks 21 to 25 are common. The output line 41 is connected to the output terminal 43 via the inverter 42. A parasitic capacitance C10 is present at the output terminals 26-30.
[0039]
More specifically, the circuit block 21 includes PMOS transistors P1 and P1 ′ connected in series between the power supply terminal VD and the output terminal 26, and NMOS transistors N1 connected in series between the output terminal 26 and the ground terminal. N1 ′. The input terminal 51 is directly connected to the gate of the PMOS transistor P1 and is connected to the gate of the PMOS transistor P1 ′ via the inverter 31. Further, the input terminal 52 is directly connected to the gate of the NMOS transistor N1 and is connected to the gate of the PMOS transistor N1 ′ via the inverter 32.
[0040]
Here, the clock Ck1B from the delay circuit 13 is input to the gate of the PMOS transistor P1, and the clock Ck1 ′ obtained by inverting the clock Ck1B by the inverter 31 is input to the gate of the PMOS transistor P1 ′. It has become.
The clock Ck2 from the delay circuit 13 is input to the gate of the NMOS transistor N1, and the clock Ck2B ′ obtained by inverting the clock Ck2 by the inverter 32 is input to the gate of the NMOS transistor N1 ′. ing.
[0041]
The circuit block 22 includes PMOS transistors P2 and P2 ′ connected in series between the power supply terminal VD and the output terminal 27, and NMOS transistors N2 and N2 ′ connected in series between the output terminal 27 and the ground terminal. ing. The input terminal 53 is directly connected to the gate of the PMOS transistor P2 and is connected to the gate of the PMOS transistor P2 ′ via the inverter 33. Further, the input terminal 54 is directly connected to the gate of the NMOS transistor N2 and is connected to the gate of the PMOS transistor N2 ′ via the inverter 34.
[0042]
Here, the clock Ck3B from the delay circuit 13 is input to the gate of the PMOS transistor P2, and the clock Ck3 ′ obtained by inverting the clock Ck3B by the inverter 33 is input to the gate of the PMOS transistor P2 ′. It has become.
The clock Ck4 from the delay circuit 13 is input to the gate of the NMOS transistor N2, and the clock Ck4B ′ obtained by inverting the clock Ck4 by the inverter 34 is input to the gate of the NMOS transistor N2 ′. ing.
[0043]
The circuit block 23 includes PMOS transistors P3 and P3 ′ connected in series between the power supply terminal VD and the output terminal 28, and NMOS transistors N3 and N3 ′ connected in series between the output terminal 28 and the ground terminal. ing. The input terminal 55 is directly connected to the gate of the PMOS transistor P3 and is connected to the gate of the PMOS transistor P3 ′ via the inverter 35. Further, the input terminal 56 is directly connected to the gate of the NMOS transistor N3 and is connected to the gate of the PMOS transistor N3 ′ via the inverter 36.
[0044]
Here, the clock Ck5B from the delay circuit 13 is input to the gate of the PMOS transistor P3, and the clock Ck5 ′ obtained by inverting the clock Ck5B by the inverter 35 is input to the gate of the PMOS transistor P3 ′. It has become.
The clock Ck6 from the delay circuit 13 is input to the gate of the NMOS transistor N3, and the clock Ck6B ′ obtained by inverting the clock Ck6 by the inverter 36 is input to the gate of the NMOS transistor N3 ′. ing.
[0045]
The circuit block 24 includes PMOS transistors P4 and P4 ′ connected in series between the power supply terminal VD and the output terminal 29, and NMOS transistors N4 and N4 ′ connected in series between the output terminal 29 and the ground terminal. ing. The input terminal 57 is directly connected to the gate of the PMOS transistor P4 and is connected to the gate of the PMOS transistor P4 ′ via the inverter 37. Further, the input terminal 58 is directly connected to the gate of the NMOS transistor N4, and is connected to the gate of the PMOS transistor N4 ′ via the inverter 38.
[0046]
Here, the clock Ck7B from the delay circuit 13 is input to the gate of the PMOS transistor P4, and the clock Ck7 ′ obtained by inverting the clock Ck7B by the inverter 37 is input to the gate of the PMOS transistor P4 ′. It has become.
The clock Ck8 from the delay circuit 13 is input to the gate of the NMOS transistor N4, and the clock Ck8B ′ obtained by inverting the clock Ck8 by the inverter 38 is input to the gate of the NMOS transistor N4 ′. ing.
[0047]
The circuit block 25 includes PMOS transistors P5 and P5 ′ connected in series between the power supply terminal VD and the output terminal 30, and NMOS transistors N5 and N5 ′ connected in series between the output terminal 30 and the ground terminal. ing. The input terminal 59 is directly connected to the gate of the PMOS transistor P5 and is connected to the gate of the PMOS transistor P5 ′ via the inverter 39. Further, the input terminal 60 is directly connected to the gate of the NMOS transistor N5 and is connected to the gate of the NMOS transistor N5 ′ via the inverter 40.
[0048]
Here, the clock Ck9B from the delay circuit 13 is input to the gate of the PMOS transistor P5, and the clock Ck9 ′ obtained by inverting the clock Ck9B by the inverter 39 is input to the gate of the PMOS transistor P5 ′. It has become.
The clock Ck10 from the delay circuit 13 is input to the gate of the NMOS transistor N5, and the clock Ck10B ′ obtained by inverting the clock Ck10 by the inverter 40 is input to the gate of the NMOS transistor N5 ′. ing.
[0049]
Here, the inverters 31 to 40 are for inverting the input signal and securing a minimum delay time of the input signal that is required at the minimum. In order to secure the necessary delay time, the inverters 31 to 40 are used. Is designed with a deliberate drop in drive capability.
In the example of FIG. 4, the inverters 31 to 40 are provided at the gates of the PMOS transistors P1 ′ to P5 ′ and the NMOS transistors N1 ′ to N5 ′, respectively, but instead, the PMOS transistors P1 to P5 and Inverters 31 to 40 may be provided at the gates of the NMOS transistors N1 to N5, respectively.
[0050]
Next, an operation example of the multiphase clock logic synthesis circuit 14 having such a configuration will be described with reference to the time chart of FIG.
In the following description, it is assumed that t is set for each delay time of the inverters 31 to 40.
When the clock Ck1 rises at time t1 in FIG. 5 (that is, when the clock Ck1B changes from “L” level (low level) to “H” level (high level)), the inverted clock Ck1B falls (ie, , “H” level is changed to “L” level). Since the clock Ck1B is input to the gate of the PMOS transistor P1, the PMOS transistor P1 is turned on.
[0051]
On the other hand, the clock Ck1 ′ obtained by inverting the clock Ck1B by the inverter 31 is input to the gate of the PMOS transistor P1 ′. For this reason, the clock Ck1 ′ falls after a delay time from the fall time t1 of the clock Ck1B, so that the clock Ck1 ′ remains at the “L” level at the time t1.
[0052]
As a result, at time t1, the PMOS transistor P1 is turned on, but the PMOS transistor P1 ′ is kept on, so that the output potential OUTB of the output terminal 26 is at the “H” level.
On the other hand, at the time t1, the level of the clock Ck2 is in a steady state, and at least one of the NMOS transistors N1 and N1 ′ is turned off, so that the output terminal 26 is cut off from the “L” level.
[0053]
As a result, the output OUTB of the output terminal 26 of the circuit block 21 changes to the “H” level.
At time t1, the clocks input to the other circuit blocks 22 to 25 are in a steady state except for the clock Ck6 as shown in FIG. 5, and the clock Ck6B ′ obtained by inverting the clock Ck6 is at the “L” level. Therefore, the NMOS transistor N3 ′ is off.
[0054]
For this reason, at time t1, the output terminals 27 to 30 of the other circuit blocks 22 to 25 are not in the “H” level or the “L” level, and are in a floating state.
As a result, even when the output terminals 26 to 30 of the circuit blocks 21 to 25 are commonly connected, the output of the output terminal 26 of the circuit block 21 interferes with the outputs of the other circuit blocks 22 to 25 at time t1. Can be prevented.
[0055]
Therefore, at time t1, the output OUTB of the entire circuit blocks 21 to 25 is defined by the output from the output terminal 26 of the circuit block 21, and the level of the output terminal 26 of the circuit block 21 is inverted by the inverter 42 and multiplied. The clock OUT changes from “H” level to “L” level.
Next, at time t2 when the delay time t has elapsed from time t1, the clock signal Ck1 ′ delayed by the inverter 31 rises, and the gate of the PMOS transistor P1 ′ becomes “H” level, so that the PMOS transistor P1 ′. Turns off.
[0056]
As a result, the output terminal 26 is cut off from the “H” level potential, and the output terminal 26 enters a floating state (indicated by Z in FIG. 5).
Here, the parasitic capacitance C10 exists in the output terminal 26, and even when the output terminal 26 is in a floating state, the output OUTB of the entire circuit blocks 21 to 25 is “H” by the charge holding action of the parasitic capacitance C10. The “multiplied clock OUT” can maintain the “L” level.
[0057]
Next, at time t3, the clock Ck2 rises and the clock signal Ck2 is input to the gate of the NMOS transistor N1, so that the NMOS transistor N1 is turned on.
On the other hand, a clock Ck2B ′ obtained by inverting the clock signal Ck2 by the inverter 32 is input to the gate of the NMOS transistor N1 ′. For this reason, the clock Ck2B ′ falls after a delay time t from the rising time t3 of the clock Ck2, so that the gate of the NMOS transistor N1 ′ remains at the “H” level at the time t3.
[0058]
As a result, at time t3, the NMOS transistor N1 is turned on and the on state of the NMOS transistor N1 ′ is maintained as it is, and the output terminal 26 becomes the “L” level potential.
On the other hand, at time t3, the level of the clock signal Ck1 is in a steady state, and at least one of the PMOS transistors P1 and P1 ′ is turned off, so that the output terminal 26 is cut off from the “H” level potential.
[0059]
As a result, the output terminal 26 of the circuit block 21 changes to the “L” level.
At time t3, the clocks of the other circuit blocks 22 to 25 are in a steady state except for the clock Ck7B, and at time t3, the level of the clock Ck4 ′ obtained by inverting the clock signal Ck7B is high. The PMOS transistor P4 ′ is off.
[0060]
For this reason, at time t3, the output terminals 27 to 30 of the other circuit blocks 22 to 25 are cut off from both the “H” level and “L” level potentials and are in a floating state.
As a result, even when the output terminals 26 to 29 of the circuit blocks 21 to 25 are connected in common, the output of the output terminal 26 of the circuit block 21 interferes with the outputs of the other circuit blocks 22 to 25 at time t3. Can be prevented.
[0061]
Therefore, at time t3, the output OUTB of the entire circuit blocks 21 to 25 is defined by the output from the output terminal 26 of the circuit block 21, and the level of the output terminal 26 of the circuit block 21 is inverted by the inverter 42 and multiplied. The clock OUT changes from “L” level to “H” level.
Next, at time t4 when the delay time t has elapsed from time t3, the clock Ck2B ′ delayed by the inverter 32 falls and the gate of the NMOS transistor N1 ′ becomes “L” level, so that the NMOS transistor N1 ′. Turns off.
[0062]
As a result, the output terminal 26 is cut off from the “L” level potential, and the output terminal 26 enters a floating state (indicated by Z in FIG. 5).
Here, the parasitic capacitance C10 exists in the output terminal 26, and even when the output terminal 26 is in a floating state, the output OUTB of the entire circuit blocks 21 to 25 is “L” due to the charge holding action of the parasitic capacitance C10. The “multiplied clock OUT” can maintain the “H” level.
[0063]
Thereafter, the same operation is repeated by the circuit blocks 21 to 25 for the other clocks Ck3 to Ck10.
Therefore, the multiplied clock OUT repeats the state transition between the “H” level and the “L” level each time the multiphase clocks Ck1 to Ck10 sequentially rise, and has a frequency five times that of the multiphase clocks Ck1 to Ck10. A multiplied clock OUT can be generated.
[0064]
Thus, after the level change of the output terminals 26-30 of the circuit blocks 21-25, the output terminals 26-30 of the circuit blocks 21-25 are connected in common by bringing the output terminals 26-30 into a floating state. Even in the case, the output of each circuit block 21-25 can be made the output of the whole circuit block 21-25, preventing the output interference between each circuit block 21-25.
[0065]
As a result, even when the number of phases of the multiphase clock increases, a multiplied clock can be generated by simply connecting the circuit blocks 21 to 25 in parallel, and the outputs from the circuit blocks 21 to 25 are synthesized. Therefore, it is not necessary to use a multi-input OR circuit.
For this reason, even when the number of phases of the multi-phase clock increases, it is not necessary to increase the number of transistors connected in series, so that the frequency of the clock can be increased using a low-voltage IC process.
[0066]
In addition, even when the number of phases of the multiphase clock increases, the circuit blocks 21 to 25 need only be connected in parallel, and the symmetrical structure of each input terminal can be maintained. The frequency of the clock can be increased while suppressing.
Further, since it is possible to directly generate the multiplied clock OUT using only the rising edges of the multiphase clocks Ck1 to Ck10, RS for generating non-overlapping pulses from the multiphase clocks Ck1 to Ck10. No flip-flop is required.
[0067]
For this reason, even when the number of input terminals of the multiphase clocks Ck1 to Ck10 is increased, it is possible to suppress an increase in circuit scale and suppress an increase in chip area and power consumption, and the multiphase clocks Ck1 to Ck1. Jitter can be suppressed by reducing the mismatch of the circuit blocks 21 to 25 between the phases of Ck10.
Further, by generating the multiplied clock OUT using only the rising edges of the multiphase clocks Ck1 to Ck10, even when the duty ratio of the multiphase clocks Ck1 to Ck10 deviates from 50%, the duty ratio of the multiplied clock OUT Can be maintained at 50%, and the duty ratio of the multiplied clock OUT can be less than 0% or more than 100%, thereby preventing pulses from being lost.
[0068]
In addition, when the output terminals 26 to 30 of the circuit blocks 21 to 25 are connected in common, in order to prevent output interference between the circuit blocks 21 to 25, each delay amount t of the inverters 31 to 40 is set to a multiphase clock. It is necessary to set it to be smaller than the phase shift amount (π / N).
[2] Second embodiment
Next, the configuration of the second embodiment of the jitter reduction circuit of the present invention will be described with reference to FIG.
[0069]
As shown in FIG. 6, the jitter reduction circuit according to the second embodiment includes a phase comparator 1, a low-pass filter 2, a voltage controlled crystal oscillator 3, a frequency multiplication circuit 4, and a frequency divider 5. The output signal of the frequency multiplier 4 is taken out, and the output of the frequency divider 5 is fed back to the input side of the phase comparator 1, thereby forming a feedback loop as a whole.
[0070]
The phase comparator 1 compares the phase of the reference clock, which is an input signal, with the output signal from the frequency divider 5, and outputs an error signal corresponding to the phase difference.
The low-pass filter 2 is a filter that integrates and outputs the error signal output from the phase comparator 1.
The voltage controlled crystal oscillator 3 is an oscillator that oscillates at a predetermined frequency and whose oscillation frequency is controlled according to an output signal from the low-pass filter 2. This voltage controlled crystal oscillator 3 uses a crystal AT resonator, a crystal SAW resonator, a crystal SAW filter, or the like as its oscillation element.
[0071]
The frequency multiplication circuit 4 is a circuit that multiplies the output frequency of the voltage controlled crystal oscillator 3 by N (N times). For example, a DLL type N multiplication circuit as shown in FIG. 2 is used.
The frequency divider 5 divides the frequency of the output signal of the frequency multiplication circuit 4 by 1 / M, and the frequency-divided output signal is fed back to the phase comparator 1.
[0072]
Next, an operation example of the jitter reduction circuit according to the second embodiment having such a configuration will be described.
In the phase comparator 1, the phase of the output signal from the reference clock and the frequency divider 5 is compared, and an error signal corresponding to the phase difference is output to the low-pass filter 2.
The error signal is integrated by the low-pass filter 2 and supplied to the voltage controlled crystal oscillator 3, and the oscillation frequency of the voltage controlled crystal oscillator 3 is controlled. The frequency of the output of the voltage controlled crystal oscillator 3 is multiplied by N by the frequency multiplying circuit 4, then divided by 1 / M by the frequency divider 5 and fed back to the phase comparator 1.
[0073]
As a result, the operation is performed so that the phase of the input reference clock matches the phase of the output signal of the frequency divider 5. When the phase is synchronized, assuming that the oscillation frequency of the voltage controlled crystal oscillator 3 is Fvcxo, the frequency multiplier 4 is N, and the frequency divider 5 is 1 / M, Fin = Fvcxo × (N / M). At this time, the output frequency Fout is Fout = Fvcxo × N = Fin × M.
[0074]
For this reason, the jitter of the reference clock can be reduced, an output M times the input frequency Fin can be obtained, the frequency multiplication function can be obtained, and the oscillation frequency required for the voltage controlled crystal oscillator 3 can be reduced to the conventional 1 / N. Can be.
[3] Third embodiment
Next, the configuration of the third embodiment of the jitter reduction circuit of the present invention will be described with reference to FIG.
[0075]
As shown in FIG. 7, the jitter reduction circuit according to the third embodiment includes a frequency divider 6, a phase comparator 1, a low-pass filter 2, a voltage controlled crystal oscillator 3, and a frequency multiplication circuit 4. And the output signal of the frequency multiplier 4 is fed back to the input side of the phase comparator 1, thereby forming a feedback loop as a whole.
[0076]
The frequency divider 6 divides the frequency Fin of the reference clock as an input signal by 1 / L, and the frequency-divided reference clock is output to the phase comparator 1.
The phase comparator 1 compares the divided reference clock with the phase of the output signal from the frequency multiplication circuit 4 and outputs an error signal corresponding to the phase difference.
[0077]
The low-pass filter 2 is a filter that integrates and outputs the error signal output from the phase comparator 1.
The voltage controlled crystal oscillator 3 is an oscillator that oscillates at a predetermined frequency and whose oscillation frequency is controlled according to an output signal from the low-pass filter 2. This voltage controlled crystal oscillator 3 uses a crystal AT resonator, a crystal SAW resonator, a crystal SAW filter, or the like as its oscillation element.
[0078]
The frequency multiplication circuit 4 is a circuit that multiplies the output frequency of the voltage controlled crystal oscillator 3 by N (N times). For example, a DLL type N multiplication circuit as shown in FIG. 2 is used.
Next, an operation example of the jitter reduction circuit according to the third embodiment having such a configuration will be described.
[0079]
In the frequency divider 6, the frequency Fin of the inputted reference clock is divided by 1 / L, and this divided reference clock is inputted to the phase comparator 1. In the phase comparator 1, the phase of the divided reference clock and the output of the frequency multiplication circuit 4 are compared, and an error signal corresponding to the phase difference is output to the low-pass filter 2.
The error signal is integrated by the low-pass filter 2 and supplied to the voltage controlled crystal oscillator 3, and the oscillation frequency of the voltage controlled crystal oscillator 3 is controlled. The frequency of the output of the voltage controlled crystal oscillator 3 is multiplied by N by the frequency multiplication circuit 4.
[0080]
As a result, the operation is performed so that the phase of the output signal from the frequency divider 6 and the phase of the output signal from the frequency multiplication circuit 4 coincide. When the phase is synchronized, the frequency of the input reference clock is Fin, the frequency division value of the frequency divider 6 is 1 / L, the oscillation frequency of the voltage controlled crystal oscillator 3 is Fvcxo, and the frequency multiplication circuit 4 is multiplied by the frequency. When N, Fin / L = Fvcxo × N. At this time, the output frequency Fout is Fout = Fvcxo × N = Fin / L.
[0081]
Therefore, the jitter of the reference clock can be reduced, an output M times the input frequency Fin can be obtained, the frequency multiplication function can be obtained, and the oscillation frequency required for the voltage controlled crystal oscillator 3 can be reduced to the conventional 1 / ( L × N).
[4] Fourth embodiment
Next, the configuration of the fourth embodiment of the jitter reduction circuit of the present invention will be described with reference to FIG.
[0082]
As shown in FIG. 8, the jitter reduction circuit according to the fourth embodiment includes a frequency divider 6, a phase comparator 1, a low-pass filter 2, a voltage controlled crystal oscillator 3, and a frequency multiplication circuit 4. The frequency divider 5 is provided, the output signal of the frequency multiplier 4 is taken out, and the output signal of the frequency divider 5 is fed back to the input side of the phase comparator 1, thereby forming a feedback loop as a whole. .
[0083]
The frequency divider 6 divides the frequency Fin of the reference clock as an input signal by 1 / L, and the frequency-divided reference clock is output to the phase comparator 1.
The phase comparator 1 compares the phase of the reference clock divided by the frequency divider 6 and the output signal from the frequency divider 5 and outputs an error signal corresponding to the phase difference.
[0084]
The low-pass filter 2 is a filter that integrates and outputs the error signal output from the phase comparator 1.
The voltage controlled crystal oscillator 3 is an oscillator that oscillates at a predetermined frequency and whose oscillation frequency is controlled according to an output signal from the low-pass filter 2. This voltage controlled crystal oscillator 3 uses a crystal AT resonator, a crystal SAW resonator, a crystal SAW filter, or the like as its oscillation element.
[0085]
The frequency multiplication circuit 4 is a circuit that multiplies the output frequency of the voltage controlled crystal oscillator 3 by N. For example, a DLL type N multiplication circuit as shown in FIG. 2 is used.
The frequency divider 5 divides the frequency of the output signal of the frequency multiplication circuit 4 by 1 / M, and the divided output signal is fed back to the input side of the phase comparator 1. Yes.
[0086]
Next, an operation example of the jitter reduction circuit according to the fourth embodiment having such a configuration will be described.
In the frequency divider 6, the frequency Fin of the inputted reference clock is divided by 1 / L, and this divided reference clock is inputted to the phase comparator 1. In the phase comparator 1, the phase of the divided reference clock and the output of the frequency divider 5 are compared, and an error signal corresponding to the phase difference is output to the low-pass filter 2.
The error signal is integrated by the low-pass filter 2 and supplied to the voltage controlled crystal oscillator 3, and the oscillation frequency of the voltage controlled crystal oscillator 3 is controlled. The frequency of the output of the voltage controlled crystal oscillator 3 is multiplied by N by the frequency multiplication circuit 4. The signal multiplied by N is frequency-divided to 1 / M by the frequency divider 5 and fed back to the input side of the phase comparator 1.
[0087]
As a result, the operation is performed so that the phase of the output signal from the frequency divider 6 matches the phase of the output signal from the frequency divider 5. When the phase is synchronized, the frequency of the input reference clock is Fin, the frequency division value of the frequency divider 6 is 1 / L, the oscillation frequency of the voltage controlled crystal oscillator 3 is Fvcxo, and the frequency multiplication circuit 4 is multiplied by the frequency. N, Fin / L = Fvcxo × N × (1 / M) where 1 / M is the frequency division value of the frequency divider 6. At this time, the output frequency Fout is Fout = Fvcxo × N = Fin × (M / L).
[0088]
For this reason, the jitter of the reference clock can be reduced, the output of (M / L) times the input frequency Fin is obtained, the frequency multiplication function is provided, and the oscillation frequency necessary for the voltage controlled crystal oscillator 3 is conventionally obtained. 1 / N.
[5] Fifth embodiment
Next, an embodiment in which the jitter reduction circuit of the present invention is applied to the electronic apparatus of the present invention will be described with reference to FIG.
[0089]
As shown in FIG. 9, the communication device according to this embodiment includes a data transmission unit 61 that transmits data, a data reception unit 62 that receives data, and a data transmission unit 61 that is used when data is transmitted. The receiving unit 62 includes a jitter reduction circuit 63 that reduces jitter of a clock to be used when receiving data.
Here, the jitter reduction circuit 63 uses each jitter reduction circuit as shown in FIG. 1, FIG. 6, FIG. 7, or FIG.
[0090]
In the communication device having such a configuration, for example, when a jitter is included in a reference clock (RefClock) supplied from the outside, the reference clock is input to the jitter reduction circuit 63. Thereby, a reference clock with reduced jitter is obtained from the jitter reduction circuit 63, and the reference clock is supplied to the data transmission unit 61 and the data reception unit 62, respectively.
[0091]
Therefore, according to the communication device according to the embodiment, the accuracy of the reference clock used for each data processing at the time of data transmission by the data transmission unit 61 or at the time of data reception by the data reception unit 62 becomes high, and errors at the time of transmission / reception are reduced. Can be reduced.
[Modification of Embodiment]
Next, a modified example of the configuration of the jitter reduction circuit described in the embodiment will be described.
[0092]
In the jitter reduction circuit described in each of the above embodiments, a voltage controlled crystal oscillator using a crystal AT resonator, a crystal SAW resonator, a crystal SAW filter, or the like is used as an oscillation element. A SAW resonator or SAW filter using a piezoelectric material other than the above may be replaced with a voltage-controlled piezoelectric oscillator used as an oscillation element. Examples of the piezoelectric material include langasite, LBO (Lithium Tetraborate), and piezoelectric film-forming diamond. According to the above configuration, it is possible to realize a jitter reduction circuit that is superior in terms of high-frequency operation, temperature stability, and the like as compared with the above-described embodiment.
[0093]
【The invention's effect】
As described above, according to the jitter reduction circuit of the present invention, even when the frequency of the input signal is high, it is possible to use a voltage controlled crystal oscillator with high accuracy but low oscillation frequency. Production difficulty can be avoided and production costs can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment of a jitter reduction circuit of the present invention.
FIG. 2 is a block diagram illustrating an example of a frequency multiplication circuit.
FIG. 3 is a circuit diagram showing an example of a delay circuit.
FIG. 4 is a circuit diagram showing an example of a multiphase clock logic synthesis circuit.
FIG. 5 is a time chart for explaining an operation example of the multiphase clock logic synthesis circuit;
FIG. 6 is a block diagram showing a configuration of a second embodiment of the jitter reduction circuit of the present invention.
FIG. 7 is a block diagram showing a configuration of a third embodiment of a jitter reduction circuit of the present invention.
FIG. 8 is a block diagram showing a configuration of a fourth embodiment of a jitter reduction circuit of the present invention.
FIG. 9 is a block diagram illustrating a configuration of an electronic device according to an embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration of a conventional jitter reduction circuit.
[Explanation of symbols]
1 is a phase comparator, 2 is a low-pass filter, 3 is a voltage controlled crystal oscillator, 4 is a frequency multiplier circuit, 5 and 6 are frequency dividers, 11 is a phase comparator, 12 is a low-pass filter, and 13 is a delay. Circuit, 14 is a multi-phase clock logic synthesis circuit, 21 to 25 are circuit blocks, 26 to 30 are output terminals, 31 to 40 are inverters, 61 is a data transmission unit, 62 is a data reception unit, and 63 is a jitter reduction circuit. .

Claims (10)

A phase comparator that compares the phase of the input signal and the feedback signal and outputs an error signal according to the phase difference;
A low-pass filter for integrating the error signal output from the phase comparator;
A voltage-controlled crystal oscillator whose oscillation frequency changes according to the output of the low-pass filter;
A frequency multiplication circuit for multiplying the frequency of the output of the voltage controlled crystal oscillator to an arbitrary value,
The output of the frequency multiplication circuit is fed back to the phase comparator as the feedback signal, and the output of the frequency multiplication circuit is taken out.
The frequency multiplier circuit is:
A delay synchronization circuit for generating a multi-phase clock based on the output of the voltage controlled crystal oscillator;
A logic synthesis circuit that generates a multiplied clock based on the multiphase clock generated by the delay synchronization circuit;
The logic synthesis circuit is
A charge storage section provided at the output terminal;
A first switching element that fixes the output terminal at a high level potential for a predetermined time in synchronization with a rising edge or a falling edge of any one of the multiphase clocks;
A second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock;
A jitter reduction circuit comprising: A phase comparator that compares the phase of the input signal and the feedback signal and outputs an error signal according to the phase difference;
A low-pass filter for integrating the error signal output from the phase comparator;
A voltage-controlled crystal oscillator whose oscillation frequency changes according to the output of the low-pass filter;
A frequency multiplier for multiplying the frequency of the output of the voltage controlled crystal oscillator to an arbitrary value;
A frequency divider for dividing the output of the frequency multiplier circuit;
The output of the frequency divider is fed back to the phase comparator as the feedback signal, and the output of the frequency multiplication circuit is extracted,
The frequency multiplier circuit is:
A delay synchronization circuit for generating a multi-phase clock based on the output of the voltage controlled crystal oscillator;
A logic synthesis circuit that generates a multiplied clock based on the multiphase clock generated by the delay synchronization circuit;
The logic synthesis circuit is
A charge storage section provided at the output terminal;
A first switching element that fixes the output terminal at a high level potential for a predetermined time in synchronization with a rising edge or a falling edge of any one of the multiphase clocks;
A second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock;
A jitter reduction circuit comprising: A frequency divider for dividing the input signal;
A phase comparator that compares the phase of the output signal of the frequency divider and the feedback signal and outputs an error signal according to the phase difference;
A low-pass filter for integrating the error signal output from the phase comparator;
A voltage-controlled crystal oscillator whose oscillation frequency changes according to the output of the low-pass filter;
A frequency multiplication circuit for multiplying the frequency of the output of the voltage controlled crystal oscillator to an arbitrary value,
The output of the frequency multiplication circuit is fed back to the phase comparator as the feedback signal, and the output of the frequency multiplication circuit is taken out.
The frequency multiplier circuit is:
A delay synchronization circuit for generating a multi-phase clock based on the output of the voltage controlled crystal oscillator;
A logic synthesis circuit that generates a multiplied clock based on the multiphase clock generated by the delay synchronization circuit;
The logic synthesis circuit is
A charge storage section provided at the output terminal;
A first switching element that fixes the output terminal at a high level potential for a predetermined time in synchronization with a rising edge or a falling edge of any one of the multiphase clocks;
A second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock;
A jitter reduction circuit comprising: A first divider for dividing the input signal;
A phase comparator that compares the phase of the output signal of the first frequency divider and the feedback signal and outputs an error signal according to the phase difference;
A low-pass filter for integrating the error signal output from the phase comparator;
A voltage-controlled crystal oscillator whose oscillation frequency changes according to the output of the low-pass filter;
A frequency multiplier for multiplying the frequency of the output of the voltage controlled crystal oscillator to an arbitrary value;
A second divider for dividing the output of the frequency multiplier circuit;
The output of the second frequency divider is fed back to the phase comparator as the feedback signal, and the output of the frequency multiplication circuit is extracted,
The frequency multiplier circuit is:
A delay synchronization circuit for generating a multi-phase clock based on the output of the voltage controlled crystal oscillator;
A logic synthesis circuit that generates a multiplied clock based on the multiphase clock generated by the delay synchronization circuit;
The logic synthesis circuit is
A charge storage section provided at the output terminal;
A first switching element that fixes the output terminal at a high level potential for a predetermined time in synchronization with a rising edge or a falling edge of any one of the multiphase clocks;
A second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock;
A jitter reduction circuit comprising: A first phase comparator that compares the phase of the input signal and the feedback signal and outputs an error signal according to the phase difference;
A first low-pass filter for integrating the error signal output from the first phase comparator;
A voltage controlled crystal oscillator whose oscillation frequency changes according to the output of the first low-pass filter;
A frequency multiplication circuit for multiplying the frequency of the output of the voltage controlled crystal oscillator to an arbitrary value,
The output of the frequency multiplication circuit is fed back to the first phase comparator as the feedback signal, and the output of the frequency multiplication circuit is extracted.
The frequency multiplier circuit is:
A delay synchronization circuit for generating a multi-phase clock based on the output of the voltage controlled crystal oscillator;
A logic synthesis circuit that generates a multiplied clock based on the multiphase clock generated by the delay synchronization circuit;
The delay synchronization circuit includes:
A second phase comparator that compares the phase of the output signal of the voltage controlled crystal oscillator and the phase of the feedback signal and outputs an error signal according to the phase difference;
A second low-pass filter for integrating the error signal output from the second phase comparator;
The delay circuit includes a plurality of delay elements, and sequentially delays the output signal of the voltage controlled crystal oscillator to generate a multiphase clock, and the delay time of each delay element is variable according to the output of the second low-pass filter. A delay circuit,
The output of the delay element in the final stage of the plurality of delay elements is fed back to the second phase comparator as the feedback signal, and the multiphase clock generated by the delay circuit is extracted.
The logic synthesis circuit is
A charge storage section provided at the output terminal;
A first switching element that fixes the output terminal at a high level potential for a predetermined time in synchronization with a rising edge or a falling edge of any one of the multiphase clocks;
A second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock;
A jitter reduction circuit comprising: A first phase comparator that compares the phase of the input signal and the feedback signal and outputs an error signal according to the phase difference;
A first low-pass filter for integrating the error signal output from the first phase comparator;
A voltage controlled crystal oscillator whose oscillation frequency changes according to the output of the first low-pass filter;
A frequency multiplier for multiplying the frequency of the output of the voltage controlled crystal oscillator to an arbitrary value;
A frequency divider for dividing the output of the frequency multiplier circuit;
The output of the frequency divider is fed back to the first phase comparator as the feedback signal, and the output of the frequency multiplication circuit is taken out.
The frequency multiplier circuit is:
A delay synchronization circuit for generating a multi-phase clock based on the output of the voltage controlled crystal oscillator;
A logic synthesis circuit that generates a multiplied clock based on the multiphase clock generated by the delay synchronization circuit;
The delay synchronization circuit includes:
A second phase comparator that compares the phase of the output signal of the voltage controlled crystal oscillator and the phase of the feedback signal and outputs an error signal according to the phase difference;
A second low-pass filter for integrating the error signal output from the second phase comparator;
The delay circuit includes a plurality of delay elements, and sequentially delays the output signal of the voltage controlled crystal oscillator to generate a multiphase clock, and the delay time of each delay element is variable according to the output of the second low-pass filter. A delay circuit,
The output of the delay element in the final stage of the plurality of delay elements is fed back to the second phase comparator as the feedback signal, and the multiphase clock generated by the delay circuit is extracted.
The logic synthesis circuit is
A charge storage section provided at the output terminal;
A first switching element that fixes the output terminal at a high level potential for a predetermined time in synchronization with a rising edge or a falling edge of any one of the multiphase clocks;
A second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock;
A jitter reduction circuit comprising: A frequency divider for dividing the input signal;
A first phase comparator that compares the phase of the output signal of the frequency divider and the feedback signal and outputs an error signal according to the phase difference;
A first low-pass filter for integrating the error signal output from the first phase comparator;
A voltage controlled crystal oscillator whose oscillation frequency changes according to the output of the first low-pass filter;
A frequency multiplication circuit for multiplying the frequency of the output of the voltage controlled crystal oscillator to an arbitrary value,
The output of the frequency multiplication circuit is fed back to the first phase comparator as the feedback signal, and the output of the frequency multiplication circuit is extracted.
The frequency multiplier circuit is:
A delay synchronization circuit for generating a multi-phase clock based on the output of the voltage controlled crystal oscillator;
A logic synthesis circuit that generates a multiplied clock based on the multiphase clock generated by the delay synchronization circuit;
The delay synchronization circuit includes:
A second phase comparator that compares the phase of the output signal of the voltage controlled crystal oscillator and the phase of the feedback signal and outputs an error signal according to the phase difference;
A second low-pass filter for integrating the error signal output from the second phase comparator;
The delay circuit includes a plurality of delay elements, and sequentially delays the output signal of the voltage controlled crystal oscillator to generate a multiphase clock, and the delay time of each delay element is variable according to the output of the second low-pass filter. A delay circuit,
The output of the delay element in the final stage of the plurality of delay elements is fed back to the second phase comparator as the feedback signal, and the multiphase clock generated by the delay circuit is extracted.
The logic synthesis circuit is
A charge storage section provided at the output terminal;
A first switching element that fixes the output terminal at a high level potential for a predetermined time in synchronization with a rising edge or a falling edge of any one of the multiphase clocks;
A second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock;
A jitter reduction circuit comprising: A first divider for dividing the input signal;
A first phase comparator that compares the phase of the output signal of the first frequency divider and the phase of the feedback signal and outputs an error signal in accordance with the phase difference;
A first low-pass filter for integrating the error signal output from the first phase comparator;
A voltage controlled crystal oscillator whose oscillation frequency changes according to the output of the first low-pass filter;
A frequency multiplier for multiplying the frequency of the output of the voltage controlled crystal oscillator to an arbitrary value;
A second divider for dividing the output of the frequency multiplier circuit;
The output of the second frequency divider is fed back to the first phase comparator as the feedback signal, and the output of the frequency multiplication circuit is taken out.
The frequency multiplier circuit is:
A delay synchronization circuit for generating a multi-phase clock based on the output of the voltage controlled crystal oscillator;
A logic synthesis circuit that generates a multiplied clock based on the multiphase clock generated by the delay synchronization circuit;
The delay synchronization circuit includes:
A second phase comparator that compares the phase of the output signal of the voltage controlled crystal oscillator and the phase of the feedback signal and outputs an error signal according to the phase difference;
A second low-pass filter for integrating the error signal output from the second phase comparator;
The delay circuit includes a plurality of delay elements, and sequentially delays the output signal of the voltage controlled crystal oscillator to generate a multiphase clock, and the delay time of each delay element is variable according to the output of the second low-pass filter. A delay circuit,
The output of the delay element in the final stage of the plurality of delay elements is fed back to the second phase comparator as the feedback signal, and the multiphase clock generated by the delay circuit is extracted.
The logic synthesis circuit is
A charge storage section provided at the output terminal;
A first switching element that fixes the output terminal at a high level potential for a predetermined time in synchronization with a rising edge or a falling edge of any one of the multiphase clocks;
A second switching element that fixes the output terminal at a low level potential for a predetermined time in synchronization with another rising edge or falling edge of the multiphase clock;
A jitter reduction circuit comprising: The logic synthesis circuit is
A plurality of the first switching elements and the second switching elements are connected in parallel,
The first switching element and the second switching element are configured to be alternately conducted in synchronization with a rising edge or a falling edge of each phase of the multiphase clock. The jitter reduction circuit according to claim 8. The first switching element includes:
First and second PMOS transistors connected in series between a power supply terminal and an output terminal;
A first inverter that inverts any one of the multi-phase clocks input to one of the PMOS transistors and delays the inversion timing by the predetermined time and outputs the inverted signal to the other gate; With
The second switching element is
First and second NMOS transistors connected in series between a ground terminal and an output terminal;
A second inverter that inverts any one of the multiphase clocks input to one of the NMOS transistors and delays the inversion timing by the predetermined time and outputs the inverted signal to the other gate; The jitter reduction circuit according to claim 9, further comprising:

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