JP3999943B2 - Multi-bank access control device and multi-bank access control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multi-bank access control apparatus and a multi-bank access control method for controlling access to a plurality of memory banks accessed in common by a plurality of processors or a plurality of threads.
[0002]
[Prior art]
In a multiprocessor system, a memory accessed from a plurality of processors generally accesses a plurality of banks simultaneously for speeding up. For example, when a memory is accessed from a certain processor, the access from the processor is divided into accesses to each bank, and each bank is accessed independently. Access from the processor may access relatively short data such as a cache miss, or may access relatively long data using DMA or the like. Banks are generally assigned by addresses in such a manner that consecutive addresses are accessed across a plurality of banks and interleaved so that the bandwidth can be increased.
[0003]
[Problems to be solved by the invention]
When a plurality of memory accesses are generated from each processor, a bank conflicts with a request from another processor, so that the memory access order does not necessarily end in the order issued by the processor. However, if there is no way to know that the memory access is completed, an instruction using the result of these memory accesses cannot be executed.
[0004]
Therefore, there is a method of restricting the execution of memory access so that the memory access always ends in the issue order. However, this method has a problem that the processing efficiency of the memory access itself is lowered and the performance of the processor is lowered. It was.
[0005]
In order not to limit, it is necessary to detect the end of all memory accesses by generating an interrupt, for example, when the bank access ends. However, even in the method using this interrupt, an interrupt is generated every time each memory access is completed, so that there is a problem that the performance of the processor is lowered.
[0006]
The present invention has been made in view of the above circumstances, and implements an efficient multi-bank access and a multi-bank access control device and a multi-bank capable of detecting the end of a memory access command as required An object is to provide an access control method.
[0007]
[Means for Solving the Problems]
  The present invention is a multi-bank access control device that performs access control to a plurality of memory banks that are accessed in common by a plurality of processors, and is provided one by one for each of the plurality of processors. First storage means for storing commands related to issued bank accesses, and second storage means for storing microcommands for the corresponding memory banks provided one by one corresponding to the plurality of memory banks. And subdividing the memory access command stored in the first storage means into one or a plurality of microcommands for accessing the memory bank according to the contents, and subdividing each microcommand, It issues to the second storage means corresponding to the memory bank to be accessed Control means, first detection means for detecting the end of each of the memory access commands by managing issuance and termination of the microcommand corresponding to the memory access command, and detection by the first detection means Based on the result, it is detected whether or not all the memory access commands issued prior to the synchronization command by the processor that has issued the synchronization command fetched from the first storage means to the control means have been completed. With second detection meansThe second detection means is provided in a set corresponding to a plurality of the processors, and the number of the memory access commands issued from the corresponding processors and fetched into the control means but not yet finished. And a flag indicating the presence / absence of a synchronization command issued from the corresponding processor and fetched into the control means but not yet finished, and when the memory access command is fetched into the control means The counter corresponding to the processor that issued the memory access command is incremented, and when the end of the memory access command is detected by the first detection means, the memory access command is issued. The counter is decremented and the sync command is When incorporated into the control means, when said counter corresponding to the processor that issued the synchronous command is not the initial state, child in a state indicating that the synchronization command has not been completed the corresponding said flag still existsAnd features.
[0008]
Preferably, the control means obtains identification information to be assigned to the memory access command prior to subdividing the memory access command into the microcommand, and the subdivided microcommand is converted into the second microcommand. When issuing to the storage means, the identification information assigned to the memory access command that is the source of the microcommand is added to the microcommand, and the first detection means adds the identification information added to the microcommand. The end of the memory access command to which the identification information is assigned may be detected by managing the issuance and termination of the microcommand based on
[0010]
  Further, the present invention is a multi-bank access control device that performs access control to a plurality of memory banks that are commonly accessed from a plurality of threads, and is provided one by one corresponding to the plurality of threads, A first accumulator for accumulating commands related to bank access issued by a thread; and a second accumulator provided for each of the plurality of memory banks and for accumulating microcommands for the corresponding memory banks. The memory access command stored in the storage means and the first storage means is subdivided into one or a plurality of microcommands for accessing the memory bank according to the contents, and each microcommand subdivided Is issued to the second storage means corresponding to the memory bank to be accessed Control means, first detection means for detecting the end of each of the memory access commands by managing issuance and termination of the microcommand corresponding to the memory access command, and detection by the first detection means Based on the result, it is detected whether or not all the memory access commands issued prior to the synchronization command by the thread that issued the synchronization command fetched from the first storage unit to the control unit have ended. With second detection meansThe second detection means is provided for each of the plurality of threads, and the number of the memory access commands issued from the corresponding thread and taken into the control means but not yet finished. And a flag indicating the presence / absence of a synchronization command issued from the corresponding thread and fetched into the control means but not yet terminated, and when the memory access command is fetched into the control means The counter corresponding to the thread that issued the memory access command is incremented, and when the end of the memory access command is detected by the first detection means, the memory access command is issued. Decrementing the counter, the synchronization command is the control means When incorporated, when the counter corresponding to the thread that issued the synchronous command is not the initial state, child in a state indicating that the synchronization corresponding the flag is not yet completed command existsAnd features.
[0011]
  The present invention is also a multi-bank access control method for controlling access to a plurality of memory banks accessed in common by a plurality of processors, and when a command related to bank access is issued from the processor, The command is stored in the first storage means corresponding to the processorSteps to do, Control meansButA command stored from any one of the first storage means corresponding to the plurality of processors is fetched, and if the command is a memory access command, the memory access command is The memory bank is subdivided into one or a plurality of microcommands to be accessed, and each subdivided microcommand corresponds to the memory bank to be accessed.FirstIssued to 2 storage meansSteps to do,First1 detection meansButDetecting the end of the memory access command by detecting the issuance and termination of the microcommand corresponding to the memory access commandFirst 1 Detection step and,First2 detection meansButThe memory access command issued prior to the synchronization command by the processor that has issued the synchronization command fetched from the second storage means to the control means based on the detection result by the first detection means is: Check if everything is finishedA second detection step to issue,
  The second detection means is provided in a set corresponding to a plurality of the processors, and holds the number of the memory access commands issued from the corresponding processors and fetched into the control means but not yet finished. And a flag indicating the presence / absence of a synchronization command issued from the corresponding processor and fetched into the control means but not yet finished, and the second detection means in the second detection step When the memory access command is fetched by the control means, the counter corresponding to the processor that issued the memory access command is incremented, and the end of the memory access command is detected by the first detection means. To the processor that issued the memory access command When the counter corresponding to the processor that issued the synchronization command is not in an initial state when the corresponding counter is decremented and the synchronization command is fetched into the control means, the corresponding flag has not been terminated yet. State that there are no sync commandsIt is characterized by that.
[0012]
The present invention relating to the apparatus is also established as an invention relating to a method, and the present invention relating to a method is also established as an invention relating to an apparatus.
[0013]
In the present invention, the end of the memory access command is detected by managing the issuance / end of the microcommand corresponding to the memory access command, and the number of unfinished memory access commands for each processor (thread). By managing the presence / absence of unsynchronized synchronization commands, it is detected whether or not all the memory access commands issued prior to the synchronization command by the processor that issued the synchronization command have been completed. This makes it possible to guarantee the order relationship between the memory access and the command that uses the memory access. As a result, the performance of the processor can be improved.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the invention will be described with reference to the drawings.
[0015]
In this embodiment, a multiprocessor system will be described as an example, but the present invention is also applied to a multithread processor system (for example, a system having a plurality of DMA controllers controlled by a plurality of threads) instead of a plurality of processors. Is possible.
[0016]
In the present embodiment, when there are a plurality of memory access commands from the processor, a synchronization command (SYNC command) that can execute a subsequent command (instruction) only when the memory access is completed is introduced. In order to realize this synchronization command, a synchronization counter for synchronization is provided for each processor. The synchronization counter is incremented when a memory access command is issued, and is decremented when a corresponding response is returned to 0. Then the processor is controlled so that the synchronization command can be passed. Therefore, when there are a plurality of memory access commands from the processor, the order relationship between the memory access and the instruction (following command) using the memory access is ensured without using interrupt processing for all the commands as in the prior art. Will be able to. As a result, the performance of the processor can be improved.
[0017]
FIG. 1 shows a configuration example of a multiprocessor system according to an embodiment of the present invention. As shown in FIG. 1, in the multiprocessor system of this embodiment, m (m is a plurality, FIG. 1 is an example where m = 4) processors (Processors) 1 and memory controllers (Memory Controllers) 2 are provided. The memory controller 2 controls the access to n memory banks 4 (where n is a plurality and n = 4 in FIG. 1).
[0018]
In the example of FIG. 1, the number of processors and the number of banks are the same, but of course, the number of processors and the number of banks may be different.
[0019]
Further, the memory bank and the real memory (for example, a memory chip or a memory unit) may have any relationship. For example, as illustrated in FIG. 2A, all the banks may correspond to one obtained by dividing one memory into a plurality of areas, or as illustrated in FIG. One bank may correspond to one obtained by dividing one memory into a plurality of areas, or one bank may correspond to a plurality of memories as illustrated in FIG. May be. Further, the correspondence relationship between the bank and the memory may be different for each bank or each memory.
[0020]
FIG. 3 shows a configuration example of the memory controller 2 according to an embodiment of the present invention. As shown in FIG. 3, the memory controller 2 of this embodiment includes a bus interface (bus interface) 21 and m pieces provided corresponding to each processor 1 (m is a plurality, FIG. 3 is an example of m = 4). Command queue 22, interleave unit 23, and n (n is a plurality, FIG. 3 shows an example of n = 4) bank queue 24 provided corresponding to each memory bank 2. A data buffer 25, a completion controller 26, and a synchronization controller 27.
[0021]
The command queues (0) to (3) in FIG. 3 correspond to the processors (0) to (3) in FIG. 1, respectively. Also, the bank queues (0) to (3) in FIG. 3 correspond to the memory banks (0) to (3) in FIG. 1, respectively.
[0022]
A memory access command from each processor 1 is input to the command queue 22 corresponding to the processor via the bus interface 21. In the example of FIGS. 1 and 3, the memory access command from the processor (0) is input to the command queue (0) corresponding to the processor (0). Similarly, memory access commands from the processors (1) to (3) are input to the corresponding command queues (1) to (3), respectively.
[0023]
A synchronization command from each processor (i) is also placed in the command queue (i) corresponding to the processor (i).
[0024]
Within each command queue 22, commands are held in the order issued by the processor 1, and are taken into the interleave unit 23 in that order (that is, FIFO).
[0025]
The interleave unit 23 selects one command queue 22 and fetches the head command, and performs a process corresponding to the command depending on whether the command is a memory access command or a synchronization command. For example, the command queue 22 may be sequentially selected in a round-robin manner (the empty command queue 22 is skipped). Also, for example, other methods such as a method of giving priority to the command queue 22 and preferentially selecting the command queue 22 from a higher priority, or a method of selecting at random are also possible.
[0026]
The interleave unit 23 first selects a command queue 22 as a candidate. If the command is held in the command queue 22, the interleave unit 23 takes the head command, and if the command is held in the command queue 22. The procedure may be to select the next candidate, or first, the command queue 22 that holds the command is examined (this is an inquiry about whether the command is held in the command queue 22 and a response is received) It may be an active form or a passive form such as receiving a notification from the command queue 22 holding the command), and one of them is selected and the head command is selected. The procedure of importing may be used, and other methods are also possible.
[0027]
The interleave unit 23 functions to subdivide the memory access command issued from each processor 1 into commands (microcommands) divided into banks (note that some microcommands are not Whether it is generated depends on the memory access command (it may be one).
[0028]
However, in this embodiment, an identification number (described later) assigned to each memory access command is assigned to all microcommands belonging to one memory access command, and each memory access command to which the microcommand belongs is specified. Since the number has an upper limit, the memory access command can be subdivided into microcommands only when there is a free identification number. The identification number is given from the termination controller 26 (for example, the identification number is requested from the termination controller 26, and if there is a vacancy, the identification number is returned, and if there is no vacancy, this is returned).
[0029]
The generated microcommand is issued to the bank queue 24 corresponding to the memory bank 4 to be accessed by the microcommand.
[0030]
For example, in the example of FIG. 1 and FIG. 3, when adopting a configuration that supports 128-byte continuous access in one bank, 4096 bytes of “memory addresses“ 0x1000 ”to“ 0x1fff ”” from the processor (1). Is transferred to the processor (1) ", 4096/128 = 32 microcommands are issued. The 32 microcommands are issued to the corresponding bank queue 24 in order to access one assigned bank (for example, eight each in the bank queues (0) to (3)). Microcommands can be entered).
[0031]
In each bank queue 24, the microcommand is held by the issued issue and is issued to the memory bank 4 in that order (ie, FIFO).
[0032]
In each bank queue 24, not only microcommands belonging to different memory access commands issued by the same processor 1 can be mixed, but also microcommands belonging to memory access commands issued by different processors 1 can be mixed. .
[0033]
By the way, although various methods are possible for address allocation, for example, in the above example, access is made from a plurality of banks with consecutive addresses, and bank interleaving is performed as an example in order to exhibit throughput. The following address assignment can be considered. Assuming that 128 bytes of data are supported in one bank access, 7 bits from the 0th bit to the 6th bit of the address are offset in 128 bytes (which one byte in 128 bytes) 8 bits and 7 bits indicate which bank of the four banks, 23 bits from 9th bit to 31st bit indicate which 128 bytes in the bank. Yes. In this example, the 2nd bit of the 8th bit and the 7th bit is referred to for selecting the corresponding bank queue 24 when the microcommand is input from the interleave unit 23 to the bank queue 24, and from the 9th bit. The 31th bit, 23 bits, is referred to select the corresponding 128 bytes in the memory bank during the actual bank access (in this example, 7 bits from the 0th bit to the 6th bit are Field used in the processor).
[0034]
The microcommand issued from the bank queue 24 to the corresponding memory bank 4 accesses the memory bank 4, and at the time of read access, the data at the corresponding address is written from the memory bank 4 to the data buffer 25, At the time of write access, data to be written is written from the data buffer 25 to the memory bank 4. The data buffer 25 exchanges data with the bus and the processor 1 via the bus interface 21.
[0035]
For reading from the memory bank 4, when a command is issued from the command queue 22 to the interleave unit 23, the processor number of the corresponding processor 1 is attached to the command. When a microcommand is issued from the interleave unit 23 to the bank queue 24, the processor number of the corresponding processor 1 and an identification number corresponding to the memory access command to which the microcommand is attached are attached to the microcommand. Further, when a response (for example, 128-byte data) from the memory bank 4 is returned from the data buffer 25, the processor number of the corresponding processor 1 and the responding address are added to the data, and which packet is sent on the processor side. Can be identified.
[0036]
As for the write to the memory bank 4, when a command is issued from the command queue 22 to the interleave unit 23 as described above, the processor number of the corresponding processor 1 is attached to the command, and the interleave unit 23 sends the bank queue to the command. When a microcommand is issued to 24, the processor number and identification number of the corresponding processor 1 are attached to the microcommand. When a microcommand is issued from the interleave unit 23 to the bank queue 24, the processor number and address of the corresponding processor 1 are sent to the bus 3 via the bus interface 21 as a write request, and the corresponding processor 1 sends data to be written to the bus 3. The data to be written is input to the data buffer 25 via the bus interface 21.
[0037]
The timing at which each processor 1 sends data is set at a time when the processor 1 sends a command, for example. Also, for example, there is a method of setting a time when a microcommand is issued from the interleave unit 23 to the bank queue 24. The latter method can reduce the memory capacity of the data buffer 25 as compared with the former method.
[0038]
When a write command is issued from the bank queue 24 to each memory bank 4, the corresponding data is output from the data buffer 25.
[0039]
The data buffer 25 is preferably provided with a write buffer corresponding to the bank queue 24.
[0040]
FIG. 4 shows an example of the processing procedure of the interleave unit 23.
[0041]
The interleave unit 23 checks whether there is a non-empty command queue 22 (step S1).
[0042]
If there is a non-empty command queue 22 (step S1), one non-empty command queue 22 is selected (step S2).
[0043]
If the command held at the head of the selected command queue 22 is a synchronous command (step S3), the synchronous counter is notified (step S4), the process returns to step S1, and the processing is continued.
[0044]
If the command held at the head of the selected command queue 22 is a memory access command (step S3), if there is no empty identification number assigned to the memory access command (step S5), the process returns to step S1 and processed. Continue.
[0045]
If there is a free identification number assigned to the memory access command (step S5), the head command of the selected command queue 22 is taken out (step S6). Then, based on the extracted memory access command, a microcommand is generated, and the generated microcommand is put into the corresponding bank queue 24 (step S7). In addition, the synchronous controller 27 is notified of the memory access command (step S7). In addition, the end controller 26 is notified of the microcommand generated from the memory access command (step S7). And it returns to step S1 and continues a process.
[0046]
As described above, the memory access command from the processor 1 is broken down into a plurality of microcommands. In this embodiment, in order to detect the end of each memory access command from each processor 1, the end controller 26 that manages the generation / end of all microcommands belonging to the memory access command and all the synchronization commands. A synchronization controller 27 is provided for detecting the end of the memory access command and notifying the corresponding processor 1 that the synchronization command is completed and can be passed.
[0047]
First, the synchronization controller 27 will be described.
[0048]
FIG. 5 shows a configuration example of the synchronization controller 27 of the present embodiment. As shown in FIG. 5, the synchronization controller 27 includes output decoders (Output Decoders) 271 and m (m is plural, FIG. 5 is an example of m = 4) provided corresponding to each processor 1. A counter (SYNC Counter) 272, a synchronization bit (SYNC Bit) 273, and an input decoder (Input Decoder) 274 are included.
[0049]
The synchronization counters (0) to (3) in FIG. 5 correspond to the processors (0) to (3) in FIG. 1, respectively. Also, the synchronization bits (0) to (3) in FIG. 5 correspond to the processors (0) to (3) in FIG. 1, respectively.
[0050]
Here, the synchronization counter (0) and the synchronization bit (0) in FIG. 3 corresponding to the processor (0) in FIG. 1 will be described as an example.
[0051]
In the synchronous controller 27, when one memory access command from the processor (0) is newly notified from the interleave unit 23, the synchronous counter (0) corresponding to the processor (0) of the synchronous controller 27 is incremented. The When the end controller 26 detects the end of one memory access command from the processor (0), the synchronous counter (0) is decremented.
[0052]
On the other hand, when the synchronization command enters the interleave unit 23, the synchronization bit (0) is set (for example, becomes 1).
[0053]
The notification to the corresponding processor 1 that all the memory access commands preceding the synchronization command have been completed (that is, that the synchronization command has been completed) is performed under the following conditions.
When the counter value of the synchronization counter (0) is 0 and a synchronization command is output from the command queue (0) to the interleave unit 23, all memory access commands corresponding to the synchronization command are sent to the processor (0). Notify that it has finished. At this time, the synchronization bit (0) is not set (Note that it may be set once and immediately detected that the notification condition is met and reset immediately).
When the value of the synchronization counter (0) becomes 0 when the synchronization bit (0) is 1 (when the memory access command is completed), the memory access command corresponding to the synchronization command is sent to the processor (0). Is completed, and the synchronization bit (0) is reset (for example, set to 0).
When the synchronization bit (0) is 0 (when the memory access command is completed) and the value of the synchronization counter (0) becomes 0, the processor is not notified.
[0054]
The processor (0) has been described above as an example, but the same applies to other processors.
[0055]
By the way, there are various methods for handling the synchronization command on the processor 1 side. For example, when the processor 1 sends the synchronization command to the memory controller 2 (command queue 22 thereof), the processor 1 enters a busy wait state. The busy wait state may be canceled when a response to the end of the synchronization command is returned from the memory controller 2 (the synchronization controller 27). Further, for example, an interrupt may be used for the end of the synchronous command (in the past, it was necessary to use an interrupt for all commands, but in the present embodiment, an interrupt may be used only for the synchronous command). .
In the case of a multi-thread processor, threads may be switched using a synchronization command. In this case, for example, the thread that executed the synchronous command is saved, and when the response of the synchronous command end is returned from the synchronous controller, the thread that executed the synchronous command corresponding to the response is restored (or can be restored). ).
[0056]
For example, assume that the program executed by the processor (0) is as follows.
:
DMA command 1
DMA command 2
Synchronous command
DMA command 3
:
In this example, in order to execute the DMA command 3 after both the DMA command 1 and the DMA command 2 are completed, a synchronization command is described between the DMA command 1 and the DMA command 2 and the DMA command 3. In this case, after the DMA command 1 and the DMA command 2 are ended (and the synchronization command is issued), the memory controller 2 notifies the corresponding processor 1 of the end of the synchronization command.
[0057]
In the processor 1 that has received the notification, for example, the busy wait state is canceled and the DMA command 3 is executed.
[0058]
In the case of a multi-thread processor, the thread that executed the synchronization command can be restored, and after the restoration, the DMA command 3 is executed.
[0059]
FIG. 6 shows an example of a processing procedure for the synchronization counter 272 or the synchronization bit 273 when the notification in the synchronization controller 27 is received.
[0060]
The synchronous controller 27 checks whether there is a notification from the interleave unit 23 or the end controller 26 (step S11).
[0061]
When there is a notification (step S11), if the notification is a notification of issuance of a memory access command from the interleave unit 23 (step S12), the synchronization counter 272 corresponding to the processor 1 related to the notification is incremented ( Step S13), returning to step S11, the processing is continued.
[0062]
If the notification is a notification of the end of the memory access command from the end controller 26 (step S12), the synchronization counter 272 corresponding to the processor 1 related to the notification is decremented (step S14), and the process returns to step S11 to perform the processing. to continue.
[0063]
When the notification is a notification of a synchronization command from the interleave unit 23 (step S12), if the value of the synchronization counter 272 corresponding to the processor 1 related to the notification is 1 or more (step S15), the processor 1 related to the notification is notified. The corresponding synchronization flag 273 is set (step S16), the process returns to step S11, and the processing is continued. If the value of the corresponding synchronization counter is 0 (step S15), the corresponding synchronization flag 273 is not set and the process returns to step S11 to continue the processing.
[0064]
FIG. 7 shows an example of a processing procedure regarding notification from the synchronous controller 27 to the processor.
[0065]
The synchronization controller 27 checks whether the state of the synchronization counter 272 or the synchronization bit 273 has changed and whether a notification of a synchronization command has been received (occurrence of an event) (step S21).
[0066]
If the value of the synchronization counter 272 corresponding to a certain processor 1 is 0 and if a synchronization command notification is received from the processor 1 (step S22), the processor 1 is notified (step S23), Returning to step S21, the processing is continued.
[0067]
If the synchronization counter corresponding to a certain processor 1 is set and the synchronization counter corresponding to the processor 1 becomes 0 (step S24), the processor 1 is notified and the synchronization bit is set. 273 is reset (step S23), and the process returns to step S21 to continue the processing.
[0068]
If it is another event, nothing is done (return to step S21 and continue the process).
[0069]
In FIG. 6, when the notification of the synchronization command is made in step S <b> 12, the corresponding synchronization flag 273 may be set regardless of the value of the corresponding synchronization counter 272. In this case, in steps S22 / S23 of FIG. 7, if the corresponding synchronization flag 273 is set when the value of the synchronization counter 272 corresponding to a certain processor 1 is 0 (step S22), the process goes to the processor 1. The synchronization bit 273 may be reset (in this case, in step S21, it is checked whether the state of the synchronization counter 272 or the synchronization bit 273 has changed, and the notification of the synchronization command is received). Do not check).
[0070]
Next, the end controller 26 will be described.
[0071]
In the interleave unit 23, the memory access command is decomposed into micro commands, and the micro commands from the plurality of processors 1 compete in the bank queue 24. Therefore, the end order of the micro commands is generally the issue order from the interleave unit 23. Will be different (and may be the same as a result). In the end controller 26, when all the plurality of microcommands corresponding to one memory access command are ended, the synchronization controller 27 is notified that the one memory access command is ended.
[0072]
FIG. 8 shows a configuration example of the end controller 26 of the present embodiment. As shown in FIG. 8, the end controller 26 includes a first decoder (Decoder_A) 261, k (k is plural, K = 6 in the example of FIG. 8) microcounter 262, and processor number holding. Part (Proc Num) 263 and a second decoder (Decoder_B) 264.
[0073]
First, when the memory access command is decomposed into microcommands by the interleave unit 23, the decoder (Decoder_A) 261 issues an identification number. The identification number is uniquely assigned to each microcounter / processor number holding unit in FIG. 8, for example, microcounter (0) / processor number holding unit (0) to microcounter (5) / processor number holding. Identification numbers 0 to 5 are assigned to the respective groups of the part (5). The number of pairs of microcounter / processor number holding units (the maximum number of identification numbers that can be issued) does not necessarily need to match the number of processors (may match the number of processors).
[0074]
The identification number is issued when the corresponding microcounter / processor number holding unit is empty, but when the identification number is empty (when the microcounter / processor number holding unit is empty), the identification number is issued. In the latter case, the interleave unit 23 is controlled so as not to generate a microcommand.
[0075]
When the interleave unit 23 successfully acquires the identification number, the identification number can be assigned to the memory access command, and the microcommand can be generated. Each time one microcommand is generated, the microcounter 262 corresponding to the identification number is incremented. Further, when an identification number is assigned to the memory access command, the processor number of the processor 1 that issued the memory access command is set in the processor number holding unit 263, and this processor number is notified when the memory access command ends later. Used for.
[0076]
Acquired identification numbers are assigned to the microcommands generated from the interleave unit 23. When a response is returned from the memory out of the bank queue 24, the microcounter 262 is selected by this identification number, and the selected microcounter 262 is decremented. In other words, the micro counter 262 is incremented when the micro command is generated for the corresponding memory access command, and is decremented when the micro command is completed, so that the end of the memory access command can be known.
[0077]
When the count value of the micro counter 262 reaches 0, the decoder (Decoder_A) 261 notifies the synchronous controller 27 of the corresponding processor number.
[0078]
FIG. 9 shows an example of a processing procedure in the end controller 26.
[0079]
The end controller 26 checks whether the microcommand has been generated and ended (occurrence of an event) (step S31).
[0080]
If a microcommand is generated (step S32), the microcounter 262 corresponding to the identifier assigned to the microcommand is incremented (step S33), the process returns to step S31, and the processing is continued.
[0081]
When the microcommand is terminated (step S32), the microcounter 262 corresponding to the identifier assigned to the microcommand is decremented (step S34). If the microcounter 262 reaches 0, the synchronous controller 27 is notified that one memory access command corresponding to the processor number held in the processor number holding unit 263 corresponding to the microcounter 262 has ended. Notification is made (step S36). Further, the identification number is released, and the identification number and the corresponding microcounter 262 / processor number holding unit 263 are unused (step S36). And it returns to step S31 and continues a process.
[0082]
As described above, according to the present embodiment, the memory access is interleaved with the bank access, and the interleaved access is efficiently accessed without following the order of the memory access, and the memory access is completed as necessary. be able to.
[0083]
In this embodiment, the multiprocessor system is described as an example. However, the present invention is applied to a memory controller for a multithread processor system (corresponding to a thread (hardware thread) of the processor in FIG. 1). Basically, it is the same as that described so far (in the description, the processor may be read as a thread).
[0084]
Note that the configuration illustrated in the embodiment of the present invention is an example, and is not intended to exclude other configurations, and a part of the illustrated configuration may be replaced with another or one of the illustrated configurations. Other configurations obtained by omitting a part, adding another function or element to the illustrated configuration, or combining them are also possible. Also, another configuration that is logically equivalent to the exemplified configuration, another configuration that includes a portion that is logically equivalent to the exemplified configuration, another configuration that is logically equivalent to the main part of the illustrated configuration, and the like are possible. is there. Further, another configuration that achieves the same or similar purpose as the illustrated configuration, another configuration that achieves the same or similar effect as the illustrated configuration, and the like are possible.
In addition, various variations of various components illustrated in the embodiment of the present invention can be implemented in appropriate combination.
Further, the embodiment of the present invention is an invention of an invention as an individual device, an invention of two or more related devices, an invention of the entire system, an invention of components within an individual device, or a method corresponding thereto. The invention includes inventions according to various viewpoints, stages, concepts, or categories.
Therefore, the present invention can be extracted from the contents disclosed in the embodiments of the present invention without being limited to the exemplified configuration.
[0085]
The present invention is not limited to the embodiment described above, and can be implemented with various modifications within the technical scope thereof.
[0086]
【The invention's effect】
According to the present invention, it is possible to realize efficient multi-bank access and to detect the end of a memory access command as necessary.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of a multiprocessor system according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining the relationship between banks and memories;
FIG. 3 is a view showing a configuration example of a memory controller according to the embodiment;
FIG. 4 is a flowchart showing an example of a processing procedure of an interleave unit according to the embodiment.
FIG. 5 is a view showing a configuration example of a synchronous controller according to the embodiment;
FIG. 6 is a flowchart showing an example of a first processing procedure of the synchronous controller according to the embodiment;
FIG. 7 is a flowchart showing an example of a second processing procedure of the synchronous controller according to the embodiment;
FIG. 8 is a view showing a configuration example of an end controller according to the embodiment;
FIG. 9 is a flowchart showing an example of a processing procedure of the end controller according to the embodiment;
[Explanation of symbols]
1 ... Processor
2 ... Memory controller
3 ... Bus
4 ... Memory bank
21 ... Bus interface
22 ... Command queue
23 ... Interleave unit
24 ... Bank Queue
25 ... Data buffer
26: End controller
27 ... Synchronous controller
261: First coder
262 ... Micro counter
263: Processor number holding unit
H.264 second decoder
271: Output decoder
272 ... Synchronous counter
273 ... Synchronization bit
274 ... Input decoder

Claims (11)

A multi-bank access control device that performs access control to a plurality of memory banks accessed in common by a plurality of processors,
A first storage unit that is provided one by one for each of the plurality of processors, and stores a command related to bank access issued from the corresponding processor;
A second storage unit that is provided one by one corresponding to the plurality of memory banks, and stores microcommands for the corresponding memory banks;
The memory access command stored in the first storage means is subdivided into one or a plurality of microcommands for accessing the memory bank according to the contents, and each subdivided microcommand is Control means for issuing to the second storage means corresponding to the memory bank to be accessed;
First detecting means for detecting the end of each memory access command by managing the issuance and termination of the microcommand corresponding to the memory access command;
Based on the detection result by the first detection means, all the memory access commands issued prior to the synchronization command by the processor that issued the synchronization command fetched from the first storage means to the control means are all Second detecting means for detecting whether or not the processing has ended,
The second detection means includes
A counter provided for each of the plurality of processors, a counter for holding the number of memory access commands issued from the corresponding processor and fetched into the control means but not yet completed, and the corresponding processor Including a flag indicating the presence or absence of a synchronization command issued from and taken into the control means but not yet terminated,
When the memory access command is taken into the control means, the counter corresponding to the processor that issued the memory access command is incremented, and the end of the memory access command is detected by the first detection means The counter corresponding to the processor that issued the memory access command is decremented, and the counter corresponding to the processor that issued the synchronization command is initialized when the counter is fetched by the control means. when not in state, corresponding the flag yet completed have no synchronization command, wherein the to luma Ruchi bank access controller to the state indicating that there is. When the counter corresponding to the flag in a state indicating that there is an unfinished synchronization command is decremented to an initial state, the synchronization is performed with respect to the counter and the processor corresponding to the flag. multi-bank access control apparatus according to claim 1, prior to the command issued memory access command and notifies that it has completed. If the counter corresponding to the processor that issued the synchronization command is in an initial state when the synchronization command is taken into the control unit, the counter and the processor corresponding to the flag multi-bank access control apparatus according to claim 1, synchronization commands in prior to the issued memory access command and notifies that it has completed. When the counter corresponding to the flag in a state indicating that there is no synchronization command that has not been completed has been decremented to the initial state, the notification to the counter and the processor corresponding to the flag is performed. 2. The multi-bank access control device according to claim 1 , wherein the multi-bank access control device is not performed. Prior to subdividing the memory access command into the microcommand, the control means acquires identification information to be assigned to the memory access command, and sends the subdivided microcommand to the second storage means. When issuing the microcommand, the identification information assigned to the memory access command that is the source of the microcommand is added,
The first detection means detects the end of the memory access command to which the identification information is assigned by managing the issuance and termination of the microcommand based on the identification information added to the microcommand. it multi-bank access controller according to any one of claims 1 to 4, wherein the. The first detection means includes
A counter corresponding to a predetermined number of the identification information,
When the microcommand is issued, the counter corresponding to the identification information added to the microcommand is incremented. When the microcommand is completed, the counter corresponds to the identification information added to the microcommand. The counter is decremented, and when the value of the counter returns to the initial state, it is detected that the memory access command to which the identification information corresponding to the counter is assigned is completed. 5. The multi-bank access control device according to 5. The first detection means includes
In association with the counter corresponding to the identification information, holding information for specifying the processor that issued the memory access command corresponding to the identification information,
When it is detected that the memory access command has ended, information for specifying the processor held in correspondence with the identification information added to the memory access for which the end has been detected, The multi-bank access control apparatus according to claim 6 , wherein the detection means is notified.   2. The multi-bank access control apparatus according to claim 1, wherein the control unit selects a command to be fetched from a plurality of the first storage units according to a predetermined selection criterion.   2. The multi-bank access control apparatus according to claim 1, wherein the control unit does not perform processing for the memory access command while the identification information cannot be acquired because all the identification information is used. A multi-bank access control device that performs access control to a plurality of memory banks accessed in common from a plurality of threads,
1st accumulation means which is provided one by one corresponding to the plurality of threads, and accumulates commands related to bank access issued from the corresponding threads;
A second storage unit that is provided one by one corresponding to the plurality of memory banks, and stores microcommands for the corresponding memory banks;
The memory access command stored in the first storage means is subdivided into one or a plurality of microcommands for accessing the memory bank according to the contents, and each subdivided microcommand is Control means for issuing to the second storage means corresponding to the memory bank to be accessed;
First detecting means for detecting the end of each memory access command by managing the issuance and termination of the microcommand corresponding to the memory access command;
Based on the detection result by the first detection means, all the memory access commands issued prior to the synchronization command by the thread that issued the synchronization command fetched from the first storage means to the control means are all Bei give a second detection means for detecting whether or not it is completed,
The second detection means includes
A counter provided for each of the plurality of threads, a counter for holding the number of the memory access commands issued from the corresponding thread and fetched into the control means but not yet terminated, and the corresponding thread Including a flag indicating the presence or absence of a synchronization command issued from and taken into the control means but not yet terminated,
When the memory access command is taken into the control means, the counter corresponding to the thread that issued the memory access command is incremented, and the end of the memory access command is detected by the first detection means The counter corresponding to the thread that issued the memory access command is decremented, and the counter corresponding to the thread that issued the synchronization command is initialized when the counter is fetched by the control means. when not in a state, the corresponding multi-bank access control device, characterized that you to the state shown yet that finished non synchronization command is present the flag. A multi-bank access control method for controlling access to a plurality of memory banks accessed in common by a plurality of processors,
When a command related to bank access is issued from the processor, the command is stored in a first storage means corresponding to the processor;
Control means captures the stored commands from one of said first storage means corresponding to a plurality of said processors, said command if a memory access command, the memory access command, the contents subdivided into one or more micro-commands and accessed the memory bank in response to the micro-command of each subdivided, it to the second storage means that corresponds to the memory bank to be accessed Issuing step ;
By the first detecting means, for detecting the issuance and termination of the micro command corresponding to the memory access command, a first detecting step of detecting the completion of the memory access command,
Second detecting means, the first based on the result of detection by the detecting means, and said processor which has issued the synchronization command fetched into the control unit from the second storage means prior to the synchronizing command issued memory access commands are, and a second detection step of detect whether or not completed,
The second detection means is provided in a set corresponding to a plurality of the processors, and holds the number of the memory access commands issued from the corresponding processors and fetched into the control means but not yet finished. And a flag indicating the presence / absence of a synchronization command issued from the corresponding processor and fetched into the control means but not yet finished,
In the second detection step, when the memory access command is fetched by the control means, the second detection means increments the counter corresponding to the processor that issued the memory access command, and When the end of the memory access command is detected by one detection means, the counter corresponding to the processor that issued the memory access command is decremented, and when the synchronization command is taken into the control means, when the counter corresponding to the processor that issued the synchronous command is not the initial state, the corresponding multi-bank access control method according to claim to Rukoto the state indicating that the synchronization flag is not yet completed command exists .

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