JP3969190B2 - Imaging signal processing method, imaging signal processing apparatus, and imaging apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging signal processing method and apparatus for a solid-state imaging device, and an imaging apparatus. More specifically, the DC level of an imaging signal output from a current output type solid-state imaging device that outputs a pixel signal obtained by a pixel as a current signal, such as a CMOS imaging device or an amplification imaging device, is held at a constant value. It relates to clamping technology.
[0002]
[Prior art]
In general, a solid-state imaging device performs photoelectric conversion with each light receiving element formed of a photodiode or the like, detects generated charges with a detection circuit, and then amplifies and sequentially outputs them. In most cases, this detection circuit performs a detection operation and a reset operation alternately, generates a noise signal called reset noise, and generates an offset component for each pixel. Further, in the case of a so-called amplification type solid-state imaging device in which this detection circuit is provided for each light receiving element, variation in the detection circuit itself becomes a problem, and a noise signal called fixed pattern noise (FPN) is known. Cause the occurrence of The FPN signal can be removed by a known signal processing method called correlated double sampling (hereinafter referred to as CDS).
[0003]
On the other hand, the signal from which noise has been removed by the CDS circuit passes through signal processing such as PGA (Programmable Gain Amp), and is then converted into a digital signal by an A / D converter (analog-digital converter). A video signal is formed by digital signal processing.
[0004]
In general, the DC level (direct current level) of the signal output from the solid-state imaging device varies due to various factors such as variations in power supply voltage, temperature, semiconductor manufacturing process, etc., so that the pixel signal is a CDS circuit, While passing through the PGA and A / D converter, it is clamped (held) at an arbitrary DC level at an arbitrary time using a clamp circuit. For example, in the case of a solid-state imaging device, the DC level is often set by matching the OPB (OPtical Black) level of the imaging element with a reference level. As a method for realizing the clamp circuit, various configurations have been proposed.
[0005]
FIG. 12 is a schematic block diagram illustrating a configuration example of a solid-state imaging device conventionally used. Here, in the configuration shown in FIGS. 12A to 12D, a case where a current output type solid-state imaging device is used will be described as an example. The imaging signal in the current mode output from the solid-state imaging device 3 is converted into a voltage signal by an I / V (current / voltage) conversion circuit 902, and a CDS circuit 903, a PGA 904, a DC shift circuit 905, an A / D converter 906 and the like. It passes through and is finally sent to the digital signal processing circuit.
[0006]
As the clamp circuit 900, a differential amplifier 907 disposed before the A / D converter 906 compares the output signal level with the reference voltage of the reference voltage source 908, and a DC shift circuit so that the difference is eliminated. It is set as the structure which returns to 905 and clamps.
[0007]
In this configuration, the feedback signal for applying the clamp is fed back after the PGA 904, but it may be configured to feed back further. For example, when returning to the front of PGA904, since the input signal level of PGA904 is managed, the effect which prevents the dynamic range of PGA904 from reducing by the dispersion | variation in DC level is also acquired. However, it is not realistic to return before the CDS circuit 903. This is because the DC component is once removed by the subtraction process of the CDS circuit 903. Although it is not impossible to return to the front of the CDS circuit 903, it is necessary to adjust the DC level again after the CDS due to the above-described circumstances. Therefore, the clamp circuit configured to return to the front of the CDS circuit 903 is useless. become.
[0008]
On the other hand, FIG. 12B is characterized in that another independent clamp circuit 901 is provided to ensure the dynamic range of the CDS circuit 903. As shown in the figure, a DC shift circuit 909 is inserted in front of the CDS circuit 903, and the input level of the CDS circuit 903 is monitored by a differential amplifier 910 so as to be equal to the DC voltage of an arbitrary reference voltage source 922, and feedback is performed. It is configured to be applied.
[0009]
As described above, the conventional clamp circuit shown in FIGS. 12A and 12B absorbs fluctuations in the DC level of the signal, thereby preventing problems such as black floating and black sinking of the video signal. It is also required from the viewpoint of securing the dynamic range of analog circuits such as the CDS circuit 903 and the PGA 904.
[0010]
The problem here is that in the conventional solid-state imaging device illustrated in FIGS. 12A and 12B, a DC shift circuit is always required for clamping, and the system becomes more complicated. Is to go. In general, a signal processing circuit such as a CDS circuit or a PGA processes a signal with a voltage. In this case, the clamp circuit is also realized by applying a feedback to the voltage signal. Therefore, although the DC shift circuits 905 and 909 are configured using a voltage adder or the like, there is a method in which the DC component of the signal is once cut using a larger capacitive element depending on the case. .
[0011]
FIG. 12C illustrates an example in which the DC shift circuit 905 in FIG. 12A is configured using a voltage adder. A voltage adder is composed of a resistance element 911, 912, 913, a differential amplifier 914, and a reference voltage source 915, and is obtained by adding the output voltage of the differential amplifier 907 to the output voltage of the variable gain amplifier 904. Is output to the A / D converter 906. The input voltage of the A / D converter 906 is passed to the input terminal of the switch element 917 via the buffer 916, and the clamp potential is held in the hold capacitor 918 by controlling the switch element 917 with a clamp pulse. The differential amplifier 907 monitors the input voltage of the A / D converter 906 at any time controlled by the switch element 917 and applies an appropriate voltage to the resistance element so that it becomes the same voltage as the reference voltage source 908. 912, that is, feedback is applied to the input of the voltage adder.
[0012]
FIG. 12D illustrates an example in which the DC shift circuit 905 in FIG. 12A is formed using a capacitor. The output signal of the variable gain amplifier 904 is received by the capacitive element 917, the DC component is cut, and output to the A / D converter 906 via the buffer 918. The lost DC component is given by the differential amplifier 907 at an arbitrary time controlled by the switch element 919 and held by the capacitive element 917. The differential amplifier 907 monitors the input signal voltage of the A / D converter 906 and applies feedback to the capacitive element 917 so that it is the same as the reference voltage source 908.
[0013]
Thus, the DC shift circuit necessary for clamping the voltage signal needs to use a voltage adder as shown in FIG. 12C or a capacitive element as shown in FIG. This increases the circuit scale and layout area. In particular, it is difficult to form a large capacitive element on a semiconductor substrate due to the problem of the layout area. However, if it is exposed outside the semiconductor, a new problem such as an increase in the number of PADs (terminals) is caused.
[0014]
[Problems to be solved by the invention]
As described above, in the conventional solid-state imaging device, a complex analog signal processing circuit such as a current-voltage conversion circuit, a CDS circuit, a PGA, or an A / D converter is required. A clamp circuit that stabilizes the DC level is required. For this reason, as shown in FIGS. 12C and 12D, a new DC shift circuit is required, which causes further complication of the system. It was.
[0015]
The present invention has been made in view of the above circumstances, and an imaging signal processing method and apparatus capable of forming a clamp circuit without using a special circuit such as a DC shift circuit using a voltage adder or the like, and imaging An object is to provide an apparatus.
[0016]
[Means for Solving the Problems]
  An imaging signal processing method according to the present invention is an imaging signal output as a current signal from a solid-state imaging device.outputlevel(DC level)Is an imaging signal processing method for holding an image signal at a constant value,Is converted to a voltage signal, and the converted voltage signalIn a given period of timeoutputDetect level and detect thisoutputLevels and predetermined criteriaVoltageThe clamp current is fed back to the imaging signal so that the difference from the value becomes substantially zero.In addition, when the clamp current is fed back to the imaging signal, the clamp current that has stopped feedback to the imaging signal during the reset period is returned to a reference voltage source for setting an operation reference point for converting the voltage signal. I decided to let them.
[0017]
  An imaging signal processing apparatus according to the present invention is an apparatus for performing the imaging signal processing method according to the present invention, wherein the imaging signal processing apparatusA voltage signal converted by the current-voltage converter and the current-voltage converterIn a given period of timeoutputDetect level and detect thisoutputLevels and predetermined criteriaVoltageBy comparing with the valueoutputLevels and standardsVoltageFind the difference from the valueoutputA level comparison unit;outputCalculated by the level comparatoroutputLevels and standardsVoltageAnd a current feedback unit that feeds back a clamp current to the imaging signal so that a difference from the value becomes substantially zero.Here, the current feedback unit circulates the clamp current that has stopped feedback to the imaging signal during the reset period to a reference voltage source for setting an operation reference point of the current voltage unit.
[0018]
The current feedback unit may include, for example, a MOS transistor to which a voltage signal is applied to the gate terminal, and generate a clamp current using the constant current characteristics of the MOS transistor.
[0019]
  outputThe level comparison unit is a predetermined period in the voltage signal converted by the current-voltage conversion unit.outputLevels and predetermined criteriaVoltageCriteria as a valueoutputThe voltage is compared.
[0020]
In addition, the imaging signal processing apparatus according to the present invention has a current type CDS function that suppresses an offset component included in a current signal output from each pixel of a solid-state imaging device via a pixel signal line in a current mode. It is preferable to combine with a signal detector.
[0021]
The current signal detection unit having the current type CDS function receives and holds the current component of the reset period in the current signal during the input phase corresponding to the reset period, and holds during the input phase during the output phase corresponding to the detection period. A current copier that outputs a current component is provided, and during the detection period of the current signal, fixed pattern noise is suppressed by obtaining the difference between the component of this detection period and the component output from the current input / output terminal of the current copier. Can take a configuration.
[0022]
Also, a switching element that turns on and off the current signal, a capacitive element that receives the current signal when the switching element is turned on during the reset period and holds a voltage corresponding to the current signal, and an input-side element connected to the solid-state imaging device side And a current mirror circuit in which a device on the output side is mirror-connected, and in the detection period in the current signal, the component of the detection period output from the device on the output side of the current mirror circuit and the capacitive element are held. It is good also as a structure which suppresses fixed pattern noise by calculating | requiring the difference with the electric current component according to the voltage which has.
[0023]
Alternatively, a switching element that turns on and off the current signal, a capacitive element that receives a current signal when the switching element is turned on during the reset period and holds a voltage corresponding to the current signal, and an input side arranged on the capacitive element side A current mirror circuit in which the element and the output side element are mirror-connected, and the detection period in the current signal is a current component corresponding to the component of the detection period and the voltage held by the capacitive element. A fixed pattern noise can be suppressed by obtaining a difference from a current component output from an element on the output side of the current mirror circuit.
[0024]
When combined with a current signal detection unit having a configuration including a current copier, the current feedback unit is preferably configured to stop feedback of the clamp current to the imaging signal during the reset period. Furthermore, when the clamp current that has stopped feedback to the imaging signal during the reset period is recirculated to a predetermined reference voltage source, such as a reference voltage source that defines an operation reference point of the current-voltage converter, for example, More preferred.
[0025]
An imaging apparatus according to the present invention includes a solid-state imaging element that outputs a current signal from each pixel through a pixel signal line, and an imaging signal processing apparatus according to the present invention.
[0026]
[Action]
  In the above configuration,outputThe level comparison unit outputs from the solid-state image sensor.RudenBy detecting the current mode image signal using the voltage signal obtained by current-voltage conversion,outputDetect level. And this detectedoutputLevels and predetermined criteriaVoltageBy comparing the value with the image signaloutputLevels and criteriaVoltageFind the difference from the value. The current feedback section isoutputCalculated by the level comparatoroutputLevels and standardsVoltageThe clamp current is fed back to the imaging signal in the current mode so that the difference from the value becomes substantially zero.
[0027]
  In other words, in the above configuration, unlike the conventional clamp that feeds back with a voltage signal, the clamp current of the imaging signal is directly added to the signal current using a current feedback type clamp configuration.outputControl the level.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0029]
FIG. 1 is a diagram showing a configuration example of an embodiment of an imaging apparatus including a current output type solid-state imaging device and an imaging signal processing apparatus according to the present invention. The imaging apparatus 1 includes, for example, a CMOS type imaging device as the solid-state imaging device 3. In addition, the imaging apparatus 1 includes a current signal detection unit 5 and a current clamp unit 26 that include a voltage operating point setting unit 7 and a current sampling unit 9 at the subsequent stage of the solid-state imaging device 3. Note that the solid-state imaging device 3, the current signal detection unit 5, and the current clamp unit 26 may be formed on one semiconductor substrate.
[0030]
In FIG. 1A, a unit pixel 11 of a photosensitive portion (sensor array) 10 constituting the solid-state imaging device 3 includes a photodiode 12, an amplification transistor 13, a vertical selection transistor 14, and a reset transistor 15. ing. As these transistors 13 to 15, NchMOS transistors are used in this example. The unit pixels 11 are arranged in the X direction (column direction) and the Y direction (row direction) to form a pixel portion. Here, for simplification of the drawing, only pixels of m rows and n columns are shown.
[0031]
In the unit pixel 11, a vertical scanning pulse φVm is applied from the vertical scanning circuit 16 through the vertical selection line 17 to the gate electrode of the vertical selection transistor 14, and the vertical reset line from the vertical scanning circuit 16 to the gate electrode of the reset transistor 15. A vertical reset pulse φVR m is applied through 18. The signal charge photoelectrically converted by the photodiode 12 is converted to a signal current by the amplifying transistor 13 and output to the vertical signal line 19 through the vertical selecting transistor 14.
[0032]
A horizontal selection transistor 21 is connected between the vertical signal line 19 and the horizontal signal line 20. A horizontal scanning pulse φHn is applied from the horizontal scanning circuit 22 to the gate electrode of the horizontal selection transistor 21. As a result, the signal current output from the pixel 11 to the vertical signal line 19 flows to the horizontal signal line 20 through the horizontal selection transistor 21.
[0033]
A current signal detection unit 5 is connected to one end of the horizontal signal line 20, and a current clamp unit 26 is further connected via a voltage operation point setting unit 7 and a current sampling unit 9 therein. As the current signal detector 5, it is preferable to use, for example, a device having a current mode CDS processing function described in Japanese Patent Application No. 2002-102108 by the applicant of the present application.
[0034]
The voltage operating point setting unit 7 always keeps the voltage of the horizontal signal line 20 stable at a substantially constant level (for example, near the GND level). The current sampling unit 9 receives the pixel signal as a current through the horizontal signal line 20 which is an example of the pixel signal line, and removes the offset current included in the current signal by sampling the current, so that only a pure signal is obtained. Take out. Thereby, FPN (fixed pattern noise) contained in the pixel signal is suppressed.
[0035]
The current clamp unit 26 clamps a predetermined position (specifically, an optical black level; OPB) of a signal current input from the horizontal signal line 20 through the current signal detection unit 5 to be a reference level of the current signal. The OPB level is held at a constant value. A current-voltage conversion circuit that converts a signal current input from the current clamp unit 26 into a signal voltage and outputs the signal current is provided at a subsequent stage of the current clamp unit 26 as necessary.
[0036]
The solid-state image pickup device 3 includes photodiodes 11 arranged vertically and horizontally on a photosensitive portion (sensor array) 10 (see FIG. 1B), and output control circuits and output circuits such as vertical and horizontal scanning circuits. (Both not shown). As needed, it is good also as a structure which arrange | positions a micro lens on each photodiode 11, and condenses the image of imaging object.
[0037]
As shown in FIG. 1B, a sensor row (light-shielding part) in which the upper part of the photodiode 11 is shielded is arranged at a part of the end of the photosensitive part 10. The output of this part is always a black level (optical black level) in a part where there is no light. Such a pixel is called an OPB pixel. In general, the OPB pixels are provided for several lines (line; one horizontal scanning period) on the start side of vertical scanning and for several pixels on the start side of horizontal scanning.
[0038]
The current clamp unit 26 detects a direct current level for a predetermined period in the imaging signal output from the current signal detector 5 in the current mode, and the difference between the detected direct current level and a predetermined reference value is substantially zero. Thus, the clamp current is fed back to the imaging signal. Specifically, the current clamp unit 26 includes an output circuit 202, a clamp circuit 250, and an adder 280. The current clamp unit 26 detects the output signal of the OPB pixel and compares the value with a preset reference value. In the present embodiment, the current signal output from the current signal detection unit 5 is converted into a voltage signal by the output circuit 202, and the OPB level in this voltage signal is compared with the voltage reference value by the clamp circuit 250.
[0039]
Then, the clamp circuit 250 varies the clamp level (that is, the OPB level) according to the comparison result so that the output of the OPB pixel is smaller than the voltage reference value, and converges the output level of the OPB pixel to the reference value. Negative feedback control is performed. In this configuration example, the feedback signal from the current clamp unit 26 is added as a current (clamp current) after the CDS processing by the current signal detection unit 5, whereby the DC level of the subsequent signal is set to a desired value (preliminary value). It can be changed to a set reference value).
[0040]
FIG. 2 is a block diagram showing a functional configuration of the current clamp unit 26 in the imaging apparatus 1 having the above configuration together with the entire imaging apparatus 1. As illustrated, the current clamp unit 26 includes a variable gain amplifier (PGA) 200 that controls a current gain, and a current-voltage conversion unit (hereinafter, current-voltage conversion unit) that is an example of an output circuit 202 that converts a current signal into a voltage signal. 220) and a clamp circuit 250.
[0041]
  The clamp circuit 250 includes a current output type differential amplifier 252 that monitors (monitors) the voltage signal S3 output from the current-voltage conversion unit 220 and outputs the result as a clamp current Scp. That is, the current output type differential amplifier 252 has a predetermined period in the imaging signal.outputDetect level and detect thisoutputLevels and predetermined criteriaVoltageBy comparing with the valueoutputLevels and standardsVoltageFind the difference from the valueoutputA level comparison unit;outputLevels and standardsVoltageBoth functions of a current feedback unit that feeds back a clamp current to the imaging signal so that a difference from the value becomes substantially zero are provided.
[0042]
For example, a clamp pulse that defines the clamp timing is input to a predetermined position of the current output type differential amplifier 252 (the location varies depending on the circuit configuration). Specifically, the OPB clamp is realized by inputting a pulse corresponding to the OPB pixel position of the solid-state imaging device 3.
[0043]
The current clamp unit 26 adds a current signal S1 amplified to a predetermined level by the variable gain amplifier 200 and the clamp current Scp from the differential amplifier 252 and outputs a combined current S2; A reference voltage source 290 that is an example of an operation reference point setting unit that sets an operation reference point of the dynamic amplifier 252. An A / D converter 28 for a signal processing system that converts an analog signal into a digital signal is connected to the subsequent stage of the current clamp unit 26.
[0044]
In this configuration, the current signal detector 5 detects the image signal output from the current-type solid-state image sensor 3 as a current signal S0 by subtracting the CDS while maintaining the current signal, and variably changes the current signal S0. Supply to the gain amplifier 200. The variable gain amplifier 200 amplifies the current signal S0 subjected to the CDS processing by the current signal detection unit 5 to a predetermined level and supplies the amplified signal to one terminal of the current addition unit 280. The current-voltage converter 220 converts the current signal S2 supplied from the current adder 280 into a voltage signal S3. This voltage signal S3 is converted into a digital signal by a multi-bit (for example, 8 to 11 bits) A / D converter 28 for a signal processing system.
[0045]
The differential amplifier 252 constituting the clamp circuit 250 monitors the optical black level voltage value of the voltage signal S3 output from the current-voltage converter 220, and supplies the result to the current adder 280 as a clamp current Scp. Thus, feedback is applied to the input of the current-voltage converter 220 in the current mode. That is, since the solid-state imaging device 3, the current signal detection unit 5, the variable gain amplifier 200, the current-voltage conversion unit 220, and the like output an offset component in addition to a pure signal component, a DC level fluctuation occurs in the output signal. End up. In order to absorb this by the clamp current Scp, a clamp circuit 250 is provided.
[0046]
In the clamp function of this configuration example, the output level of the OPB pixel of the voltage signal S3 output from the current-voltage converter 220 is compared with the reference voltage V1 of an arbitrary reference voltage source 290 by the differential amplifier 252, and the difference is eliminated. As described above, this is realized by applying feedback after the variable gain amplifier 200 in the form of current. Since the CDS subtraction process has already been completed in the current signal detection unit 5, clamping can be performed at this position.
[0047]
Further, since feedback is applied by current, a special circuit such as a voltage adder using a resistor or the like is not required, and the OPB pixel is simply added to the signal current S1 from the variable gain amplifier 200 by simply adding the clamp current Scp. There is an advantage that the DC level of the signal component can be controlled. For this reason, a system can be simplified and the number of parts can also be reduced.
[0048]
Further, since the current signal detection unit 5 and the variable gain amplifier 200 having the CDS function perform signal processing with a current signal, when processing a signal in a limited power supply voltage, the circuit is more than processing with a voltage signal. There is also an advantage that it is easy to ensure the dynamic range. Therefore, an independent DC shift circuit 909 for securing the dynamic range of the CDS circuit 903 as illustrated in FIG. 12 of the prior art is not particularly required, and the current / voltage conversion unit 220 converts it into a voltage signal. The objective of securing the dynamic range of the analog circuit can be achieved by only applying feedback by the current clamp unit 26 once before the operation.
[0049]
In this example, the variable gain amplifier 200 is inserted after the current signal detector 5. However, the variable gain amplifier 200 can be inserted before the current signal detector 5 having the CDS function. The variable gain amplifier 200 can be omitted. In addition to the variable gain amplifier 200, other circuit blocks such as a current type sample and hold circuit may be inserted.
[0050]
In this example, the clamp current is fed back to the subsequent stage of the variable gain amplifier 200, but can be fed back immediately after the current signal detector 5. In this case, when the gain of the variable gain amplifier 200 is changed, the gain is similarly applied to the offset component output from the solid-state imaging device 3 and the current signal detection unit 5 and the clamp current for removing the offset component. There is an advantage that the clamp is difficult to be removed when the gain of the amplifier 200 is changed. However, the gain component of the noise component of the clamp current is also controlled, and there is a possibility that S / N is disadvantageous when the gain is increased.
[0051]
FIG. 3 is a diagram illustrating a configuration example of an embodiment of the current signal detection unit 5. 3A is a circuit diagram thereof, and FIG. 3B is a timing chart for explaining the operation. The configuration shown in the figure is characterized in that a current mirror 70 is used as the voltage operating point setting unit 7 and a current copier (current storage cell) 90 is used as the current sampling unit 9. This configuration is the same as the configuration of an embodiment of the current signal detection unit described in Japanese Patent Application No. 2002-102108 by the applicant of the present application.
[0052]
The current mirror 70 receives a current signal output via the horizontal signal line 20 which is an example of the pixel signal line of the solid-state image sensor 3, and outputs a current signal having a magnitude corresponding to the magnitude of the received current signal. It is an example of a current / current conversion unit.
[0053]
As shown in FIG. 3A, the current mirror 70 has an NchMOS as an input-side element whose drain and gate are connected in common to the horizontal signal line 20 and whose source is connected to the ground which is a potential reference. The transistor is composed of a transistor Q71 and an NchMOS transistor Q72 as an output side element having a gate connected to the NchMOS transistor Q71 in common and a source connected to the ground (GND). That is, the pixel signal line 20 through which a signal flows from the solid-state imaging device 3 is connected to a current mirror 70 composed of Nch MOS transistors Q71 and Q72. Both NchMOS transistors Q71 and Q72 have the same characteristics.
[0054]
As shown in FIG. 3A, the current copier 90 includes a PchMOS transistor Q91 whose drain as an input / output terminal is connected to the drain of the NchMOS transistor Q72 and whose source is connected to the power supply line VDD, and the PchMOS transistor. Capacitor C91 for sampling connected between the gate of Q91 and power supply line VDD, switch element SW91 connected between the gate and drain of PchMOS transistor Q91, the drain of PchMOS transistor Q91 and current output terminal Iout Switch element SW92 connected between the two.
[0055]
That is, first, the output of the current mirror 70, that is, the drain terminal of the Nch MOS transistor Q72 is connected to the drain terminal of the Pch MOS transistor Q91. A sampling capacitive element C91 is connected to the power supply voltage VDD at the gate of the Pch MOS transistor Q91, and a switch element SW91 is inserted between the gate and the drain to constitute a current copier 90.
[0056]
A switch element SW92 is connected to the end of the node connecting the drain terminals of the Nch MOS transistor Q72 and the Pch MOS transistor Q91, and is connected to the output terminal Iout.
[0057]
Here, as shown in FIG. 3 (A1), when the switch element SW91 is controlled to be conductive and the switch element SW92 is controlled to be nonconductive, the current copier 90 enters the input phase, and as shown in FIG. When the SW 91 is controlled to be in a non-conductive state and the switch element SW 92 is controlled to be in a conductive state, the current copier 90 enters an output phase.
[0058]
In the example of FIG. 3A, since the solid-state imaging device 3 includes an NchMOS transistor as the amplification transistor 13, an NchMOS transistor is used as the current mirror 70 and a PchMOS transistor is used as the current copier 90, respectively. If the solid-state image pickup device 3 is provided with a PchMOS transistor as the amplification transistor 13, the current mirror 70 and the current copier 90 are also configured as shown in FIG. What inverts the polarity of Nch and Pch may be used.
[0059]
FIG. 3B shows the control signal ΦRST of the switch element SW91, the control pulse ΦDET of the switch element SW92, and the output signal waveform Iout appearing at the output terminal Iout, together with the output signal waveform IIN of the solid-state imaging device 3. Has been. However, the control pulses ΦRST and ΦDET control the respective switch elements to be in a conductive state (on) during a high (H) period and to be non-conductive (off) during a low (L) period. With the switch control of ΦRST and ΦDET, the Pch MOS transistor Q91 and the capacitive element C91 operate as a current copier.
[0060]
A signal current IIN having a signal waveform shown in FIG. 3B is supplied from the solid-state imaging device 3 to the NchMOS transistor Q71 of the current mirror 70 through the horizontal signal line 20. This signal waveform is the same as a general output signal waveform of a current output type solid-state imaging device. For example, there are a reset period and a detection period within one pixel period, and an offset component signal Ioff is output during the reset period, and a detection current “Ioff-Isig” is output during the detection period. The difference Isg is the signal current that is originally required.
[0061]
The signal current IIN output from the solid-state imaging device 3 is supplied to the current mirror 70 including NchMOS transistors Q71 and Q72 via the pixel signal line 20. Since the current mirror 70 operates so that the input and output currents are the same, the signal current input to the Nch MOS transistor Q71 appears as it is at the drain of the Nch MOS transistor Q72.
[0062]
When the output signal IIN of the solid-state imaging device 3 is in the reset period, as shown in FIG. 3A1, the switch element SW91 is turned on by the H period of the control pulse ΦRST, and the switch element SW92 is turned on by the L period of the control pulse ΦDET. Control to non-conduction state. At this time, the current copier 90 enters an input phase and inputs all the current Ioff flowing from the solid-state imaging device 3 via the current mirror 70.
[0063]
Then, a voltage corresponding to the magnitude of the signal current (offset component) Ioff at this time appears at the gate terminal of the Pch MOS transistor Q91, and the next instantaneous switching element SW91 is turned off, so that the gate voltage at that time is reduced. The capacitive element C91 stores it. The current copier 90 enters the output phase, stores the offset current Ioff input earlier, and continues to flow as it is.
[0064]
In this state, the output signal IIN of the solid-state imaging device 3 next moves to the detection period, and the signal “Ioff-Isig” flows in through the current mirror 70, but the current copier 90 is in the output phase, so The current Ioff stored in the capacitive element C91 is kept flowing. At this time, by making the switch element SW92 conductive, only the difference between the current Ioff stored in the current copier 90 and the signal current “Ioff−Isig” flowing through the current mirror 70 appears at the Iout terminal. . That is, “Iout = Ioff− (Ioff−Isig) = Isig”, and only a pure signal Isig that does not include the offset component Ioff appears at the Iout terminal.
[0065]
In this way, by using the configuration shown in FIG. 3, the offset current Ioff causing the FPN can be removed, and only the original signal component Isig can be taken out from the output terminal Iout as the current signal Iout. A processing function (that is, an FPN suppression function) can be realized. The output current signal is not a continuous wave, but is converted to a continuous wave by sampling.
[0066]
This circuit includes only one current mirror 70 including NchMOS transistors Q71 and Q72, and one current copier 90 including PchMOS transistor Q91, capacitive element C91, and switch elements SW91 and SW92, and the circuit configuration is very simple. The feature is that the number of elements is small. Also, the control for the current copier 90 functioning as the current sampling unit 9 has a feature that it is very easy to control because it has only two phases: storage during the reset period and output during the detection period.
[0067]
The potential of the pixel signal line 20 is always determined by the diode-connected NchMOS transistor Q71 constituting the current mirror 70, and becomes a bias value corresponding to Vth of the NchMOS transistor Q71 + current value at that time and transistor size. By appropriately selecting the Vth and size of the transistor, the transistor can always be stabilized near GND. As a result, the amplification transistor 13 in the solid-state imaging device 3 can always maintain a good amplification factor and prevent deterioration of linearity.
[0068]
FIG. 4 is a diagram illustrating a more specific configuration example of the imaging apparatus 1, and includes the variable gain amplifier 200 and the current together with the embodiment of the current signal detection unit 5 using the current copier illustrated in FIG. 3. 3 shows an embodiment of a voltage conversion unit 220.
[0069]
The variable gain amplifier 200 provided in the subsequent stage of the current signal detector 5 includes Nch MOS transistors Q201, Q202, Q203, and Q204, and current sources I201, I202, I203, and NchMOS transistors Q201 to Q204, respectively. The current mirror circuit includes switch elements SW202a, SW202b, SW203a, SW203b, SW204a, and SW204b arranged between I204 and Nch MOS transistors Q202 to Q204 and corresponding current sources I202 to I204.
[0070]
In the illustrated example, an Nch MOS transistor Q201 and a current source I201 are arranged on the current input side, and NchMOS transistors Q202 to Q204 and current sources I202 to I204 are arranged on the current output side so as to be switchable. In other words, three output stages of the current mirror circuit are arranged in parallel on the output side. However, this is configured according to the required gain, and is not limited to three parallels. Further, although the current mirror circuit is constituted by the Nch MOS transistor, it may be constituted by using a Pch MOS transistor.
[0071]
The current signal S0 output from the current signal detector 5 is input to the gate terminal of the Nch MOS transistor Q202 on the input side of the variable gain amplifier 200 having a current mirror configuration. The current mirror circuit simply outputs the input current in accordance with the mirror ratio, but the variable mirror operation can be performed by making the mirror ratio variable. Here, the switch elements SW202a to SW204b are provided to make the mirror ratio variable. When the switch elements SW202a to SW204b are turned on according to a necessary gain, the mirror ratio can be determined. Further, current sources I201 to I204 are provided as a mechanism for supplying a bias current so that the variable gain amplifier 200 operates even when the signal current S1 from the current signal detection unit 5 becomes “0”.
[0072]
The current-voltage converter 220 provided at the subsequent stage of the variable gain amplifier 200 includes a differential amplifier 222 and a resistance element 224 disposed between the inverting input terminal (−) and the output terminal of the differential amplifier 222. And a reference voltage source 226 disposed between the non-inverting input terminal (+) of the differential amplifier 222 and a reference voltage (specifically, GND (ground)). The reference voltage source 226 serves as a voltage reference when the current-voltage conversion unit 220 performs current-voltage conversion.
[0073]
The current signal S <b> 1 output from the variable gain amplifier 200 is directly input to the inverting input terminal (−) of the differential amplifier 222 constituting the current / voltage conversion unit 220. Further, the clamp current Scp is also directly input to the inverting input terminal (−) of the differential amplifier 222 from the differential amplifier 252 having a current mode clamp function.
[0074]
That is, according to this configuration, the current signal S1 from the variable gain amplifier 200 and the clamp current Scp from the differential amplifier 252 are combined at the inverting input terminal (−) of the differential amplifier 222, and the differential amplifier In 222, it is immediately converted into a voltage signal S3. Since the current is directly added at the inverting input terminal (−) of the differential amplifier 222, a special circuit such as a voltage adder using a resistor or the like is not required, and the number of parts can be reduced. . A current type clamp circuit that matches the combination with the current output type solid-state imaging device 3 can be obtained.
[0075]
In this configuration, the differential amplifier 252 has an input voltage of the A / D converter 28, that is, a voltage output from the current-voltage converter 220 at an arbitrary time controlled by the switch element 254 (OPB timing in the previous example). The signal S3 is monitored, and the input of the current-voltage conversion unit 220 (in this example, the differential amplifier) so that there is no difference from the voltage of the reference voltage source 290 connected to the non-inverting input terminal (+) of the differential amplifier 252. The feedback is applied in the current mode to the inverting input terminal (−) of 222. Note that a sample hold circuit or the like may be inserted in front of the differential amplifier 252 in order to hold the value monitored when the switch element 254 is off while the switch element 254 is off.
[0076]
Here, according to such a current feedback type current clamp unit 26, the voltage adder required in the case of the voltage feedback type, the capacitive element for cutting the DC component, and the like are not required, and the signal simply Clamping can be performed only by adding the clamp current Scp to the current S1. For this reason, the number of parts can be reduced, and the number of circuits through which signals pass can be reduced, so that noise can be reduced.
[0077]
Further, the circuit itself for injecting the clamp current can be easily formed by using, for example, the constant current characteristic of the MOS transistor, and the complexity of the system can be suppressed. In particular, by configuring a current type CDS circuit like the current signal detector 5 illustrated in FIG. 4, a current feedback type clamp circuit can be used, which contributes to simplification of the system. For example, the solid-state imaging device 3, the current signal detection unit 5, and the current clamp unit 26 can be integrally formed on a semiconductor substrate using a CMOS transistor or the like.
[0078]
Furthermore, since the current signal detector 5 and the variable gain amplifier 200 having the CDS function perform current-type signal processing, when processing a signal in a limited power supply voltage, the circuit of the circuit is more than processing with a voltage signal. There is also an advantage that it is easy to secure a dynamic range.
[0079]
FIG. 5 is a diagram illustrating a specific configuration example of the clamp circuit 250. Here, the example shown in FIG. 5A shows a case where the current output type differential amplifier 252 is specifically composed of CMOS transistors. The current output type differential amplifier 252 includes a differential amplifier 252a, a Pch MOS transistor 252b, and a sampling circuit 252c. Sampling circuit 252c includes a switch element 252d and a hold capacitor 252e. The hold capacitor 252e holds the output voltage of the differential amplifier 252a sampled during the clamp period specified by the clamp pulse.
[0080]
The clamp circuit 250 receives the sampling voltage held in the hold capacitor 252e between the sampling circuit 252c and the Pch MOS transistor 252b, and generates a clamp voltage Vcp for controlling the gate terminal of the Pch MOS transistor 252b accordingly. And a control voltage generation circuit 260.
[0081]
The source terminal of the Pch MOS transistor 252b is connected to the voltage source (VDD in this example), and the drain terminal is connected to the input of the current-voltage converter 220. 4, the drain terminal is connected to the inverting input terminal (−) of the differential amplifier 222, and the clamp current Scp generated by the Pch MOS transistor 252b is inverted of the differential amplifier 222. The input terminal (−) is input.
[0082]
When the control voltage generation circuit 260 applies a voltage that causes the Pch MOS transistor 252b to operate in the saturation region, the Pch MOS transistor 252b operates as a current source that supplies a current according to the voltage between the gate and the source. That is, the Pch MOS transistor 252b functions as a voltage / current converter that converts the clamp voltage Vcp output from the control voltage generation circuit 260 into the clamp current Scp. Thus, the clamp circuit 250 can function as a current output type clamp circuit.
[0083]
Even if the sampling voltage held in the hold capacitor 252e is directly applied to the gate terminal of the Pch MOS transistor 252b without using the control voltage generation circuit 260, the DC level of the output signal is controlled, that is, the clamp function is activated. Can be made.
[0084]
In the example shown in FIG. 5A, the clamp current Scp is supplied to the input of the current-voltage conversion unit 220 only by the Pch MOS transistor 252b. However, the P-channel MOS transistor 252b is replaced with an N-channel MOS transistor to replace the current-voltage conversion unit. The clamp current Scp may be drawn from the input 220 to the Nch MOS transistor side. Further, it is also possible to use a configuration in which the direction of current flow is switched using both the Pch MOS transistor and the Nch MOS transistor.
[0085]
In the example shown in FIG. 5A, the clamp voltage Vcp output from the control voltage generation circuit 260 is converted into the clamp current Scp by using the Pch MOS transistor 252b. By configuring the output terminal of the dynamic amplifier 252a as a current output type, the output of the current output type differential amplifier can be directly used without providing a voltage-current conversion unit such as a control voltage generation circuit 260 or a MOS transistor. A configuration in which the clamp current Scp is generated can also be adopted.
[0086]
The second example shown in FIG. 5B shows a configuration example in which a three-terminal switch element 258 is inserted into the drain terminal of the Pch MOS transistor 252b. The three-terminal switch element 258 has an input terminal a connected to the drain terminal of the Pch MOS transistor 252b, one output terminal b connected to the input part of the current-voltage converter 220, and the other output terminal c connected to the current-voltage converter 220. The operation reference point is connected.
[0087]
In correspondence with the current-voltage converter 220 shown in FIG. 4, the output terminal b is connected to the inverting input terminal (−) of the differential amplifier 222, and the clamp current Scp generated by the Pch MOS transistor 252b is the three-terminal switch element 258. Through the inverting input terminal (−) of the differential amplifier 222. Further, the output terminal c is connected to the non-inverting input terminal (+) of the current-voltage conversion unit 220 so that the same reference voltage V2 as that of the reference voltage source 226 connected to the non-inverting input terminal (+) is applied. To do. Hereinafter, the role of the three-terminal switch element 258 will be described.
[0088]
As shown in a specific example of the current signal detection unit 5 in FIG. 3, when performing CDS processing in the current mode using the current copier cell, it is necessary to close the switch element SW92 for sampling during the reset period. At this time, since the signal current S1 does not flow into the variable gain amplifier 200 and the clamp circuit 250, only the clamp current Scp flows into the current-voltage converter 220.
[0089]
Since the clamp current Scp flows so that the dynamic range of the current-voltage conversion unit 220 is properly secured during the period in which the signal current flows, if the signal current S1 disappears, the current-voltage conversion is performed due to the clamp current Scp. There is a possibility that the unit 220 temporarily loses its dynamic range. In general, in the case of an I / V conversion circuit made using a differential amplifier, once it is out of the dynamic range, the operation speed becomes extremely slow. It may take such a case.
[0090]
In order to avoid such a problem, the switch element 258 is on / off controlled at the same timing as the on / off control of the switch element SW92. That is, when the switch element SW92 becomes non-conductive and the signal current S1 does not flow to the current-voltage converter 220 side, the switch element 258 is disconnected from the output terminal b and the current-voltage converter 220 is connected to the input section. The PchMOS transistor 252b is disconnected. Accordingly, by stopping feedback of the clamp current Scp to the imaging signal S1 input to the current-voltage conversion unit 220, the inflow of the clamp current Scp to the current-voltage conversion unit 220 is prevented, and the dynamic range is removed. To prevent.
[0091]
Further, if the switch element 258 is simply disconnected, the destination of the clamp current Scp from the Pch MOS transistor 252b is lost, and the current value of the clamp current Scp becomes “0”. Then, when the switch element 258 is next connected to the output terminal b side and the clamp current Scp starts to flow, it takes time to settle down to a desired current value, so that the signal is faithfully reproduced within a specified time. There is a risk that it will be impossible.
[0092]
Therefore, instead of simply controlling the on / off of the switch element 258, as shown in FIG. 5B, when the switch element SW92 is turned off, the switch element 258 is switched from the output terminal b to the output terminal c side. By connecting to the non-inverting input terminal (+) side of the current-voltage conversion unit 220, it is connected to the reference voltage source 226 to which the non-inverting input terminal (+) is connected. That is, during the reset period in which the switch element SW92 is turned off, the feedback of the clamp current Scp to the imaging signal is stopped, and the clamp current Scp from which the feedback is stopped is used as the operation reference point of the current-voltage conversion unit 220. Is returned to the reference voltage source 226 for setting.
[0093]
In this way, when viewed from the Pch MOS transistor 252b that flows the clamp current Scp, it does not seem to change anything when the clamp current Scp is flowed into the current-voltage converter 220 or when it is cut off (cut). Therefore, the current controlled by the control voltage generation circuit 260 can always flow, and the stability of the clamp current Scp can be maintained. That is, the stability of the clamp current Scp is always maintained, and a desired current can be obtained immediately when the clamp current Scp is again flowed into the imaging signal S1.
[0094]
A third example illustrated in FIG. 5C illustrates a specific configuration example of the control voltage generation circuit 260. This control voltage generation circuit 260 has a differential amplifier 262, a Pch MOS transistor 264, and a resistance element 266. The Pch MOS transistor 264 has a source terminal connected to a voltage source (VDD in this example), a gate terminal connected to the output terminal of the differential amplifier 262 in common with the gate terminal of the Pch MOS transistor 252b, and a drain terminal connected to the differential amplifier 262. Is connected to the non-inverting input terminal (+). The output voltage of the differential amplifier 252 a is input to the inverting input terminal (−) of the differential amplifier 262.
[0095]
In this configuration, the control voltage generation circuit 260 receives the output voltage of the differential amplifier 252a and generates a voltage suitable for driving the Pch MOS transistor 252b. That is, the differential amplifier 262 controls the gate voltage of the Pch MOS transistor 264 so that the output voltage of the differential amplifier 252a and the voltage applied to the resistance element 266 are the same. At this time, the current flowing in the Pch MOS transistor 264 is controlled by the resistance element 266 and the voltage applied thereto, so that the gate voltage of the Pch MOS transistor 264 that can flow the current value is automatically determined.
[0096]
When the capability (performance / characteristic) of the Pch MOS transistor 264 and the Pch MOS transistor 252b in the subsequent stage are made the same, and the capability and the value of the resistance element 266 are determined so that the Pch MOS transistors 264 and 252b operate in the saturation region. By supplying the gate voltage of the Pch MOS transistor 264 as it is to the gate terminal of the Pch MOS transistor 252b, the currents flowing through the Pch MOS transistors 264 and 252b can be made exactly the same. That is, the clamp current Scp flowing through the Pch MOS transistor 252b can be controlled by the resistance element 266 and the voltage applied thereto.
[0097]
Note that the configuration example of the control voltage generation circuit 260 shown in FIG. 5C is merely an example, and various other configuration examples can be taken. For example, the differential amplifier 252a may be used as a comparator, and the control voltage generation circuit 260 in the subsequent stage may be configured to perform various processes using a digital circuit, that is, a configuration including an arithmetic processing unit using a digital circuit. In this case, the processing result (digital value) of the digital circuit is converted back to an analog signal (for example, a voltage signal) using a D / A converter and supplied as the input voltage of the Pch MOS transistor 252b, whereby the Pch MOS transistor 252b A clamp current Scp can also be generated.
[0098]
As described above, according to the configuration of the above embodiment, since the current feedback type clamp circuit is used, the voltage adder necessary for the voltage feedback type, the capacitive element for cutting the DC component, etc. Becomes unnecessary, and DC clamping can be performed simply by feeding back the clamp current to the signal current. For this reason, the number of parts can be reduced, and the number of circuits through which signals pass can be reduced, so that noise can be reduced.
[0099]
In addition, as shown in a specific configuration example in FIG. 5, the circuit itself for injecting the clamp current can be easily formed by using the constant current characteristic of the MOS transistor, and the complexity of the system is suppressed. be able to. In addition, when combined with a CDS circuit or PGA circuit configured to perform current-type signal processing, when processing signals within a limited power supply voltage, the dynamic range of the circuit is secured rather than processing with voltage signals. You can also enjoy the effect of being easy to do.
[0100]
FIG. 6 is a diagram illustrating a configuration example of another embodiment of the current signal detection unit 5. Here, FIG. 6A is a circuit diagram thereof, and FIG. 6B is a timing chart for explaining the operation. This configuration is the same as the configuration of the sixth embodiment of the current signal detection unit described in Japanese Patent Application No. 2002-102108 by the applicant of the present application.
[0101]
The current signal detection unit 5 of this embodiment uses the current mirror 70 as the voltage operating point setting unit 7 as in the embodiment shown in FIG. 3, while the current sampling unit 9 uses the current mirror 70 of the embodiment shown in FIG. Instead of the current copier 90, when the switch element SW81, the capacitive element C81 that receives a current signal when the switch element SW81 is turned on and holds a voltage corresponding to the current signal, the current mirror 80, and the switch element SW81 are turned on The transistor Q83 that forms a current mirror with another transistor is used. A sample-and-hold (S / H) circuit composed of the switch element SW81 and the capacitive element C81 and a current mirror cause the same action as the current copier 90.
[0102]
The current mirror 80 is connected to the drain side of an Nch MOS transistor Q72, which is a constituent element of the current mirror 70 functioning as the voltage operating point setting unit 7, and the input side has the drain and gate connected in common and the source connected to the power supply VDD. PchMOS transistor Q81, and a PchMOS transistor Q82 which is an output side element having a gate connected to the PchMOS transistor Q81 and a source connected to the power supply VDD. Both Pch MOS transistors Q81 and Q82 have the same characteristics.
[0103]
The gate of the Nch MOS transistor Q71 is connected to one end of the capacitive element C81 and the gate of the Nch MOS transistor Q83 via the switch element SW81. The other end of the capacitive element C81 and the source of the Nch MOS transistor Q83 are connected to GND which is a voltage reference.
[0104]
The switch element SW81 is supplied with a control pulse ΦRST that controls the switch element SW81, and the switch element SW81 is turned on (turned on) only when the control pulse ΦRST is in the H period. As shown in FIG. 6, the switch element SW81 is made conductive (ON) only when the output current of the solid-state image sensor 3 is in the reset period. When switch element SW81 is on, Nch MOS transistors Q71 and Q83 form a current mirror.
[0105]
Next, the operation of the current signal detector 5 of this embodiment will be described. First, the Nch MOS transistors Q71 and Q72 form a current mirror 70, and the Nch MOS transistor Q72 operates to flow the signal current IIN received by the Nch MOS transistor Q71 as it is. Further, the output current of the Nch MOS transistor Q72 is input to the current mirror 80 formed from the Pch MOS transistors Q81 and Q82, and appears directly as the output current at the drain of the Pch MOS transistor Q82.
[0106]
For example, when the output current of the solid-state imaging device 3 is in the reset period, the current mirror 70 inputs the offset current Ioff as it is to the current mirror 80 including the Pch MOS transistors Q81 and Q82, and the current mirror 80 further offsets the offset in the reset period. The current Ioff is output as it is toward the Nch MOS transistor Q83 and the output terminal Iout.
[0107]
Further, during this reset period, the gates of the Nch MOS transistors Q71 and Q83 are connected to each other via the switch element SW81 to form a current mirror, so that the offset current Ioff during the reset period appears as it is at the drain of the Nch MOS transistor Q83. At this time, since the gate of the Nch MOS transistor Q71 is connected to the capacitive element C81 via the switch element SW81, the gate voltage of the Nch MOS transistor Q71 is stored and held in the capacitive element C81.
[0108]
Here, the difference between the currents of the Nch MOS transistor Q83 and the Pch MOS transistor Q82 is output to the output terminal Iout. At this time, the Nch MOS transistor Q83 and the Pch MOS transistor Q82 flow the same offset current Ioff. Therefore, as shown in FIG. 6B, the output current Iout is “0”.
[0109]
Next, when the output current of the solid-state image sensor 3 is detected, the switch element SW81 is in a non-conduction state (off). At this time, the gate voltage corresponding to the current flowing through the Nch MOS transistor Q71 during the reset period is stored and held in the capacitive element C81 and supplied to the gate of the Nch MOS transistor Q83. Therefore, the Nch MOS transistor Q83 allows a current corresponding to the voltage stored in the capacitive element C81 to flow even when the switch element SW81 is off.
[0110]
If the Nch MOS transistors Q71 and Q81 have the same size, the Nch MOS transistor Q83 stores the offset current Ioff during the reset period of the solid-state imaging device 3 and continues to flow even when the switch element SW81 is off. That is, the Nch MOS transistor Q83 still stores the offset current Ioff of the previous reset period.
[0111]
In addition, since the Nch MOS transistor Q72 forms a current mirror with the Nch MOS transistor Q71 during the detection period, the detection current “Ioff-Isig” during the detection period is directly input to the current mirror 80 including the Pch MOS transistors Q81 and Q82. Further, the current mirror 80 outputs the detection current “Ioff-Isig” during the detection period as it is to the Nch MOS transistor Q83 and the output terminal Iout.
[0112]
Here, since the difference in current between the Nch MOS transistor Q83 and the Pch MOS transistor Q82 is output to the output terminal Iout, as shown in FIG. 6B, “Iout = (Ioff−Isig) −Ioff = −Isig Thus, only the signal component is output from the output terminal Iout. That is, the offset component Ioff is caused to flow from the Nch MOS transistor Q83 and the detection current “Ioff-Isig” in the detection period is turned back by the current mirror 80 composed of the Pch MOS transistors Q81 and Q82 to perform subtraction. A pure signal component “-Isig” not including Ioff is generated.
[0113]
In short, the current sampling unit 9 holds the current component “Ioff-Isig” output from the Pch MOS transistor Q82, which is an element on the output side of the current mirror 80, and the capacitive element C81 during the detection period of the current signal IIN. By obtaining a difference from the current component Ioff corresponding to the voltage, the signal component “−Isig” in which the offset component is suppressed is extracted.
[0114]
Thus, even in the configuration of the embodiment shown in FIG. 6 that does not use the current copier as the current sampling unit 9, the direction of the output current is opposite to that of the first to fifth embodiments using the current copier. The cause offset current Ioff is removed, and only the original signal component “−Isig” can be taken out from the output terminal Iout as the current signal Iout, and the function as a current mode CDS circuit can be achieved.
[0115]
Unlike the embodiment shown in FIG. 3, when the control signal ΦRST to the switch element SW81 is OFF during the reset period, a reset noise component appears at the output terminal Iout, but a process of making a continuous signal voltage, that is, a current clamp Since it can be removed in the process of being converted into a continuous signal by the sample and hold circuit after the I / V conversion by the current-voltage converter 220 in the unit 26, there is no problem.
[0116]
The circuit of this embodiment also includes a single current mirror 70 composed of Nch MOS transistors Q71 and Q72, a switch element SW81, a capacitive element C81, a single current mirror 80 composed of Pch MOS transistors Q81 and Q82, and a switch element SW81. It is composed only of the current sampling unit 9 composed of the Nch MOS transistor Q83 that forms a current mirror with the Nch MOS transistor Q71 when it is on, and the circuit configuration is very simple and substantially the same as in the previous embodiment. It has the feature that the number is small. Also, the control of the current sampling section 9 has a feature that it is very easy to control because it has only two phases: storage during the reset period and output during the detection period.
[0117]
FIG. 7 is a diagram illustrating a configuration example of another embodiment of the clamp circuit. Here, FIG. 7A is a block diagram showing the configuration, and FIG. 7B is a timing chart of a pulse signal used in this clamp circuit.
[0118]
The configuration of the clamp circuit 300 of the present embodiment includes an arithmetic processing unit of a digital circuit including a dedicated A / D converter provided independently of the A / D converter 28 for the signal processing system, The processing result (digital value) is converted back to an analog voltage signal using a D / A converter and supplied as an input voltage to the Pch MOS transistor 252b, thereby generating a clamp current Scp in the Pch MOS transistor 252b. Have The clamp circuit 300 is configured to be operable in either a startup mode with a relatively high response speed or a normal mode with a relatively low response speed.
[0119]
As shown in FIG. 7A, the clamp circuit 300 of this embodiment counts the number of comparison pulses CP and a comparator (comparator) 302 corresponding to the differential amplifier 252a in the clamp circuit 250 of the previous embodiment. An up / down counter 304 and a determination circuit 306 that determines whether or not the count value CNT of the up / down counter 304 matches a predetermined condition. An inverted vertical synchronizing signal NVS obtained by inverting the vertical synchronizing signal VS by the inverter 308 is input to the reset terminal RST of the up / down counter 304, and the count value CNT1 is reset for each inverted vertical synchronizing signal NVS. Yes.
[0120]
The clamp circuit 300 is output from the register counter 310 having an up / down count function, the D / A converter 312 that directly converts the count value CNT2 of the register counter 310 into an analog voltage, and the D / A converter 312. A voltage-current converter (V / I converter) 314 for converting the analog voltage into a current signal. The current signal (clamp current Scp) output from the voltage / current converter 314 is supplied to the input unit of the current / voltage converter 220.
[0121]
The control system from the register counter 310 to the current-voltage converter 220 has a polarity that increases the OPB level when the count value CNT2 is increased, and conversely decreases the OPB level when the count value CNT2 is decreased. As the voltage-current converter 314, the PchMOS transistor 252b in the clamp circuit 250 of the previous embodiment may be used. In this case, the output of the D / A converter 312 is connected to the gate terminal of the Pch MOS transistor 252b. What is necessary is just to provide an inverting amplifier as needed so that it may become the above control polarities.
[0122]
The register counter 310 is to be counted differently depending on the operation mode of the clamp circuit 300. Because of this mechanism, the clamp circuit 300 converts the pulse input to the clock terminal CK of the register counter 310 under the control of the mode switching determination circuit 320 and the mode switching determination circuit 320 into the vertical synchronization signal VS and the comparison pulse CP. A first switch 322 for switching to any one of the above, and a second switch for switching the signal input to the up / down switching terminal (U / D) of the register counter 310 to any one of the output of the comparator 302 and the determination circuit 306. A switch 324.
[0123]
Although the up / down counter 304 and the register counter 310 have different count targets, the basic operation is the same in that an up / down counter function is provided. However, since the count value CNT2 of the register counter 310 directly takes on the register value of the D / A converter 312 at the subsequent stage, the initial value D1 corresponding to the OPB level to be converged is set in the register counter 310. The
[0124]
In addition, the A / D converter for the signal processing system is independent of the A / D converter 28 for the signal processing system that converts the imaging signal S3 obtained from the current-voltage conversion unit 220 into a digital signal and performs digital signal processing. A comparator 302, an up / down counter 304, or a register counter 310 is provided as an A / D converter for direct current level comparison having a bit resolution lower than that of the comparator 302.
[0125]
For example, in the start-up mode, the comparator 302 and the register counter 310 constitute a substantially 1-bit A / D conversion unit whose actual sampling frequency is the frequency of the comparison pulse CP. In the normal mode, the comparator 302 and the up / down counter 304 substantially constitute a 1-bit A / D converter. In addition, the determination circuit 306 and the register counter 310 are configured to detect the direct current level based on the digital data obtained by the comparator 302, the up / down counter 304, or the register counter 310 that functions as an A / D converter for direct current level comparison. It functions as a digital arithmetic processing unit that obtains a control voltage signal corresponding to the difference from the reference value by digital signal processing.
[0126]
The operation control vertical synchronizing signal VS and the comparison pulse CP used in the clamp circuit 300 are emitted from a timing generator (not shown). Here, as shown in FIG. 7B, the vertical synchronization signal VS is a pulse transmitted at the beginning of one frame (or one field). The comparison pulse CP is a pulse transmitted at the OPB pixel position on the head side in the horizontal scanning direction in conjunction with the horizontal synchronization signal HS transmitted at the beginning of each horizontal scanning line (1H) of the photosensitive portion 10. This comparison pulse CP is for comparing an output signal of an arbitrary column of OPB pixels prepared on the head side in the horizontal scanning direction of the solid-state imaging device 3 with a reference voltage at the timing of the comparison pulse CP. Note that the comparison pulse CP is not transmitted at the OPB pixel position on the head side in the vertical scanning direction.
[0127]
The reference voltage V 3 is input from the reference voltage generation circuit 303 to one input terminal of the comparator 302. The reference voltage generation circuit 303 generates not a fixed reference voltage but a reference voltage V3 that is swung with a substantially constant width for each comparison pulse CP (high voltage side and low voltage side are switched alternately). The reference voltage V3 is a voltage at which the OPB level is desired to converge, and the median value V30 and the swing width ΔV3 are determined in accordance with the signal processing at the subsequent stage of the current clamp unit 26.
[0128]
The comparator 302 compares the reference voltage V3 with the voltage signal S3 output from the current-voltage converter 220, and outputs the result as a digital value. Specifically, if “reference voltage V3> voltage signal S3”, “H: high” is output, otherwise “L: low” is output. This comparison result is input to the up / down switching terminal (U / D) of the register counter 310 at startup, and is input to the up / down switching terminal (U / D) of the up / down counter 304 in the normal mode.
[0129]
The up / down counter 304 and the determination circuit 306 are portions that operate only in the normal mode. The up / down counter 304 sets the count value CNT1 when the comparison pulse CP is input to the clock terminal CK when the up / down switching terminal (U / D) is “H”, that is, “reference voltage V3> voltage signal S3”. “+1”. On the contrary, if the comparison pulse CP is input to the clock terminal CK when the up / down switching terminal (U / D) is “L”, that is, “reference voltage V3 ≦ voltage signal S3”, the count value CNT1 is set to “−1”. To do.
[0130]
Here, as shown in FIG. 7B, since the comparison pulse CP is transmitted at the position of the OPB pixel, as a result, the comparator 302 and the up / down counter 304 cause a predetermined column of OPB pixels in the horizontal scanning direction. The output signal S3 and the reference voltage V3 are compared at the timing of the comparison pulse CP, and the comparison result is reflected in the count value CNT1 of the up / down counter 304.
[0131]
The count value CNT1 of the up / down counter 304 is input to one input terminal of the determination circuit 306. The determination circuit 306 is specifically configured as a digital comparator, and D0 (digital value) is input to the other input terminal as a determination reference.
[0132]
When the count value CNT1 of the up / down counter 304 exceeds the positive determination reference value “D0”, the determination circuit 306 outputs a signal to “−1” the count value CNT2 of the register counter 310 with the next vertical synchronization signal VS. . On the other hand, when the value falls below the negative determination reference value “−D0”, a signal for “+1” the count value CNT2 of the register counter 310 is output. The output of the determination circuit 306 is input to the up / down switching terminal (U / D) of the register counter 310.
[0133]
Although the comparison output of the comparator 302 uses the register counter 310 in the startup mode and the up / down counter 304 in the normal mode, the counting operation based on the comparison output is horizontal synchronized in both the startup mode and the normal mode. This is performed by the comparison pulse CP after the signal HS. That is, substantially, the comparison operation between the reference voltage V3 and the OPB level is performed only by the comparison pulse CP after the horizontal synchronization signal HS.
[0134]
Therefore, the comparator 302 and the reference voltage generation circuit 303 do not need to operate during the time period when the comparison pulse CP is not active. Rather, since DC current flows through the comparator 302 and the reference voltage generation circuit 303 and the current consumption is wasted if it is operated, it is only necessary to enable the comparison pulse CP when it is active. Therefore, in the present embodiment, the on / off control unit 309 creates a control signal that falls with the rising comparison pulse CP by the horizontal synchronization signal HS, and enables the comparator 302 and the reference voltage generation circuit 303 with this control signal. It is configured as follows. A specific circuit of the on / off control unit 309 is not shown. Thereby, current consumption can be reduced.
[0135]
In the clamp circuit 300 configured as described above, the output of the comparator 302 is “L” when the OPB pixel output level of the voltage signal S3 output from the current-voltage converter 220 is higher than the reference voltage V3 in both the startup mode and the normal mode. The count value CNT2 of the register counter 310 is decreased by “1”, and the analog output of the D / A converter 312 is decreased by “1LSB”. As a result, the OPB pixel output level (OPB level) of the current-voltage converter 220 is also reduced, and the whole forms a negative feedback control system so that the difference from the reference voltage V3 is reduced.
[0136]
As can be seen from FIG. 7B, the comparison pulse CP and the vertical synchronization signal VS have a higher frequency. Therefore, when the comparison pulse CP is input to the clock input terminal CK of the register counter 310 that sets the register value of the voltage-current converter 314, the entire control system operates at a relatively high speed. The clamp circuit 300 sets this operation state as a startup mode. On the other hand, when the vertical synchronization signal VS is input to the clock input terminal CK, the entire control system operates at a relatively low speed. The clamp circuit 300 sets this state as a normal mode.
[0137]
By the way, when the difference between the OPB pixel output and the reference voltage V3 becomes smaller than the change in output due to the fluctuation of “1LSB” of the voltage-current converter 314, the output voltage of the voltage-current converter 314 is raised or lowered for each comparison. Become. This state can be said to be a stable point from the viewpoint of the digital control described above. However, if this voltage fluctuation appears in the image unevenness, it cannot be said to be a stable point, but rather it should be regarded as an oscillation state. On the other hand, this state indicates that the OPB pixel output is sufficiently close to the reference voltage V3.
[0138]
Therefore, in actual control, an operation state in which the OPB pixel output is close to the reference voltage V3 when the OPB pixel output is greatly separated from the reference voltage V3 is set to the start-up mode (mode output L), and the register counter 310 is counted based on the comparison pulse CP. It is operated at a relatively high speed. When the mode switching determination circuit 320 detects that the OPB pixel output and the reference voltage V3 are sufficiently close when operated in the startup mode, the mode is shifted to the normal mode (mode output H) of the low speed operation. In the normal mode, the operation is performed at a lower speed and with lower sensitivity than in the start-up mode so that the oscillation state does not occur.
[0139]
The mode switching determination circuit 320 determines whether the OPB pixel output has approached the reference voltage V3 by monitoring the change of the output voltage of the D / A converter 312 from the increased state to the decreased state. As this determination method, it is also possible to perform the change once from the increase state to the decrease state of the output voltage of the D / A converter 312 based on the state of the count value CNT2 of the register counter 310. It is also possible to detect by counting up and down several times.
[0140]
FIG. 8 is a flowchart showing the control operation in the startup mode in the clamp circuit 300. First, the clamp circuit 300 performs “initialization of startup mode” (S100). For example, the mode switching determination circuit 320 sets the mode output to “L”. The clamp circuit 300 sets an initial value D1 in the register counter 310. In response to this, a voltage corresponding to the initial value D1 is output from the voltage / current converter 314, and the voltage / current converter 314 receiving the voltage supplies the initial clamp current Scp to the input part of the current / voltage converter 220.
[0141]
Next, the clamp circuit 300 compares the OPB level indicated by the voltage signal S3 of the current-voltage conversion unit 220 with the reference voltage V3, and the comparison result is sent to the register counter 310 that bears the register value of the D / A converter 312. input. The result is captured by the comparison pulse CP that rises at the timing when the OPB pixel is output, and is reflected as a comparison result between the OPB pixel and the reference voltage V3.
[0142]
Specifically, first, the comparator 302 and the register counter 310 compare the OPB level indicated by the voltage signal S3 of the current-voltage converter 220 with the reference voltage V3 based on the comparison pulse CP (S102). If the OPB level is greater than the reference voltage V3, the register counter 310 decrements the register counter value CNT2 by “−1” (S102—YES, S110). In response, the D / A converter 312 reduces the output voltage (S112). As a result, the OPB level decreases (S114). Thereafter, the process returns to step S102, and the above processing (S102 to S114) is repeated for the next horizontal scanning. That is, until the OPB level becomes equal to or lower than the reference voltage V3, the OPB level is lowered to the reference voltage V3 by repeating the above processing for each OPB pixel in horizontal scanning.
[0143]
Conversely, when the OPB level is equal to or lower than the reference voltage V3 (when it is smaller or equal), the register counter 310 increments the register counter value CNT2 by “+1” (S102—NO, S120). In response to this, the D / A converter 312 increases the output voltage (S122). As a result, the OPB level rises low (S124). Thereafter, the process returns to step S102, and the above processing (S102 to S124) is repeated for the next horizontal scanning. That is, until the OPB level becomes equal to or higher than the reference voltage V3, the OPB level is raised to the reference voltage V3 by repeating the above process for each horizontal scanning OPB pixel.
[0144]
In this process, the mode switching determination circuit 320 monitors the count value CNT2 of the register counter 310, and counts the number of changes in the count value CNT2 from up to down, or from down to up (S130). Then, it is determined whether or not the count number satisfies a predetermined condition for switching to the normal mode (S132). When the switching condition is satisfied, the mode switching determination circuit 320 switches the mode output from “L” to “H” to shift the clamp circuit 300 to the normal mode (S134).
[0145]
Since the switching of the OPB level control voltage in steps S122 and S132 is performed for each comparison pulse CP, the control operation is relatively fast. That is, in the start-up mode, the OPB clamp level can be operated as a mode for rapidly converging to the set value.
[0146]
When the clamp operation becomes unstable for some reason after the transition to the normal mode and the OPB level is out of the predetermined range, the mode switching determination circuit 320 switches the mode output from “H” to “L”. Thus, the clamp circuit 300 is shifted to the start-up mode (S140). As a result, the high-speed pull-in operation can be restarted.
[0147]
FIG. 9 is a diagram for explaining a normal mode control operation in the clamp circuit 300. Here, FIG. 9A is a flowchart illustrating a control procedure, and FIG. 9B is a diagram illustrating an example of the reference voltage V3 generated by the reference voltage generation circuit 303.
[0148]
When shifting from the startup mode to the normal mode, the clamp circuit 300 first initializes the count value CNT1 of the up / down counter 304 (S200). In this normal mode, the comparison output of the comparator 302 is switched and input to the register counter 310 side that is cleared each time by the vertical synchronization signal VS.
[0149]
If the OPB pixel output level is greater than the reference voltage V3 in one frame, “+1” is repeated, and if it is smaller, “−1” is repeated. If the counter value CNT1 exceeds the positive reference value “D0”, the determination circuit 306 The next vertical synchronizing signal VS sends a signal to set the count value CNT2 of the register counter 310 to “−1”. On the other hand, if the negative reference value “−D0” is not reached, a signal to count value CNT2 “+1” is sent.
[0150]
Specifically, first, the comparator 302 and the up / down counter 304 compare the OPB level indicated by the voltage signal S3 of the current-voltage converter 220 with the reference voltage V3 based on the comparison pulse CP (S202). If the OPB level is greater than the reference voltage V3, the up / down counter 304 increments the counter value CNT1 by “+1” (S204). Conversely, when the OPB level is equal to or lower than the reference voltage V3 (when it is smaller or equal), the up / down counter 304 decrements the counter value CNT1 by “−1” (S206). The determination circuit 306 compares the count value CNT1 with the determination reference D0 and inputs the result to the register counter 310. The vertical synchronization signal VS is input to the clock terminal CK of the register counter 310, and the register counter 310 checks the determination result of the determination circuit 306 for each vertical synchronization signal VS (S210).
[0151]
Here, as shown in FIG. 9B, the reference voltage generation circuit 303 varies the reference voltage V3 in the normal mode up and down by the variation width ΔV3 for each comparison pulse CP. In response to this, for example, “64” is set as the determination reference value D0 in the determination circuit 306 so that the register counter 310 is operated when the count value CNT1 of the up / down counter 304 exceeds “± 64”. When the OPB pixel output is larger than the large level “V3 +” of the reference voltage V3, the up / down counter 304 repeats “+1” for each comparison pulse CP and reaches “+64” in the 64th comparison (S202, S204, S210). .
[0152]
When the determination result of the determination circuit 306 indicates that the counter value CNT1 exceeds the positive reference value “D0” (64 in the previous example), the register counter 310 counts simultaneously with the next vertical synchronization signal VS. CNT2 is set to "-1" (S220). In response to this, the D / A converter 312 reduces the output voltage (S222). As a result, the OPB level decreases (S224). Thereafter, the process returns to step S200, and the above processing (S200 to S224) is repeated for the next frame. That is, the above process is repeated until the OPB pixel output approaches the median value V30 of the reference voltage V3.
[0153]
Conversely, when the OPB pixel output is larger than the small level “V3−” of the reference voltage V3, the up / down counter 304 repeats “−1” for each comparison pulse CP and reaches “−64” in the 64th comparison ( S202, S206, S210). When the determination result of the determination circuit 306 indicates that the counter value CNT1 is below the negative reference value “−D0” (−64 in the previous example), the register counter 310 simultaneously with the next vertical synchronization signal VS. The count value CNT2 is incremented by “+1” (S230). In response to this, the D / A converter 312 increases its output voltage (S232). As a result, the OPB level rises (S234). Thereafter, the process returns to step S200, and the above processing (S200 to S234) is repeated for the next frame. That is, the above process is repeated until the OPB pixel output approaches the median value V30 of the reference voltage V3.
[0154]
On the other hand, when the OPB pixel output is between the high level “V3 +” and the low level “V3−” of the reference voltage V3, the up / down counter 304 increases “+1” with respect to the count value CNT1 for each comparison based on the comparison pulse CP. "And" -1 "are repeated. As a result, the up / down counter cannot reach “± 64”, and the clamp level remains fixed. Thus, the fluctuation range ΔV3 of the reference voltage V3 acts as a dead zone of the clamp circuit 300. The clamp level corresponds to a value obtained by converting the count value CNT2 of the register counter 310 to an analog value by the D / A converter 312, and takes a discrete value. By making the fluctuation range ΔV3 of the reference voltage V3 larger than the clamp level fluctuation corresponding to 1LSB of the D / A converter 312, the OPB pixel output can be dropped into the dead zone.
[0155]
That is, in this normal mode, the OPB clamp operation can be performed with lower sensitivity than in the startup mode. This also ensures stability against noise. However, in reality, since noise is mixed in the OPB pixel output, even if it falls on the dead zone on average, the fluctuation range may be exceeded momentarily. If the noise is large, it can be counted up or down 64 times in the previous example. This variation has a high probability of returning in the next frame, and if this is repeated, surface flicker occurs. In this case, the sensitivity of the OPB clamp can be set by adjusting the fluctuation range ΔV3 of the reference voltage V3.
[0156]
In the normal mode, the change of the register counter 310 is performed in synchronization with the vertical synchronization signal VS. That is, the actual sampling frequency becomes the frequency of the vertical synchronization signal VS. This means that the clamp level is changed at the head of one image. Thereby, there is an effect that it is possible to prevent clamp noise from being mixed in the middle of the image. Further, since the OPB level control voltage is switched for each vertical synchronization signal VS in steps S222 and S232, the control operation is relatively slow. In this respect, the effect is high in stably operating the OPB clamp control. That is, in the normal mode, when the OPB level almost converges to the reference value, the operation can be performed in a state where the sensitivity is low with respect to the fluctuation of the clamp level.
[0157]
When the clamp operation becomes unstable for some reason after the transition to the normal mode and the OPB level falls outside the predetermined range (S202), the mode switching determination circuit 320 changes the mode output from “H” to “L”. Is switched to the startup mode (S240). As a result, the high-speed pull-in operation in the startup mode can be restarted.
[0158]
As described above, the arithmetic processing unit using the digital circuit has a DC shift amount necessary for fixing the optical black level (OPB) output from the solid-state image sensor 3 to a certain set value, that is, in the solid-state image sensor 3. By holding the OPB clamp level as a digital value, an external capacitor is not required as when holding it as an analog value. Therefore, the OPB clamp function that suppresses the black level fluctuation in the screen while reducing the number of components and the mounting area can be realized by digital processing.
[0159]
Further, by providing a circuit (A / D converter) for digitizing the clamp level independently of the signal system, a low resolution A / D converter can be used. For example, it is possible to use a comparator 302, that is, a comparator that digitizes OPB level digitizing by 1 bit. Compared with the case of using a multi-bit A / D converter, digital noise can be reduced by lowering the sampling frequency. The problem can be alleviated and the circuit scale can be reduced. Therefore, by integrating the clamp circuit 300 on the same semiconductor substrate as that of the solid-state image sensor 3, it is possible to provide a solid-state image pickup device having a clamp system that can be highly integrated.
[0160]
In addition, by switching between multiple modes with different operating speeds and sensitivities for fluctuations in OPB level, for example, by having a high-speed and normal-sensitivity start-up mode and a low-speed and normal mode with a deadband, The contradictory characteristic of stability can be provided. As a result, the value can be rapidly converged for a large change in clamp level due to a sudden change in the offset amount due to the release of standby or a change in the gain of the PGA. By suppressing it, fluctuations in the clamp level due to noise can be suppressed.
[0161]
FIG. 10 is a block diagram showing another configuration example of the clamp circuit 250. In the configuration of the above embodiment, the signal current S0 obtained by the current signal detection unit 5 is converted into the voltage signal S3 by the current-voltage conversion unit 220, and this voltage signal S3 is monitored to realize the DC clamp. The present embodiment is characterized in that the imaging signal is configured to be monitored in the current mode.
[0162]
The clamp circuit 250 having this configuration includes a current detection circuit 293 having a current mirror configuration that receives the signal current S2 from the current signal detection unit 5, and a reference current source 296 having a current mirror configuration. The current detection circuit 293 includes a current mirror unit 294 that passes the received signal current to the differential amplifier 252 and a current mirror unit 295 that receives the signal current S2 projected by the current mirror unit 294 and passes the signal current S2 to the current-voltage conversion unit 220. including.
[0163]
A clamp pulse that defines the clamp timing is input to a predetermined position of the differential amplifier 252 (the location varies depending on the circuit configuration). Specifically, the OPB clamp is realized by inputting a pulse corresponding to the OPB pixel position of the solid-state imaging device 3. This differential amplifier 252 is of a current input and current output type, and is defined by a signal current S2 (or a current corresponding thereto) detected by the current mirror unit 294 of the current detection circuit 293 and a reference current source 296. Is compared with the reference current S4, and the clamp current Scp is fed back to the current adder 280 so that the difference is eliminated. As a result, the DC level of the signal current S2 is held at a constant value at the input of the current-voltage converter 220 provided at the subsequent stage of the current clamp unit 26.
[0164]
FIG. 11 is a diagram illustrating another example of a configuration in which an imaging signal is monitored in the current mode. The clamp circuit 250 having this configuration includes a current detection circuit 298 having a current mirror configuration that receives the signal current S2 from the current signal detection unit 5 via the switch element 297a, and a reference current source 299 having a current mirror configuration.
The switch element 297a is controlled by a clamp pulse and defines the timing for monitoring the clamp level. Corresponding to this, a switch element 297b controlled by a pulse having a polarity opposite to that of the clamp pulse is provided between the clamp circuit 250 and the current-voltage converter 220. The switch element 297b is controlled by the clamp pulse via an inverter 297c for making the clamp pulse reverse polarity.
[0165]
The differential amplifier 252 is a current input type and a current output type, and generates a signal current S2 (or a current corresponding thereto) detected by the current detection circuit 298 and a reference current S4 defined by the reference current source 299. In comparison, the clamp current Scp is fed back to the current adder 280 so that the difference is eliminated. As a result, the DC level of the signal current S2 is held at a constant value at the input of the current-voltage converter 220 provided at the subsequent stage of the current clamp unit 26.
[0166]
Note that the variable gain amplifier 200 may be provided between the current signal detection unit 5 and the current addition unit 280 even in the configuration in which monitoring is performed in the current mode illustrated in FIGS. 10 and 11. Also in this case, the feedback destination of the clamp current Scp may be either the front side or the rear side of the variable gain amplifier 200 (before the current adding unit 280).
[0167]
As described above, according to each of the above embodiments, the clamp circuit that stabilizes the DC level of the imaging signal is combined with the current feedback clamp circuit in combination with a current output type solid-state imaging device such as a CMOS sensor. This eliminates the need for a voltage adder and a capacitive element for cutting the DC component, which were necessary in the case of a voltage feedback type configuration as in the past, and simply feeding back the clamp current to the signal current, A DC clamp that stabilizes the DC level of the output signal is possible. For this reason, the number of parts can be reduced, and the number of circuits through which signals pass can be reduced, so that noise can be reduced.
[0168]
Furthermore, the circuit itself for injecting the clamp current can be easily formed by using the constant current characteristic of the MOS transistor, which can contribute to simplification of the system and reduction of the number of elements. In other words, in the combination with the current output type solid-state imaging device, the voltage operation point setting unit, the current sampling unit, or the clamp unit configuring the current signal detection unit are all configured as a current operation type, thereby obtaining an imaging unit (light receiving unit). An integrated solid-state imaging device itself in which a current signal detection unit and a clamp unit are formed on the same semiconductor substrate as that of the / pixel unit) can be used as an imaging apparatus, which is very convenient.
[0169]
In addition, the CDS circuit and the PGA circuit are configured to perform current type signal processing, and when these are combined with the current feedback type clamp unit, when a signal is processed in a limited power supply voltage, a voltage signal is used. There is also an advantage that it is easier to secure the dynamic range of the circuit than processing.
[0170]
As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.
[0171]
Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.
[0172]
For example, in the above embodiment, the configuration of the first or sixth embodiment described in Japanese Patent Application No. 2002-102108 by the applicant of the present application is used as a specific example of the current signal detection unit 5 that performs the CDS function in the current mode. However, the present invention is not limited to this, and the configurations of other embodiments described in Japanese Patent Application No. 2002-102108 can also be used. Of course, the configuration is not limited to the configuration example described in Japanese Patent Application No. 2002-102108, and any configuration may be used as long as the signal acquired by the solid-state imaging device 3 is transmitted to the current clamp unit 26 side as a current signal. For example, FPN using a current copier with a two-cell configuration proposed in “IEEE TRANSACTIONS ON ELECTRON DEVICE, VOL44, No. 10“ On-Focal-Plane Signal Processing for Current-Mode Active Pixel Sensors ”. It may be combined with a suppression circuit (CDS circuit).
[0173]
Further, for example, a CDS circuit that operates in a current mode may not be provided between the solid-state imaging device 3 and the current clamp unit 26. In this case, the CDS process may be performed in the voltage mode after the current clamp unit 26. However, in this case, as can be seen from the above description, the circuit scale as a whole increases significantly, which is not a good idea. That is, in the combination of the solid-state imaging device 3 that outputs an imaging signal as a current signal and the current clamp unit 26 that performs a clamp operation in a current mode, a configuration in which the current signal detection unit 5 that performs CDS processing in the current mode is provided between them. It becomes composition. Thus, the number of members can be reduced as much as possible, and the effect is great in terms of space and cost.
[0174]
In the above embodiment, an example in which a MOS transistor is used to configure a voltage operating point setting unit, a current sampling unit, or a current feedback unit for feeding back a clamp current to an imaging signal has been described. A configuration using a field effect transistor or a bipolar transistor may also be used.
[0175]
Furthermore, in the above-described embodiment, the area sensor in which the photosensitive portions are arranged in a matrix (two-dimensional shape) has been described as an example.
[0176]
Further, it goes without saying that each circuit described in the above embodiment can be transformed into a circuit complementary to these circuits.
[0177]
【The invention's effect】
As described above, according to the present invention, by using the current feedback type clamp circuit, the voltage adder necessary for the voltage feedback type, the capacitive element for cutting the DC component, and the like are not required. DC clamping can be achieved simply by adding a clamp current to the signal current. For this reason, it is possible to contribute to the simplification of the system and the reduction in the number of elements as well as the stabilization of the DC level of the output signal and the securing of the dynamic range of the analog circuit. This is particularly effective when combined with a current output type solid-state imaging device such as a CMOS sensor and a current operation type CDS circuit.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of an embodiment of an imaging apparatus including a current output type solid-state imaging device and an imaging signal processing apparatus according to the present invention.
FIG. 2 is a block diagram showing a current clamp unit together with the entire imaging apparatus.
FIG. 3 is a diagram illustrating a configuration example of an embodiment of a current signal detection unit.
FIG. 4 is a diagram illustrating a more specific configuration example of an imaging apparatus.
FIG. 5 is a diagram illustrating a specific configuration example of a clamp circuit.
FIG. 6 is a diagram illustrating a configuration example of another embodiment of a current signal detection unit.
FIG. 7 is a diagram illustrating a configuration example of another embodiment of a clamp circuit.
FIG. 8 is a flowchart showing a control operation in a startup mode in the clamp circuit.
FIG. 9 is a diagram for explaining a normal mode control operation in a clamp circuit;
FIG. 10 is a block diagram showing another configuration example of the clamp circuit.
FIG. 11 is a diagram illustrating another example of a configuration in which an imaging signal is monitored in a current mode.
FIG. 12 is a schematic block diagram illustrating a configuration example of a solid-state imaging device that has been conventionally used.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Imaging device, 3 ... Solid-state image sensor, 5 ... Current signal detection part, 7 ... Voltage operation point setting part, 9 ... Current sampling part, 26 ... Current clamp part, 28 ... A / D converter, 200 ... Variable gain Amplifier ... 220 ... Current / voltage converter 250 ... Clamp circuit 252 ... Differential amplifier 260 ... Control voltage generator 280 ... Current adder 290 ... Reference voltage source 300 ... Clamp circuit 302 ... Comparator 303 Reference voltage generator circuit 304 Up / down counter 306 Determination circuit 309 On / off control unit 310 Register register 312 D / A converter 314 Voltage-current converter 320 Mode switching determination circuit

Claims (12)

An imaging signal processing method for holding an output level of an imaging signal output as a current signal from a solid-state imaging device at a constant value,
The imaging signal is converted into a voltage signal, an output level of the voltage signal for a predetermined period is detected, and the imaging is performed so that a difference between the detected output level and a predetermined reference voltage value is substantially zero. It has to return the clamp current signal,
When the clamp current is fed back to the imaging signal, the clamp current that has stopped feedback to the imaging signal during the reset period is returned to a reference voltage source for setting an operation reference point for conversion to the voltage signal. An imaging signal processing method characterized by the above. An imaging signal processing apparatus that holds an output level of an imaging signal output as a current signal from a solid-state imaging device at a constant value,
A current-voltage converter that converts the imaging signal into a voltage signal;
The output level and the reference voltage value are detected by detecting the output level of the voltage signal converted by the current-voltage converter in a predetermined period and comparing the detected output level with a predetermined reference voltage value. An output level comparison unit for calculating the difference between
A current feedback unit that feeds back a clamp current to the imaging signal so that a difference between the output level obtained by the output level comparison unit and the reference voltage value is substantially zero ;
The current feedback unit circulates the clamp current that has stopped feedback to the imaging signal in a reset period to a reference voltage source for setting an operation reference point of the current voltage unit. Processing equipment. The output level comparison unit compares the output level of the voltage signal converted by the current-voltage conversion unit in the predetermined period with a reference output voltage as the predetermined reference voltage value. The imaging signal processing device according to claim 2. The output level comparison unit includes a control voltage generation unit that outputs a control voltage signal according to a difference between the output level and the reference voltage value,
The imaging signal processing apparatus according to claim 2, wherein the current feedback unit includes a voltage-current conversion unit that generates the clamp current based on the control voltage signal output from the control voltage generation unit. The voltage-current conversion unit includes a MOS transistor to which the control voltage signal is applied to a gate terminal, and generates the clamp current using a constant current characteristic of the MOS transistor. Imaging signal processing device. A current signal detection unit that suppresses an offset component included in a current signal output from each pixel of the solid-state imaging device via a pixel signal line;
The current signal output via the pixel signal line is received in the form of this current signal, and for each pixel, the component of the reset period in the received current signal is sampled, and the sampled component and the Obtaining a difference from the component of the detection period in the current signal, thereby having a current signal detection unit for extracting the imaging signal in which the offset component is suppressed,
The imaging signal processing apparatus according to claim 2, wherein the output level comparison unit detects an output level of the imaging signal detected by the current signal detection unit in the predetermined period. The current signal detection unit receives and holds the current component of the reset period in the current signal during the input phase corresponding to the reset period, and holds the current component held during the input phase during the output phase corresponding to the detection period. Has a current copier to output,
The imaging signal processing apparatus according to claim 6, wherein a difference between a component of the detection period and a component output from the current input / output terminal of the current copier is obtained in the detection period of the current signal. The imaging according to claim 2 , wherein the current-voltage conversion unit converts an imaging signal in a current mode output from the solid-state imaging device into a voltage signal by setting an operation reference point by the reference voltage source. Signal processing device. The output level comparison unit converts the imaging signal into a digital signal and performs digital signal processing, independently of the A / D conversion unit for the signal processing system, and more bit than the A / D conversion unit for the signal processing system. The imaging signal processing apparatus according to claim 2, further comprising an A / D conversion unit for output level comparison having inferior resolution. The A / D conversion unit for output level comparison is a 1-bit A / D conversion unit that compares the output level of the imaging signal for the predetermined period with the predetermined reference value. The imaging signal processing device according to claim 9 . The output level comparison unit is configured to perform control according to a difference between the output level and the reference value based on digital data representing the output level of the predetermined period obtained by the A / D conversion unit for output level comparison. A digital arithmetic processing unit that obtains a voltage signal by digital signal processing,
The imaging signal processing device according to claim 9 , wherein the current feedback unit includes a voltage-current conversion unit that generates the clamp current based on the control voltage signal obtained by the digital arithmetic processing unit. A solid-state imaging device that outputs a current signal from each pixel via a pixel signal line;
A current-voltage converter that converts an imaging signal output as the current signal from the solid-state imaging device into a voltage signal;
The output level and the reference voltage value are detected by detecting the output level of the voltage signal converted by the current-voltage converter in a predetermined period and comparing the detected output level with a predetermined reference voltage value. An output level comparison unit for calculating the difference between
A current feedback unit that feeds back a clamp current to the imaging signal so that a difference between the output level obtained by the output level comparison unit and the reference voltage value is substantially zero ;
The current feedback unit circulates the clamp current that has stopped feedback to the imaging signal during a reset period to a reference voltage source for setting an operation reference point of the current voltage unit. .

Images